Back to index

plt-scheme  4.2.1
gc_locks.h
Go to the documentation of this file.
00001 /* 
00002  * Copyright 1988, 1989 Hans-J. Boehm, Alan J. Demers
00003  * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
00004  * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
00005  * Copyright (c) 1999 by Hewlett-Packard Company. All rights reserved.
00006  *
00007  *
00008  * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
00009  * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
00010  *
00011  * Permission is hereby granted to use or copy this program
00012  * for any purpose,  provided the above notices are retained on all copies.
00013  * Permission to modify the code and to distribute modified code is granted,
00014  * provided the above notices are retained, and a notice that the code was
00015  * modified is included with the above copyright notice.
00016  */
00017 
00018 #ifndef GC_LOCKS_H
00019 #define GC_LOCKS_H
00020 
00021 /*
00022  * Mutual exclusion between allocator/collector routines.
00023  * Needed if there is more than one allocator thread.
00024  * FASTLOCK() is assumed to try to acquire the lock in a cheap and
00025  * dirty way that is acceptable for a few instructions, e.g. by
00026  * inhibiting preemption.  This is assumed to have succeeded only
00027  * if a subsequent call to FASTLOCK_SUCCEEDED() returns TRUE.
00028  * FASTUNLOCK() is called whether or not FASTLOCK_SUCCEEDED().
00029  * If signals cannot be tolerated with the FASTLOCK held, then
00030  * FASTLOCK should disable signals.  The code executed under
00031  * FASTLOCK is otherwise immune to interruption, provided it is
00032  * not restarted.
00033  * DCL_LOCK_STATE declares any local variables needed by LOCK and UNLOCK
00034  * and/or DISABLE_SIGNALS and ENABLE_SIGNALS and/or FASTLOCK.
00035  * (There is currently no equivalent for FASTLOCK.)
00036  *
00037  * In the PARALLEL_MARK case, we also need to define a number of
00038  * other inline finctions here:
00039  *   GC_bool GC_compare_and_exchange( volatile GC_word *addr,
00040  *                                GC_word old, GC_word new )
00041  *   GC_word GC_atomic_add( volatile GC_word *addr, GC_word how_much )
00042  *   void GC_memory_barrier( )
00043  *   
00044  */  
00045 # ifdef THREADS
00046    void GC_noop1 GC_PROTO((word));
00047 #  ifdef PCR_OBSOLETE       /* Faster, but broken with multiple lwp's */
00048 #    include  "th/PCR_Th.h"
00049 #    include  "th/PCR_ThCrSec.h"
00050      extern struct PCR_Th_MLRep GC_allocate_ml;
00051 #    define DCL_LOCK_STATE  PCR_sigset_t GC_old_sig_mask
00052 #    define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml) 
00053 #    define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
00054 #    define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
00055 #    define FASTLOCK() PCR_ThCrSec_EnterSys()
00056      /* Here we cheat (a lot): */
00057 #        define FASTLOCK_SUCCEEDED() (*(int *)(&GC_allocate_ml) == 0)
00058               /* TRUE if nobody currently holds the lock */
00059 #    define FASTUNLOCK() PCR_ThCrSec_ExitSys()
00060 #  endif
00061 #  ifdef PCR
00062 #    include <base/PCR_Base.h>
00063 #    include <th/PCR_Th.h>
00064      extern PCR_Th_ML GC_allocate_ml;
00065 #    define DCL_LOCK_STATE \
00066         PCR_ERes GC_fastLockRes; PCR_sigset_t GC_old_sig_mask
00067 #    define LOCK() PCR_Th_ML_Acquire(&GC_allocate_ml)
00068 #    define UNLOCK() PCR_Th_ML_Release(&GC_allocate_ml)
00069 #    define FASTLOCK() (GC_fastLockRes = PCR_Th_ML_Try(&GC_allocate_ml))
00070 #    define FASTLOCK_SUCCEEDED() (GC_fastLockRes == PCR_ERes_okay)
00071 #    define FASTUNLOCK()  {\
00072         if( FASTLOCK_SUCCEEDED() ) PCR_Th_ML_Release(&GC_allocate_ml); }
00073 #  endif
00074 #  ifdef SRC_M3
00075      extern GC_word RT0u__inCritical;
00076 #    define LOCK() RT0u__inCritical++
00077 #    define UNLOCK() RT0u__inCritical--
00078 #  endif
00079 #  ifdef GC_SOLARIS_THREADS
00080 #    include <thread.h>
00081 #    include <signal.h>
00082      extern mutex_t GC_allocate_ml;
00083 #    define LOCK() mutex_lock(&GC_allocate_ml);
00084 #    define UNLOCK() mutex_unlock(&GC_allocate_ml);
00085 #  endif
00086 
00087 /* Try to define GC_TEST_AND_SET and a matching GC_CLEAR for spin lock       */
00088 /* acquisition and release.  We need this for correct operation of the       */
00089 /* incremental GC.                                             */
00090 #  ifdef __GNUC__
00091 #    if defined(I386)
00092        inline static int GC_test_and_set(volatile unsigned int *addr) {
00093          int oldval;
00094          /* Note: the "xchg" instruction does not need a "lock" prefix */
00095          __asm__ __volatile__("xchgl %0, %1"
00096               : "=r"(oldval), "=m"(*(addr))
00097               : "0"(1), "m"(*(addr)) : "memory");
00098          return oldval;
00099        }
00100 #      define GC_TEST_AND_SET_DEFINED
00101 #    endif
00102 #    if defined(IA64)
00103 #      if defined(__INTEL_COMPILER)
00104 #        include <ia64intrin.h>
00105 #      endif
00106        inline static int GC_test_and_set(volatile unsigned int *addr) {
00107          long oldval, n = 1;
00108 #      ifndef __INTEL_COMPILER
00109          __asm__ __volatile__("xchg4 %0=%1,%2"
00110               : "=r"(oldval), "=m"(*addr)
00111               : "r"(n), "1"(*addr) : "memory");
00112 #      else
00113          oldval = _InterlockedExchange(addr, n);
00114 #      endif
00115          return oldval;
00116        }
00117 #      define GC_TEST_AND_SET_DEFINED
00118        /* Should this handle post-increment addressing?? */
00119        inline static void GC_clear(volatile unsigned int *addr) {
00120 #      ifndef __INTEL_COMPILER
00121         __asm__ __volatile__("st4.rel %0=r0" : "=m" (*addr) : : "memory");
00122 #      else
00123        // there is no st4 but I can use xchg I hope
00124         _InterlockedExchange(addr, 0);
00125 #      endif
00126        }
00127 #      define GC_CLEAR_DEFINED
00128 #    endif
00129 #    ifdef SPARC
00130        inline static int GC_test_and_set(volatile unsigned int *addr) {
00131         int oldval;
00132 
00133         __asm__ __volatile__("ldstub %1,%0"
00134         : "=r"(oldval), "=m"(*addr)
00135         : "m"(*addr) : "memory");
00136         return oldval;
00137        }
00138 #      define GC_TEST_AND_SET_DEFINED
00139 #    endif
00140 #    ifdef M68K
00141        /* Contributed by Tony Mantler.  I'm not sure how well it was  */
00142        /* tested.                                              */
00143        inline static int GC_test_and_set(volatile unsigned int *addr) {
00144           char oldval; /* this must be no longer than 8 bits */
00145 
00146           /* The return value is semi-phony. */
00147           /* 'tas' sets bit 7 while the return */
00148           /* value pretends bit 0 was set */
00149           __asm__ __volatile__(
00150                  "tas %1@; sne %0; negb %0"
00151                  : "=d" (oldval)
00152                  : "a" (addr) : "memory");
00153           return oldval;
00154        }
00155 #      define GC_TEST_AND_SET_DEFINED
00156 #    endif
00157 #    if defined(POWERPC)
00158         inline static int GC_test_and_set(volatile unsigned int *addr) {
00159           int oldval;
00160           int temp = 1; /* locked value */
00161 
00162           __asm__ __volatile__(
00163                "1:\tlwarx %0,0,%3\n"   /* load and reserve               */
00164                "\tcmpwi %0, 0\n"       /* if load is                     */
00165                "\tbne 2f\n"            /*   non-zero, return already set */
00166                "\tstwcx. %2,0,%1\n"    /* else store conditional         */
00167                "\tbne- 1b\n"           /* retry if lost reservation      */
00168                "\tsync\n"              /* import barrier                 */
00169                "2:\t\n"                /* oldval is zero if we set       */
00170               : "=&r"(oldval), "=p"(addr)
00171               : "r"(temp), "1"(addr)
00172               : "cr0","memory");
00173           return oldval;
00174         }
00175 #     define GC_TEST_AND_SET_DEFINED
00176       inline static void GC_clear(volatile unsigned int *addr) {
00177        __asm__ __volatile__("lwsync" : : : "memory");
00178         *(addr) = 0;
00179       }
00180 #     define GC_CLEAR_DEFINED
00181 #    endif
00182 #    if defined(ALPHA) 
00183         inline static int GC_test_and_set(volatile unsigned int * addr)
00184         {
00185           unsigned long oldvalue;
00186           unsigned long temp;
00187 
00188           __asm__ __volatile__(
00189                              "1:     ldl_l %0,%1\n"
00190                              "       and %0,%3,%2\n"
00191                              "       bne %2,2f\n"
00192                              "       xor %0,%3,%0\n"
00193                              "       stl_c %0,%1\n"
00194 #      ifdef __ELF__
00195                              "       beq %0,3f\n"
00196 #      else
00197                              "       beq %0,1b\n"
00198 #      endif
00199                              "       mb\n"
00200                              "2:\n"
00201 #      ifdef __ELF__
00202                              ".section .text2,\"ax\"\n"
00203                              "3:     br 1b\n"
00204                              ".previous"
00205 #      endif
00206                              :"=&r" (temp), "=m" (*addr), "=&r" (oldvalue)
00207                              :"Ir" (1), "m" (*addr)
00208                           :"memory");
00209 
00210           return oldvalue;
00211         }
00212 #       define GC_TEST_AND_SET_DEFINED
00213         inline static void GC_clear(volatile unsigned int *addr) {
00214           __asm__ __volatile__("mb" : : : "memory");
00215           *(addr) = 0;
00216         }
00217 #       define GC_CLEAR_DEFINED
00218 #    endif /* ALPHA */
00219 #    ifdef ARM32
00220         inline static int GC_test_and_set(volatile unsigned int *addr) {
00221           int oldval;
00222           /* SWP on ARM is very similar to XCHG on x86.               */
00223          /* The first operand is the result, the second the value     */
00224          /* to be stored.  Both registers must be different from addr.       */
00225          /* Make the address operand an early clobber output so it     */
00226          /* doesn't overlap with the other operands.  The early clobber*/
00227          /* on oldval is neccessary to prevent the compiler allocating */
00228          /* them to the same register if they are both unused.        */
00229           __asm__ __volatile__("swp %0, %2, [%3]"
00230                              : "=&r"(oldval), "=&r"(addr)
00231                              : "r"(1), "1"(addr)
00232                              : "memory");
00233           return oldval;
00234         }
00235 #       define GC_TEST_AND_SET_DEFINED
00236 #    endif /* ARM32 */
00237 #    ifdef CRIS
00238         inline static int GC_test_and_set(volatile unsigned int *addr) {
00239          /* Ripped from linuxthreads/sysdeps/cris/pt-machine.h.       */
00240          /* Included with Hans-Peter Nilsson's permission.            */
00241          register unsigned long int ret;
00242 
00243          /* Note the use of a dummy output of *addr to expose the write.
00244           * The memory barrier is to stop *other* writes being moved past
00245           * this code.
00246           */
00247            __asm__ __volatile__("clearf\n"
00248                               "0:\n\t"
00249                              "movu.b [%2],%0\n\t"
00250                              "ax\n\t"
00251                              "move.b %3,[%2]\n\t"
00252                              "bwf 0b\n\t"
00253                              "clearf"
00254                              : "=&r" (ret), "=m" (*addr)
00255                              : "r" (addr), "r" ((int) 1), "m" (*addr)
00256                              : "memory");
00257            return ret;
00258         }
00259 #       define GC_TEST_AND_SET_DEFINED
00260 #    endif /* CRIS */
00261 #    ifdef S390
00262        inline static int GC_test_and_set(volatile unsigned int *addr) {
00263          int ret;
00264          __asm__ __volatile__ (
00265           "     l     %0,0(%2)\n"
00266           "0:   cs    %0,%1,0(%2)\n"
00267           "     jl    0b"
00268           : "=&d" (ret)
00269           : "d" (1), "a" (addr)
00270           : "cc", "memory");
00271          return ret;
00272        }
00273 #    endif
00274 #  endif /* __GNUC__ */
00275 #  if (defined(ALPHA) && !defined(__GNUC__))
00276 #    ifndef OSF1
00277        --> We currently assume that if gcc is not used, we are
00278        --> running under Tru64.
00279 #    endif
00280 #    include <machine/builtins.h>
00281 #    include <c_asm.h>
00282 #    define GC_test_and_set(addr) __ATOMIC_EXCH_LONG(addr, 1)
00283 #    define GC_TEST_AND_SET_DEFINED
00284 #    define GC_clear(addr) { asm("mb"); *(volatile unsigned *)addr = 0; }
00285 #    define GC_CLEAR_DEFINED
00286 #  endif
00287 #  if defined(MSWIN32)
00288 #    define GC_test_and_set(addr) InterlockedExchange((LPLONG)addr,1)
00289 #    define GC_TEST_AND_SET_DEFINED
00290 #  endif
00291 #  ifdef MIPS
00292 #    ifdef LINUX
00293 #      include <sys/tas.h>
00294 #      define GC_test_and_set(addr) _test_and_set((int *) addr,1)
00295 #      define GC_TEST_AND_SET_DEFINED
00296 #    elif __mips < 3 || !(defined (_ABIN32) || defined(_ABI64)) \
00297        || !defined(_COMPILER_VERSION) || _COMPILER_VERSION < 700
00298 #       ifdef __GNUC__
00299 #          define GC_test_and_set(addr) _test_and_set((void *)addr,1)
00300 #       else
00301 #          define GC_test_and_set(addr) test_and_set((void *)addr,1)
00302 #       endif
00303 #    else
00304 #       include <sgidefs.h>
00305 #       include <mutex.h>
00306 #       define GC_test_and_set(addr) __test_and_set32((void *)addr,1)
00307 #       define GC_clear(addr) __lock_release(addr);
00308 #       define GC_CLEAR_DEFINED
00309 #    endif
00310 #    define GC_TEST_AND_SET_DEFINED
00311 #  endif /* MIPS */
00312 #  if defined(_AIX)
00313 #    include <sys/atomic_op.h>
00314 #    if (defined(_POWER) || defined(_POWERPC)) 
00315 #      if defined(__GNUC__)  
00316          inline static void GC_memsync() {
00317            __asm__ __volatile__ ("sync" : : : "memory");
00318          }
00319 #      else
00320 #        ifndef inline
00321 #          define inline __inline
00322 #        endif
00323 #        pragma mc_func GC_memsync { \
00324            "7c0004ac" /* sync (same opcode used for dcs)*/ \
00325          }
00326 #      endif
00327 #    else 
00328 #    error dont know how to memsync
00329 #    endif
00330      inline static int GC_test_and_set(volatile unsigned int * addr) {
00331           int oldvalue = 0;
00332           if (compare_and_swap((void *)addr, &oldvalue, 1)) {
00333             GC_memsync();
00334             return 0;
00335           } else return 1;
00336      }
00337 #    define GC_TEST_AND_SET_DEFINED
00338      inline static void GC_clear(volatile unsigned int *addr) {
00339           GC_memsync();
00340           *(addr) = 0;
00341      }
00342 #    define GC_CLEAR_DEFINED
00343 
00344 #  endif
00345 #  if 0 /* defined(HP_PA) */
00346      /* The official recommendation seems to be to not use ldcw from  */
00347      /* user mode.  Since multithreaded incremental collection doesn't       */
00348      /* work anyway on HP_PA, this shouldn't be a major loss.         */
00349 
00350      /* "set" means 0 and "clear" means 1 here.         */
00351 #    define GC_test_and_set(addr) !GC_test_and_clear(addr);
00352 #    define GC_TEST_AND_SET_DEFINED
00353 #    define GC_clear(addr) GC_noop1((word)(addr)); *(volatile unsigned int *)addr = 1;
00354        /* The above needs a memory barrier! */
00355 #    define GC_CLEAR_DEFINED
00356 #  endif
00357 #  if defined(GC_TEST_AND_SET_DEFINED) && !defined(GC_CLEAR_DEFINED)
00358 #    ifdef __GNUC__
00359        inline static void GC_clear(volatile unsigned int *addr) {
00360          /* Try to discourage gcc from moving anything past this. */
00361          __asm__ __volatile__(" " : : : "memory");
00362          *(addr) = 0;
00363        }
00364 #    else
00365            /* The function call in the following should prevent the   */
00366            /* compiler from moving assignments to below the UNLOCK.   */
00367 #      define GC_clear(addr) GC_noop1((word)(addr)); \
00368                           *((volatile unsigned int *)(addr)) = 0;
00369 #    endif
00370 #    define GC_CLEAR_DEFINED
00371 #  endif /* !GC_CLEAR_DEFINED */
00372 
00373 #  if !defined(GC_TEST_AND_SET_DEFINED)
00374 #    define USE_PTHREAD_LOCKS
00375 #  endif
00376 
00377 #  if defined(GC_PTHREADS) && !defined(GC_SOLARIS_THREADS) \
00378       && !defined(GC_WIN32_THREADS)
00379 #    define NO_THREAD (pthread_t)(-1)
00380 #    include <pthread.h>
00381 #    if defined(PARALLEL_MARK) 
00382       /* We need compare-and-swap to update mark bits, where it's     */
00383       /* performance critical.  If USE_MARK_BYTES is defined, it is   */
00384       /* no longer needed for this purpose.  However we use it in     */
00385       /* either case to implement atomic fetch-and-add, though that's */
00386       /* less performance critical, and could perhaps be done with    */
00387       /* a lock.                                               */
00388 #     if defined(GENERIC_COMPARE_AND_SWAP)
00389        /* Probably not useful, except for debugging.    */
00390        /* We do use GENERIC_COMPARE_AND_SWAP on PA_RISC, but we       */
00391        /* minimize its use.                                    */
00392        extern pthread_mutex_t GC_compare_and_swap_lock;
00393 
00394        /* Note that if GC_word updates are not atomic, a concurrent   */
00395        /* reader should acquire GC_compare_and_swap_lock.  On         */
00396        /* currently supported platforms, such updates are atomic.     */
00397        extern GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00398                                           GC_word old, GC_word new_val);
00399 #     endif /* GENERIC_COMPARE_AND_SWAP */
00400 #     if defined(I386)
00401 #      if !defined(GENERIC_COMPARE_AND_SWAP)
00402          /* Returns TRUE if the comparison succeeded. */
00403          inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00404                                                  GC_word old,
00405                                                  GC_word new_val) 
00406          {
00407           char result;
00408           __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1"
00409               : "+m"(*(addr)), "=r"(result)
00410               : "r" (new_val), "a"(old) : "memory");
00411           return (GC_bool) result;
00412          }
00413 #      endif /* !GENERIC_COMPARE_AND_SWAP */
00414        inline static void GC_memory_barrier()
00415        {
00416         /* We believe the processor ensures at least processor */
00417         /* consistent ordering.  Thus a compiler barrier       */
00418         /* should suffice.                              */
00419          __asm__ __volatile__("" : : : "memory");
00420        }
00421 #     endif /* I386 */
00422 
00423 #     if defined(POWERPC)
00424 #      if !defined(GENERIC_COMPARE_AND_SWAP)
00425 #       if CPP_WORDSZ == 64
00426         /* Returns TRUE if the comparison succeeded. */
00427         inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00428             GC_word old, GC_word new_val) 
00429         {
00430             unsigned long result, dummy;
00431             __asm__ __volatile__(
00432                 "1:\tldarx %0,0,%5\n"
00433                   "\tcmpd %0,%4\n"
00434                   "\tbne  2f\n"
00435                   "\tstdcx. %3,0,%2\n"
00436                   "\tbne- 1b\n"
00437                   "\tsync\n"
00438                   "\tli %1, 1\n"
00439                   "\tb 3f\n"
00440                 "2:\tli %1, 0\n"
00441                 "3:\t\n"
00442                 :  "=&r" (dummy), "=r" (result), "=p" (addr)
00443                 :  "r" (new_val), "r" (old), "2"(addr)
00444                 : "cr0","memory");
00445             return (GC_bool) result;
00446         }
00447 #       else
00448         /* Returns TRUE if the comparison succeeded. */
00449         inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00450             GC_word old, GC_word new_val) 
00451         {
00452             int result, dummy;
00453             __asm__ __volatile__(
00454                 "1:\tlwarx %0,0,%5\n"
00455                   "\tcmpw %0,%4\n"
00456                   "\tbne  2f\n"
00457                   "\tstwcx. %3,0,%2\n"
00458                   "\tbne- 1b\n"
00459                   "\tsync\n"
00460                   "\tli %1, 1\n"
00461                   "\tb 3f\n"
00462                 "2:\tli %1, 0\n"
00463                 "3:\t\n"
00464                 :  "=&r" (dummy), "=r" (result), "=p" (addr)
00465                 :  "r" (new_val), "r" (old), "2"(addr)
00466                 : "cr0","memory");
00467             return (GC_bool) result;
00468         }
00469 #       endif
00470 #      endif /* !GENERIC_COMPARE_AND_SWAP */
00471         inline static void GC_memory_barrier()
00472         {
00473             __asm__ __volatile__("sync" : : : "memory");
00474         }
00475 #     endif /* POWERPC */
00476 
00477 #     if defined(IA64)
00478 #      if !defined(GENERIC_COMPARE_AND_SWAP)
00479          inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00480                                                  GC_word old, GC_word new_val) 
00481         {
00482          unsigned long oldval;
00483 #        if CPP_WORDSZ == 32
00484             __asm__ __volatile__(
00485                  "addp4 %0=0,%1\n"
00486                  "mov ar.ccv=%3 ;; cmpxchg4.rel %0=[%0],%2,ar.ccv"
00487                  : "=&r"(oldval)
00488                  : "r"(addr), "r"(new_val), "r"(old) : "memory");
00489 #        else
00490            __asm__ __volatile__(
00491                 "mov ar.ccv=%3 ;; cmpxchg8.rel %0=[%1],%2,ar.ccv"
00492                 : "=r"(oldval)
00493                 : "r"(addr), "r"(new_val), "r"(old) : "memory");
00494 #        endif
00495          return (oldval == old);
00496          }
00497 #      endif /* !GENERIC_COMPARE_AND_SWAP */
00498 #      if 0
00499        /* Shouldn't be needed; we use volatile stores instead. */
00500         inline static void GC_memory_barrier()
00501         {
00502           __asm__ __volatile__("mf" : : : "memory");
00503         }
00504 #      endif /* 0 */
00505 #     endif /* IA64 */
00506 #     if defined(ALPHA)
00507 #      if !defined(GENERIC_COMPARE_AND_SWAP)
00508 #        if defined(__GNUC__)
00509            inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00510                                                    GC_word old, GC_word new_val) 
00511           {
00512             unsigned long was_equal;
00513              unsigned long temp;
00514 
00515              __asm__ __volatile__(
00516                              "1:     ldq_l %0,%1\n"
00517                              "       cmpeq %0,%4,%2\n"
00518                           "      mov %3,%0\n"
00519                              "       beq %2,2f\n"
00520                              "       stq_c %0,%1\n"
00521                              "       beq %0,1b\n"
00522                              "2:\n"
00523                              "       mb\n"
00524                              :"=&r" (temp), "=m" (*addr), "=&r" (was_equal)
00525                              : "r" (new_val), "Ir" (old)
00526                           :"memory");
00527              return was_equal;
00528            }
00529 #        else /* !__GNUC__ */
00530            inline static GC_bool GC_compare_and_exchange(volatile GC_word *addr,
00531                                                    GC_word old, GC_word new_val) 
00532          {
00533            return __CMP_STORE_QUAD(addr, old, new_val, addr);
00534           }
00535 #        endif /* !__GNUC__ */
00536 #      endif /* !GENERIC_COMPARE_AND_SWAP */
00537 #      ifdef __GNUC__
00538          inline static void GC_memory_barrier()
00539          {
00540            __asm__ __volatile__("mb" : : : "memory");
00541          }
00542 #      else
00543 #       define GC_memory_barrier() asm("mb")
00544 #      endif /* !__GNUC__ */
00545 #     endif /* ALPHA */
00546 #     if defined(S390)
00547 #      if !defined(GENERIC_COMPARE_AND_SWAP)
00548          inline static GC_bool GC_compare_and_exchange(volatile C_word *addr,
00549                                          GC_word old, GC_word new_val)
00550          {
00551            int retval;
00552            __asm__ __volatile__ (
00553 #            ifndef __s390x__
00554                "     cs  %1,%2,0(%3)\n"
00555 #            else
00556                "     csg %1,%2,0(%3)\n"
00557 #            endif
00558              "     ipm %0\n"
00559              "     srl %0,28\n"
00560              : "=&d" (retval), "+d" (old)
00561              : "d" (new_val), "a" (addr)
00562              : "cc", "memory");
00563            return retval == 0;
00564          }
00565 #      endif
00566 #     endif
00567 #     if !defined(GENERIC_COMPARE_AND_SWAP)
00568         /* Returns the original value of *addr.  */
00569         inline static GC_word GC_atomic_add(volatile GC_word *addr,
00570                                        GC_word how_much)
00571         {
00572          GC_word old;
00573          do {
00574            old = *addr;
00575          } while (!GC_compare_and_exchange(addr, old, old+how_much));
00576           return old;
00577         }
00578 #     else /* GENERIC_COMPARE_AND_SWAP */
00579        /* So long as a GC_word can be atomically updated, it should   */
00580        /* be OK to read *addr without a lock.                         */
00581        extern GC_word GC_atomic_add(volatile GC_word *addr, GC_word how_much);
00582 #     endif /* GENERIC_COMPARE_AND_SWAP */
00583 
00584 #    endif /* PARALLEL_MARK */
00585 
00586 #    if !defined(THREAD_LOCAL_ALLOC) && !defined(USE_PTHREAD_LOCKS)
00587       /* In the THREAD_LOCAL_ALLOC case, the allocation lock tends to */
00588       /* be held for long periods, if it is held at all.  Thus spinning      */
00589       /* and sleeping for fixed periods are likely to result in       */
00590       /* significant wasted time.  We thus rely mostly on queued locks. */
00591 #     define USE_SPIN_LOCK
00592       extern volatile unsigned int GC_allocate_lock;
00593       extern void GC_lock(void);
00594        /* Allocation lock holder.  Only set if acquired by client through */
00595        /* GC_call_with_alloc_lock.                                */
00596 #     ifdef GC_ASSERTIONS
00597 #        define LOCK() \
00598               { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); \
00599                 SET_LOCK_HOLDER(); }
00600 #        define UNLOCK() \
00601               { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
00602                  GC_clear(&GC_allocate_lock); }
00603 #     else
00604 #        define LOCK() \
00605               { if (GC_test_and_set(&GC_allocate_lock)) GC_lock(); }
00606 #        define UNLOCK() \
00607               GC_clear(&GC_allocate_lock)
00608 #     endif /* !GC_ASSERTIONS */
00609 #     if 0
00610        /* Another alternative for OSF1 might be:        */
00611 #       include <sys/mman.h>
00612         extern msemaphore GC_allocate_semaphore;
00613 #       define LOCK() { if (msem_lock(&GC_allocate_semaphore, MSEM_IF_NOWAIT) \
00614                          != 0) GC_lock(); else GC_allocate_lock = 1; }
00615         /* The following is INCORRECT, since the memory model is too weak. */
00616        /* Is this true?  Presumably msem_unlock has the right semantics?  */
00617        /*            - HB                                         */
00618 #       define UNLOCK() { GC_allocate_lock = 0; \
00619                           msem_unlock(&GC_allocate_semaphore, 0); }
00620 #     endif /* 0 */
00621 #    else /* THREAD_LOCAL_ALLOC  || USE_PTHREAD_LOCKS */
00622 #      ifndef USE_PTHREAD_LOCKS
00623 #        define USE_PTHREAD_LOCKS
00624 #      endif
00625 #    endif /* THREAD_LOCAL_ALLOC */
00626 #   ifdef USE_PTHREAD_LOCKS
00627 #      include <pthread.h>
00628        extern pthread_mutex_t GC_allocate_ml;
00629 #      ifdef GC_ASSERTIONS
00630 #        define LOCK() \
00631               { GC_lock(); \
00632                 SET_LOCK_HOLDER(); }
00633 #        define UNLOCK() \
00634               { GC_ASSERT(I_HOLD_LOCK()); UNSET_LOCK_HOLDER(); \
00635                  pthread_mutex_unlock(&GC_allocate_ml); }
00636 #      else /* !GC_ASSERTIONS */
00637 #        if defined(NO_PTHREAD_TRYLOCK)
00638 #          define LOCK() GC_lock();
00639 #        else /* !defined(NO_PTHREAD_TRYLOCK) */
00640 #        define LOCK() \
00641           { if (0 != pthread_mutex_trylock(&GC_allocate_ml)) GC_lock(); }
00642 #        endif
00643 #        define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
00644 #      endif /* !GC_ASSERTIONS */
00645 #   endif /* USE_PTHREAD_LOCKS */
00646 #   define SET_LOCK_HOLDER() GC_lock_holder = pthread_self()
00647 #   define UNSET_LOCK_HOLDER() GC_lock_holder = NO_THREAD
00648 #   define I_HOLD_LOCK() (pthread_equal(GC_lock_holder, pthread_self()))
00649     extern VOLATILE GC_bool GC_collecting;
00650 #   define ENTER_GC() GC_collecting = 1;
00651 #   define EXIT_GC() GC_collecting = 0;
00652     extern void GC_lock(void);
00653     extern pthread_t GC_lock_holder;
00654 #   ifdef GC_ASSERTIONS
00655       extern pthread_t GC_mark_lock_holder;
00656 #   endif
00657 #  endif /* GC_PTHREADS with linux_threads.c implementation */
00658 #  if defined(GC_WIN32_THREADS)
00659 #    if defined(GC_PTHREADS)
00660 #      include <pthread.h>
00661        extern pthread_mutex_t GC_allocate_ml;
00662 #      define LOCK()   pthread_mutex_lock(&GC_allocate_ml)
00663 #      define UNLOCK() pthread_mutex_unlock(&GC_allocate_ml)
00664 #    else
00665 #      include <windows.h>
00666        GC_API CRITICAL_SECTION GC_allocate_ml;
00667 #      define LOCK() EnterCriticalSection(&GC_allocate_ml);
00668 #      define UNLOCK() LeaveCriticalSection(&GC_allocate_ml);
00669 #    endif
00670 #  endif
00671 #  ifndef SET_LOCK_HOLDER
00672 #      define SET_LOCK_HOLDER()
00673 #      define UNSET_LOCK_HOLDER()
00674 #      define I_HOLD_LOCK() FALSE
00675               /* Used on platforms were locks can be reacquired,      */
00676               /* so it doesn't matter if we lie.               */
00677 #  endif
00678 # else /* !THREADS */
00679 #    define LOCK()
00680 #    define UNLOCK()
00681 # endif /* !THREADS */
00682 # ifndef SET_LOCK_HOLDER
00683 #   define SET_LOCK_HOLDER()
00684 #   define UNSET_LOCK_HOLDER()
00685 #   define I_HOLD_LOCK() FALSE
00686               /* Used on platforms were locks can be reacquired,      */
00687               /* so it doesn't matter if we lie.               */
00688 # endif
00689 # ifndef ENTER_GC
00690 #   define ENTER_GC()
00691 #   define EXIT_GC()
00692 # endif
00693 
00694 # ifndef DCL_LOCK_STATE
00695 #   define DCL_LOCK_STATE
00696 # endif
00697 # ifndef FASTLOCK
00698 #   define FASTLOCK() LOCK()
00699 #   define FASTLOCK_SUCCEEDED() TRUE
00700 #   define FASTUNLOCK() UNLOCK()
00701 # endif
00702 
00703 #endif /* GC_LOCKS_H */