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libdrm  2.4.37
radeon_surface.h
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00001 /*
00002  * Copyright © 2011 Red Hat All Rights Reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining
00005  * a copy of this software and associated documentation files (the
00006  * "Software"), to deal in the Software without restriction, including
00007  * without limitation the rights to use, copy, modify, merge, publish,
00008  * distribute, sub license, and/or sell copies of the Software, and to
00009  * permit persons to whom the Software is furnished to do so, subject to
00010  * the following conditions:
00011  *
00012  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
00013  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
00014  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
00015  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
00016  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00017  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00018  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
00019  * USE OR OTHER DEALINGS IN THE SOFTWARE.
00020  *
00021  * The above copyright notice and this permission notice (including the
00022  * next paragraph) shall be included in all copies or substantial portions
00023  * of the Software.
00024  */
00025 /*
00026  * Authors:
00027  *      Jérôme Glisse <jglisse@redhat.com>
00028  */
00029 #ifndef RADEON_SURFACE_H
00030 #define RADEON_SURFACE_H
00031 
00032 /* Note :
00033  *
00034  * For texture array, the n layer are stored one after the other within each
00035  * mipmap level. 0 value for field than can be hint is always valid.
00036  */
00037 
00038 #define RADEON_SURF_MAX_LEVEL                   32
00039 
00040 #define RADEON_SURF_TYPE_MASK                   0xFF
00041 #define RADEON_SURF_TYPE_SHIFT                  0
00042 #define     RADEON_SURF_TYPE_1D                     0
00043 #define     RADEON_SURF_TYPE_2D                     1
00044 #define     RADEON_SURF_TYPE_3D                     2
00045 #define     RADEON_SURF_TYPE_CUBEMAP                3
00046 #define     RADEON_SURF_TYPE_1D_ARRAY               4
00047 #define     RADEON_SURF_TYPE_2D_ARRAY               5
00048 #define RADEON_SURF_MODE_MASK                   0xFF
00049 #define RADEON_SURF_MODE_SHIFT                  8
00050 #define     RADEON_SURF_MODE_LINEAR                 0
00051 #define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
00052 #define     RADEON_SURF_MODE_1D                     2
00053 #define     RADEON_SURF_MODE_2D                     3
00054 #define RADEON_SURF_SCANOUT                     (1 << 16)
00055 #define RADEON_SURF_ZBUFFER                     (1 << 17)
00056 #define RADEON_SURF_SBUFFER                     (1 << 18)
00057 
00058 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
00059 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
00060 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
00061 
00062 /* first field up to mode need to match r6 struct so that we can reuse
00063  * same function for linear & linear aligned
00064  */
00065 struct radeon_surface_level {
00066     uint64_t                    offset;
00067     uint64_t                    slice_size;
00068     uint32_t                    npix_x;
00069     uint32_t                    npix_y;
00070     uint32_t                    npix_z;
00071     uint32_t                    nblk_x;
00072     uint32_t                    nblk_y;
00073     uint32_t                    nblk_z;
00074     uint32_t                    pitch_bytes;
00075     uint32_t                    mode;
00076 };
00077 
00078 struct radeon_surface {
00079     uint32_t                    npix_x;
00080     uint32_t                    npix_y;
00081     uint32_t                    npix_z;
00082     uint32_t                    blk_w;
00083     uint32_t                    blk_h;
00084     uint32_t                    blk_d;
00085     uint32_t                    array_size;
00086     uint32_t                    last_level;
00087     uint32_t                    bpe;
00088     uint32_t                    nsamples;
00089     uint32_t                    flags;
00090     /* Following is updated/fill by the allocator. It's allowed to
00091      * set some of the value but they are use as hint and can be
00092      * overridden (things lile bankw/bankh on evergreen for
00093      * instance).
00094      */
00095     uint64_t                    bo_size;
00096     uint64_t                    bo_alignment;
00097     /* apply to eg */
00098     uint32_t                    bankw;
00099     uint32_t                    bankh;
00100     uint32_t                    mtilea;
00101     uint32_t                    tile_split;
00102     uint32_t                    stencil_tile_split;
00103     uint64_t                    stencil_offset;
00104     struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
00105 };
00106 
00107 struct radeon_surface_manager *radeon_surface_manager_new(int fd);
00108 void radeon_surface_manager_free(struct radeon_surface_manager *surf_man);
00109 int radeon_surface_init(struct radeon_surface_manager *surf_man,
00110                         struct radeon_surface *surf);
00111 int radeon_surface_best(struct radeon_surface_manager *surf_man,
00112                         struct radeon_surface *surf);
00113 
00114 #endif