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libdrm  2.4.37
radeon_drm.h
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00001 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
00002  *
00003  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
00004  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
00005  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
00006  * All rights reserved.
00007  *
00008  * Permission is hereby granted, free of charge, to any person obtaining a
00009  * copy of this software and associated documentation files (the "Software"),
00010  * to deal in the Software without restriction, including without limitation
00011  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00012  * and/or sell copies of the Software, and to permit persons to whom the
00013  * Software is furnished to do so, subject to the following conditions:
00014  *
00015  * The above copyright notice and this permission notice (including the next
00016  * paragraph) shall be included in all copies or substantial portions of the
00017  * Software.
00018  *
00019  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00020  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00021  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
00022  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
00023  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00024  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
00025  * DEALINGS IN THE SOFTWARE.
00026  *
00027  * Authors:
00028  *    Kevin E. Martin <martin@valinux.com>
00029  *    Gareth Hughes <gareth@valinux.com>
00030  *    Keith Whitwell <keith@tungstengraphics.com>
00031  */
00032 
00033 #ifndef __RADEON_DRM_H__
00034 #define __RADEON_DRM_H__
00035 
00036 #include "drm.h"
00037 
00038 /* WARNING: If you change any of these defines, make sure to change the
00039  * defines in the X server file (radeon_sarea.h)
00040  */
00041 #ifndef __RADEON_SAREA_DEFINES__
00042 #define __RADEON_SAREA_DEFINES__
00043 
00044 /* Old style state flags, required for sarea interface (1.1 and 1.2
00045  * clears) and 1.2 drm_vertex2 ioctl.
00046  */
00047 #define RADEON_UPLOAD_CONTEXT             0x00000001
00048 #define RADEON_UPLOAD_VERTFMT             0x00000002
00049 #define RADEON_UPLOAD_LINE         0x00000004
00050 #define RADEON_UPLOAD_BUMPMAP             0x00000008
00051 #define RADEON_UPLOAD_MASKS        0x00000010
00052 #define RADEON_UPLOAD_VIEWPORT            0x00000020
00053 #define RADEON_UPLOAD_SETUP        0x00000040
00054 #define RADEON_UPLOAD_TCL          0x00000080
00055 #define RADEON_UPLOAD_MISC         0x00000100
00056 #define RADEON_UPLOAD_TEX0         0x00000200
00057 #define RADEON_UPLOAD_TEX1         0x00000400
00058 #define RADEON_UPLOAD_TEX2         0x00000800
00059 #define RADEON_UPLOAD_TEX0IMAGES   0x00001000
00060 #define RADEON_UPLOAD_TEX1IMAGES   0x00002000
00061 #define RADEON_UPLOAD_TEX2IMAGES   0x00004000
00062 #define RADEON_UPLOAD_CLIPRECTS           0x00008000    /* handled client-side */
00063 #define RADEON_REQUIRE_QUIESCENCE  0x00010000
00064 #define RADEON_UPLOAD_ZBIAS        0x00020000    /* version 1.2 and newer */
00065 #define RADEON_UPLOAD_ALL          0x003effff
00066 #define RADEON_UPLOAD_CONTEXT_ALL       0x003e01ff
00067 
00068 /* New style per-packet identifiers for use in cmd_buffer ioctl with
00069  * the RADEON_EMIT_PACKET command.  Comments relate new packets to old
00070  * state bits and the packet size:
00071  */
00072 #define RADEON_EMIT_PP_MISC                         0   /* context/7 */
00073 #define RADEON_EMIT_PP_CNTL                         1   /* context/3 */
00074 #define RADEON_EMIT_RB3D_COLORPITCH                 2   /* context/1 */
00075 #define RADEON_EMIT_RE_LINE_PATTERN                 3   /* line/2 */
00076 #define RADEON_EMIT_SE_LINE_WIDTH                   4   /* line/1 */
00077 #define RADEON_EMIT_PP_LUM_MATRIX                   5   /* bumpmap/1 */
00078 #define RADEON_EMIT_PP_ROT_MATRIX_0                 6   /* bumpmap/2 */
00079 #define RADEON_EMIT_RB3D_STENCILREFMASK             7   /* masks/3 */
00080 #define RADEON_EMIT_SE_VPORT_XSCALE                 8   /* viewport/6 */
00081 #define RADEON_EMIT_SE_CNTL                         9   /* setup/2 */
00082 #define RADEON_EMIT_SE_CNTL_STATUS                  10  /* setup/1 */
00083 #define RADEON_EMIT_RE_MISC                         11  /* misc/1 */
00084 #define RADEON_EMIT_PP_TXFILTER_0                   12  /* tex0/6 */
00085 #define RADEON_EMIT_PP_BORDER_COLOR_0               13  /* tex0/1 */
00086 #define RADEON_EMIT_PP_TXFILTER_1                   14  /* tex1/6 */
00087 #define RADEON_EMIT_PP_BORDER_COLOR_1               15  /* tex1/1 */
00088 #define RADEON_EMIT_PP_TXFILTER_2                   16  /* tex2/6 */
00089 #define RADEON_EMIT_PP_BORDER_COLOR_2               17  /* tex2/1 */
00090 #define RADEON_EMIT_SE_ZBIAS_FACTOR                 18  /* zbias/2 */
00091 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT           19  /* tcl/11 */
00092 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20  /* material/17 */
00093 #define R200_EMIT_PP_TXCBLEND_0                     21  /* tex0/4 */
00094 #define R200_EMIT_PP_TXCBLEND_1                     22  /* tex1/4 */
00095 #define R200_EMIT_PP_TXCBLEND_2                     23  /* tex2/4 */
00096 #define R200_EMIT_PP_TXCBLEND_3                     24  /* tex3/4 */
00097 #define R200_EMIT_PP_TXCBLEND_4                     25  /* tex4/4 */
00098 #define R200_EMIT_PP_TXCBLEND_5                     26  /* tex5/4 */
00099 #define R200_EMIT_PP_TXCBLEND_6                     27  /* /4 */
00100 #define R200_EMIT_PP_TXCBLEND_7                     28  /* /4 */
00101 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0             29  /* tcl/7 */
00102 #define R200_EMIT_TFACTOR_0                         30  /* tf/7 */
00103 #define R200_EMIT_VTX_FMT_0                         31  /* vtx/5 */
00104 #define R200_EMIT_VAP_CTL                           32  /* vap/1 */
00105 #define R200_EMIT_MATRIX_SELECT_0                   33  /* msl/5 */
00106 #define R200_EMIT_TEX_PROC_CTL_2                    34  /* tcg/5 */
00107 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL            35  /* tcl/1 */
00108 #define R200_EMIT_PP_TXFILTER_0                     36  /* tex0/6 */
00109 #define R200_EMIT_PP_TXFILTER_1                     37  /* tex1/6 */
00110 #define R200_EMIT_PP_TXFILTER_2                     38  /* tex2/6 */
00111 #define R200_EMIT_PP_TXFILTER_3                     39  /* tex3/6 */
00112 #define R200_EMIT_PP_TXFILTER_4                     40  /* tex4/6 */
00113 #define R200_EMIT_PP_TXFILTER_5                     41  /* tex5/6 */
00114 #define R200_EMIT_PP_TXOFFSET_0                     42  /* tex0/1 */
00115 #define R200_EMIT_PP_TXOFFSET_1                     43  /* tex1/1 */
00116 #define R200_EMIT_PP_TXOFFSET_2                     44  /* tex2/1 */
00117 #define R200_EMIT_PP_TXOFFSET_3                     45  /* tex3/1 */
00118 #define R200_EMIT_PP_TXOFFSET_4                     46  /* tex4/1 */
00119 #define R200_EMIT_PP_TXOFFSET_5                     47  /* tex5/1 */
00120 #define R200_EMIT_VTE_CNTL                          48  /* vte/1 */
00121 #define R200_EMIT_OUTPUT_VTX_COMP_SEL               49  /* vtx/1 */
00122 #define R200_EMIT_PP_TAM_DEBUG3                     50  /* tam/1 */
00123 #define R200_EMIT_PP_CNTL_X                         51  /* cst/1 */
00124 #define R200_EMIT_RB3D_DEPTHXY_OFFSET               52  /* cst/1 */
00125 #define R200_EMIT_RE_AUX_SCISSOR_CNTL               53  /* cst/1 */
00126 #define R200_EMIT_RE_SCISSOR_TL_0                   54  /* cst/2 */
00127 #define R200_EMIT_RE_SCISSOR_TL_1                   55  /* cst/2 */
00128 #define R200_EMIT_RE_SCISSOR_TL_2                   56  /* cst/2 */
00129 #define R200_EMIT_SE_VAP_CNTL_STATUS                57  /* cst/1 */
00130 #define R200_EMIT_SE_VTX_STATE_CNTL                 58  /* cst/1 */
00131 #define R200_EMIT_RE_POINTSIZE                      59  /* cst/1 */
00132 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0       60  /* cst/4 */
00133 #define R200_EMIT_PP_CUBIC_FACES_0                  61
00134 #define R200_EMIT_PP_CUBIC_OFFSETS_0                62
00135 #define R200_EMIT_PP_CUBIC_FACES_1                  63
00136 #define R200_EMIT_PP_CUBIC_OFFSETS_1                64
00137 #define R200_EMIT_PP_CUBIC_FACES_2                  65
00138 #define R200_EMIT_PP_CUBIC_OFFSETS_2                66
00139 #define R200_EMIT_PP_CUBIC_FACES_3                  67
00140 #define R200_EMIT_PP_CUBIC_OFFSETS_3                68
00141 #define R200_EMIT_PP_CUBIC_FACES_4                  69
00142 #define R200_EMIT_PP_CUBIC_OFFSETS_4                70
00143 #define R200_EMIT_PP_CUBIC_FACES_5                  71
00144 #define R200_EMIT_PP_CUBIC_OFFSETS_5                72
00145 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
00146 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
00147 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
00148 #define R200_EMIT_RB3D_BLENDCOLOR                   76
00149 #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
00150 #define RADEON_EMIT_PP_CUBIC_FACES_0                78
00151 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
00152 #define RADEON_EMIT_PP_CUBIC_FACES_1                80
00153 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
00154 #define RADEON_EMIT_PP_CUBIC_FACES_2                82
00155 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
00156 #define R200_EMIT_PP_TRI_PERF_CNTL                  84
00157 #define R200_EMIT_PP_AFS_0                          85
00158 #define R200_EMIT_PP_AFS_1                          86
00159 #define R200_EMIT_ATF_TFACTOR                       87
00160 #define R200_EMIT_PP_TXCTLALL_0                     88
00161 #define R200_EMIT_PP_TXCTLALL_1                     89
00162 #define R200_EMIT_PP_TXCTLALL_2                     90
00163 #define R200_EMIT_PP_TXCTLALL_3                     91
00164 #define R200_EMIT_PP_TXCTLALL_4                     92
00165 #define R200_EMIT_PP_TXCTLALL_5                     93
00166 #define R200_EMIT_VAP_PVS_CNTL                      94
00167 #define RADEON_MAX_STATE_PACKETS                    95
00168 
00169 /* Commands understood by cmd_buffer ioctl.  More can be added but
00170  * obviously these can't be removed or changed:
00171  */
00172 #define RADEON_CMD_PACKET      1   /* emit one of the register packets above */
00173 #define RADEON_CMD_SCALARS     2   /* emit scalar data */
00174 #define RADEON_CMD_VECTORS     3   /* emit vector data */
00175 #define RADEON_CMD_DMA_DISCARD 4   /* discard current dma buf */
00176 #define RADEON_CMD_PACKET3     5   /* emit hw packet */
00177 #define RADEON_CMD_PACKET3_CLIP 6  /* emit hw packet wrapped in cliprects */
00178 #define RADEON_CMD_SCALARS2     7  /* r200 stopgap */
00179 #define RADEON_CMD_WAIT         8  /* emit hw wait commands -- note:
00180                                     *  doesn't make the cpu wait, just
00181                                     *  the graphics hardware */
00182 #define RADEON_CMD_VECLINEAR       9       /* another r200 stopgap */
00183 
00184 typedef union {
00185        int i;
00186        struct {
00187               unsigned char cmd_type, pad0, pad1, pad2;
00188        } header;
00189        struct {
00190               unsigned char cmd_type, packet_id, pad0, pad1;
00191        } packet;
00192        struct {
00193               unsigned char cmd_type, offset, stride, count;
00194        } scalars;
00195        struct {
00196               unsigned char cmd_type, offset, stride, count;
00197        } vectors;
00198        struct {
00199               unsigned char cmd_type, addr_lo, addr_hi, count;
00200        } veclinear;
00201        struct {
00202               unsigned char cmd_type, buf_idx, pad0, pad1;
00203        } dma;
00204        struct {
00205               unsigned char cmd_type, flags, pad0, pad1;
00206        } wait;
00207 } drm_radeon_cmd_header_t;
00208 
00209 #define RADEON_WAIT_2D  0x1
00210 #define RADEON_WAIT_3D  0x2
00211 
00212 /* Allowed parameters for R300_CMD_PACKET3
00213  */
00214 #define R300_CMD_PACKET3_CLEAR            0
00215 #define R300_CMD_PACKET3_RAW              1
00216 
00217 /* Commands understood by cmd_buffer ioctl for R300.
00218  * The interface has not been stabilized, so some of these may be removed
00219  * and eventually reordered before stabilization.
00220  */
00221 #define R300_CMD_PACKET0           1
00222 #define R300_CMD_VPU               2      /* emit vertex program upload */
00223 #define R300_CMD_PACKET3           3      /* emit a packet3 */
00224 #define R300_CMD_END3D                    4      /* emit sequence ending 3d rendering */
00225 #define R300_CMD_CP_DELAY          5
00226 #define R300_CMD_DMA_DISCARD              6
00227 #define R300_CMD_WAIT                     7
00228 #      define R300_WAIT_2D         0x1
00229 #      define R300_WAIT_3D         0x2
00230 /* these two defines are DOING IT WRONG - however
00231  * we have userspace which relies on using these.
00232  * The wait interface is backwards compat new 
00233  * code should use the NEW_WAIT defines below
00234  * THESE ARE NOT BIT FIELDS
00235  */
00236 #      define R300_WAIT_2D_CLEAN   0x3
00237 #      define R300_WAIT_3D_CLEAN   0x4
00238 
00239 #      define R300_NEW_WAIT_2D_3D  0x3
00240 #      define R300_NEW_WAIT_2D_2D_CLEAN   0x4
00241 #      define R300_NEW_WAIT_3D_3D_CLEAN   0x6
00242 #      define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN     0x8
00243 
00244 #define R300_CMD_SCRATCH           8
00245 #define R300_CMD_R500FP                 9
00246 
00247 typedef union {
00248        unsigned int u;
00249        struct {
00250               unsigned char cmd_type, pad0, pad1, pad2;
00251        } header;
00252        struct {
00253               unsigned char cmd_type, count, reglo, reghi;
00254        } packet0;
00255        struct {
00256               unsigned char cmd_type, count, adrlo, adrhi;
00257        } vpu;
00258        struct {
00259               unsigned char cmd_type, packet, pad0, pad1;
00260        } packet3;
00261        struct {
00262               unsigned char cmd_type, packet;
00263               unsigned short count;       /* amount of packet2 to emit */
00264        } delay;
00265        struct {
00266               unsigned char cmd_type, buf_idx, pad0, pad1;
00267        } dma;
00268        struct {
00269               unsigned char cmd_type, flags, pad0, pad1;
00270        } wait;
00271        struct {
00272               unsigned char cmd_type, reg, n_bufs, flags;
00273        } scratch;
00274        struct {
00275               unsigned char cmd_type, count, adrlo, adrhi_flags;
00276        } r500fp;
00277 } drm_r300_cmd_header_t;
00278 
00279 #define RADEON_FRONT               0x1
00280 #define RADEON_BACK                0x2
00281 #define RADEON_DEPTH               0x4
00282 #define RADEON_STENCIL                    0x8
00283 #define RADEON_CLEAR_FASTZ         0x80000000
00284 #define RADEON_USE_HIERZ           0x40000000
00285 #define RADEON_USE_COMP_ZBUF              0x20000000
00286 
00287 #define R500FP_CONSTANT_TYPE  (1 << 1)
00288 #define R500FP_CONSTANT_CLAMP (1 << 2)
00289 
00290 /* Primitive types
00291  */
00292 #define RADEON_POINTS                     0x1
00293 #define RADEON_LINES               0x2
00294 #define RADEON_LINE_STRIP          0x3
00295 #define RADEON_TRIANGLES           0x4
00296 #define RADEON_TRIANGLE_FAN        0x5
00297 #define RADEON_TRIANGLE_STRIP             0x6
00298 
00299 /* Vertex/indirect buffer size
00300  */
00301 #define RADEON_BUFFER_SIZE         65536
00302 
00303 /* Byte offsets for indirect buffer data
00304  */
00305 #define RADEON_INDEX_PRIM_OFFSET   20
00306 
00307 #define RADEON_SCRATCH_REG_OFFSET  32
00308 
00309 #define R600_SCRATCH_REG_OFFSET         256
00310 
00311 #define RADEON_NR_SAREA_CLIPRECTS  12
00312 
00313 /* There are 2 heaps (local/GART).  Each region within a heap is a
00314  * minimum of 64k, and there are at most 64 of them per heap.
00315  */
00316 #define RADEON_LOCAL_TEX_HEAP             0
00317 #define RADEON_GART_TEX_HEAP              1
00318 #define RADEON_NR_TEX_HEAPS        2
00319 #define RADEON_NR_TEX_REGIONS             64
00320 #define RADEON_LOG_TEX_GRANULARITY 16
00321 
00322 #define RADEON_MAX_TEXTURE_LEVELS  12
00323 #define RADEON_MAX_TEXTURE_UNITS   3
00324 
00325 #define RADEON_MAX_SURFACES        8
00326 
00327 /* Blits have strict offset rules.  All blit offset must be aligned on
00328  * a 1K-byte boundary.
00329  */
00330 #define RADEON_OFFSET_SHIFT             10
00331 #define RADEON_OFFSET_ALIGN             (1 << RADEON_OFFSET_SHIFT)
00332 #define RADEON_OFFSET_MASK              (RADEON_OFFSET_ALIGN - 1)
00333 
00334 #endif                      /* __RADEON_SAREA_DEFINES__ */
00335 
00336 typedef struct {
00337        unsigned int red;
00338        unsigned int green;
00339        unsigned int blue;
00340        unsigned int alpha;
00341 } radeon_color_regs_t;
00342 
00343 typedef struct {
00344        /* Context state */
00345        unsigned int pp_misc;       /* 0x1c14 */
00346        unsigned int pp_fog_color;
00347        unsigned int re_solid_color;
00348        unsigned int rb3d_blendcntl;
00349        unsigned int rb3d_depthoffset;
00350        unsigned int rb3d_depthpitch;
00351        unsigned int rb3d_zstencilcntl;
00352 
00353        unsigned int pp_cntl;       /* 0x1c38 */
00354        unsigned int rb3d_cntl;
00355        unsigned int rb3d_coloroffset;
00356        unsigned int re_width_height;
00357        unsigned int rb3d_colorpitch;
00358        unsigned int se_cntl;
00359 
00360        /* Vertex format state */
00361        unsigned int se_coord_fmt;  /* 0x1c50 */
00362 
00363        /* Line state */
00364        unsigned int re_line_pattern;      /* 0x1cd0 */
00365        unsigned int re_line_state;
00366 
00367        unsigned int se_line_width; /* 0x1db8 */
00368 
00369        /* Bumpmap state */
00370        unsigned int pp_lum_matrix; /* 0x1d00 */
00371 
00372        unsigned int pp_rot_matrix_0;      /* 0x1d58 */
00373        unsigned int pp_rot_matrix_1;
00374 
00375        /* Mask state */
00376        unsigned int rb3d_stencilrefmask;  /* 0x1d7c */
00377        unsigned int rb3d_ropcntl;
00378        unsigned int rb3d_planemask;
00379 
00380        /* Viewport state */
00381        unsigned int se_vport_xscale;      /* 0x1d98 */
00382        unsigned int se_vport_xoffset;
00383        unsigned int se_vport_yscale;
00384        unsigned int se_vport_yoffset;
00385        unsigned int se_vport_zscale;
00386        unsigned int se_vport_zoffset;
00387 
00388        /* Setup state */
00389        unsigned int se_cntl_status;       /* 0x2140 */
00390 
00391        /* Misc state */
00392        unsigned int re_top_left;   /* 0x26c0 */
00393        unsigned int re_misc;
00394 } drm_radeon_context_regs_t;
00395 
00396 typedef struct {
00397        /* Zbias state */
00398        unsigned int se_zbias_factor;      /* 0x1dac */
00399        unsigned int se_zbias_constant;
00400 } drm_radeon_context2_regs_t;
00401 
00402 /* Setup registers for each texture unit
00403  */
00404 typedef struct {
00405        unsigned int pp_txfilter;
00406        unsigned int pp_txformat;
00407        unsigned int pp_txoffset;
00408        unsigned int pp_txcblend;
00409        unsigned int pp_txablend;
00410        unsigned int pp_tfactor;
00411        unsigned int pp_border_color;
00412 } drm_radeon_texture_regs_t;
00413 
00414 typedef struct {
00415        unsigned int start;
00416        unsigned int finish;
00417        unsigned int prim:8;
00418        unsigned int stateidx:8;
00419        unsigned int numverts:16;   /* overloaded as offset/64 for elt prims */
00420        unsigned int vc_format;     /* vertex format */
00421 } drm_radeon_prim_t;
00422 
00423 typedef struct {
00424        drm_radeon_context_regs_t context;
00425        drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
00426        drm_radeon_context2_regs_t context2;
00427        unsigned int dirty;
00428 } drm_radeon_state_t;
00429 
00430 typedef struct {
00431        /* The channel for communication of state information to the
00432         * kernel on firing a vertex buffer with either of the
00433         * obsoleted vertex/index ioctls.
00434         */
00435        drm_radeon_context_regs_t context_state;
00436        drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
00437        unsigned int dirty;
00438        unsigned int vertsize;
00439        unsigned int vc_format;
00440 
00441        /* The current cliprects, or a subset thereof.
00442         */
00443        struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
00444        unsigned int nbox;
00445 
00446        /* Counters for client-side throttling of rendering clients.
00447         */
00448        unsigned int last_frame;
00449        unsigned int last_dispatch;
00450        unsigned int last_clear;
00451 
00452        struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
00453                                                  1];
00454        unsigned int tex_age[RADEON_NR_TEX_HEAPS];
00455        int ctx_owner;
00456        int pfState;         /* number of 3d windows (0,1,2ormore) */
00457        int pfCurrentPage;   /* which buffer is being displayed? */
00458        int crtc2_base;             /* CRTC2 frame offset */
00459        int tiling_enabled;  /* set by drm, read by 2d + 3d clients */
00460 } drm_radeon_sarea_t;
00461 
00462 /* WARNING: If you change any of these defines, make sure to change the
00463  * defines in the Xserver file (xf86drmRadeon.h)
00464  *
00465  * KW: actually it's illegal to change any of this (backwards compatibility).
00466  */
00467 
00468 /* Radeon specific ioctls
00469  * The device specific ioctl range is 0x40 to 0x79.
00470  */
00471 #define DRM_RADEON_CP_INIT    0x00
00472 #define DRM_RADEON_CP_START   0x01
00473 #define DRM_RADEON_CP_STOP    0x02
00474 #define DRM_RADEON_CP_RESET   0x03
00475 #define DRM_RADEON_CP_IDLE    0x04
00476 #define DRM_RADEON_RESET      0x05
00477 #define DRM_RADEON_FULLSCREEN 0x06
00478 #define DRM_RADEON_SWAP       0x07
00479 #define DRM_RADEON_CLEAR      0x08
00480 #define DRM_RADEON_VERTEX     0x09
00481 #define DRM_RADEON_INDICES    0x0A
00482 #define DRM_RADEON_NOT_USED
00483 #define DRM_RADEON_STIPPLE    0x0C
00484 #define DRM_RADEON_INDIRECT   0x0D
00485 #define DRM_RADEON_TEXTURE    0x0E
00486 #define DRM_RADEON_VERTEX2    0x0F
00487 #define DRM_RADEON_CMDBUF     0x10
00488 #define DRM_RADEON_GETPARAM   0x11
00489 #define DRM_RADEON_FLIP       0x12
00490 #define DRM_RADEON_ALLOC      0x13
00491 #define DRM_RADEON_FREE       0x14
00492 #define DRM_RADEON_INIT_HEAP  0x15
00493 #define DRM_RADEON_IRQ_EMIT   0x16
00494 #define DRM_RADEON_IRQ_WAIT   0x17
00495 #define DRM_RADEON_CP_RESUME  0x18
00496 #define DRM_RADEON_SETPARAM   0x19
00497 #define DRM_RADEON_SURF_ALLOC 0x1a
00498 #define DRM_RADEON_SURF_FREE  0x1b
00499 /* KMS ioctl */
00500 #define DRM_RADEON_GEM_INFO        0x1c
00501 #define DRM_RADEON_GEM_CREATE             0x1d
00502 #define DRM_RADEON_GEM_MMAP        0x1e
00503 #define DRM_RADEON_GEM_PREAD              0x21
00504 #define DRM_RADEON_GEM_PWRITE             0x22
00505 #define DRM_RADEON_GEM_SET_DOMAIN  0x23
00506 #define DRM_RADEON_GEM_WAIT_IDLE   0x24
00507 #define DRM_RADEON_CS                     0x26
00508 #define DRM_RADEON_INFO                   0x27
00509 #define DRM_RADEON_GEM_SET_TILING  0x28
00510 #define DRM_RADEON_GEM_GET_TILING  0x29
00511 #define DRM_RADEON_GEM_BUSY        0x2a
00512 
00513 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
00514 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
00515 #define DRM_IOCTL_RADEON_CP_STOP    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
00516 #define DRM_IOCTL_RADEON_CP_RESET   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
00517 #define DRM_IOCTL_RADEON_CP_IDLE    DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
00518 #define DRM_IOCTL_RADEON_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_RESET)
00519 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
00520 #define DRM_IOCTL_RADEON_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_SWAP)
00521 #define DRM_IOCTL_RADEON_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
00522 #define DRM_IOCTL_RADEON_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
00523 #define DRM_IOCTL_RADEON_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
00524 #define DRM_IOCTL_RADEON_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
00525 #define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
00526 #define DRM_IOCTL_RADEON_TEXTURE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
00527 #define DRM_IOCTL_RADEON_VERTEX2    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
00528 #define DRM_IOCTL_RADEON_CMDBUF     DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
00529 #define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
00530 #define DRM_IOCTL_RADEON_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_FLIP)
00531 #define DRM_IOCTL_RADEON_ALLOC      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
00532 #define DRM_IOCTL_RADEON_FREE       DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
00533 #define DRM_IOCTL_RADEON_INIT_HEAP  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
00534 #define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
00535 #define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
00536 #define DRM_IOCTL_RADEON_CP_RESUME  DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
00537 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
00538 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
00539 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
00540 /* KMS */
00541 #define DRM_IOCTL_RADEON_GEM_INFO  DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
00542 #define DRM_IOCTL_RADEON_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
00543 #define DRM_IOCTL_RADEON_GEM_MMAP  DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
00544 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
00545 #define DRM_IOCTL_RADEON_GEM_PWRITE       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
00546 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
00547 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE    DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
00548 #define DRM_IOCTL_RADEON_CS        DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
00549 #define DRM_IOCTL_RADEON_INFO             DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
00550 #define DRM_IOCTL_RADEON_SET_TILING       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
00551 #define DRM_IOCTL_RADEON_GET_TILING       DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
00552 #define DRM_IOCTL_RADEON_GEM_BUSY  DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
00553 
00554 typedef struct drm_radeon_init {
00555        enum {
00556               RADEON_INIT_CP = 0x01,
00557               RADEON_CLEANUP_CP = 0x02,
00558               RADEON_INIT_R200_CP = 0x03,
00559               RADEON_INIT_R300_CP = 0x04,
00560               RADEON_INIT_R600_CP = 0x05
00561        } func;
00562        unsigned long sarea_priv_offset;
00563        int is_pci;
00564        int cp_mode;
00565        int gart_size;
00566        int ring_size;
00567        int usec_timeout;
00568 
00569        unsigned int fb_bpp;
00570        unsigned int front_offset, front_pitch;
00571        unsigned int back_offset, back_pitch;
00572        unsigned int depth_bpp;
00573        unsigned int depth_offset, depth_pitch;
00574 
00575        unsigned long fb_offset;
00576        unsigned long mmio_offset;
00577        unsigned long ring_offset;
00578        unsigned long ring_rptr_offset;
00579        unsigned long buffers_offset;
00580        unsigned long gart_textures_offset;
00581 } drm_radeon_init_t;
00582 
00583 typedef struct drm_radeon_cp_stop {
00584        int flush;
00585        int idle;
00586 } drm_radeon_cp_stop_t;
00587 
00588 typedef struct drm_radeon_fullscreen {
00589        enum {
00590               RADEON_INIT_FULLSCREEN = 0x01,
00591               RADEON_CLEANUP_FULLSCREEN = 0x02
00592        } func;
00593 } drm_radeon_fullscreen_t;
00594 
00595 #define CLEAR_X1     0
00596 #define CLEAR_Y1     1
00597 #define CLEAR_X2     2
00598 #define CLEAR_Y2     3
00599 #define CLEAR_DEPTH  4
00600 
00601 typedef union drm_radeon_clear_rect {
00602        float f[5];
00603        unsigned int ui[5];
00604 } drm_radeon_clear_rect_t;
00605 
00606 typedef struct drm_radeon_clear {
00607        unsigned int flags;
00608        unsigned int clear_color;
00609        unsigned int clear_depth;
00610        unsigned int color_mask;
00611        unsigned int depth_mask;    /* misnamed field:  should be stencil */
00612        drm_radeon_clear_rect_t *depth_boxes;
00613 } drm_radeon_clear_t;
00614 
00615 typedef struct drm_radeon_vertex {
00616        int prim;
00617        int idx;             /* Index of vertex buffer */
00618        int count;           /* Number of vertices in buffer */
00619        int discard;         /* Client finished with buffer? */
00620 } drm_radeon_vertex_t;
00621 
00622 typedef struct drm_radeon_indices {
00623        int prim;
00624        int idx;
00625        int start;
00626        int end;
00627        int discard;         /* Client finished with buffer? */
00628 } drm_radeon_indices_t;
00629 
00630 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
00631  *      - allows multiple primitives and state changes in a single ioctl
00632  *      - supports driver change to emit native primitives
00633  */
00634 typedef struct drm_radeon_vertex2 {
00635        int idx;             /* Index of vertex buffer */
00636        int discard;         /* Client finished with buffer? */
00637        int nr_states;
00638        drm_radeon_state_t *state;
00639        int nr_prims;
00640        drm_radeon_prim_t *prim;
00641 } drm_radeon_vertex2_t;
00642 
00643 /* v1.3 - obsoletes drm_radeon_vertex2
00644  *      - allows arbitarily large cliprect list
00645  *      - allows updating of tcl packet, vector and scalar state
00646  *      - allows memory-efficient description of state updates
00647  *      - allows state to be emitted without a primitive
00648  *           (for clears, ctx switches)
00649  *      - allows more than one dma buffer to be referenced per ioctl
00650  *      - supports tcl driver
00651  *      - may be extended in future versions with new cmd types, packets
00652  */
00653 typedef struct drm_radeon_cmd_buffer {
00654        int bufsz;
00655        char *buf;
00656        int nbox;
00657        struct drm_clip_rect *boxes;
00658 } drm_radeon_cmd_buffer_t;
00659 
00660 typedef struct drm_radeon_tex_image {
00661        unsigned int x, y;   /* Blit coordinates */
00662        unsigned int width, height;
00663        const void *data;
00664 } drm_radeon_tex_image_t;
00665 
00666 typedef struct drm_radeon_texture {
00667        unsigned int offset;
00668        int pitch;
00669        int format;
00670        int width;           /* Texture image coordinates */
00671        int height;
00672        drm_radeon_tex_image_t *image;
00673 } drm_radeon_texture_t;
00674 
00675 typedef struct drm_radeon_stipple {
00676        unsigned int *mask;
00677 } drm_radeon_stipple_t;
00678 
00679 typedef struct drm_radeon_indirect {
00680        int idx;
00681        int start;
00682        int end;
00683        int discard;
00684 } drm_radeon_indirect_t;
00685 
00686 /* enum for card type parameters */
00687 #define RADEON_CARD_PCI 0
00688 #define RADEON_CARD_AGP 1
00689 #define RADEON_CARD_PCIE 2
00690 
00691 /* 1.3: An ioctl to get parameters that aren't available to the 3d
00692  * client any other way.
00693  */
00694 #define RADEON_PARAM_GART_BUFFER_OFFSET    1     /* card offset of 1st GART buffer */
00695 #define RADEON_PARAM_LAST_FRAME            2
00696 #define RADEON_PARAM_LAST_DISPATCH         3
00697 #define RADEON_PARAM_LAST_CLEAR            4
00698 /* Added with DRM version 1.6. */
00699 #define RADEON_PARAM_IRQ_NR                5
00700 #define RADEON_PARAM_GART_BASE             6     /* card offset of GART base */
00701 /* Added with DRM version 1.8. */
00702 #define RADEON_PARAM_REGISTER_HANDLE       7     /* for drmMap() */
00703 #define RADEON_PARAM_STATUS_HANDLE         8
00704 #define RADEON_PARAM_SAREA_HANDLE          9
00705 #define RADEON_PARAM_GART_TEX_HANDLE       10
00706 #define RADEON_PARAM_SCRATCH_OFFSET        11
00707 #define RADEON_PARAM_CARD_TYPE             12
00708 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
00709 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
00710 #define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
00711 #define RADEON_PARAM_DEVICE_ID             16
00712 #define RADEON_PARAM_NUM_Z_PIPES           17   /* num Z pipes */
00713 
00714 typedef struct drm_radeon_getparam {
00715        int param;
00716        void *value;
00717 } drm_radeon_getparam_t;
00718 
00719 /* 1.6: Set up a memory manager for regions of shared memory:
00720  */
00721 #define RADEON_MEM_REGION_GART 1
00722 #define RADEON_MEM_REGION_FB   2
00723 
00724 typedef struct drm_radeon_mem_alloc {
00725        int region;
00726        int alignment;
00727        int size;
00728        int *region_offset;  /* offset from start of fb or GART */
00729 } drm_radeon_mem_alloc_t;
00730 
00731 typedef struct drm_radeon_mem_free {
00732        int region;
00733        int region_offset;
00734 } drm_radeon_mem_free_t;
00735 
00736 typedef struct drm_radeon_mem_init_heap {
00737        int region;
00738        int size;
00739        int start;
00740 } drm_radeon_mem_init_heap_t;
00741 
00742 /* 1.6: Userspace can request & wait on irq's:
00743  */
00744 typedef struct drm_radeon_irq_emit {
00745        int *irq_seq;
00746 } drm_radeon_irq_emit_t;
00747 
00748 typedef struct drm_radeon_irq_wait {
00749        int irq_seq;
00750 } drm_radeon_irq_wait_t;
00751 
00752 /* 1.10: Clients tell the DRM where they think the framebuffer is located in
00753  * the card's address space, via a new generic ioctl to set parameters
00754  */
00755 
00756 typedef struct drm_radeon_setparam {
00757        unsigned int param;
00758        __s64 value;
00759 } drm_radeon_setparam_t;
00760 
00761 #define RADEON_SETPARAM_FB_LOCATION    1  /* determined framebuffer location */
00762 #define RADEON_SETPARAM_SWITCH_TILING  2  /* enable/disable color tiling */
00763 #define RADEON_SETPARAM_PCIGART_LOCATION 3       /* PCI Gart Location */
00764 #define RADEON_SETPARAM_NEW_MEMMAP 4             /* Use new memory map */
00765 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
00766 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
00767 /* 1.14: Clients can allocate/free a surface
00768  */
00769 typedef struct drm_radeon_surface_alloc {
00770        unsigned int address;
00771        unsigned int size;
00772        unsigned int flags;
00773 } drm_radeon_surface_alloc_t;
00774 
00775 typedef struct drm_radeon_surface_free {
00776        unsigned int address;
00777 } drm_radeon_surface_free_t;
00778 
00779 #define       DRM_RADEON_VBLANK_CRTC1            1
00780 #define       DRM_RADEON_VBLANK_CRTC2            2
00781 
00782 /*
00783  * Kernel modesetting world below.
00784  */
00785 #define RADEON_GEM_DOMAIN_CPU             0x1
00786 #define RADEON_GEM_DOMAIN_GTT             0x2
00787 #define RADEON_GEM_DOMAIN_VRAM            0x4
00788 
00789 struct drm_radeon_gem_info {
00790        uint64_t      gart_size;
00791        uint64_t      vram_size;
00792        uint64_t      vram_visible;
00793 };
00794 
00795 #define RADEON_GEM_NO_BACKING_STORE 1
00796 
00797 struct drm_radeon_gem_create {
00798        uint64_t      size;
00799        uint64_t      alignment;
00800        uint32_t      handle;
00801        uint32_t      initial_domain;
00802        uint32_t      flags;
00803 };
00804 
00805 #define RADEON_TILING_MACRO                      0x1
00806 #define RADEON_TILING_MICRO                      0x2
00807 #define RADEON_TILING_SWAP_16BIT                 0x4
00808 #define RADEON_TILING_SWAP_32BIT                 0x8
00809 /* this object requires a surface when mapped - i.e. front buffer */
00810 #define RADEON_TILING_SURFACE                           0x10
00811 #define RADEON_TILING_MICRO_SQUARE               0x20
00812 #define RADEON_TILING_EG_BANKW_SHIFT                    8
00813 #define RADEON_TILING_EG_BANKW_MASK                     0xf
00814 #define RADEON_TILING_EG_BANKH_SHIFT                    12
00815 #define RADEON_TILING_EG_BANKH_MASK                     0xf
00816 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
00817 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK         0xf
00818 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT        24
00819 #define RADEON_TILING_EG_TILE_SPLIT_MASK         0xf
00820 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT       28
00821 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
00822 
00823 struct drm_radeon_gem_set_tiling {
00824        uint32_t      handle;
00825        uint32_t      tiling_flags;
00826        uint32_t      pitch;
00827 };
00828 
00829 struct drm_radeon_gem_get_tiling {
00830        uint32_t      handle;
00831        uint32_t      tiling_flags;
00832        uint32_t      pitch;
00833 };
00834 
00835 struct drm_radeon_gem_mmap {
00836        uint32_t      handle;
00837        uint32_t      pad;
00838        uint64_t      offset;
00839        uint64_t      size;
00840        uint64_t      addr_ptr;
00841 };
00842 
00843 struct drm_radeon_gem_set_domain {
00844        uint32_t      handle;
00845        uint32_t      read_domains;
00846        uint32_t      write_domain;
00847 };
00848 
00849 struct drm_radeon_gem_wait_idle {
00850        uint32_t      handle;
00851        uint32_t      pad;
00852 };
00853 
00854 struct drm_radeon_gem_busy {
00855        uint32_t      handle;
00856        uint32_t        domain;
00857 };
00858 
00859 struct drm_radeon_gem_pread {
00861        uint32_t handle;
00862        uint32_t pad;
00864        uint64_t offset;
00866        uint64_t size;
00868        /* void *, but pointers are not 32/64 compatible */
00869        uint64_t data_ptr;
00870 };
00871 
00872 struct drm_radeon_gem_pwrite {
00874        uint32_t handle;
00875        uint32_t pad;
00877        uint64_t offset;
00879        uint64_t size;
00881        /* void *, but pointers are not 32/64 compatible */
00882        uint64_t data_ptr;
00883 };
00884 
00885 #define RADEON_CHUNK_ID_RELOCS     0x01
00886 #define RADEON_CHUNK_ID_IB  0x02
00887 
00888 struct drm_radeon_cs_chunk {
00889        uint32_t             chunk_id;
00890        uint32_t             length_dw;
00891        uint64_t             chunk_data;
00892 };
00893 
00894 struct drm_radeon_cs_reloc {
00895        uint32_t             handle;
00896        uint32_t             read_domains;
00897        uint32_t             write_domain;
00898        uint32_t             flags;
00899 };
00900 
00901 struct drm_radeon_cs {
00902        uint32_t             num_chunks;
00903        uint32_t             cs_id;
00904        /* this points to uint64_t * which point to cs chunks */
00905        uint64_t             chunks;
00906        /* updates to the limits after this CS ioctl */
00907        uint64_t             gart_limit;
00908        uint64_t             vram_limit;
00909 };
00910 
00911 #define RADEON_INFO_DEVICE_ID             0x00
00912 #define RADEON_INFO_NUM_GB_PIPES   0x01
00913 #define RADEON_INFO_NUM_Z_PIPES    0x02
00914 #define RADEON_INFO_ACCEL_WORKING  0x03
00915 #define RADEON_INFO_CRTC_FROM_ID   0x04
00916 #define RADEON_INFO_ACCEL_WORKING2 0x05
00917 #define RADEON_INFO_TILING_CONFIG  0x06
00918 #define RADEON_INFO_WANT_HYPERZ           0x07
00919 
00920 struct drm_radeon_info {
00921        uint32_t             request;
00922        uint32_t             pad;
00923        uint64_t             value;
00924 };
00925 
00926 #endif