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libdrm  2.4.37
nouveau_drm.h
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00001 /*
00002  * Copyright 2005 Stephane Marchesin.
00003  * All Rights Reserved.
00004  *
00005  * Permission is hereby granted, free of charge, to any person obtaining a
00006  * copy of this software and associated documentation files (the "Software"),
00007  * to deal in the Software without restriction, including without limitation
00008  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00009  * and/or sell copies of the Software, and to permit persons to whom the
00010  * Software is furnished to do so, subject to the following conditions:
00011  *
00012  * The above copyright notice and this permission notice (including the next
00013  * paragraph) shall be included in all copies or substantial portions of the
00014  * Software.
00015  *
00016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
00019  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
00020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00022  * OTHER DEALINGS IN THE SOFTWARE.
00023  */
00024 
00025 #ifndef __NOUVEAU_DRM_H__
00026 #define __NOUVEAU_DRM_H__
00027 
00028 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
00029 
00030 struct drm_nouveau_channel_alloc {
00031        uint32_t     fb_ctxdma_handle;
00032        uint32_t     tt_ctxdma_handle;
00033 
00034        int          channel;
00035        uint32_t     pushbuf_domains;
00036 
00037        /* Notifier memory */
00038        uint32_t     notifier_handle;
00039 
00040        /* DRM-enforced subchannel assignments */
00041        struct {
00042               uint32_t handle;
00043               uint32_t grclass;
00044        } subchan[8];
00045        uint32_t nr_subchan;
00046 };
00047 
00048 struct drm_nouveau_channel_free {
00049        int channel;
00050 };
00051 
00052 struct drm_nouveau_grobj_alloc {
00053        int      channel;
00054        uint32_t handle;
00055        int      class;
00056 };
00057 
00058 struct drm_nouveau_notifierobj_alloc {
00059        uint32_t channel;
00060        uint32_t handle;
00061        uint32_t size;
00062        uint32_t offset;
00063 };
00064 
00065 struct drm_nouveau_gpuobj_free {
00066        int      channel;
00067        uint32_t handle;
00068 };
00069 
00070 /* FIXME : maybe unify {GET,SET}PARAMs */
00071 #define NOUVEAU_GETPARAM_PCI_VENDOR      3
00072 #define NOUVEAU_GETPARAM_PCI_DEVICE      4
00073 #define NOUVEAU_GETPARAM_BUS_TYPE        5
00074 #define NOUVEAU_GETPARAM_FB_PHYSICAL     6
00075 #define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
00076 #define NOUVEAU_GETPARAM_FB_SIZE         8
00077 #define NOUVEAU_GETPARAM_AGP_SIZE        9
00078 #define NOUVEAU_GETPARAM_PCI_PHYSICAL    10
00079 #define NOUVEAU_GETPARAM_CHIPSET_ID      11
00080 #define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
00081 #define NOUVEAU_GETPARAM_GRAPH_UNITS     13
00082 #define NOUVEAU_GETPARAM_PTIMER_TIME     14
00083 #define NOUVEAU_GETPARAM_HAS_BO_USAGE    15
00084 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP    16
00085 struct drm_nouveau_getparam {
00086        uint64_t param;
00087        uint64_t value;
00088 };
00089 
00090 struct drm_nouveau_setparam {
00091        uint64_t param;
00092        uint64_t value;
00093 };
00094 
00095 #define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
00096 #define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
00097 #define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
00098 #define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
00099 
00100 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
00101 #define NOUVEAU_GEM_TILE_16BPP       0x00000001
00102 #define NOUVEAU_GEM_TILE_32BPP       0x00000002
00103 #define NOUVEAU_GEM_TILE_ZETA        0x00000004
00104 #define NOUVEAU_GEM_TILE_NONCONTIG   0x00000008
00105 
00106 struct drm_nouveau_gem_info {
00107        uint32_t handle;
00108        uint32_t domain;
00109        uint64_t size;
00110        uint64_t offset;
00111        uint64_t map_handle;
00112        uint32_t tile_mode;
00113        uint32_t tile_flags;
00114 };
00115 
00116 struct drm_nouveau_gem_new {
00117        struct drm_nouveau_gem_info info;
00118        uint32_t channel_hint;
00119        uint32_t align;
00120 };
00121 
00122 #define NOUVEAU_GEM_MAX_BUFFERS 1024
00123 struct drm_nouveau_gem_pushbuf_bo_presumed {
00124        uint32_t valid;
00125        uint32_t domain;
00126        uint64_t offset;
00127 };
00128 
00129 struct drm_nouveau_gem_pushbuf_bo {
00130        uint64_t user_priv;
00131        uint32_t handle;
00132        uint32_t read_domains;
00133        uint32_t write_domains;
00134        uint32_t valid_domains;
00135        struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
00136 };
00137 
00138 #define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
00139 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
00140 #define NOUVEAU_GEM_RELOC_OR   (1 << 2)
00141 #define NOUVEAU_GEM_MAX_RELOCS 1024
00142 struct drm_nouveau_gem_pushbuf_reloc {
00143        uint32_t reloc_bo_index;
00144        uint32_t reloc_bo_offset;
00145        uint32_t bo_index;
00146        uint32_t flags;
00147        uint32_t data;
00148        uint32_t vor;
00149        uint32_t tor;
00150 };
00151 
00152 #define NOUVEAU_GEM_MAX_PUSH 512
00153 struct drm_nouveau_gem_pushbuf_push {
00154        uint32_t bo_index;
00155        uint32_t pad;
00156        uint64_t offset;
00157        uint64_t length;
00158 };
00159 
00160 struct drm_nouveau_gem_pushbuf {
00161        uint32_t channel;
00162        uint32_t nr_buffers;
00163        uint64_t buffers;
00164        uint32_t nr_relocs;
00165        uint32_t nr_push;
00166        uint64_t relocs;
00167        uint64_t push;
00168        uint32_t suffix0;
00169        uint32_t suffix1;
00170        uint64_t vram_available;
00171        uint64_t gart_available;
00172 };
00173 
00174 #define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
00175 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK                                 0x00000002
00176 #define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
00177 struct drm_nouveau_gem_cpu_prep {
00178        uint32_t handle;
00179        uint32_t flags;
00180 };
00181 
00182 struct drm_nouveau_gem_cpu_fini {
00183        uint32_t handle;
00184 };
00185 
00186 enum nouveau_bus_type {
00187        NV_AGP     = 0,
00188        NV_PCI     = 1,
00189        NV_PCIE    = 2,
00190 };
00191 
00192 struct drm_nouveau_sarea {
00193 };
00194 
00195 #define DRM_NOUVEAU_GETPARAM           0x00
00196 #define DRM_NOUVEAU_SETPARAM           0x01
00197 #define DRM_NOUVEAU_CHANNEL_ALLOC      0x02
00198 #define DRM_NOUVEAU_CHANNEL_FREE       0x03
00199 #define DRM_NOUVEAU_GROBJ_ALLOC        0x04
00200 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x05
00201 #define DRM_NOUVEAU_GPUOBJ_FREE        0x06
00202 #define DRM_NOUVEAU_GEM_NEW            0x40
00203 #define DRM_NOUVEAU_GEM_PUSHBUF        0x41
00204 #define DRM_NOUVEAU_GEM_CPU_PREP       0x42
00205 #define DRM_NOUVEAU_GEM_CPU_FINI       0x43
00206 #define DRM_NOUVEAU_GEM_INFO           0x44
00207 
00208 #endif /* __NOUVEAU_DRM_H__ */