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libdrm  2.4.37
mga_drm.h
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00001 /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
00002  * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
00003  *
00004  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
00005  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
00006  * All rights reserved.
00007  *
00008  * Permission is hereby granted, free of charge, to any person obtaining a
00009  * copy of this software and associated documentation files (the "Software"),
00010  * to deal in the Software without restriction, including without limitation
00011  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00012  * and/or sell copies of the Software, and to permit persons to whom the
00013  * Software is furnished to do so, subject to the following conditions:
00014  *
00015  * The above copyright notice and this permission notice (including the next
00016  * paragraph) shall be included in all copies or substantial portions of the
00017  * Software.
00018  *
00019  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00020  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00021  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
00022  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
00023  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
00024  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00025  * OTHER DEALINGS IN THE SOFTWARE.
00026  *
00027  * Authors:
00028  *    Jeff Hartmann <jhartmann@valinux.com>
00029  *    Keith Whitwell <keith@tungstengraphics.com>
00030  *
00031  * Rewritten by:
00032  *    Gareth Hughes <gareth@valinux.com>
00033  */
00034 
00035 #ifndef __MGA_DRM_H__
00036 #define __MGA_DRM_H__
00037 
00038 #include "drm.h"
00039 
00040 /* WARNING: If you change any of these defines, make sure to change the
00041  * defines in the Xserver file (mga_sarea.h)
00042  */
00043 
00044 #ifndef __MGA_SAREA_DEFINES__
00045 #define __MGA_SAREA_DEFINES__
00046 
00047 /* WARP pipe flags
00048  */
00049 #define MGA_F               0x1    /* fog */
00050 #define MGA_A               0x2    /* alpha */
00051 #define MGA_S               0x4    /* specular */
00052 #define MGA_T2                     0x8    /* multitexture */
00053 
00054 #define MGA_WARP_TGZ        0
00055 #define MGA_WARP_TGZF              (MGA_F)
00056 #define MGA_WARP_TGZA              (MGA_A)
00057 #define MGA_WARP_TGZAF             (MGA_F|MGA_A)
00058 #define MGA_WARP_TGZS              (MGA_S)
00059 #define MGA_WARP_TGZSF             (MGA_S|MGA_F)
00060 #define MGA_WARP_TGZSA             (MGA_S|MGA_A)
00061 #define MGA_WARP_TGZSAF            (MGA_S|MGA_F|MGA_A)
00062 #define MGA_WARP_T2GZ              (MGA_T2)
00063 #define MGA_WARP_T2GZF             (MGA_T2|MGA_F)
00064 #define MGA_WARP_T2GZA             (MGA_T2|MGA_A)
00065 #define MGA_WARP_T2GZAF            (MGA_T2|MGA_A|MGA_F)
00066 #define MGA_WARP_T2GZS             (MGA_T2|MGA_S)
00067 #define MGA_WARP_T2GZSF            (MGA_T2|MGA_S|MGA_F)
00068 #define MGA_WARP_T2GZSA            (MGA_T2|MGA_S|MGA_A)
00069 #define MGA_WARP_T2GZSAF    (MGA_T2|MGA_S|MGA_F|MGA_A)
00070 
00071 #define MGA_MAX_G200_PIPES  8      /* no multitex */
00072 #define MGA_MAX_G400_PIPES  16
00073 #define MGA_MAX_WARP_PIPES  MGA_MAX_G400_PIPES
00074 #define MGA_WARP_UCODE_SIZE 32768  /* in bytes */
00075 
00076 #define MGA_CARD_TYPE_G200  1
00077 #define MGA_CARD_TYPE_G400  2
00078 #define MGA_CARD_TYPE_G450  3      /* not currently used */
00079 #define MGA_CARD_TYPE_G550  4
00080 
00081 #define MGA_FRONT           0x1
00082 #define MGA_BACK            0x2
00083 #define MGA_DEPTH           0x4
00084 
00085 /* What needs to be changed for the current vertex dma buffer?
00086  */
00087 #define MGA_UPLOAD_CONTEXT  0x1
00088 #define MGA_UPLOAD_TEX0            0x2
00089 #define MGA_UPLOAD_TEX1            0x4
00090 #define MGA_UPLOAD_PIPE            0x8
00091 #define MGA_UPLOAD_TEX0IMAGE       0x10   /* handled client-side */
00092 #define MGA_UPLOAD_TEX1IMAGE       0x20   /* handled client-side */
00093 #define MGA_UPLOAD_2D              0x40
00094 #define MGA_WAIT_AGE        0x80   /* handled client-side */
00095 #define MGA_UPLOAD_CLIPRECTS       0x100  /* handled client-side */
00096 #if 0
00097 #define MGA_DMA_FLUSH              0x200  /* set when someone gets the lock
00098                                       quiescent */
00099 #endif
00100 
00101 /* 32 buffers of 64k each, total 2 meg.
00102  */
00103 #define MGA_BUFFER_SIZE            (1 << 16)
00104 #define MGA_NUM_BUFFERS            128
00105 
00106 /* Keep these small for testing.
00107  */
00108 #define MGA_NR_SAREA_CLIPRECTS     8
00109 
00110 /* 2 heaps (1 for card, 1 for agp), each divided into upto 128
00111  * regions, subject to a minimum region size of (1<<16) == 64k.
00112  *
00113  * Clients may subdivide regions internally, but when sharing between
00114  * clients, the region size is the minimum granularity.
00115  */
00116 
00117 #define MGA_CARD_HEAP                     0
00118 #define MGA_AGP_HEAP               1
00119 #define MGA_NR_TEX_HEAPS           2
00120 #define MGA_NR_TEX_REGIONS         16
00121 #define MGA_LOG_MIN_TEX_REGION_SIZE       16
00122 
00123 #define  DRM_MGA_IDLE_RETRY          2048
00124 
00125 #endif                      /* __MGA_SAREA_DEFINES__ */
00126 
00127 /* Setup registers for 3D context
00128  */
00129 typedef struct {
00130        unsigned int dstorg;
00131        unsigned int maccess;
00132        unsigned int plnwt;
00133        unsigned int dwgctl;
00134        unsigned int alphactrl;
00135        unsigned int fogcolor;
00136        unsigned int wflag;
00137        unsigned int tdualstage0;
00138        unsigned int tdualstage1;
00139        unsigned int fcol;
00140        unsigned int stencil;
00141        unsigned int stencilctl;
00142 } drm_mga_context_regs_t;
00143 
00144 /* Setup registers for 2D, X server
00145  */
00146 typedef struct {
00147        unsigned int pitch;
00148 } drm_mga_server_regs_t;
00149 
00150 /* Setup registers for each texture unit
00151  */
00152 typedef struct {
00153        unsigned int texctl;
00154        unsigned int texctl2;
00155        unsigned int texfilter;
00156        unsigned int texbordercol;
00157        unsigned int texorg;
00158        unsigned int texwidth;
00159        unsigned int texheight;
00160        unsigned int texorg1;
00161        unsigned int texorg2;
00162        unsigned int texorg3;
00163        unsigned int texorg4;
00164 } drm_mga_texture_regs_t;
00165 
00166 /* General aging mechanism
00167  */
00168 typedef struct {
00169        unsigned int head;   /* Position of head pointer          */
00170        unsigned int wrap;   /* Primary DMA wrap count            */
00171 } drm_mga_age_t;
00172 
00173 typedef struct _drm_mga_sarea {
00174        /* The channel for communication of state information to the kernel
00175         * on firing a vertex dma buffer.
00176         */
00177        drm_mga_context_regs_t context_state;
00178        drm_mga_server_regs_t server_state;
00179        drm_mga_texture_regs_t tex_state[2];
00180        unsigned int warp_pipe;
00181        unsigned int dirty;
00182        unsigned int vertsize;
00183 
00184        /* The current cliprects, or a subset thereof.
00185         */
00186        struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
00187        unsigned int nbox;
00188 
00189        /* Information about the most recently used 3d drawable.  The
00190         * client fills in the req_* fields, the server fills in the
00191         * exported_ fields and puts the cliprects into boxes, above.
00192         *
00193         * The client clears the exported_drawable field before
00194         * clobbering the boxes data.
00195         */
00196        unsigned int req_drawable;  /* the X drawable id */
00197        unsigned int req_draw_buffer;      /* MGA_FRONT or MGA_BACK */
00198 
00199        unsigned int exported_drawable;
00200        unsigned int exported_index;
00201        unsigned int exported_stamp;
00202        unsigned int exported_buffers;
00203        unsigned int exported_nfront;
00204        unsigned int exported_nback;
00205        int exported_back_x, exported_front_x, exported_w;
00206        int exported_back_y, exported_front_y, exported_h;
00207        struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
00208 
00209        /* Counters for aging textures and for client-side throttling.
00210         */
00211        unsigned int status[4];
00212        unsigned int last_wrap;
00213 
00214        drm_mga_age_t last_frame;
00215        unsigned int last_enqueue;  /* last time a buffer was enqueued */
00216        unsigned int last_dispatch; /* age of the most recently dispatched buffer */
00217        unsigned int last_quiescent;       /*  */
00218 
00219        /* LRU lists for texture memory in agp space and on the card.
00220         */
00221        struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
00222        unsigned int texAge[MGA_NR_TEX_HEAPS];
00223 
00224        /* Mechanism to validate card state.
00225         */
00226        int ctxOwner;
00227 } drm_mga_sarea_t;
00228 
00229 /* MGA specific ioctls
00230  * The device specific ioctl range is 0x40 to 0x79.
00231  */
00232 #define DRM_MGA_INIT     0x00
00233 #define DRM_MGA_FLUSH    0x01
00234 #define DRM_MGA_RESET    0x02
00235 #define DRM_MGA_SWAP     0x03
00236 #define DRM_MGA_CLEAR    0x04
00237 #define DRM_MGA_VERTEX   0x05
00238 #define DRM_MGA_INDICES  0x06
00239 #define DRM_MGA_ILOAD    0x07
00240 #define DRM_MGA_BLIT     0x08
00241 #define DRM_MGA_GETPARAM 0x09
00242 
00243 /* 3.2:
00244  * ioctls for operating on fences.
00245  */
00246 #define DRM_MGA_SET_FENCE      0x0a
00247 #define DRM_MGA_WAIT_FENCE     0x0b
00248 #define DRM_MGA_DMA_BOOTSTRAP  0x0c
00249 
00250 #define DRM_IOCTL_MGA_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
00251 #define DRM_IOCTL_MGA_FLUSH    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
00252 #define DRM_IOCTL_MGA_RESET    DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_RESET)
00253 #define DRM_IOCTL_MGA_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_MGA_SWAP)
00254 #define DRM_IOCTL_MGA_CLEAR    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
00255 #define DRM_IOCTL_MGA_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
00256 #define DRM_IOCTL_MGA_INDICES  DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
00257 #define DRM_IOCTL_MGA_ILOAD    DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
00258 #define DRM_IOCTL_MGA_BLIT     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
00259 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
00260 #define DRM_IOCTL_MGA_SET_FENCE     DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
00261 #define DRM_IOCTL_MGA_WAIT_FENCE    DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
00262 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
00263 
00264 typedef struct _drm_mga_warp_index {
00265        int installed;
00266        unsigned long phys_addr;
00267        int size;
00268 } drm_mga_warp_index_t;
00269 
00270 typedef struct drm_mga_init {
00271        enum {
00272               MGA_INIT_DMA = 0x01,
00273               MGA_CLEANUP_DMA = 0x02
00274        } func;
00275 
00276        unsigned long sarea_priv_offset;
00277 
00278        int chipset;
00279        int sgram;
00280 
00281        unsigned int maccess;
00282 
00283        unsigned int fb_cpp;
00284        unsigned int front_offset, front_pitch;
00285        unsigned int back_offset, back_pitch;
00286 
00287        unsigned int depth_cpp;
00288        unsigned int depth_offset, depth_pitch;
00289 
00290        unsigned int texture_offset[MGA_NR_TEX_HEAPS];
00291        unsigned int texture_size[MGA_NR_TEX_HEAPS];
00292 
00293        unsigned long fb_offset;
00294        unsigned long mmio_offset;
00295        unsigned long status_offset;
00296        unsigned long warp_offset;
00297        unsigned long primary_offset;
00298        unsigned long buffers_offset;
00299 } drm_mga_init_t;
00300 
00301 typedef struct drm_mga_dma_bootstrap {
00313 
00314        unsigned long texture_handle; 
00315        __u32 texture_size;        
00316 
00324        __u32 primary_size;
00325 
00334        __u32 secondary_bin_count;
00335 
00343        __u32 secondary_bin_size;
00344 
00355        __u32 agp_mode;
00356 
00360        __u8 agp_size;
00361 } drm_mga_dma_bootstrap_t;
00362 
00363 typedef struct drm_mga_clear {
00364        unsigned int flags;
00365        unsigned int clear_color;
00366        unsigned int clear_depth;
00367        unsigned int color_mask;
00368        unsigned int depth_mask;
00369 } drm_mga_clear_t;
00370 
00371 typedef struct drm_mga_vertex {
00372        int idx;             /* buffer to queue */
00373        int used;            /* bytes in use */
00374        int discard;         /* client finished with buffer?  */
00375 } drm_mga_vertex_t;
00376 
00377 typedef struct drm_mga_indices {
00378        int idx;             /* buffer to queue */
00379        unsigned int start;
00380        unsigned int end;
00381        int discard;         /* client finished with buffer?  */
00382 } drm_mga_indices_t;
00383 
00384 typedef struct drm_mga_iload {
00385        int idx;
00386        unsigned int dstorg;
00387        unsigned int length;
00388 } drm_mga_iload_t;
00389 
00390 typedef struct _drm_mga_blit {
00391        unsigned int planemask;
00392        unsigned int srcorg;
00393        unsigned int dstorg;
00394        int src_pitch, dst_pitch;
00395        int delta_sx, delta_sy;
00396        int delta_dx, delta_dy;
00397        int height, ydir;    /* flip image vertically */
00398        int source_pitch, dest_pitch;
00399 } drm_mga_blit_t;
00400 
00401 /* 3.1: An ioctl to get parameters that aren't available to the 3d
00402  * client any other way.
00403  */
00404 #define MGA_PARAM_IRQ_NR            1
00405 
00406 /* 3.2: Query the actual card type.  The DDX only distinguishes between
00407  * G200 chips and non-G200 chips, which it calls G400.  It turns out that
00408  * there are some very sublte differences between the G4x0 chips and the G550
00409  * chips.  Using this parameter query, a client-side driver can detect the
00410  * difference between a G4x0 and a G550.
00411  */
00412 #define MGA_PARAM_CARD_TYPE         2
00413 
00414 typedef struct drm_mga_getparam {
00415        int param;
00416        void *value;
00417 } drm_mga_getparam_t;
00418 
00419 #endif