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libdrm  2.4.37
intel_chipset.h
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00001 /*
00002  *
00003  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
00004  * All Rights Reserved.
00005  *
00006  * Permission is hereby granted, free of charge, to any person obtaining a
00007  * copy of this software and associated documentation files (the
00008  * "Software"), to deal in the Software without restriction, including
00009  * without limitation the rights to use, copy, modify, merge, publish,
00010  * distribute, sub license, and/or sell copies of the Software, and to
00011  * permit persons to whom the Software is furnished to do so, subject to
00012  * the following conditions:
00013  *
00014  * The above copyright notice and this permission notice (including the
00015  * next paragraph) shall be included in all copies or substantial portions
00016  * of the Software.
00017  *
00018  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00019  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00020  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
00021  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
00022  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
00023  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
00024  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00025  *
00026  */
00027 
00028 #ifndef _INTEL_CHIPSET_H
00029 #define _INTEL_CHIPSET_H
00030 
00031 #define PCI_CHIP_ILD_G                  0x0042
00032 #define PCI_CHIP_ILM_G                  0x0046
00033 
00034 #define PCI_CHIP_SANDYBRIDGE_GT1   0x0102 /* desktop */
00035 #define PCI_CHIP_SANDYBRIDGE_GT2   0x0112
00036 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS     0x0122
00037 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
00038 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
00039 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS   0x0126
00040 #define PCI_CHIP_SANDYBRIDGE_S            0x010A /* server */
00041 
00042 #define PCI_CHIP_IVYBRIDGE_GT1            0x0152 /* desktop */
00043 #define PCI_CHIP_IVYBRIDGE_GT2            0x0162
00044 #define PCI_CHIP_IVYBRIDGE_M_GT1   0x0156 /* mobile */
00045 #define PCI_CHIP_IVYBRIDGE_M_GT2   0x0166
00046 #define PCI_CHIP_IVYBRIDGE_S              0x015a /* server */
00047 #define PCI_CHIP_IVYBRIDGE_S_GT2   0x016a /* server */
00048 
00049 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
00050 #define PCI_CHIP_HASWELL_GT2            0x0412
00051 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
00052 #define PCI_CHIP_HASWELL_M_GT2          0x0416
00053 #define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
00054 
00055 #define IS_830(dev) (dev == 0x3577)
00056 #define IS_845(dev) (dev == 0x2562)
00057 #define IS_85X(dev) (dev == 0x3582)
00058 #define IS_865(dev) (dev == 0x2572)
00059 
00060 #define IS_GEN2(dev) (IS_830(dev) ||                           \
00061                     IS_845(dev) ||                      \
00062                     IS_85X(dev) ||                      \
00063                     IS_865(dev))
00064 
00065 #define IS_915G(dev) (dev == 0x2582 ||           \
00066                      dev == 0x258a)
00067 #define IS_915GM(dev) (dev == 0x2592)
00068 #define IS_945G(dev) (dev == 0x2772)
00069 #define IS_945GM(dev) (dev == 0x27A2 ||          \
00070                         dev == 0x27AE)
00071 
00072 #define IS_915(dev) (IS_915G(dev) ||                           \
00073                    IS_915GM(dev))
00074 
00075 #define IS_945(dev) (IS_945G(dev) ||                           \
00076                    IS_945GM(dev) ||                            \
00077                    IS_G33(dev) ||                       \
00078                    IS_PINEVIEW(dev))
00079 
00080 #define IS_G33(dev)    (dev == 0x29C2 ||         \
00081                         dev == 0x29B2 ||         \
00082                         dev == 0x29D2)
00083 
00084 #define IS_PINEVIEW(dev) (dev == 0xa001 ||       \
00085                        dev == 0xa011)
00086 
00087 #define IS_GEN3(dev) (IS_915(dev) ||                           \
00088                     IS_945(dev) ||                      \
00089                     IS_G33(dev) ||                      \
00090                     IS_PINEVIEW(dev))
00091 
00092 #define IS_I965GM(dev) (dev == 0x2A02)
00093 
00094 #define IS_GEN4(dev) (dev == 0x2972 ||    \
00095                     dev == 0x2982 ||      \
00096                     dev == 0x2992 ||      \
00097                     dev == 0x29A2 ||      \
00098                     dev == 0x2A02 ||      \
00099                     dev == 0x2A12 ||      \
00100                     dev == 0x2A42 ||      \
00101                     dev == 0x2E02 ||      \
00102                     dev == 0x2E12 ||      \
00103                     dev == 0x2E22 ||      \
00104                     dev == 0x2E32 ||      \
00105                     dev == 0x2E42 ||      \
00106                     dev == 0x0042 ||      \
00107                     dev == 0x0046 ||      \
00108                     IS_I965GM(dev) || \
00109                     IS_G4X(dev))
00110 
00111 #define IS_GM45(dev) (dev == 0x2A42)
00112 
00113 
00114 #define IS_GEN5(dev) (dev == PCI_CHIP_ILD_G || \
00115                       dev == PCI_CHIP_ILM_G)
00116 
00117 #define IS_GEN6(dev) (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \
00118                       dev == PCI_CHIP_SANDYBRIDGE_GT2 || \
00119                       dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
00120                       dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
00121                       dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
00122                       dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
00123                       dev == PCI_CHIP_SANDYBRIDGE_S)
00124 
00125 #define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
00126                                  IS_HASWELL(devid))
00127 
00128 #define IS_IVYBRIDGE(dev)   (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
00129                              dev == PCI_CHIP_IVYBRIDGE_GT2 || \
00130                              dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
00131                              dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
00132                              dev == PCI_CHIP_IVYBRIDGE_S || \
00133                              dev == PCI_CHIP_IVYBRIDGE_S_GT2)
00134 
00135 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
00136                                  devid == PCI_CHIP_HASWELL_M_GT1)
00137 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
00138                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
00139                                  devid == PCI_CHIP_HASWELL_M_ULT_GT2)
00140 
00141 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
00142                                  IS_HSW_GT2(devid))
00143 
00144 #define IS_G4X(dev) (dev == 0x2E02 || \
00145                      dev == 0x2E12 || \
00146                      dev == 0x2E22 || \
00147                      dev == 0x2E32 || \
00148                      dev == 0x2E42 || \
00149                    IS_GM45(dev))
00150 
00151 #define IS_9XX(dev) (IS_GEN3(dev) ||                           \
00152                    IS_GEN4(dev) ||                      \
00153                    IS_GEN5(dev) ||                      \
00154                    IS_GEN6(dev) ||                      \
00155                    IS_GEN7(dev))
00156 
00157 #endif /* _INTEL_CHIPSET_H */