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libdrm  2.4.37
intel_bufmgr.c
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00001 /*
00002  * Copyright © 2007 Intel Corporation
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
00006  * to deal in the Software without restriction, including without limitation
00007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008  * and/or sell copies of the Software, and to permit persons to whom the
00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice (including the next
00012  * paragraph) shall be included in all copies or substantial portions of the
00013  * Software.
00014  *
00015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
00018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
00020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
00021  * IN THE SOFTWARE.
00022  *
00023  * Authors:
00024  *    Eric Anholt <eric@anholt.net>
00025  *
00026  */
00027 
00028 #ifdef HAVE_CONFIG_H
00029 #include "config.h"
00030 #endif
00031 
00032 #include <string.h>
00033 #include <stdlib.h>
00034 #include <stdint.h>
00035 #include <assert.h>
00036 #include <errno.h>
00037 #include <drm.h>
00038 #include <i915_drm.h>
00039 #include <pciaccess.h>
00040 #include "intel_bufmgr.h"
00041 #include "intel_bufmgr_priv.h"
00042 #include "xf86drm.h"
00043 
00049 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
00050                              unsigned long size, unsigned int alignment)
00051 {
00052        return bufmgr->bo_alloc(bufmgr, name, size, alignment);
00053 }
00054 
00055 drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
00056                                        const char *name,
00057                                        unsigned long size,
00058                                        unsigned int alignment)
00059 {
00060        return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
00061 }
00062 
00063 drm_intel_bo *
00064 drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
00065                         int x, int y, int cpp, uint32_t *tiling_mode,
00066                         unsigned long *pitch, unsigned long flags)
00067 {
00068        return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
00069                                   tiling_mode, pitch, flags);
00070 }
00071 
00072 void drm_intel_bo_reference(drm_intel_bo *bo)
00073 {
00074        bo->bufmgr->bo_reference(bo);
00075 }
00076 
00077 void drm_intel_bo_unreference(drm_intel_bo *bo)
00078 {
00079        if (bo == NULL)
00080               return;
00081 
00082        bo->bufmgr->bo_unreference(bo);
00083 }
00084 
00085 int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
00086 {
00087        return buf->bufmgr->bo_map(buf, write_enable);
00088 }
00089 
00090 int drm_intel_bo_unmap(drm_intel_bo *buf)
00091 {
00092        return buf->bufmgr->bo_unmap(buf);
00093 }
00094 
00095 int
00096 drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
00097                    unsigned long size, const void *data)
00098 {
00099        return bo->bufmgr->bo_subdata(bo, offset, size, data);
00100 }
00101 
00102 int
00103 drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
00104                       unsigned long size, void *data)
00105 {
00106        int ret;
00107        if (bo->bufmgr->bo_get_subdata)
00108               return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
00109 
00110        if (size == 0 || data == NULL)
00111               return 0;
00112 
00113        ret = drm_intel_bo_map(bo, 0);
00114        if (ret)
00115               return ret;
00116        memcpy(data, (unsigned char *)bo->virtual + offset, size);
00117        drm_intel_bo_unmap(bo);
00118        return 0;
00119 }
00120 
00121 void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
00122 {
00123        bo->bufmgr->bo_wait_rendering(bo);
00124 }
00125 
00126 void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
00127 {
00128        bufmgr->destroy(bufmgr);
00129 }
00130 
00131 int
00132 drm_intel_bo_exec(drm_intel_bo *bo, int used,
00133                 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
00134 {
00135        return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
00136 }
00137 
00138 int
00139 drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
00140               drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
00141               unsigned int rings)
00142 {
00143        if (bo->bufmgr->bo_mrb_exec)
00144               return bo->bufmgr->bo_mrb_exec(bo, used,
00145                                    cliprects, num_cliprects, DR4,
00146                                    rings);
00147 
00148        switch (rings) {
00149        case I915_EXEC_DEFAULT:
00150        case I915_EXEC_RENDER:
00151               return bo->bufmgr->bo_exec(bo, used,
00152                                       cliprects, num_cliprects, DR4);
00153        default:
00154               return -ENODEV;
00155        }
00156 }
00157 
00158 void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
00159 {
00160        bufmgr->debug = enable_debug;
00161 }
00162 
00163 int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
00164 {
00165        return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
00166 }
00167 
00168 int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
00169 {
00170        if (bo->bufmgr->bo_flink)
00171               return bo->bufmgr->bo_flink(bo, name);
00172 
00173        return -ENODEV;
00174 }
00175 
00176 int
00177 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
00178                      drm_intel_bo *target_bo, uint32_t target_offset,
00179                      uint32_t read_domains, uint32_t write_domain)
00180 {
00181        return bo->bufmgr->bo_emit_reloc(bo, offset,
00182                                     target_bo, target_offset,
00183                                     read_domains, write_domain);
00184 }
00185 
00186 /* For fence registers, not GL fences */
00187 int
00188 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
00189                            drm_intel_bo *target_bo, uint32_t target_offset,
00190                            uint32_t read_domains, uint32_t write_domain)
00191 {
00192        return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
00193                                           target_bo, target_offset,
00194                                           read_domains, write_domain);
00195 }
00196 
00197 
00198 int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
00199 {
00200        if (bo->bufmgr->bo_pin)
00201               return bo->bufmgr->bo_pin(bo, alignment);
00202 
00203        return -ENODEV;
00204 }
00205 
00206 int drm_intel_bo_unpin(drm_intel_bo *bo)
00207 {
00208        if (bo->bufmgr->bo_unpin)
00209               return bo->bufmgr->bo_unpin(bo);
00210 
00211        return -ENODEV;
00212 }
00213 
00214 int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
00215                          uint32_t stride)
00216 {
00217        if (bo->bufmgr->bo_set_tiling)
00218               return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
00219 
00220        *tiling_mode = I915_TILING_NONE;
00221        return 0;
00222 }
00223 
00224 int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
00225                          uint32_t * swizzle_mode)
00226 {
00227        if (bo->bufmgr->bo_get_tiling)
00228               return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
00229 
00230        *tiling_mode = I915_TILING_NONE;
00231        *swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
00232        return 0;
00233 }
00234 
00235 int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
00236 {
00237        if (bo->bufmgr->bo_disable_reuse)
00238               return bo->bufmgr->bo_disable_reuse(bo);
00239        return 0;
00240 }
00241 
00242 int drm_intel_bo_is_reusable(drm_intel_bo *bo)
00243 {
00244        if (bo->bufmgr->bo_is_reusable)
00245               return bo->bufmgr->bo_is_reusable(bo);
00246        return 0;
00247 }
00248 
00249 int drm_intel_bo_busy(drm_intel_bo *bo)
00250 {
00251        if (bo->bufmgr->bo_busy)
00252               return bo->bufmgr->bo_busy(bo);
00253        return 0;
00254 }
00255 
00256 int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
00257 {
00258        if (bo->bufmgr->bo_madvise)
00259               return bo->bufmgr->bo_madvise(bo, madv);
00260        return -1;
00261 }
00262 
00263 int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
00264 {
00265        return bo->bufmgr->bo_references(bo, target_bo);
00266 }
00267 
00268 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
00269 {
00270        if (bufmgr->get_pipe_from_crtc_id)
00271               return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
00272        return -1;
00273 }
00274 
00275 static size_t
00276 drm_intel_probe_agp_aperture_size(int fd)
00277 {
00278        struct pci_device *pci_dev;
00279        size_t size = 0;
00280        int ret;
00281 
00282        ret = pci_system_init();
00283        if (ret)
00284               goto err;
00285 
00286        /* XXX handle multiple adaptors? */
00287        pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
00288        if (pci_dev == NULL)
00289               goto err;
00290 
00291        ret = pci_device_probe(pci_dev);
00292        if (ret)
00293               goto err;
00294 
00295        size = pci_dev->regions[2].size;
00296 err:
00297        pci_system_cleanup ();
00298        return size;
00299 }
00300 
00301 int drm_intel_get_aperture_sizes(int fd,
00302                              size_t *mappable,
00303                              size_t *total)
00304 {
00305 
00306        struct drm_i915_gem_get_aperture aperture;
00307        int ret;
00308 
00309        ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
00310        if (ret)
00311               return ret;
00312 
00313        *mappable = 0;
00314        /* XXX add a query for the kernel value? */
00315        if (*mappable == 0)
00316               *mappable = drm_intel_probe_agp_aperture_size(fd);
00317        if (*mappable == 0)
00318               *mappable = 64 * 1024 * 1024; /* minimum possible value */
00319        *total = aperture.aper_size;
00320        return 0;
00321 }