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libdrm  2.4.37
intel_aub.h
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00001 /*
00002  * Copyright © 2010 Intel Corporation
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a
00005  * copy of this software and associated documentation files (the "Software"),
00006  * to deal in the Software without restriction, including without limitation
00007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
00008  * and/or sell copies of the Software, and to permit persons to whom the
00009  * Software is furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice (including the next
00012  * paragraph) shall be included in all copies or substantial portions of the
00013  * Software.
00014  *
00015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
00018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
00020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
00021  * IN THE SOFTWARE.
00022  *
00023  * Authors:
00024  *    Eric Anholt <eric@anholt.net>
00025  *
00026  */
00027 
00040 #ifndef _INTEL_AUB_H
00041 #define _INTEL_AUB_H
00042 
00043 #define AUB_MI_NOOP                (0)
00044 #define AUB_MI_BATCH_BUFFER_START  (0x31 << 23)
00045 #define AUB_PIPE_CONTROL           (0x7a000002)
00046 
00047 /* DW0: instruction type. */
00048 
00049 #define CMD_AUB                    (7 << 29)
00050 
00051 #define CMD_AUB_HEADER             (CMD_AUB | (1 << 23) | (0x05 << 16))
00052 /* DW1 */
00053 # define AUB_HEADER_MAJOR_SHIFT           24
00054 # define AUB_HEADER_MINOR_SHIFT           16
00055 
00056 #define CMD_AUB_TRACE_HEADER_BLOCK (CMD_AUB | (1 << 23) | (0x41 << 16))
00057 #define CMD_AUB_DUMP_BMP           (CMD_AUB | (1 << 23) | (0x9e << 16))
00058 
00059 /* DW1 */
00060 #define AUB_TRACE_OPERATION_MASK   0x000000ff
00061 #define AUB_TRACE_OP_COMMENT              0x00000000
00062 #define AUB_TRACE_OP_DATA_WRITE           0x00000001
00063 #define AUB_TRACE_OP_COMMAND_WRITE 0x00000002
00064 #define AUB_TRACE_OP_MMIO_WRITE           0x00000003
00065 // operation = TRACE_DATA_WRITE, Type
00066 #define AUB_TRACE_TYPE_MASK        0x0000ff00
00067 #define AUB_TRACE_TYPE_NOTYPE             (0 << 8)
00068 #define AUB_TRACE_TYPE_BATCH              (1 << 8)
00069 #define AUB_TRACE_TYPE_VERTEX_BUFFER      (5 << 8)
00070 #define AUB_TRACE_TYPE_2D_MAP             (6 << 8)
00071 #define AUB_TRACE_TYPE_CUBE_MAP           (7 << 8)
00072 #define AUB_TRACE_TYPE_VOLUME_MAP  (9 << 8)
00073 #define AUB_TRACE_TYPE_1D_MAP             (10 << 8)
00074 #define AUB_TRACE_TYPE_CONSTANT_BUFFER    (11 << 8)
00075 #define AUB_TRACE_TYPE_CONSTANT_URB       (12 << 8)
00076 #define AUB_TRACE_TYPE_INDEX_BUFFER       (13 << 8)
00077 #define AUB_TRACE_TYPE_GENERAL            (14 << 8)
00078 #define AUB_TRACE_TYPE_SURFACE            (15 << 8)
00079 
00080 
00081 // operation = TRACE_COMMAND_WRITE, Type =
00082 #define AUB_TRACE_TYPE_RING_HWB           (1 << 8)
00083 #define AUB_TRACE_TYPE_RING_PRB0   (2 << 8)
00084 #define AUB_TRACE_TYPE_RING_PRB1   (3 << 8)
00085 #define AUB_TRACE_TYPE_RING_PRB2   (4 << 8)
00086 
00087 // Address space
00088 #define AUB_TRACE_ADDRESS_SPACE_MASK      0x00ff0000
00089 #define AUB_TRACE_MEMTYPE_GTT             (0 << 16)
00090 #define AUB_TRACE_MEMTYPE_LOCAL           (1 << 16)
00091 #define AUB_TRACE_MEMTYPE_NONLOCAL (2 << 16)
00092 #define AUB_TRACE_MEMTYPE_PCI             (3 << 16)
00093 #define AUB_TRACE_MEMTYPE_GTT_ENTRY     (4 << 16)
00094 
00095 /* DW2 */
00096 // operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_GENERAL_STATE
00097 #define AUB_TRACE_GENERAL_STATE_MASK      0x000000ff
00098 
00099 #define AUB_TRACE_VS_STATE         0x00000001
00100 #define AUB_TRACE_GS_STATE         0x00000002
00101 #define AUB_TRACE_CL_STATE         0x00000003
00102 #define AUB_TRACE_SF_STATE         0x00000004
00103 #define AUB_TRACE_WM_STATE         0x00000005
00104 #define AUB_TRACE_CC_STATE         0x00000006
00105 #define AUB_TRACE_CL_VP                   0x00000007
00106 #define AUB_TRACE_SF_VP                   0x00000008
00107 #define AUB_TRACE_CC_VP                   0x00000009
00108 #define AUB_TRACE_SAMPLER_STATE           0x0000000a
00109 #define AUB_TRACE_KERNEL           0x0000000b
00110 #define AUB_TRACE_SCRATCH          0x0000000c
00111 #define AUB_TRACE_SDC                     0x0000000d
00112 #define AUB_TRACE_BLEND_STATE             0x00000016
00113 #define AUB_TRACE_DEPTH_STENCIL_STATE     0x00000017
00114 
00115 // operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_SURFACE_STATE
00116 #define AUB_TRACE_SURFACE_STATE_MASK      0x00000ff00
00117 #define AUB_TRACE_BINDING_TABLE           0x000000100
00118 #define AUB_TRACE_SURFACE_STATE           0x000000200
00119 
00120 /* DW3: address */
00121 /* DW4: len */
00122 
00123 #endif /* _INTEL_AUB_H */