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libdrm  2.4.37
i915_drm.h
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00001 /*
00002  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
00003  * All Rights Reserved.
00004  *
00005  * Permission is hereby granted, free of charge, to any person obtaining a
00006  * copy of this software and associated documentation files (the
00007  * "Software"), to deal in the Software without restriction, including
00008  * without limitation the rights to use, copy, modify, merge, publish,
00009  * distribute, sub license, and/or sell copies of the Software, and to
00010  * permit persons to whom the Software is furnished to do so, subject to
00011  * the following conditions:
00012  *
00013  * The above copyright notice and this permission notice (including the
00014  * next paragraph) shall be included in all copies or substantial portions
00015  * of the Software.
00016  *
00017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00018  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
00020  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
00021  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
00022  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
00023  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00024  *
00025  */
00026 
00027 #ifndef _I915_DRM_H_
00028 #define _I915_DRM_H_
00029 
00030 #include "drm.h"
00031 
00032 /* Please note that modifications to all structs defined here are
00033  * subject to backwards-compatibility constraints.
00034  */
00035 
00036 
00037 /* Each region is a minimum of 16k, and there are at most 255 of them.
00038  */
00039 #define I915_NR_TEX_REGIONS 255    /* table size 2k - maximum due to use
00040                              * of chars for next/prev indices */
00041 #define I915_LOG_MIN_TEX_REGION_SIZE 14
00042 
00043 typedef struct _drm_i915_init {
00044        enum {
00045               I915_INIT_DMA = 0x01,
00046               I915_CLEANUP_DMA = 0x02,
00047               I915_RESUME_DMA = 0x03
00048        } func;
00049        unsigned int mmio_offset;
00050        int sarea_priv_offset;
00051        unsigned int ring_start;
00052        unsigned int ring_end;
00053        unsigned int ring_size;
00054        unsigned int front_offset;
00055        unsigned int back_offset;
00056        unsigned int depth_offset;
00057        unsigned int w;
00058        unsigned int h;
00059        unsigned int pitch;
00060        unsigned int pitch_bits;
00061        unsigned int back_pitch;
00062        unsigned int depth_pitch;
00063        unsigned int cpp;
00064        unsigned int chipset;
00065 } drm_i915_init_t;
00066 
00067 typedef struct _drm_i915_sarea {
00068        struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
00069        int last_upload;     /* last time texture was uploaded */
00070        int last_enqueue;    /* last time a buffer was enqueued */
00071        int last_dispatch;   /* age of the most recently dispatched buffer */
00072        int ctxOwner;        /* last context to upload state */
00073        int texAge;
00074        int pf_enabled;             /* is pageflipping allowed? */
00075        int pf_active;
00076        int pf_current_page; /* which buffer is being displayed? */
00077        int perf_boxes;             /* performance boxes to be displayed */
00078        int width, height;      /* screen size in pixels */
00079 
00080        drm_handle_t front_handle;
00081        int front_offset;
00082        int front_size;
00083 
00084        drm_handle_t back_handle;
00085        int back_offset;
00086        int back_size;
00087 
00088        drm_handle_t depth_handle;
00089        int depth_offset;
00090        int depth_size;
00091 
00092        drm_handle_t tex_handle;
00093        int tex_offset;
00094        int tex_size;
00095        int log_tex_granularity;
00096        int pitch;
00097        int rotation;           /* 0, 90, 180 or 270 */
00098        int rotated_offset;
00099        int rotated_size;
00100        int rotated_pitch;
00101        int virtualX, virtualY;
00102 
00103        unsigned int front_tiled;
00104        unsigned int back_tiled;
00105        unsigned int depth_tiled;
00106        unsigned int rotated_tiled;
00107        unsigned int rotated2_tiled;
00108 
00109        int pipeA_x;
00110        int pipeA_y;
00111        int pipeA_w;
00112        int pipeA_h;
00113        int pipeB_x;
00114        int pipeB_y;
00115        int pipeB_w;
00116        int pipeB_h;
00117 
00118        /* fill out some space for old userspace triple buffer */
00119        drm_handle_t unused_handle;
00120        __u32 unused1, unused2, unused3;
00121 
00122        /* buffer object handles for static buffers. May change
00123         * over the lifetime of the client.
00124         */
00125        __u32 front_bo_handle;
00126        __u32 back_bo_handle;
00127        __u32 unused_bo_handle;
00128        __u32 depth_bo_handle;
00129 
00130 } drm_i915_sarea_t;
00131 
00132 /* due to userspace building against these headers we need some compat here */
00133 #define planeA_x pipeA_x
00134 #define planeA_y pipeA_y
00135 #define planeA_w pipeA_w
00136 #define planeA_h pipeA_h
00137 #define planeB_x pipeB_x
00138 #define planeB_y pipeB_y
00139 #define planeB_w pipeB_w
00140 #define planeB_h pipeB_h
00141 
00142 /* Flags for perf_boxes
00143  */
00144 #define I915_BOX_RING_EMPTY    0x1
00145 #define I915_BOX_FLIP          0x2
00146 #define I915_BOX_WAIT          0x4
00147 #define I915_BOX_TEXTURE_LOAD  0x8
00148 #define I915_BOX_LOST_CONTEXT  0x10
00149 
00150 /* I915 specific ioctls
00151  * The device specific ioctl range is 0x40 to 0x79.
00152  */
00153 #define DRM_I915_INIT              0x00
00154 #define DRM_I915_FLUSH             0x01
00155 #define DRM_I915_FLIP              0x02
00156 #define DRM_I915_BATCHBUFFER       0x03
00157 #define DRM_I915_IRQ_EMIT   0x04
00158 #define DRM_I915_IRQ_WAIT   0x05
00159 #define DRM_I915_GETPARAM   0x06
00160 #define DRM_I915_SETPARAM   0x07
00161 #define DRM_I915_ALLOC             0x08
00162 #define DRM_I915_FREE              0x09
00163 #define DRM_I915_INIT_HEAP  0x0a
00164 #define DRM_I915_CMDBUFFER  0x0b
00165 #define DRM_I915_DESTROY_HEAP      0x0c
00166 #define DRM_I915_SET_VBLANK_PIPE   0x0d
00167 #define DRM_I915_GET_VBLANK_PIPE   0x0e
00168 #define DRM_I915_VBLANK_SWAP       0x0f
00169 #define DRM_I915_HWS_ADDR   0x11
00170 #define DRM_I915_GEM_INIT   0x13
00171 #define DRM_I915_GEM_EXECBUFFER    0x14
00172 #define DRM_I915_GEM_PIN    0x15
00173 #define DRM_I915_GEM_UNPIN  0x16
00174 #define DRM_I915_GEM_BUSY   0x17
00175 #define DRM_I915_GEM_THROTTLE      0x18
00176 #define DRM_I915_GEM_ENTERVT       0x19
00177 #define DRM_I915_GEM_LEAVEVT       0x1a
00178 #define DRM_I915_GEM_CREATE 0x1b
00179 #define DRM_I915_GEM_PREAD  0x1c
00180 #define DRM_I915_GEM_PWRITE 0x1d
00181 #define DRM_I915_GEM_MMAP   0x1e
00182 #define DRM_I915_GEM_SET_DOMAIN    0x1f
00183 #define DRM_I915_GEM_SW_FINISH     0x20
00184 #define DRM_I915_GEM_SET_TILING    0x21
00185 #define DRM_I915_GEM_GET_TILING    0x22
00186 #define DRM_I915_GEM_GET_APERTURE 0x23
00187 #define DRM_I915_GEM_MMAP_GTT      0x24
00188 #define DRM_I915_GET_PIPE_FROM_CRTC_ID    0x25
00189 #define DRM_I915_GEM_MADVISE       0x26
00190 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
00191 #define DRM_I915_OVERLAY_ATTRS     0x28
00192 #define DRM_I915_GEM_EXECBUFFER2   0x29
00193 #define DRM_I915_GET_SPRITE_COLORKEY      0x2a
00194 #define DRM_I915_SET_SPRITE_COLORKEY      0x2b
00195 #define DRM_I915_GEM_WAIT   0x2c
00196 #define DRM_I915_GEM_CONTEXT_CREATE       0x2d
00197 #define DRM_I915_GEM_CONTEXT_DESTROY      0x2e
00198 
00199 #define DRM_IOCTL_I915_INIT        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
00200 #define DRM_IOCTL_I915_FLUSH              DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
00201 #define DRM_IOCTL_I915_FLIP        DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
00202 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
00203 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
00204 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
00205 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
00206 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
00207 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
00208 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
00209 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
00210 #define DRM_IOCTL_I915_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
00211 #define DRM_IOCTL_I915_DESTROY_HEAP       DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
00212 #define DRM_IOCTL_I915_SET_VBLANK_PIPE    DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
00213 #define DRM_IOCTL_I915_GET_VBLANK_PIPE    DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
00214 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
00215 #define DRM_IOCTL_I915_HWS_ADDR           DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
00216 #define DRM_IOCTL_I915_GEM_INIT           DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
00217 #define DRM_IOCTL_I915_GEM_EXECBUFFER     DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
00218 #define DRM_IOCTL_I915_GEM_EXECBUFFER2    DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
00219 #define DRM_IOCTL_I915_GEM_PIN            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
00220 #define DRM_IOCTL_I915_GEM_UNPIN   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
00221 #define DRM_IOCTL_I915_GEM_BUSY           DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
00222 #define DRM_IOCTL_I915_GEM_THROTTLE       DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
00223 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
00224 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
00225 #define DRM_IOCTL_I915_GEM_CREATE  DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
00226 #define DRM_IOCTL_I915_GEM_PREAD   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
00227 #define DRM_IOCTL_I915_GEM_PWRITE  DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
00228 #define DRM_IOCTL_I915_GEM_MMAP           DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
00229 #define DRM_IOCTL_I915_GEM_MMAP_GTT       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
00230 #define DRM_IOCTL_I915_GEM_SET_DOMAIN     DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
00231 #define DRM_IOCTL_I915_GEM_SW_FINISH      DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
00232 #define DRM_IOCTL_I915_GEM_SET_TILING     DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
00233 #define DRM_IOCTL_I915_GEM_GET_TILING     DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
00234 #define DRM_IOCTL_I915_GEM_GET_APERTURE   DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
00235 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
00236 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
00237 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
00238 #define DRM_IOCTL_I915_OVERLAY_ATTRS      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
00239 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
00240 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
00241 #define DRM_IOCTL_I915_GEM_WAIT           DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
00242 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
00243 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
00244 
00245 /* Allow drivers to submit batchbuffers directly to hardware, relying
00246  * on the security mechanisms provided by hardware.
00247  */
00248 typedef struct drm_i915_batchbuffer {
00249        int start;           /* agp offset */
00250        int used;            /* nr bytes in use */
00251        int DR1;             /* hw flags for GFX_OP_DRAWRECT_INFO */
00252        int DR4;             /* window origin for GFX_OP_DRAWRECT_INFO */
00253        int num_cliprects;   /* mulitpass with multiple cliprects? */
00254        struct drm_clip_rect *cliprects;   /* pointer to userspace cliprects */
00255 } drm_i915_batchbuffer_t;
00256 
00257 /* As above, but pass a pointer to userspace buffer which can be
00258  * validated by the kernel prior to sending to hardware.
00259  */
00260 typedef struct _drm_i915_cmdbuffer {
00261        char *buf;    /* pointer to userspace command buffer */
00262        int sz;                     /* nr bytes in buf */
00263        int DR1;             /* hw flags for GFX_OP_DRAWRECT_INFO */
00264        int DR4;             /* window origin for GFX_OP_DRAWRECT_INFO */
00265        int num_cliprects;   /* mulitpass with multiple cliprects? */
00266        struct drm_clip_rect *cliprects;   /* pointer to userspace cliprects */
00267 } drm_i915_cmdbuffer_t;
00268 
00269 /* Userspace can request & wait on irq's:
00270  */
00271 typedef struct drm_i915_irq_emit {
00272        int *irq_seq;
00273 } drm_i915_irq_emit_t;
00274 
00275 typedef struct drm_i915_irq_wait {
00276        int irq_seq;
00277 } drm_i915_irq_wait_t;
00278 
00279 /* Ioctl to query kernel params:
00280  */
00281 #define I915_PARAM_IRQ_ACTIVE            1
00282 #define I915_PARAM_ALLOW_BATCHBUFFER     2
00283 #define I915_PARAM_LAST_DISPATCH         3
00284 #define I915_PARAM_CHIPSET_ID            4
00285 #define I915_PARAM_HAS_GEM               5
00286 #define I915_PARAM_NUM_FENCES_AVAIL      6
00287 #define I915_PARAM_HAS_OVERLAY           7
00288 #define I915_PARAM_HAS_PAGEFLIPPING        8
00289 #define I915_PARAM_HAS_EXECBUF2          9
00290 #define I915_PARAM_HAS_BSD          10
00291 #define I915_PARAM_HAS_BLT          11
00292 #define I915_PARAM_HAS_RELAXED_FENCING     12
00293 #define I915_PARAM_HAS_COHERENT_RINGS      13
00294 #define I915_PARAM_HAS_EXEC_CONSTANTS      14
00295 #define I915_PARAM_HAS_RELAXED_DELTA       15
00296 #define I915_PARAM_HAS_GEN7_SOL_RESET      16
00297 #define I915_PARAM_HAS_LLC                 17
00298 #define I915_PARAM_HAS_ALIASING_PPGTT      18
00299 #define I915_PARAM_HAS_WAIT_TIMEOUT        19
00300 
00301 typedef struct drm_i915_getparam {
00302        int param;
00303        int *value;
00304 } drm_i915_getparam_t;
00305 
00306 /* Ioctl to set kernel params:
00307  */
00308 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
00309 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
00310 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
00311 #define I915_SETPARAM_NUM_USED_FENCES                     4
00312 
00313 typedef struct drm_i915_setparam {
00314        int param;
00315        int value;
00316 } drm_i915_setparam_t;
00317 
00318 /* A memory manager for regions of shared memory:
00319  */
00320 #define I915_MEM_REGION_AGP 1
00321 
00322 typedef struct drm_i915_mem_alloc {
00323        int region;
00324        int alignment;
00325        int size;
00326        int *region_offset;  /* offset from start of fb or agp */
00327 } drm_i915_mem_alloc_t;
00328 
00329 typedef struct drm_i915_mem_free {
00330        int region;
00331        int region_offset;
00332 } drm_i915_mem_free_t;
00333 
00334 typedef struct drm_i915_mem_init_heap {
00335        int region;
00336        int size;
00337        int start;
00338 } drm_i915_mem_init_heap_t;
00339 
00340 /* Allow memory manager to be torn down and re-initialized (eg on
00341  * rotate):
00342  */
00343 typedef struct drm_i915_mem_destroy_heap {
00344        int region;
00345 } drm_i915_mem_destroy_heap_t;
00346 
00347 /* Allow X server to configure which pipes to monitor for vblank signals
00348  */
00349 #define       DRM_I915_VBLANK_PIPE_A      1
00350 #define       DRM_I915_VBLANK_PIPE_B      2
00351 
00352 typedef struct drm_i915_vblank_pipe {
00353        int pipe;
00354 } drm_i915_vblank_pipe_t;
00355 
00356 /* Schedule buffer swap at given vertical blank:
00357  */
00358 typedef struct drm_i915_vblank_swap {
00359        drm_drawable_t drawable;
00360        enum drm_vblank_seq_type seqtype;
00361        unsigned int sequence;
00362 } drm_i915_vblank_swap_t;
00363 
00364 typedef struct drm_i915_hws_addr {
00365        __u64 addr;
00366 } drm_i915_hws_addr_t;
00367 
00368 struct drm_i915_gem_init {
00373        __u64 gtt_start;
00378        __u64 gtt_end;
00379 };
00380 
00381 struct drm_i915_gem_create {
00387        __u64 size;
00393        __u32 handle;
00394        __u32 pad;
00395 };
00396 
00397 struct drm_i915_gem_pread {
00399        __u32 handle;
00400        __u32 pad;
00402        __u64 offset;
00404        __u64 size;
00410        __u64 data_ptr;
00411 };
00412 
00413 struct drm_i915_gem_pwrite {
00415        __u32 handle;
00416        __u32 pad;
00418        __u64 offset;
00420        __u64 size;
00426        __u64 data_ptr;
00427 };
00428 
00429 struct drm_i915_gem_mmap {
00431        __u32 handle;
00432        __u32 pad;
00434        __u64 offset;
00440        __u64 size;
00446        __u64 addr_ptr;
00447 };
00448 
00449 struct drm_i915_gem_mmap_gtt {
00451        __u32 handle;
00452        __u32 pad;
00458        __u64 offset;
00459 };
00460 
00461 struct drm_i915_gem_set_domain {
00463        __u32 handle;
00464 
00466        __u32 read_domains;
00467 
00469        __u32 write_domain;
00470 };
00471 
00472 struct drm_i915_gem_sw_finish {
00474        __u32 handle;
00475 };
00476 
00477 struct drm_i915_gem_relocation_entry {
00486        __u32 target_handle;
00487 
00492        __u32 delta;
00493 
00495        __u64 offset;
00496 
00505        __u64 presumed_offset;
00506 
00510        __u32 read_domains;
00511 
00519        __u32 write_domain;
00520 };
00521 
00530 #define I915_GEM_DOMAIN_CPU        0x00000001
00531 
00532 #define I915_GEM_DOMAIN_RENDER            0x00000002
00533 
00534 #define I915_GEM_DOMAIN_SAMPLER           0x00000004
00535 
00536 #define I915_GEM_DOMAIN_COMMAND           0x00000008
00537 
00538 #define I915_GEM_DOMAIN_INSTRUCTION       0x00000010
00539 
00540 #define I915_GEM_DOMAIN_VERTEX            0x00000020
00541 
00542 #define I915_GEM_DOMAIN_GTT        0x00000040
00543 
00545 struct drm_i915_gem_exec_object {
00550        __u32 handle;
00551 
00553        __u32 relocation_count;
00558        __u64 relocs_ptr;
00559 
00561        __u64 alignment;
00562 
00567        __u64 offset;
00568 };
00569 
00570 struct drm_i915_gem_execbuffer {
00581        __u64 buffers_ptr;
00582        __u32 buffer_count;
00583 
00585        __u32 batch_start_offset;
00587        __u32 batch_len;
00588        __u32 DR1;
00589        __u32 DR4;
00590        __u32 num_cliprects;
00592        __u64 cliprects_ptr;
00593 };
00594 
00595 struct drm_i915_gem_exec_object2 {
00600        __u32 handle;
00601 
00603        __u32 relocation_count;
00608        __u64 relocs_ptr;
00609 
00611        __u64 alignment;
00612 
00617        __u64 offset;
00618 
00619 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
00620        __u64 flags;
00621        __u64 rsvd1;
00622        __u64 rsvd2;
00623 };
00624 
00625 struct drm_i915_gem_execbuffer2 {
00629        __u64 buffers_ptr;
00630        __u32 buffer_count;
00631 
00633        __u32 batch_start_offset;
00635        __u32 batch_len;
00636        __u32 DR1;
00637        __u32 DR4;
00638        __u32 num_cliprects;
00640        __u64 cliprects_ptr;
00641 #define I915_EXEC_RING_MASK              (7<<0)
00642 #define I915_EXEC_DEFAULT                (0<<0)
00643 #define I915_EXEC_RENDER                 (1<<0)
00644 #define I915_EXEC_BSD                    (2<<0)
00645 #define I915_EXEC_BLT                    (3<<0)
00646 
00647 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
00648  * Gen6+ only supports relative addressing to dynamic state (default) and
00649  * absolute addressing.
00650  *
00651  * These flags are ignored for the BSD and BLT rings.
00652  */
00653 #define I915_EXEC_CONSTANTS_MASK   (3<<6)
00654 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
00655 #define I915_EXEC_CONSTANTS_ABSOLUTE      (1<<6)
00656 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
00657        __u64 flags;
00658        __u64 rsvd1; /* now used for context info */
00659        __u64 rsvd2;
00660 };
00661 
00663 #define I915_EXEC_GEN7_SOL_RESET   (1<<8)
00664 
00665 #define I915_EXEC_CONTEXT_ID_MASK  (0xffffffff)
00666 #define i915_execbuffer2_set_context_id(eb2, context) \
00667        (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
00668 #define i915_execbuffer2_get_context_id(eb2) \
00669        ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
00670 
00671 struct drm_i915_gem_pin {
00673        __u32 handle;
00674        __u32 pad;
00675 
00677        __u64 alignment;
00678 
00680        __u64 offset;
00681 };
00682 
00683 struct drm_i915_gem_unpin {
00685        __u32 handle;
00686        __u32 pad;
00687 };
00688 
00689 struct drm_i915_gem_busy {
00691        __u32 handle;
00692 
00694        __u32 busy;
00695 };
00696 
00697 #define I915_TILING_NONE    0
00698 #define I915_TILING_X              1
00699 #define I915_TILING_Y              2
00700 
00701 #define I915_BIT_6_SWIZZLE_NONE           0
00702 #define I915_BIT_6_SWIZZLE_9              1
00703 #define I915_BIT_6_SWIZZLE_9_10           2
00704 #define I915_BIT_6_SWIZZLE_9_11           3
00705 #define I915_BIT_6_SWIZZLE_9_10_11 4
00706 /* Not seen by userland */
00707 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
00708 /* Seen by userland. */
00709 #define I915_BIT_6_SWIZZLE_9_17           6
00710 #define I915_BIT_6_SWIZZLE_9_10_17 7
00711 
00712 struct drm_i915_gem_set_tiling {
00714        __u32 handle;
00715 
00728        __u32 tiling_mode;
00729 
00734        __u32 stride;
00735 
00740        __u32 swizzle_mode;
00741 };
00742 
00743 struct drm_i915_gem_get_tiling {
00745        __u32 handle;
00746 
00751        __u32 tiling_mode;
00752 
00757        __u32 swizzle_mode;
00758 };
00759 
00760 struct drm_i915_gem_get_aperture {
00762        __u64 aper_size;
00763 
00768        __u64 aper_available_size;
00769 };
00770 
00771 struct drm_i915_get_pipe_from_crtc_id {
00773        __u32 crtc_id;
00774 
00776        __u32 pipe;
00777 };
00778 
00779 #define I915_MADV_WILLNEED 0
00780 #define I915_MADV_DONTNEED 1
00781 #define __I915_MADV_PURGED 2 /* internal state */
00782 
00783 struct drm_i915_gem_madvise {
00785        __u32 handle;
00786 
00787        /* Advice: either the buffer will be needed again in the near future,
00788         *         or wont be and could be discarded under memory pressure.
00789         */
00790        __u32 madv;
00791 
00793        __u32 retained;
00794 };
00795 
00796 /* flags */
00797 #define I915_OVERLAY_TYPE_MASK            0xff
00798 #define I915_OVERLAY_YUV_PLANAR    0x01
00799 #define I915_OVERLAY_YUV_PACKED    0x02
00800 #define I915_OVERLAY_RGB           0x03
00801 
00802 #define I915_OVERLAY_DEPTH_MASK           0xff00
00803 #define I915_OVERLAY_RGB24         0x1000
00804 #define I915_OVERLAY_RGB16         0x2000
00805 #define I915_OVERLAY_RGB15         0x3000
00806 #define I915_OVERLAY_YUV422        0x0100
00807 #define I915_OVERLAY_YUV411        0x0200
00808 #define I915_OVERLAY_YUV420        0x0300
00809 #define I915_OVERLAY_YUV410        0x0400
00810 
00811 #define I915_OVERLAY_SWAP_MASK            0xff0000
00812 #define I915_OVERLAY_NO_SWAP              0x000000
00813 #define I915_OVERLAY_UV_SWAP              0x010000
00814 #define I915_OVERLAY_Y_SWAP        0x020000
00815 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
00816 
00817 #define I915_OVERLAY_FLAGS_MASK           0xff000000
00818 #define I915_OVERLAY_ENABLE        0x01000000
00819 
00820 struct drm_intel_overlay_put_image {
00821        /* various flags and src format description */
00822        __u32 flags;
00823        /* source picture description */
00824        __u32 bo_handle;
00825        /* stride values and offsets are in bytes, buffer relative */
00826        __u16 stride_Y; /* stride for packed formats */
00827        __u16 stride_UV;
00828        __u32 offset_Y; /* offset for packet formats */
00829        __u32 offset_U;
00830        __u32 offset_V;
00831        /* in pixels */
00832        __u16 src_width;
00833        __u16 src_height;
00834        /* to compensate the scaling factors for partially covered surfaces */
00835        __u16 src_scan_width;
00836        __u16 src_scan_height;
00837        /* output crtc description */
00838        __u32 crtc_id;
00839        __u16 dst_x;
00840        __u16 dst_y;
00841        __u16 dst_width;
00842        __u16 dst_height;
00843 };
00844 
00845 /* flags */
00846 #define I915_OVERLAY_UPDATE_ATTRS  (1<<0)
00847 #define I915_OVERLAY_UPDATE_GAMMA  (1<<1)
00848 struct drm_intel_overlay_attrs {
00849        __u32 flags;
00850        __u32 color_key;
00851        __s32 brightness;
00852        __u32 contrast;
00853        __u32 saturation;
00854        __u32 gamma0;
00855        __u32 gamma1;
00856        __u32 gamma2;
00857        __u32 gamma3;
00858        __u32 gamma4;
00859        __u32 gamma5;
00860 };
00861 
00862 /*
00863  * Intel sprite handling
00864  *
00865  * Color keying works with a min/mask/max tuple.  Both source and destination
00866  * color keying is allowed.
00867  *
00868  * Source keying:
00869  * Sprite pixels within the min & max values, masked against the color channels
00870  * specified in the mask field, will be transparent.  All other pixels will
00871  * be displayed on top of the primary plane.  For RGB surfaces, only the min
00872  * and mask fields will be used; ranged compares are not allowed.
00873  *
00874  * Destination keying:
00875  * Primary plane pixels that match the min value, masked against the color
00876  * channels specified in the mask field, will be replaced by corresponding
00877  * pixels from the sprite plane.
00878  *
00879  * Note that source & destination keying are exclusive; only one can be
00880  * active on a given plane.
00881  */
00882 
00883 #define I915_SET_COLORKEY_NONE            (1<<0) /* disable color key matching */
00884 #define I915_SET_COLORKEY_DESTINATION     (1<<1)
00885 #define I915_SET_COLORKEY_SOURCE   (1<<2)
00886 struct drm_intel_sprite_colorkey {
00887        __u32 plane_id;
00888        __u32 min_value;
00889        __u32 channel_mask;
00890        __u32 max_value;
00891        __u32 flags;
00892 };
00893 
00894 struct drm_i915_gem_wait {
00896        __u32 bo_handle;
00897        __u32 flags;
00899        __s64 timeout_ns;
00900 };
00901 
00902 struct drm_i915_gem_context_create {
00903        /*  output: id of new context*/
00904        __u32 ctx_id;
00905        __u32 pad;
00906 };
00907 
00908 struct drm_i915_gem_context_destroy {
00909        __u32 ctx_id;
00910        __u32 pad;
00911 };
00912 
00913 #endif                      /* _I915_DRM_H_ */