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libdrm  2.4.37
i830_drm.h
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00001 #ifndef _I830_DRM_H_
00002 #define _I830_DRM_H_
00003 
00004 /* WARNING: These defines must be the same as what the Xserver uses.
00005  * if you change them, you must change the defines in the Xserver.
00006  *
00007  * KW: Actually, you can't ever change them because doing so would
00008  * break backwards compatibility.
00009  */
00010 
00011 #ifndef _I830_DEFINES_
00012 #define _I830_DEFINES_
00013 
00014 #define I830_DMA_BUF_ORDER         12
00015 #define I830_DMA_BUF_SZ                   (1<<I830_DMA_BUF_ORDER)
00016 #define I830_DMA_BUF_NR                   256
00017 #define I830_NR_SAREA_CLIPRECTS           8
00018 
00019 /* Each region is a minimum of 64k, and there are at most 64 of them.
00020  */
00021 #define I830_NR_TEX_REGIONS 64
00022 #define I830_LOG_MIN_TEX_REGION_SIZE 16
00023 
00024 /* KW: These aren't correct but someone set them to two and then
00025  * released the module.  Now we can't change them as doing so would
00026  * break backwards compatibility.
00027  */
00028 #define I830_TEXTURE_COUNT  2
00029 #define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT
00030 
00031 #define I830_TEXBLEND_SIZE  12     /* (4 args + op) * 2 + COLOR_FACTOR */
00032 
00033 #define I830_UPLOAD_CTX                   0x1
00034 #define I830_UPLOAD_BUFFERS        0x2
00035 #define I830_UPLOAD_CLIPRECTS             0x4
00036 #define I830_UPLOAD_TEX0_IMAGE            0x100  /* handled clientside */
00037 #define I830_UPLOAD_TEX0_CUBE             0x200  /* handled clientside */
00038 #define I830_UPLOAD_TEX1_IMAGE            0x400  /* handled clientside */
00039 #define I830_UPLOAD_TEX1_CUBE             0x800  /* handled clientside */
00040 #define I830_UPLOAD_TEX2_IMAGE            0x1000 /* handled clientside */
00041 #define I830_UPLOAD_TEX2_CUBE             0x2000 /* handled clientside */
00042 #define I830_UPLOAD_TEX3_IMAGE            0x4000 /* handled clientside */
00043 #define I830_UPLOAD_TEX3_CUBE             0x8000 /* handled clientside */
00044 #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2))
00045 #define I830_UPLOAD_TEX_N_CUBE(n)  (0x200 << (n * 2))
00046 #define I830_UPLOAD_TEXIMAGE_MASK  0xff00
00047 #define I830_UPLOAD_TEX0                  0x10000
00048 #define I830_UPLOAD_TEX1                  0x20000
00049 #define I830_UPLOAD_TEX2                  0x40000
00050 #define I830_UPLOAD_TEX3                  0x80000
00051 #define I830_UPLOAD_TEX_N(n)              (0x10000 << (n))
00052 #define I830_UPLOAD_TEX_MASK              0xf0000
00053 #define I830_UPLOAD_TEXBLEND0             0x100000
00054 #define I830_UPLOAD_TEXBLEND1             0x200000
00055 #define I830_UPLOAD_TEXBLEND2             0x400000
00056 #define I830_UPLOAD_TEXBLEND3             0x800000
00057 #define I830_UPLOAD_TEXBLEND_N(n)  (0x100000 << (n))
00058 #define I830_UPLOAD_TEXBLEND_MASK  0xf00000
00059 #define I830_UPLOAD_TEX_PALETTE_N(n)    (0x1000000 << (n))
00060 #define I830_UPLOAD_TEX_PALETTE_SHARED    0x4000000
00061 #define I830_UPLOAD_STIPPLE        0x8000000
00062 
00063 /* Indices into buf.Setup where various bits of state are mirrored per
00064  * context and per buffer.  These can be fired at the card as a unit,
00065  * or in a piecewise fashion as required.
00066  */
00067 
00068 /* Destbuffer state
00069  *    - backbuffer linear offset and pitch -- invarient in the current dri
00070  *    - zbuffer linear offset and pitch -- also invarient
00071  *    - drawing origin in back and depth buffers.
00072  *
00073  * Keep the depth/back buffer state here to accommodate private buffers
00074  * in the future.
00075  */
00076 
00077 #define I830_DESTREG_CBUFADDR 0
00078 #define I830_DESTREG_DBUFADDR 1
00079 #define I830_DESTREG_DV0 2
00080 #define I830_DESTREG_DV1 3
00081 #define I830_DESTREG_SENABLE 4
00082 #define I830_DESTREG_SR0 5
00083 #define I830_DESTREG_SR1 6
00084 #define I830_DESTREG_SR2 7
00085 #define I830_DESTREG_DR0 8
00086 #define I830_DESTREG_DR1 9
00087 #define I830_DESTREG_DR2 10
00088 #define I830_DESTREG_DR3 11
00089 #define I830_DESTREG_DR4 12
00090 #define I830_DEST_SETUP_SIZE 13
00091 
00092 /* Context state
00093  */
00094 #define I830_CTXREG_STATE1         0
00095 #define I830_CTXREG_STATE2         1
00096 #define I830_CTXREG_STATE3         2
00097 #define I830_CTXREG_STATE4         3
00098 #define I830_CTXREG_STATE5         4
00099 #define I830_CTXREG_IALPHAB        5
00100 #define I830_CTXREG_STENCILTST            6
00101 #define I830_CTXREG_ENABLES_1             7
00102 #define I830_CTXREG_ENABLES_2             8
00103 #define I830_CTXREG_AA                    9
00104 #define I830_CTXREG_FOGCOLOR              10
00105 #define I830_CTXREG_BLENDCOLR0            11
00106 #define I830_CTXREG_BLENDCOLR             12     /* Dword 1 of 2 dword command */
00107 #define I830_CTXREG_VF                    13
00108 #define I830_CTXREG_VF2                   14
00109 #define I830_CTXREG_MCSB0          15
00110 #define I830_CTXREG_MCSB1          16
00111 #define I830_CTX_SETUP_SIZE        17
00112 
00113 /* 1.3: Stipple state
00114  */
00115 #define I830_STPREG_ST0 0
00116 #define I830_STPREG_ST1 1
00117 #define I830_STP_SETUP_SIZE 2
00118 
00119 /* Texture state (per tex unit)
00120  */
00121 
00122 #define I830_TEXREG_MI0     0      /* GFX_OP_MAP_INFO (6 dwords) */
00123 #define I830_TEXREG_MI1     1
00124 #define I830_TEXREG_MI2     2
00125 #define I830_TEXREG_MI3     3
00126 #define I830_TEXREG_MI4     4
00127 #define I830_TEXREG_MI5     5
00128 #define I830_TEXREG_MF      6      /* GFX_OP_MAP_FILTER */
00129 #define I830_TEXREG_MLC     7      /* GFX_OP_MAP_LOD_CTL */
00130 #define I830_TEXREG_MLL     8      /* GFX_OP_MAP_LOD_LIMITS */
00131 #define I830_TEXREG_MCS     9      /* GFX_OP_MAP_COORD_SETS */
00132 #define I830_TEX_SETUP_SIZE 10
00133 
00134 #define I830_TEXREG_TM0LI      0   /* load immediate 2 texture map n */
00135 #define I830_TEXREG_TM0S0      1
00136 #define I830_TEXREG_TM0S1      2
00137 #define I830_TEXREG_TM0S2      3
00138 #define I830_TEXREG_TM0S3      4
00139 #define I830_TEXREG_TM0S4      5
00140 #define I830_TEXREG_NOP0       6   /* noop */
00141 #define I830_TEXREG_NOP1       7   /* noop */
00142 #define I830_TEXREG_NOP2       8   /* noop */
00143 #define __I830_TEXREG_MCS      9   /* GFX_OP_MAP_COORD_SETS -- shared */
00144 #define __I830_TEX_SETUP_SIZE   10
00145 
00146 #define I830_FRONT   0x1
00147 #define I830_BACK    0x2
00148 #define I830_DEPTH   0x4
00149 
00150 #endif                      /* _I830_DEFINES_ */
00151 
00152 typedef struct _drm_i830_init {
00153        enum {
00154               I830_INIT_DMA = 0x01,
00155               I830_CLEANUP_DMA = 0x02
00156        } func;
00157        unsigned int mmio_offset;
00158        unsigned int buffers_offset;
00159        int sarea_priv_offset;
00160        unsigned int ring_start;
00161        unsigned int ring_end;
00162        unsigned int ring_size;
00163        unsigned int front_offset;
00164        unsigned int back_offset;
00165        unsigned int depth_offset;
00166        unsigned int w;
00167        unsigned int h;
00168        unsigned int pitch;
00169        unsigned int pitch_bits;
00170        unsigned int back_pitch;
00171        unsigned int depth_pitch;
00172        unsigned int cpp;
00173 } drm_i830_init_t;
00174 
00175 /* Warning: If you change the SAREA structure you must change the Xserver
00176  * structure as well */
00177 
00178 typedef struct _drm_i830_tex_region {
00179        unsigned char next, prev;   /* indices to form a circular LRU  */
00180        unsigned char in_use;       /* owned by a client, or free? */
00181        int age;             /* tracked by clients to update local LRU's */
00182 } drm_i830_tex_region_t;
00183 
00184 typedef struct _drm_i830_sarea {
00185        unsigned int ContextState[I830_CTX_SETUP_SIZE];
00186        unsigned int BufferState[I830_DEST_SETUP_SIZE];
00187        unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
00188        unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
00189        unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
00190        unsigned int Palette[2][256];
00191        unsigned int dirty;
00192 
00193        unsigned int nbox;
00194        struct drm_clip_rect boxes[I830_NR_SAREA_CLIPRECTS];
00195 
00196        /* Maintain an LRU of contiguous regions of texture space.  If
00197         * you think you own a region of texture memory, and it has an
00198         * age different to the one you set, then you are mistaken and
00199         * it has been stolen by another client.  If global texAge
00200         * hasn't changed, there is no need to walk the list.
00201         *
00202         * These regions can be used as a proxy for the fine-grained
00203         * texture information of other clients - by maintaining them
00204         * in the same lru which is used to age their own textures,
00205         * clients have an approximate lru for the whole of global
00206         * texture space, and can make informed decisions as to which
00207         * areas to kick out.  There is no need to choose whether to
00208         * kick out your own texture or someone else's - simply eject
00209         * them all in LRU order.
00210         */
00211 
00212        drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
00213        /* Last elt is sentinal */
00214        int texAge;          /* last time texture was uploaded */
00215        int last_enqueue;    /* last time a buffer was enqueued */
00216        int last_dispatch;   /* age of the most recently dispatched buffer */
00217        int last_quiescent;  /*  */
00218        int ctxOwner;        /* last context to upload state */
00219 
00220        int vertex_prim;
00221 
00222        int pf_enabled;             /* is pageflipping allowed? */
00223        int pf_active;
00224        int pf_current_page; /* which buffer is being displayed? */
00225 
00226        int perf_boxes;             /* performance boxes to be displayed */
00227 
00228        /* Here's the state for texunits 2,3:
00229         */
00230        unsigned int TexState2[I830_TEX_SETUP_SIZE];
00231        unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
00232        unsigned int TexBlendStateWordsUsed2;
00233 
00234        unsigned int TexState3[I830_TEX_SETUP_SIZE];
00235        unsigned int TexBlendState3[I830_TEXBLEND_SIZE];
00236        unsigned int TexBlendStateWordsUsed3;
00237 
00238        unsigned int StippleState[I830_STP_SETUP_SIZE];
00239 } drm_i830_sarea_t;
00240 
00241 /* Flags for perf_boxes
00242  */
00243 #define I830_BOX_RING_EMPTY    0x1 /* populated by kernel */
00244 #define I830_BOX_FLIP          0x2 /* populated by kernel */
00245 #define I830_BOX_WAIT          0x4 /* populated by kernel & client */
00246 #define I830_BOX_TEXTURE_LOAD  0x8 /* populated by kernel */
00247 #define I830_BOX_LOST_CONTEXT  0x10       /* populated by client */
00248 
00249 /* I830 specific ioctls
00250  * The device specific ioctl range is 0x40 to 0x79.
00251  */
00252 #define DRM_I830_INIT       0x00
00253 #define DRM_I830_VERTEX     0x01
00254 #define DRM_I830_CLEAR      0x02
00255 #define DRM_I830_FLUSH      0x03
00256 #define DRM_I830_GETAGE     0x04
00257 #define DRM_I830_GETBUF     0x05
00258 #define DRM_I830_SWAP       0x06
00259 #define DRM_I830_COPY       0x07
00260 #define DRM_I830_DOCOPY     0x08
00261 #define DRM_I830_FLIP       0x09
00262 #define DRM_I830_IRQ_EMIT   0x0a
00263 #define DRM_I830_IRQ_WAIT   0x0b
00264 #define DRM_I830_GETPARAM   0x0c
00265 #define DRM_I830_SETPARAM   0x0d
00266 
00267 #define DRM_IOCTL_I830_INIT        DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t)
00268 #define DRM_IOCTL_I830_VERTEX             DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t)
00269 #define DRM_IOCTL_I830_CLEAR              DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t)
00270 #define DRM_IOCTL_I830_FLUSH              DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH)
00271 #define DRM_IOCTL_I830_GETAGE             DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE)
00272 #define DRM_IOCTL_I830_GETBUF             DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t)
00273 #define DRM_IOCTL_I830_SWAP        DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP)
00274 #define DRM_IOCTL_I830_COPY        DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t)
00275 #define DRM_IOCTL_I830_DOCOPY             DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY)
00276 #define DRM_IOCTL_I830_FLIP        DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP)
00277 #define DRM_IOCTL_I830_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t)
00278 #define DRM_IOCTL_I830_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t)
00279 #define DRM_IOCTL_I830_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t)
00280 #define DRM_IOCTL_I830_SETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t)
00281 
00282 typedef struct _drm_i830_clear {
00283        int clear_color;
00284        int clear_depth;
00285        int flags;
00286        unsigned int clear_colormask;
00287        unsigned int clear_depthmask;
00288 } drm_i830_clear_t;
00289 
00290 /* These may be placeholders if we have more cliprects than
00291  * I830_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
00292  * false, indicating that the buffer will be dispatched again with a
00293  * new set of cliprects.
00294  */
00295 typedef struct _drm_i830_vertex {
00296        int idx;             /* buffer index */
00297        int used;            /* nr bytes in use */
00298        int discard;         /* client is finished with the buffer? */
00299 } drm_i830_vertex_t;
00300 
00301 typedef struct _drm_i830_copy_t {
00302        int idx;             /* buffer index */
00303        int used;            /* nr bytes in use */
00304        void *address;       /* Address to copy from */
00305 } drm_i830_copy_t;
00306 
00307 typedef struct drm_i830_dma {
00308        void *virtual;
00309        int request_idx;
00310        int request_size;
00311        int granted;
00312 } drm_i830_dma_t;
00313 
00314 /* 1.3: Userspace can request & wait on irq's:
00315  */
00316 typedef struct drm_i830_irq_emit {
00317        int *irq_seq;
00318 } drm_i830_irq_emit_t;
00319 
00320 typedef struct drm_i830_irq_wait {
00321        int irq_seq;
00322 } drm_i830_irq_wait_t;
00323 
00324 /* 1.3: New ioctl to query kernel params:
00325  */
00326 #define I830_PARAM_IRQ_ACTIVE            1
00327 
00328 typedef struct drm_i830_getparam {
00329        int param;
00330        int *value;
00331 } drm_i830_getparam_t;
00332 
00333 /* 1.3: New ioctl to set kernel params:
00334  */
00335 #define I830_SETPARAM_USE_MI_BATCHBUFFER_START            1
00336 
00337 typedef struct drm_i830_setparam {
00338        int param;
00339        int value;
00340 } drm_i830_setparam_t;
00341 
00342 #endif                      /* _I830_DRM_H_ */