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libdrm  2.4.37
i810_drm.h
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00001 #ifndef _I810_DRM_H_
00002 #define _I810_DRM_H_
00003 
00004 /* WARNING: These defines must be the same as what the Xserver uses.
00005  * if you change them, you must change the defines in the Xserver.
00006  */
00007 
00008 #ifndef _I810_DEFINES_
00009 #define _I810_DEFINES_
00010 
00011 #define I810_DMA_BUF_ORDER         12
00012 #define I810_DMA_BUF_SZ            (1<<I810_DMA_BUF_ORDER)
00013 #define I810_DMA_BUF_NR            256
00014 #define I810_NR_SAREA_CLIPRECTS    8
00015 
00016 /* Each region is a minimum of 64k, and there are at most 64 of them.
00017  */
00018 #define I810_NR_TEX_REGIONS 64
00019 #define I810_LOG_MIN_TEX_REGION_SIZE 16
00020 #endif
00021 
00022 #define I810_UPLOAD_TEX0IMAGE  0x1 /* handled clientside */
00023 #define I810_UPLOAD_TEX1IMAGE  0x2 /* handled clientside */
00024 #define I810_UPLOAD_CTX        0x4
00025 #define I810_UPLOAD_BUFFERS    0x8
00026 #define I810_UPLOAD_TEX0       0x10
00027 #define I810_UPLOAD_TEX1       0x20
00028 #define I810_UPLOAD_CLIPRECTS  0x40
00029 
00030 /* Indices into buf.Setup where various bits of state are mirrored per
00031  * context and per buffer.  These can be fired at the card as a unit,
00032  * or in a piecewise fashion as required.
00033  */
00034 
00035 /* Destbuffer state
00036  *    - backbuffer linear offset and pitch -- invarient in the current dri
00037  *    - zbuffer linear offset and pitch -- also invarient
00038  *    - drawing origin in back and depth buffers.
00039  *
00040  * Keep the depth/back buffer state here to accommodate private buffers
00041  * in the future.
00042  */
00043 #define I810_DESTREG_DI0  0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
00044 #define I810_DESTREG_DI1  1
00045 #define I810_DESTREG_DV0  2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
00046 #define I810_DESTREG_DV1  3
00047 #define I810_DESTREG_DR0  4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */
00048 #define I810_DESTREG_DR1  5
00049 #define I810_DESTREG_DR2  6
00050 #define I810_DESTREG_DR3  7
00051 #define I810_DESTREG_DR4  8
00052 #define I810_DEST_SETUP_SIZE 10
00053 
00054 /* Context state
00055  */
00056 #define I810_CTXREG_CF0   0 /* GFX_OP_COLOR_FACTOR */
00057 #define I810_CTXREG_CF1   1
00058 #define I810_CTXREG_ST0   2 /* GFX_OP_STIPPLE */
00059 #define I810_CTXREG_ST1   3
00060 #define I810_CTXREG_VF    4 /* GFX_OP_VERTEX_FMT */
00061 #define I810_CTXREG_MT    5 /* GFX_OP_MAP_TEXELS */
00062 #define I810_CTXREG_MC0   6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
00063 #define I810_CTXREG_MC1   7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
00064 #define I810_CTXREG_MC2   8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
00065 #define I810_CTXREG_MA0   9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
00066 #define I810_CTXREG_MA1   10       /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
00067 #define I810_CTXREG_MA2   11       /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
00068 #define I810_CTXREG_SDM   12       /* GFX_OP_SRC_DEST_MONO */
00069 #define I810_CTXREG_FOG   13       /* GFX_OP_FOG_COLOR */
00070 #define I810_CTXREG_B1    14       /* GFX_OP_BOOL_1 */
00071 #define I810_CTXREG_B2    15       /* GFX_OP_BOOL_2 */
00072 #define I810_CTXREG_LCS   16       /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
00073 #define I810_CTXREG_PV    17       /* GFX_OP_PV_RULE -- Invarient! */
00074 #define I810_CTXREG_ZA    18       /* GFX_OP_ZBIAS_ALPHAFUNC */
00075 #define I810_CTXREG_AA    19       /* GFX_OP_ANTIALIAS */
00076 #define I810_CTX_SETUP_SIZE 20
00077 
00078 /* Texture state (per tex unit)
00079  */
00080 #define I810_TEXREG_MI0  0  /* GFX_OP_MAP_INFO (4 dwords) */
00081 #define I810_TEXREG_MI1  1
00082 #define I810_TEXREG_MI2  2
00083 #define I810_TEXREG_MI3  3
00084 #define I810_TEXREG_MF   4  /* GFX_OP_MAP_FILTER */
00085 #define I810_TEXREG_MLC  5  /* GFX_OP_MAP_LOD_CTL */
00086 #define I810_TEXREG_MLL  6  /* GFX_OP_MAP_LOD_LIMITS */
00087 #define I810_TEXREG_MCS  7  /* GFX_OP_MAP_COORD_SETS ??? */
00088 #define I810_TEX_SETUP_SIZE 8
00089 
00090 /* Flags for clear ioctl
00091  */
00092 #define I810_FRONT   0x1
00093 #define I810_BACK    0x2
00094 #define I810_DEPTH   0x4
00095 
00096 typedef enum _drm_i810_init_func {
00097        I810_INIT_DMA = 0x01,
00098        I810_CLEANUP_DMA = 0x02,
00099        I810_INIT_DMA_1_4 = 0x03
00100 } drm_i810_init_func_t;
00101 
00102 /* This is the init structure after v1.2 */
00103 typedef struct _drm_i810_init {
00104        drm_i810_init_func_t func;
00105        unsigned int mmio_offset;
00106        unsigned int buffers_offset;
00107        int sarea_priv_offset;
00108        unsigned int ring_start;
00109        unsigned int ring_end;
00110        unsigned int ring_size;
00111        unsigned int front_offset;
00112        unsigned int back_offset;
00113        unsigned int depth_offset;
00114        unsigned int overlay_offset;
00115        unsigned int overlay_physical;
00116        unsigned int w;
00117        unsigned int h;
00118        unsigned int pitch;
00119        unsigned int pitch_bits;
00120 } drm_i810_init_t;
00121 
00122 /* This is the init structure prior to v1.2 */
00123 typedef struct _drm_i810_pre12_init {
00124        drm_i810_init_func_t func;
00125        unsigned int mmio_offset;
00126        unsigned int buffers_offset;
00127        int sarea_priv_offset;
00128        unsigned int ring_start;
00129        unsigned int ring_end;
00130        unsigned int ring_size;
00131        unsigned int front_offset;
00132        unsigned int back_offset;
00133        unsigned int depth_offset;
00134        unsigned int w;
00135        unsigned int h;
00136        unsigned int pitch;
00137        unsigned int pitch_bits;
00138 } drm_i810_pre12_init_t;
00139 
00140 /* Warning: If you change the SAREA structure you must change the Xserver
00141  * structure as well */
00142 
00143 typedef struct _drm_i810_tex_region {
00144        unsigned char next, prev;   /* indices to form a circular LRU  */
00145        unsigned char in_use;       /* owned by a client, or free? */
00146        int age;             /* tracked by clients to update local LRU's */
00147 } drm_i810_tex_region_t;
00148 
00149 typedef struct _drm_i810_sarea {
00150        unsigned int ContextState[I810_CTX_SETUP_SIZE];
00151        unsigned int BufferState[I810_DEST_SETUP_SIZE];
00152        unsigned int TexState[2][I810_TEX_SETUP_SIZE];
00153        unsigned int dirty;
00154 
00155        unsigned int nbox;
00156        struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
00157 
00158        /* Maintain an LRU of contiguous regions of texture space.  If
00159         * you think you own a region of texture memory, and it has an
00160         * age different to the one you set, then you are mistaken and
00161         * it has been stolen by another client.  If global texAge
00162         * hasn't changed, there is no need to walk the list.
00163         *
00164         * These regions can be used as a proxy for the fine-grained
00165         * texture information of other clients - by maintaining them
00166         * in the same lru which is used to age their own textures,
00167         * clients have an approximate lru for the whole of global
00168         * texture space, and can make informed decisions as to which
00169         * areas to kick out.  There is no need to choose whether to
00170         * kick out your own texture or someone else's - simply eject
00171         * them all in LRU order.
00172         */
00173 
00174        drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
00175        /* Last elt is sentinal */
00176        int texAge;          /* last time texture was uploaded */
00177        int last_enqueue;    /* last time a buffer was enqueued */
00178        int last_dispatch;   /* age of the most recently dispatched buffer */
00179        int last_quiescent;  /*  */
00180        int ctxOwner;        /* last context to upload state */
00181 
00182        int vertex_prim;
00183 
00184        int pf_enabled;             /* is pageflipping allowed? */
00185        int pf_active;
00186        int pf_current_page; /* which buffer is being displayed? */
00187 } drm_i810_sarea_t;
00188 
00189 /* WARNING: If you change any of these defines, make sure to change the
00190  * defines in the Xserver file (xf86drmMga.h)
00191  */
00192 
00193 /* i810 specific ioctls
00194  * The device specific ioctl range is 0x40 to 0x79.
00195  */
00196 #define DRM_I810_INIT              0x00
00197 #define DRM_I810_VERTEX            0x01
00198 #define DRM_I810_CLEAR             0x02
00199 #define DRM_I810_FLUSH             0x03
00200 #define DRM_I810_GETAGE            0x04
00201 #define DRM_I810_GETBUF            0x05
00202 #define DRM_I810_SWAP              0x06
00203 #define DRM_I810_COPY              0x07
00204 #define DRM_I810_DOCOPY            0x08
00205 #define DRM_I810_OV0INFO    0x09
00206 #define DRM_I810_FSTATUS    0x0a
00207 #define DRM_I810_OV0FLIP    0x0b
00208 #define DRM_I810_MC         0x0c
00209 #define DRM_I810_RSTATUS    0x0d
00210 #define DRM_I810_FLIP              0x0e
00211 
00212 #define DRM_IOCTL_I810_INIT        DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
00213 #define DRM_IOCTL_I810_VERTEX             DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
00214 #define DRM_IOCTL_I810_CLEAR              DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
00215 #define DRM_IOCTL_I810_FLUSH              DRM_IO(  DRM_COMMAND_BASE + DRM_I810_FLUSH)
00216 #define DRM_IOCTL_I810_GETAGE             DRM_IO(  DRM_COMMAND_BASE + DRM_I810_GETAGE)
00217 #define DRM_IOCTL_I810_GETBUF             DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
00218 #define DRM_IOCTL_I810_SWAP        DRM_IO(  DRM_COMMAND_BASE + DRM_I810_SWAP)
00219 #define DRM_IOCTL_I810_COPY        DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
00220 #define DRM_IOCTL_I810_DOCOPY             DRM_IO(  DRM_COMMAND_BASE + DRM_I810_DOCOPY)
00221 #define DRM_IOCTL_I810_OV0INFO            DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
00222 #define DRM_IOCTL_I810_FSTATUS            DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
00223 #define DRM_IOCTL_I810_OV0FLIP            DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
00224 #define DRM_IOCTL_I810_MC          DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
00225 #define DRM_IOCTL_I810_RSTATUS            DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
00226 #define DRM_IOCTL_I810_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
00227 
00228 typedef struct _drm_i810_clear {
00229        int clear_color;
00230        int clear_depth;
00231        int flags;
00232 } drm_i810_clear_t;
00233 
00234 /* These may be placeholders if we have more cliprects than
00235  * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
00236  * false, indicating that the buffer will be dispatched again with a
00237  * new set of cliprects.
00238  */
00239 typedef struct _drm_i810_vertex {
00240        int idx;             /* buffer index */
00241        int used;            /* nr bytes in use */
00242        int discard;         /* client is finished with the buffer? */
00243 } drm_i810_vertex_t;
00244 
00245 typedef struct _drm_i810_copy_t {
00246        int idx;             /* buffer index */
00247        int used;            /* nr bytes in use */
00248        void *address;              /* Address to copy from */
00249 } drm_i810_copy_t;
00250 
00251 #define PR_TRIANGLES         (0x0<<18)
00252 #define PR_TRISTRIP_0        (0x1<<18)
00253 #define PR_TRISTRIP_1        (0x2<<18)
00254 #define PR_TRIFAN            (0x3<<18)
00255 #define PR_POLYGON           (0x4<<18)
00256 #define PR_LINES             (0x5<<18)
00257 #define PR_LINESTRIP         (0x6<<18)
00258 #define PR_RECTS             (0x7<<18)
00259 #define PR_MASK              (0x7<<18)
00260 
00261 typedef struct drm_i810_dma {
00262        void *virtual;
00263        int request_idx;
00264        int request_size;
00265        int granted;
00266 } drm_i810_dma_t;
00267 
00268 typedef struct _drm_i810_overlay_t {
00269        unsigned int offset; /* Address of the Overlay Regs */
00270        unsigned int physical;
00271 } drm_i810_overlay_t;
00272 
00273 typedef struct _drm_i810_mc {
00274        int idx;             /* buffer index */
00275        int used;            /* nr bytes in use */
00276        int num_blocks;             /* number of GFXBlocks */
00277        int *length;         /* List of lengths for GFXBlocks (FUTURE) */
00278        unsigned int last_render;   /* Last Render Request */
00279 } drm_i810_mc_t;
00280 
00281 #endif                      /* _I810_DRM_H_ */