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glibc  2.9
brdinit.c
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00001 /* Copyright (C) 1994, 1997 Free Software Foundation, Inc.
00002    This file is part of the GNU C Library.
00003    Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
00004      On-Line Applications Research Corporation.
00005 
00006    The GNU C Library is free software; you can redistribute it and/or
00007    modify it under the terms of the GNU Lesser General Public
00008    License as published by the Free Software Foundation; either
00009    version 2.1 of the License, or (at your option) any later version.
00010 
00011    The GNU C Library is distributed in the hope that it will be useful,
00012    but WITHOUT ANY WARRANTY; without even the implied warranty of
00013    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00014    Lesser General Public License for more details.
00015 
00016    You should have received a copy of the GNU Lesser General Public
00017    License along with the GNU C Library; if not, write to the Free
00018    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00019    02111-1307 USA.  */
00020 
00021 #include <standalone.h>
00022 #include "i960ca.h"
00023 
00024 /*  _Board_Initialize()
00025 
00026 This routine initializes the board.
00027 
00028 NOTE: Only tested on a Cyclone CVME961 but should be OK on any i960ca board. */
00029 
00030 void
00031 _Board_Initialize ()
00032 {
00033   struct i80960ca_prcb   *prcb;     /* ptr to processor control block */
00034   struct i80960ca_ctltbl *ctl_tbl;  /* ptr to control table */
00035 
00036   static inline struct i80960ca_prcb *get_prcb()
00037   { register struct i80960ca_prcb *_prcb = 0;
00038     asm volatile( "calls 5; \
00039                    mov   g0,%0" \
00040                    : "=d" (_prcb) \
00041                    : "0" (_prcb) );
00042     return ( _prcb );
00043   }
00044 
00045   prcb    = get_prcb ();
00046   ctl_tbl = prcb->control_tbl;
00047 
00048   /*   The following configures the data breakpoint (which must be set
00049    *   before this is executed) to break on writes only.
00050    */
00051 
00052   ctl_tbl->bpcon &= ~0x00cc0000;
00053   reload_ctl_group (6);
00054 
00055    /*  bit 31 of the Register Cache Control can be set to
00056     *  enable an alternative caching algorithm.  It does
00057     *  not appear to help our applications.
00058     */
00059 
00060    /* Configure Number of Register Caches */
00061 
00062   prcb->reg_cache_cfg = 8;
00063   soft_reset (prcb);
00064 }