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glibc  2.9
fenv_libc.h
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00001 /* Internal libc stuff for floating point environment routines.
00002    Copyright (C) 1997, 2006, 2008 Free Software Foundation, Inc.
00003    This file is part of the GNU C Library.
00004 
00005    The GNU C Library is free software; you can redistribute it and/or
00006    modify it under the terms of the GNU Lesser General Public
00007    License as published by the Free Software Foundation; either
00008    version 2.1 of the License, or (at your option) any later version.
00009 
00010    The GNU C Library is distributed in the hope that it will be useful,
00011    but WITHOUT ANY WARRANTY; without even the implied warranty of
00012    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013    Lesser General Public License for more details.
00014 
00015    You should have received a copy of the GNU Lesser General Public
00016    License along with the GNU C Library; if not, write to the Free
00017    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00018    02111-1307 USA.  */
00019 
00020 #ifndef _FENV_LIBC_H
00021 #define _FENV_LIBC_H 1
00022 
00023 #include <fenv.h>
00024 
00025 libm_hidden_proto (__fe_nomask_env)
00026 
00027 /* The sticky bits in the FPSCR indicating exceptions have occurred.  */
00028 #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
00029 
00030 /* Equivalent to fegetenv, but returns a fenv_t instead of taking a
00031    pointer.  */
00032 #define fegetenv_register() \
00033         ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
00034 
00035 /* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
00036 #define fesetenv_register(env) \
00037         ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
00038 
00039 /* This very handy macro:
00040    - Sets the rounding mode to 'round to nearest';
00041    - Sets the processor into IEEE mode; and
00042    - Prevents exceptions from being raised for inexact results.
00043    These things happen to be exactly what you need for typical elementary
00044    functions.  */
00045 #define relax_fenv_state() asm ("mtfsfi 7,0")
00046 
00047 /* Set/clear a particular FPSCR bit (for instance,
00048    reset_fpscr_bit(FPSCR_VE);
00049    prevents INVALID exceptions from being raised).  */
00050 #define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
00051 #define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
00052 
00053 typedef union
00054 {
00055   fenv_t fenv;
00056   unsigned int l[2];
00057 } fenv_union_t;
00058 
00059 
00060 static inline int
00061 __fegetround (void)
00062 {
00063   int result;
00064   asm volatile ("mcrfs 7,7\n\t"
00065               "mfcr  %0" : "=r"(result) : : "cr7");
00066   return result & 3;
00067 }
00068 #define fegetround() __fegetround()
00069 
00070 static inline int
00071 __fesetround (int round)
00072 {
00073   if ((unsigned int) round < 2)
00074     {
00075        asm volatile ("mtfsb0 30");
00076        if ((unsigned int) round == 0)
00077          asm volatile ("mtfsb0 31");
00078        else
00079          asm volatile ("mtfsb1 31");
00080     }
00081   else
00082     {
00083        asm volatile ("mtfsb1 30");
00084        if ((unsigned int) round == 2)
00085          asm volatile ("mtfsb0 31");
00086        else
00087          asm volatile ("mtfsb1 31");
00088     }
00089 
00090   return 0;
00091 }
00092 #define fesetround(mode) __fesetround(mode)
00093 
00094 /* Definitions of all the FPSCR bit numbers */
00095 enum {
00096   FPSCR_FX = 0,    /* exception summary */
00097   FPSCR_FEX,       /* enabled exception summary */
00098   FPSCR_VX,        /* invalid operation summary */
00099   FPSCR_OX,        /* overflow */
00100   FPSCR_UX,        /* underflow */
00101   FPSCR_ZX,        /* zero divide */
00102   FPSCR_XX,        /* inexact */
00103   FPSCR_VXSNAN,    /* invalid operation for SNaN */
00104   FPSCR_VXISI,     /* invalid operation for Inf-Inf */
00105   FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
00106   FPSCR_VXZDZ,     /* invalid operation for 0/0 */
00107   FPSCR_VXIMZ,     /* invalid operation for Inf*0 */
00108   FPSCR_VXVC,      /* invalid operation for invalid compare */
00109   FPSCR_FR,        /* fraction rounded [fraction was incremented by round] */
00110   FPSCR_FI,        /* fraction inexact */
00111   FPSCR_FPRF_C,    /* result class descriptor */
00112   FPSCR_FPRF_FL,   /* result less than (usually, less than 0) */
00113   FPSCR_FPRF_FG,   /* result greater than */
00114   FPSCR_FPRF_FE,   /* result equal to */
00115   FPSCR_FPRF_FU,   /* result unordered */
00116   FPSCR_20,        /* reserved */
00117   FPSCR_VXSOFT,    /* invalid operation set by software */
00118   FPSCR_VXSQRT,    /* invalid operation for square root */
00119   FPSCR_VXCVI,     /* invalid operation for invalid integer convert */
00120   FPSCR_VE,        /* invalid operation exception enable */
00121   FPSCR_OE,        /* overflow exception enable */
00122   FPSCR_UE,        /* underflow exception enable */
00123   FPSCR_ZE,        /* zero divide exception enable */
00124   FPSCR_XE,        /* inexact exception enable */
00125   FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
00126   /* the remaining two least-significant bits keep the rounding mode */
00127 };
00128 
00129 /* This operation (i) sets the appropriate FPSCR bits for its
00130    parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
00131    otherwise passes its parameter through unchanged (in particular, -0
00132    and +0 stay as they were).  The `obvious' way to do this is optimised
00133    out by gcc.  */
00134 #define f_wash(x) \
00135    ({ double d; asm volatile ("fmul %0,%1,%2" \
00136                            : "=f"(d) \
00137                            : "f" (x), "f"((float)1.0)); d; })
00138 #define f_washf(x) \
00139    ({ float f; asm volatile ("fmuls %0,%1,%2" \
00140                           : "=f"(f) \
00141                           : "f" (x), "f"((float)1.0)); f; })
00142 
00143 #endif /* fenv_libc.h */