Back to index

glibc  2.9
fenv.h
Go to the documentation of this file.
00001 /* Copyright (C) 1997, 1998, 1999, 2008 Free Software Foundation, Inc.
00002    This file is part of the GNU C Library.
00003 
00004    The GNU C Library is free software; you can redistribute it and/or
00005    modify it under the terms of the GNU Lesser General Public
00006    License as published by the Free Software Foundation; either
00007    version 2.1 of the License, or (at your option) any later version.
00008 
00009    The GNU C Library is distributed in the hope that it will be useful,
00010    but WITHOUT ANY WARRANTY; without even the implied warranty of
00011    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012    Lesser General Public License for more details.
00013 
00014    You should have received a copy of the GNU Lesser General Public
00015    License along with the GNU C Library; if not, write to the Free
00016    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00017    02111-1307 USA.  */
00018 
00019 #ifndef _FENV_H
00020 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
00021 #endif
00022 
00023 
00024 /* Define bits representing the exception.  We use the bit positions of
00025    the appropriate bits in the FPSCR...  */
00026 enum
00027   {
00028     FE_INEXACT = 1 << (31 - 6),
00029 #define FE_INEXACT   FE_INEXACT
00030     FE_DIVBYZERO = 1 << (31 - 5),
00031 #define FE_DIVBYZERO FE_DIVBYZERO
00032     FE_UNDERFLOW = 1 << (31 - 4),
00033 #define FE_UNDERFLOW FE_UNDERFLOW
00034     FE_OVERFLOW = 1 << (31 - 3),
00035 #define FE_OVERFLOW  FE_OVERFLOW
00036 
00037     /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
00038        actually corresponds to bits 7 through 12 and 21 through 23
00039        in the FPSCR, but we can't use that because the current draft
00040        says that it must be a power of 2.  Instead we use bit 2 which
00041        is the summary bit for all the FE_INVALID exceptions, which
00042        kind of makes sense.  */
00043     FE_INVALID = 1 << (31 - 2),
00044 #define FE_INVALID   FE_INVALID
00045 
00046 #ifdef __USE_GNU
00047     /* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
00048        input to a routine is equivalent to setting all of these bits;
00049        FE_INVALID will be set on output from a routine iff one of
00050        these bits is set.  Note, though, that you can't disable or
00051        enable these exceptions individually.  */
00052 
00053     /* Operation with SNaN. */
00054     FE_INVALID_SNAN = 1 << (31 - 7),
00055 # define FE_INVALID_SNAN    FE_INVALID_SNAN
00056 
00057     /* Inf - Inf */
00058     FE_INVALID_ISI = 1 << (31 - 8),
00059 # define FE_INVALID_ISI            FE_INVALID_ISI
00060 
00061     /* Inf / Inf */
00062     FE_INVALID_IDI = 1 << (31 - 9),
00063 # define FE_INVALID_IDI            FE_INVALID_IDI
00064 
00065     /* 0 / 0 */
00066     FE_INVALID_ZDZ = 1 << (31 - 10),
00067 # define FE_INVALID_ZDZ            FE_INVALID_ZDZ
00068 
00069     /* Inf * 0 */
00070     FE_INVALID_IMZ = 1 << (31 - 11),
00071 # define FE_INVALID_IMZ            FE_INVALID_IMZ
00072 
00073     /* Comparison with NaN or SNaN.  */
00074     FE_INVALID_COMPARE = 1 << (31 - 12),
00075 # define FE_INVALID_COMPARE FE_INVALID_COMPARE
00076 
00077     /* Invalid operation flag for software (not set by hardware).  */
00078     /* Note that some chips don't have this implemented, presumably
00079        because no-one expected anyone to write software for them %-).  */
00080     FE_INVALID_SOFTWARE = 1 << (31 - 21),
00081 # define FE_INVALID_SOFTWARE       FE_INVALID_SOFTWARE
00082 
00083     /* Square root of negative number (including -Inf).  */
00084     /* Note that some chips don't have this implemented.  */
00085     FE_INVALID_SQRT = 1 << (31 - 22),
00086 # define FE_INVALID_SQRT    FE_INVALID_SQRT
00087 
00088     /* Conversion-to-integer of a NaN or a number too large or too small.  */
00089     FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23)
00090 # define FE_INVALID_INTEGER_CONVERSION    FE_INVALID_INTEGER_CONVERSION
00091 
00092 # define FE_ALL_INVALID \
00093         (FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
00094         | FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
00095         | FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
00096 #endif
00097   };
00098 
00099 #define FE_ALL_EXCEPT \
00100        (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
00101 
00102 /* PowerPC chips support all of the four defined rounding modes.  We
00103    use the bit pattern in the FPSCR as the values for the
00104    appropriate macros.  */
00105 enum
00106   {
00107     FE_TONEAREST = 0,
00108 #define FE_TONEAREST FE_TONEAREST
00109     FE_TOWARDZERO = 1,
00110 #define FE_TOWARDZERO       FE_TOWARDZERO
00111     FE_UPWARD = 2,
00112 #define FE_UPWARD    FE_UPWARD
00113     FE_DOWNWARD = 3
00114 #define FE_DOWNWARD  FE_DOWNWARD
00115   };
00116 
00117 /* Type representing exception flags.  */
00118 typedef unsigned int fexcept_t;
00119 
00120 /* Type representing floating-point environment.  We leave it as 'double'
00121    for efficiency reasons (rather than writing it to a 32-bit integer). */
00122 typedef double fenv_t;
00123 
00124 /* If the default argument is used we use this value.  */
00125 extern const fenv_t __fe_dfl_env;
00126 #define FE_DFL_ENV   (&__fe_dfl_env)
00127 
00128 #ifdef __USE_GNU
00129 /* Floating-point environment where all exceptions are enabled.  Note that
00130    this is not sufficient to give you SIGFPE.  */
00131 extern const fenv_t __fe_enabled_env;
00132 # define FE_ENABLED_ENV     (&__fe_enabled_env)
00133 
00134 /* Floating-point environment with (processor-dependent) non-IEEE floating
00135    point.  */
00136 extern const fenv_t __fe_nonieee_env;
00137 # define FE_NONIEEE_ENV     (&__fe_nonieee_env)
00138 
00139 __BEGIN_DECLS
00140 
00141 /* Floating-point environment with all exceptions enabled.  Note that
00142    just evaluating this value does not change the processor exception mode.
00143    Passing this mask to fesetenv will result in a prctl syscall to change
00144    the MSR FE0/FE1 bits to "Precise Mode".  On some processors this will
00145    result in slower floating point execution.  This will last until an
00146    fenv or exception mask is installed that disables all FP exceptions.  */
00147 extern const fenv_t *__fe_nomask_env (void);
00148 # define FE_NOMASK_ENV      FE_ENABLED_ENV
00149 
00150 /* Floating-point environment with all exceptions disabled.  Note that
00151    just evaluating this value does not change the processor exception mode.
00152    Passing this mask to fesetenv will result in a prctl syscall to change
00153    the MSR FE0/FE1 bits to "Ignore Exceptions Mode".  On most processors
00154    this allows the fastest possible floating point execution.*/
00155 extern const fenv_t *__fe_mask_env (void);
00156 # define FE_MASK_ENV FE_DFL_ENV
00157 
00158 __END_DECLS
00159 
00160 #endif