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glibc  2.9
ucontext.h
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00001 /* Copyright (C) 1998, 1999, 2002, 2003, 2004 Free Software Foundation, Inc.
00002    This file is part of the GNU C Library.
00003 
00004    The GNU C Library is free software; you can redistribute it and/or
00005    modify it under the terms of the GNU Lesser General Public
00006    License as published by the Free Software Foundation; either
00007    version 2.1 of the License, or (at your option) any later version.
00008 
00009    The GNU C Library is distributed in the hope that it will be useful,
00010    but WITHOUT ANY WARRANTY; without even the implied warranty of
00011    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012    Lesser General Public License for more details.
00013 
00014    You should have received a copy of the GNU Lesser General Public
00015    License along with the GNU C Library; if not, write to the Free
00016    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00017    02111-1307 USA.  */
00018 
00019 /* System V/mips ABI compliant context switching support.  */
00020 
00021 #ifndef _SYS_UCONTEXT_H
00022 #define _SYS_UCONTEXT_H     1
00023 
00024 #include <features.h>
00025 #include <sgidefs.h>
00026 #include <signal.h>
00027 
00028 /* Type for general register.  */
00029 #if _MIPS_SIM == _ABIO32
00030 typedef __uint32_t greg_t;
00031 #else
00032 typedef __uint64_t greg_t;
00033 #endif
00034 
00035 /* Number of general registers.  */
00036 #define NGREG 36
00037 
00038 /* Container for all general registers.  */
00039 typedef greg_t gregset_t[NGREG];
00040 
00041 /* Number of each register is the `gregset_t' array.  */
00042 enum
00043 {
00044   CTX_R0 = 0,
00045 #define CTX_R0       CTX_R0
00046   CTX_AT = 1,
00047 #define CTX_AT       CTX_AT
00048   CTX_V0 = 2,
00049 #define CTX_V0       CTX_V0
00050   CTX_V1 = 3,
00051 #define CTX_V1       CTX_V1
00052   CTX_A0 = 4,
00053 #define CTX_A0       CTX_A0
00054   CTX_A1 = 5,
00055 #define CTX_A1       CTX_A1
00056   CTX_A2 = 6,
00057 #define CTX_A2       CTX_A2
00058   CTX_A3 = 7,
00059 #define CTX_A3       CTX_A3
00060   CTX_T0 = 8,
00061 #define CTX_T0       CTX_T0
00062   CTX_T1 = 9,
00063 #define CTX_T1       CTX_T1
00064   CTX_T2 = 10,
00065 #define CTX_T2       CTX_T2
00066   CTX_T3 = 11,
00067 #define CTX_T3       CTX_T3
00068   CTX_T4 = 12,
00069 #define CTX_T4       CTX_T4
00070   CTX_T5 = 13,
00071 #define CTX_T5       CTX_T5
00072   CTX_T6 = 14,
00073 #define CTX_T6       CTX_T6
00074   CTX_T7 = 15,
00075 #define CTX_T7       CTX_T7
00076   CTX_S0 = 16,
00077 #define CTX_S0       CTX_S0
00078   CTX_S1 = 17,
00079 #define CTX_S1       CTX_S1
00080   CTX_S2 = 18,
00081 #define CTX_S2       CTX_S2
00082   CTX_S3 = 19,
00083 #define CTX_S3       CTX_S3
00084   CTX_S4 = 20,
00085 #define CTX_S4       CTX_S4
00086   CTX_S5 = 21,
00087 #define CTX_S5       CTX_S5
00088   CTX_S6 = 22,
00089 #define CTX_S6       CTX_S6
00090   CTX_S7 = 23,
00091 #define CTX_S7       CTX_S7
00092   CTX_T8 = 24,
00093 #define CTX_T8       CTX_T8
00094   CTX_T9 = 25,
00095 #define CTX_T9       CTX_T9
00096   CTX_K0 = 26,
00097 #define CTX_K0       CTX_K0
00098   CTX_K1 = 27,
00099 #define CTX_K1       CTX_K1
00100   CTX_GP = 28,
00101 #define CTX_GP       CTX_GP
00102   CTX_SP = 29,
00103 #define CTX_SP       CTX_SP
00104   CTX_S8 = 30,
00105 #define CTX_S8       CTX_S8
00106   CTX_RA = 31,
00107 #define CTX_RA       CTX_RA
00108   CTX_MDLO = 32,
00109 #define CTX_MDLO     CTX_MDLO
00110   CTX_MDHI = 33,
00111 #define CTX_MDHI     CTX_MDHI
00112   CTX_CAUSE = 34,
00113 #define CTX_CAUSE    CTX_CAUSE
00114   CTX_EPC = 35,
00115 #define CTX_EPC      CTX_EPC
00116 };
00117 
00118 /* Structure to describe FPU registers.  */
00119 typedef struct fpregset
00120 {
00121   union
00122   {
00123 #if _MIPS_SIM == _ABIO32
00124     double fp_dregs[16];
00125     float fp_fregs[32];
00126     unsigned int fp_regs[32];
00127 #else
00128     double fp_dregs[32];
00129     /* float fp_fregs[32]; */
00130     __uint64_t fp_regs[32];
00131 #endif
00132   } fp_r;
00133   unsigned int fp_csr;
00134   unsigned int fp_pad;
00135 } fpregset_t;
00136 
00137 /* Context to describe whole processor state.  */
00138 typedef struct
00139 {
00140   gregset_t gpregs;
00141   fpregset_t fpregs;
00142 } mcontext_t;
00143 
00144 /* Userlevel context.  */
00145 typedef struct ucontext
00146 {
00147 #if _MIPS_SIM == _ABIO32
00148   unsigned long int uc_flags;
00149 #else
00150   __uint64_t uc_flags;
00151 #endif
00152   struct ucontext *uc_link;
00153   __sigset_t uc_sigmask;
00154   stack_t uc_stack;
00155   mcontext_t uc_mcontext;
00156   int uc_filler[48];
00157 } ucontext_t;
00158 
00159 #endif /* sys/ucontext.h */