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glibc  2.9
fpu_control.h
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00001 /* FPU control word definitions.  ARM version.
00002    Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
00003    This file is part of the GNU C Library.
00004 
00005    The GNU C Library is free software; you can redistribute it and/or
00006    modify it under the terms of the GNU Lesser General Public
00007    License as published by the Free Software Foundation; either
00008    version 2.1 of the License, or (at your option) any later version.
00009 
00010    The GNU C Library is distributed in the hope that it will be useful,
00011    but WITHOUT ANY WARRANTY; without even the implied warranty of
00012    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013    Lesser General Public License for more details.
00014 
00015    You should have received a copy of the GNU Lesser General Public
00016    License along with the GNU C Library; if not, write to the Free
00017    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00018    02111-1307 USA.  */
00019 
00020 #ifndef _FPU_CONTROL_H
00021 #define _FPU_CONTROL_H
00022 
00023 /* We have a slight terminology confusion here.  On the ARM, the register
00024  * we're interested in is actually the FPU status word - the FPU control
00025  * word is something different (which is implementation-defined and only
00026  * accessible from supervisor mode.)
00027  *
00028  * The FPSR looks like this:
00029  *
00030  *     31-24        23-16          15-8              7-0
00031  * | system ID | trap enable | system control | exception flags |
00032  *
00033  * We ignore the system ID bits; for interest's sake they are:
00034  *
00035  *  0000      "old" FPE
00036  *  1000      FPPC hardware
00037  *  0001      FPE 400
00038  *  1001      FPA hardware
00039  *
00040  * The trap enable and exception flags are both structured like this:
00041  *
00042  *     7 - 5     4     3     2     1     0
00043  * | reserved | INX | UFL | OFL | DVZ | IVO |
00044  *
00045  * where a `1' bit in the enable byte means that the trap can occur, and
00046  * a `1' bit in the flags byte means the exception has occurred.
00047  *
00048  * The exceptions are:
00049  *
00050  *  IVO - invalid operation
00051  *  DVZ - divide by zero
00052  *  OFL - overflow
00053  *  UFL - underflow
00054  *  INX - inexact (do not use; implementations differ)
00055  *
00056  * The system control byte looks like this:
00057  *
00058  *     7-5      4    3    2    1    0
00059  * | reserved | AC | EP | SO | NE | ND |
00060  *
00061  * where the bits mean
00062  *
00063  *  ND - no denormalised numbers (force them all to zero)
00064  *  NE - enable NaN exceptions
00065  *  SO - synchronous operation
00066  *  EP - use expanded packed-decimal format
00067  *  AC - use alternate definition for C flag on compare operations
00068  */
00069 
00070 /* masking of interrupts */
00071 #define _FPU_MASK_IM 0x00010000    /* invalid operation */
00072 #define _FPU_MASK_ZM 0x00020000    /* divide by zero */
00073 #define _FPU_MASK_OM 0x00040000    /* overflow */
00074 #define _FPU_MASK_UM 0x00080000    /* underflow */
00075 #define _FPU_MASK_PM 0x00100000    /* inexact */
00076 #define _FPU_MASK_DM 0x00000000    /* denormalized operation */
00077 
00078 /* The system id bytes cannot be changed.
00079    Only the bottom 5 bits in the trap enable byte can be changed.
00080    Only the bottom 5 bits in the system control byte can be changed.
00081    Only the bottom 5 bits in the exception flags are used.
00082    The exception flags are set by the fpu, but can be zeroed by the user. */
00083 #define _FPU_RESERVED       0xffe0e0e0    /* These bits are reserved.  */
00084 
00085 /* The fdlibm code requires strict IEEE double precision arithmetic,
00086    no interrupts for exceptions, rounding to nearest.  Changing the
00087    rounding mode will break long double I/O.  Turn on the AC bit,
00088    the compiler generates code that assumes it is on.  */
00089 #define _FPU_DEFAULT 0x00001000    /* Default value.  */
00090 #define _FPU_IEEE    0x001f1000    /* Default + exceptions enabled. */
00091 
00092 /* Type of the control word.  */
00093 typedef unsigned int fpu_control_t;
00094 
00095 /* Macros for accessing the hardware control word.  */
00096 #define _FPU_GETCW(cw) __asm__ ("rfs %0" : "=r" (cw))
00097 #define _FPU_SETCW(cw) __asm__ ("wfs %0" : : "r" (cw))
00098 
00099 /* Default control word set at startup.  */
00100 extern fpu_control_t __fpu_control;
00101 
00102 #endif /* _FPU_CONTROL_H */