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glibc  2.9
longlong.h
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00001 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
00002    Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
00003    2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
00004 
00005    This file is part of the GNU C Library.
00006 
00007    The GNU C Library is free software; you can redistribute it and/or
00008    modify it under the terms of the GNU Lesser General Public
00009    License as published by the Free Software Foundation; either
00010    version 2.1 of the License, or (at your option) any later version.
00011 
00012    The GNU C Library is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00015    Lesser General Public License for more details.
00016 
00017    You should have received a copy of the GNU Lesser General Public
00018    License along with the GNU C Library; if not, write to the Free
00019    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00020    02111-1307 USA.  */
00021 
00022 /* You have to define the following before including this file:
00023 
00024    UWtype -- An unsigned type, default type for operations (typically a "word")
00025    UHWtype -- An unsigned type, at least half the size of UWtype.
00026    UDWtype -- An unsigned type, at least twice as large a UWtype
00027    W_TYPE_SIZE -- size in bits of UWtype
00028 
00029    UQItype -- Unsigned 8 bit type.
00030    SItype, USItype -- Signed and unsigned 32 bit types.
00031    DItype, UDItype -- Signed and unsigned 64 bit types.
00032 
00033    On a 32 bit machine UWtype should typically be USItype;
00034    on a 64 bit machine, UWtype should typically be UDItype.  */
00035 
00036 #define __BITS4 (W_TYPE_SIZE / 4)
00037 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
00038 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
00039 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
00040 
00041 #ifndef W_TYPE_SIZE
00042 #define W_TYPE_SIZE  32
00043 #define UWtype              USItype
00044 #define UHWtype             USItype
00045 #define UDWtype             UDItype
00046 #endif
00047 
00048 extern const UQItype __clz_tab[256] attribute_hidden;
00049 
00050 /* Define auxiliary asm macros.
00051 
00052    1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
00053    UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
00054    word product in HIGH_PROD and LOW_PROD.
00055 
00056    2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
00057    UDWtype product.  This is just a variant of umul_ppmm.
00058 
00059    3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
00060    denominator) divides a UDWtype, composed by the UWtype integers
00061    HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
00062    in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
00063    than DENOMINATOR for correct operation.  If, in addition, the most
00064    significant bit of DENOMINATOR must be 1, then the pre-processor symbol
00065    UDIV_NEEDS_NORMALIZATION is defined to 1.
00066 
00067    4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
00068    denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
00069    is rounded towards 0.
00070 
00071    5) count_leading_zeros(count, x) counts the number of zero-bits from the
00072    msb to the first nonzero bit in the UWtype X.  This is the number of
00073    steps X needs to be shifted left to set the msb.  Undefined for X == 0,
00074    unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
00075 
00076    6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
00077    from the least significant end.
00078 
00079    7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
00080    high_addend_2, low_addend_2) adds two UWtype integers, composed by
00081    HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
00082    respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
00083    (i.e. carry out) is not stored anywhere, and is lost.
00084 
00085    8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
00086    high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
00087    composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
00088    LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
00089    and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
00090    and is lost.
00091 
00092    If any of these macros are left undefined for a particular CPU,
00093    C macros are used.  */
00094 
00095 /* The CPUs come in alphabetical order below.
00096 
00097    Please add support for more CPUs here, or improve the current support
00098    for the CPUs below!
00099    (E.g. WE32100, IBM360.)  */
00100 
00101 #if defined (__GNUC__) && !defined (NO_ASM)
00102 
00103 /* We sometimes need to clobber "cc" with gcc2, but that would not be
00104    understood by gcc1.  Use cpp to avoid major code duplication.  */
00105 #if __GNUC__ < 2
00106 #define __CLOBBER_CC
00107 #define __AND_CLOBBER_CC
00108 #else /* __GNUC__ >= 2 */
00109 #define __CLOBBER_CC : "cc"
00110 #define __AND_CLOBBER_CC , "cc"
00111 #endif /* __GNUC__ < 2 */
00112 
00113 #if defined (__alpha) && W_TYPE_SIZE == 64
00114 #define umul_ppmm(ph, pl, m0, m1) \
00115   do {                                                         \
00116     UDItype __m0 = (m0), __m1 = (m1);                                 \
00117     (ph) = __builtin_alpha_umulh (__m0, __m1);                        \
00118     (pl) = __m0 * __m1;                                               \
00119   } while (0)
00120 #define UMUL_TIME 46
00121 #ifndef LONGLONG_STANDALONE
00122 #define udiv_qrnnd(q, r, n1, n0, d) \
00123   do { UDItype __r;                                            \
00124     (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));                       \
00125     (r) = __r;                                                        \
00126   } while (0)
00127 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
00128 #define UDIV_TIME 220
00129 #endif /* LONGLONG_STANDALONE */
00130 #ifdef __alpha_cix__
00131 #define count_leading_zeros(COUNT,X)      ((COUNT) = __builtin_clzl (X))
00132 #define count_trailing_zeros(COUNT,X)     ((COUNT) = __builtin_ctzl (X))
00133 #define COUNT_LEADING_ZEROS_0 64
00134 #else
00135 #define count_leading_zeros(COUNT,X) \
00136   do {                                                         \
00137     UDItype __xr = (X), __t, __a;                              \
00138     __t = __builtin_alpha_cmpbge (0, __xr);                           \
00139     __a = __clz_tab[__t ^ 0xff] - 1;                                  \
00140     __t = __builtin_alpha_extbl (__xr, __a);                          \
00141     (COUNT) = 64 - (__clz_tab[__t] + __a*8);                          \
00142   } while (0)
00143 #define count_trailing_zeros(COUNT,X) \
00144   do {                                                         \
00145     UDItype __xr = (X), __t, __a;                              \
00146     __t = __builtin_alpha_cmpbge (0, __xr);                           \
00147     __t = ~__t & -~__t;                                               \
00148     __a = ((__t & 0xCC) != 0) * 2;                             \
00149     __a += ((__t & 0xF0) != 0) * 4;                                   \
00150     __a += ((__t & 0xAA) != 0);                                       \
00151     __t = __builtin_alpha_extbl (__xr, __a);                          \
00152     __a <<= 3;                                                        \
00153     __t &= -__t;                                               \
00154     __a += ((__t & 0xCC) != 0) * 2;                                   \
00155     __a += ((__t & 0xF0) != 0) * 4;                                   \
00156     __a += ((__t & 0xAA) != 0);                                       \
00157     (COUNT) = __a;                                             \
00158   } while (0)
00159 #endif /* __alpha_cix__ */
00160 #endif /* __alpha */
00161 
00162 #if defined (__arc__) && W_TYPE_SIZE == 32
00163 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00164   __asm__ ("add.f    %1, %4, %5\n\tadc    %0, %2, %3"          \
00165           : "=r" ((USItype) (sh)),                             \
00166             "=&r" ((USItype) (sl))                             \
00167           : "%r" ((USItype) (ah)),                             \
00168             "rIJ" ((USItype) (bh)),                                   \
00169             "%r" ((USItype) (al)),                             \
00170             "rIJ" ((USItype) (bl)))
00171 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00172   __asm__ ("sub.f    %1, %4, %5\n\tsbc    %0, %2, %3"          \
00173           : "=r" ((USItype) (sh)),                             \
00174             "=&r" ((USItype) (sl))                             \
00175           : "r" ((USItype) (ah)),                              \
00176             "rIJ" ((USItype) (bh)),                                   \
00177             "r" ((USItype) (al)),                              \
00178             "rIJ" ((USItype) (bl)))
00179 /* Call libgcc routine.  */
00180 #define umul_ppmm(w1, w0, u, v) \
00181 do {                                                           \
00182   DWunion __w;                                                        \
00183   __w.ll = __umulsidi3 (u, v);                                        \
00184   w1 = __w.s.high;                                             \
00185   w0 = __w.s.low;                                              \
00186 } while (0)
00187 #define __umulsidi3 __umulsidi3
00188 UDItype __umulsidi3 (USItype, USItype);
00189 #endif
00190 
00191 #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
00192 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00193   __asm__ ("adds     %1, %4, %5\n\tadc    %0, %2, %3"          \
00194           : "=r" ((USItype) (sh)),                             \
00195             "=&r" ((USItype) (sl))                             \
00196           : "%r" ((USItype) (ah)),                             \
00197             "rI" ((USItype) (bh)),                             \
00198             "%r" ((USItype) (al)),                             \
00199             "rI" ((USItype) (bl)) __CLOBBER_CC)
00200 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00201   __asm__ ("subs     %1, %4, %5\n\tsbc    %0, %2, %3"          \
00202           : "=r" ((USItype) (sh)),                             \
00203             "=&r" ((USItype) (sl))                             \
00204           : "r" ((USItype) (ah)),                              \
00205             "rI" ((USItype) (bh)),                             \
00206             "r" ((USItype) (al)),                              \
00207             "rI" ((USItype) (bl)) __CLOBBER_CC)
00208 #define umul_ppmm(xh, xl, a, b) \
00209 {register USItype __t0, __t1, __t2;                                   \
00210   __asm__ ("%@ Inlined umul_ppmm\n"                                   \
00211           "   mov    %2, %5, lsr #16\n"                        \
00212           "   mov    %0, %6, lsr #16\n"                        \
00213           "   bic    %3, %5, %2, lsl #16\n"                           \
00214           "   bic    %4, %6, %0, lsl #16\n"                           \
00215           "   mul    %1, %3, %4\n"                             \
00216           "   mul    %4, %2, %4\n"                             \
00217           "   mul    %3, %0, %3\n"                             \
00218           "   mul    %0, %2, %0\n"                             \
00219           "   adds   %3, %4, %3\n"                             \
00220           "   addcs  %0, %0, #65536\n"                         \
00221           "   adds   %1, %1, %3, lsl #16\n"                           \
00222           "   adc    %0, %0, %3, lsr #16"                      \
00223           : "=&r" ((USItype) (xh)),                                   \
00224             "=r" ((USItype) (xl)),                             \
00225             "=&r" (__t0), "=&r" (__t1), "=r" (__t2)                   \
00226           : "r" ((USItype) (a)),                               \
00227             "r" ((USItype) (b)) __CLOBBER_CC );}
00228 #define UMUL_TIME 20
00229 #define UDIV_TIME 100
00230 #endif /* __arm__ */
00231 
00232 #if defined(__arm__)
00233 /* Let gcc decide how best to implement count_leading_zeros.  */
00234 #define count_leading_zeros(COUNT,X)      ((COUNT) = __builtin_clz (X))
00235 #define COUNT_LEADING_ZEROS_0 32
00236 #endif
00237 
00238 #if defined (__CRIS__) && __CRIS_arch_version >= 3
00239 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
00240 #if __CRIS_arch_version >= 8
00241 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
00242 #endif
00243 #endif /* __CRIS__ */
00244 
00245 #if defined (__hppa) && W_TYPE_SIZE == 32
00246 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00247   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"                            \
00248           : "=r" ((USItype) (sh)),                             \
00249             "=&r" ((USItype) (sl))                             \
00250           : "%rM" ((USItype) (ah)),                                   \
00251             "rM" ((USItype) (bh)),                             \
00252             "%rM" ((USItype) (al)),                                   \
00253             "rM" ((USItype) (bl)))
00254 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00255   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"                            \
00256           : "=r" ((USItype) (sh)),                             \
00257             "=&r" ((USItype) (sl))                             \
00258           : "rM" ((USItype) (ah)),                             \
00259             "rM" ((USItype) (bh)),                             \
00260             "rM" ((USItype) (al)),                             \
00261             "rM" ((USItype) (bl)))
00262 #if defined (_PA_RISC1_1)
00263 #define umul_ppmm(w1, w0, u, v) \
00264   do {                                                         \
00265     union                                                      \
00266       {                                                               \
00267        UDItype __f;                                            \
00268        struct {USItype __w1, __w0;} __w1w0;                           \
00269       } __t;                                                   \
00270     __asm__ ("xmpyu %1,%2,%0"                                         \
00271             : "=x" (__t.__f)                                          \
00272             : "x" ((USItype) (u)),                             \
00273               "x" ((USItype) (v)));                                   \
00274     (w1) = __t.__w1w0.__w1;                                    \
00275     (w0) = __t.__w1w0.__w0;                                    \
00276      } while (0)
00277 #define UMUL_TIME 8
00278 #else
00279 #define UMUL_TIME 30
00280 #endif
00281 #define UDIV_TIME 40
00282 #define count_leading_zeros(count, x) \
00283   do {                                                         \
00284     USItype __tmp;                                             \
00285     __asm__ (                                                  \
00286        "ldi          1,%0\n"                                          \
00287 "      extru,=              %1,15,16,%%r0        ; Bits 31..16 zero?\n"      \
00288 "      extru,tr      %1,15,16,%1          ; No.  Shift down, skip add.\n"\
00289 "      ldo           16(%0),%0            ; Yes.  Perform add.\n"     \
00290 "      extru,=              %1,23,8,%%r0         ; Bits 15..8 zero?\n"       \
00291 "      extru,tr      %1,23,8,%1           ; No.  Shift down, skip add.\n"\
00292 "      ldo           8(%0),%0             ; Yes.  Perform add.\n"     \
00293 "      extru,=              %1,27,4,%%r0         ; Bits 7..4 zero?\n" \
00294 "      extru,tr      %1,27,4,%1           ; No.  Shift down, skip add.\n"\
00295 "      ldo           4(%0),%0             ; Yes.  Perform add.\n"     \
00296 "      extru,=              %1,29,2,%%r0         ; Bits 3..2 zero?\n" \
00297 "      extru,tr      %1,29,2,%1           ; No.  Shift down, skip add.\n"\
00298 "      ldo           2(%0),%0             ; Yes.  Perform add.\n"     \
00299 "      extru         %1,30,1,%1           ; Extract bit 1.\n"  \
00300 "      sub           %0,%1,%0             ; Subtract it.\n"    \
00301        : "=r" (count), "=r" (__tmp) : "1" (x));                \
00302   } while (0)
00303 #endif
00304 
00305 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
00306 #define smul_ppmm(xh, xl, m0, m1) \
00307   do {                                                         \
00308     union {DItype __ll;                                               \
00309           struct {USItype __h, __l;} __i;                      \
00310          } __x;                                                \
00311     __asm__ ("lr %N0,%1\n\tmr %0,%2"                                  \
00312             : "=&r" (__x.__ll)                                        \
00313             : "r" (m0), "r" (m1));                             \
00314     (xh) = __x.__i.__h; (xl) = __x.__i.__l;                           \
00315   } while (0)
00316 #define sdiv_qrnnd(q, r, n1, n0, d) \
00317   do {                                                         \
00318     union {DItype __ll;                                               \
00319           struct {USItype __h, __l;} __i;                      \
00320          } __x;                                                \
00321     __x.__i.__h = n1; __x.__i.__l = n0;                               \
00322     __asm__ ("dr %0,%2"                                               \
00323             : "=r" (__x.__ll)                                         \
00324             : "0" (__x.__ll), "r" (d));                        \
00325     (q) = __x.__i.__l; (r) = __x.__i.__h;                      \
00326   } while (0)
00327 #endif
00328 
00329 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
00330 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00331   __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}"             \
00332           : "=r" ((USItype) (sh)),                             \
00333             "=&r" ((USItype) (sl))                             \
00334           : "%0" ((USItype) (ah)),                             \
00335             "g" ((USItype) (bh)),                              \
00336             "%1" ((USItype) (al)),                             \
00337             "g" ((USItype) (bl)))
00338 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00339   __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}"             \
00340           : "=r" ((USItype) (sh)),                             \
00341             "=&r" ((USItype) (sl))                             \
00342           : "0" ((USItype) (ah)),                              \
00343             "g" ((USItype) (bh)),                              \
00344             "1" ((USItype) (al)),                              \
00345             "g" ((USItype) (bl)))
00346 #define umul_ppmm(w1, w0, u, v) \
00347   __asm__ ("mul{l} %3"                                                \
00348           : "=a" ((USItype) (w0)),                             \
00349             "=d" ((USItype) (w1))                              \
00350           : "%0" ((USItype) (u)),                              \
00351             "rm" ((USItype) (v)))
00352 #define udiv_qrnnd(q, r, n1, n0, dv) \
00353   __asm__ ("div{l} %4"                                                \
00354           : "=a" ((USItype) (q)),                              \
00355             "=d" ((USItype) (r))                               \
00356           : "0" ((USItype) (n0)),                              \
00357             "1" ((USItype) (n1)),                              \
00358             "rm" ((USItype) (dv)))
00359 #define count_leading_zeros(count, x)     ((count) = __builtin_clz (x))
00360 #define count_trailing_zeros(count, x)    ((count) = __builtin_ctz (x))
00361 #define UMUL_TIME 40
00362 #define UDIV_TIME 40
00363 #endif /* 80x86 */
00364 
00365 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
00366 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00367   __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}"             \
00368           : "=r" ((UDItype) (sh)),                             \
00369             "=&r" ((UDItype) (sl))                             \
00370           : "%0" ((UDItype) (ah)),                             \
00371             "rme" ((UDItype) (bh)),                                   \
00372             "%1" ((UDItype) (al)),                             \
00373             "rme" ((UDItype) (bl)))
00374 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00375   __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}"             \
00376           : "=r" ((UDItype) (sh)),                             \
00377             "=&r" ((UDItype) (sl))                             \
00378           : "0" ((UDItype) (ah)),                              \
00379             "rme" ((UDItype) (bh)),                                   \
00380             "1" ((UDItype) (al)),                              \
00381             "rme" ((UDItype) (bl)))
00382 #define umul_ppmm(w1, w0, u, v) \
00383   __asm__ ("mul{q} %3"                                                \
00384           : "=a" ((UDItype) (w0)),                             \
00385             "=d" ((UDItype) (w1))                              \
00386           : "%0" ((UDItype) (u)),                              \
00387             "rm" ((UDItype) (v)))
00388 #define udiv_qrnnd(q, r, n1, n0, dv) \
00389   __asm__ ("div{q} %4"                                                \
00390           : "=a" ((UDItype) (q)),                              \
00391             "=d" ((UDItype) (r))                               \
00392           : "0" ((UDItype) (n0)),                              \
00393             "1" ((UDItype) (n1)),                              \
00394             "rm" ((UDItype) (dv)))
00395 #define count_leading_zeros(count, x)     ((count) = __builtin_clzl (x))
00396 #define count_trailing_zeros(count, x)    ((count) = __builtin_ctzl (x))
00397 #define UMUL_TIME 40
00398 #define UDIV_TIME 40
00399 #endif /* x86_64 */
00400 
00401 #if defined (__i960__) && W_TYPE_SIZE == 32
00402 #define umul_ppmm(w1, w0, u, v) \
00403   ({union {UDItype __ll;                                       \
00404           struct {USItype __l, __h;} __i;                      \
00405          } __xx;                                               \
00406   __asm__ ("emul     %2,%1,%0"                                 \
00407           : "=d" (__xx.__ll)                                          \
00408           : "%dI" ((USItype) (u)),                             \
00409             "dI" ((USItype) (v)));                             \
00410   (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
00411 #define __umulsidi3(u, v) \
00412   ({UDItype __w;                                               \
00413     __asm__ ("emul   %2,%1,%0"                                 \
00414             : "=d" (__w)                                       \
00415             : "%dI" ((USItype) (u)),                                  \
00416               "dI" ((USItype) (v)));                                  \
00417     __w; })
00418 #endif /* __i960__ */
00419 
00420 #if defined (__M32R__) && W_TYPE_SIZE == 32
00421 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00422   /* The cmp clears the condition bit.  */ \
00423   __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3"                    \
00424           : "=r" ((USItype) (sh)),                             \
00425             "=&r" ((USItype) (sl))                             \
00426           : "0" ((USItype) (ah)),                              \
00427             "r" ((USItype) (bh)),                              \
00428             "1" ((USItype) (al)),                              \
00429             "r" ((USItype) (bl))                               \
00430           : "cbit")
00431 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00432   /* The cmp clears the condition bit.  */ \
00433   __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3"                    \
00434           : "=r" ((USItype) (sh)),                             \
00435             "=&r" ((USItype) (sl))                             \
00436           : "0" ((USItype) (ah)),                              \
00437             "r" ((USItype) (bh)),                              \
00438             "1" ((USItype) (al)),                              \
00439             "r" ((USItype) (bl))                               \
00440           : "cbit")
00441 #endif /* __M32R__ */
00442 
00443 #if defined (__mc68000__) && W_TYPE_SIZE == 32
00444 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00445   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"                            \
00446           : "=d" ((USItype) (sh)),                             \
00447             "=&d" ((USItype) (sl))                             \
00448           : "%0" ((USItype) (ah)),                             \
00449             "d" ((USItype) (bh)),                              \
00450             "%1" ((USItype) (al)),                             \
00451             "g" ((USItype) (bl)))
00452 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00453   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"                            \
00454           : "=d" ((USItype) (sh)),                             \
00455             "=&d" ((USItype) (sl))                             \
00456           : "0" ((USItype) (ah)),                              \
00457             "d" ((USItype) (bh)),                              \
00458             "1" ((USItype) (al)),                              \
00459             "g" ((USItype) (bl)))
00460 
00461 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r.  */
00462 #if (defined (__mc68020__) && !defined (__mc68060__))
00463 #define umul_ppmm(w1, w0, u, v) \
00464   __asm__ ("mulu%.l %3,%1:%0"                                         \
00465           : "=d" ((USItype) (w0)),                             \
00466             "=d" ((USItype) (w1))                              \
00467           : "%0" ((USItype) (u)),                              \
00468             "dmi" ((USItype) (v)))
00469 #define UMUL_TIME 45
00470 #define udiv_qrnnd(q, r, n1, n0, d) \
00471   __asm__ ("divu%.l %4,%1:%0"                                         \
00472           : "=d" ((USItype) (q)),                              \
00473             "=d" ((USItype) (r))                               \
00474           : "0" ((USItype) (n0)),                              \
00475             "1" ((USItype) (n1)),                              \
00476             "dmi" ((USItype) (d)))
00477 #define UDIV_TIME 90
00478 #define sdiv_qrnnd(q, r, n1, n0, d) \
00479   __asm__ ("divs%.l %4,%1:%0"                                         \
00480           : "=d" ((USItype) (q)),                              \
00481             "=d" ((USItype) (r))                               \
00482           : "0" ((USItype) (n0)),                              \
00483             "1" ((USItype) (n1)),                              \
00484             "dmi" ((USItype) (d)))
00485 
00486 #elif defined (__mcoldfire__) /* not mc68020 */
00487 
00488 #define umul_ppmm(xh, xl, a, b) \
00489   __asm__ ("| Inlined umul_ppmm\n"                             \
00490           "   move%.l       %2,%/d0\n"                                \
00491           "   move%.l       %3,%/d1\n"                                \
00492           "   move%.l       %/d0,%/d2\n"                              \
00493           "   swap   %/d0\n"                                          \
00494           "   move%.l       %/d1,%/d3\n"                              \
00495           "   swap   %/d1\n"                                          \
00496           "   move%.w       %/d2,%/d4\n"                              \
00497           "   mulu   %/d3,%/d4\n"                              \
00498           "   mulu   %/d1,%/d2\n"                              \
00499           "   mulu   %/d0,%/d3\n"                              \
00500           "   mulu   %/d0,%/d1\n"                              \
00501           "   move%.l       %/d4,%/d0\n"                              \
00502           "   clr%.w %/d0\n"                                          \
00503           "   swap   %/d0\n"                                          \
00504           "   add%.l %/d0,%/d2\n"                              \
00505           "   add%.l %/d3,%/d2\n"                              \
00506           "   jcc    1f\n"                                     \
00507           "   add%.l %#65536,%/d1\n"                                  \
00508           "1: swap   %/d2\n"                                          \
00509           "   moveq  %#0,%/d0\n"                               \
00510           "   move%.w       %/d2,%/d0\n"                              \
00511           "   move%.w       %/d4,%/d2\n"                              \
00512           "   move%.l       %/d2,%1\n"                                \
00513           "   add%.l %/d1,%/d0\n"                              \
00514           "   move%.l       %/d0,%0"                                  \
00515           : "=g" ((USItype) (xh)),                             \
00516             "=g" ((USItype) (xl))                              \
00517           : "g" ((USItype) (a)),                               \
00518             "g" ((USItype) (b))                                \
00519           : "d0", "d1", "d2", "d3", "d4")
00520 #define UMUL_TIME 100
00521 #define UDIV_TIME 400
00522 #else /* not ColdFire */
00523 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */
00524 #define umul_ppmm(xh, xl, a, b) \
00525   __asm__ ("| Inlined umul_ppmm\n"                             \
00526           "   move%.l       %2,%/d0\n"                                \
00527           "   move%.l       %3,%/d1\n"                                \
00528           "   move%.l       %/d0,%/d2\n"                              \
00529           "   swap   %/d0\n"                                          \
00530           "   move%.l       %/d1,%/d3\n"                              \
00531           "   swap   %/d1\n"                                          \
00532           "   move%.w       %/d2,%/d4\n"                              \
00533           "   mulu   %/d3,%/d4\n"                              \
00534           "   mulu   %/d1,%/d2\n"                              \
00535           "   mulu   %/d0,%/d3\n"                              \
00536           "   mulu   %/d0,%/d1\n"                              \
00537           "   move%.l       %/d4,%/d0\n"                              \
00538           "   eor%.w %/d0,%/d0\n"                              \
00539           "   swap   %/d0\n"                                          \
00540           "   add%.l %/d0,%/d2\n"                              \
00541           "   add%.l %/d3,%/d2\n"                              \
00542           "   jcc    1f\n"                                     \
00543           "   add%.l %#65536,%/d1\n"                                  \
00544           "1: swap   %/d2\n"                                          \
00545           "   moveq  %#0,%/d0\n"                               \
00546           "   move%.w       %/d2,%/d0\n"                              \
00547           "   move%.w       %/d4,%/d2\n"                              \
00548           "   move%.l       %/d2,%1\n"                                \
00549           "   add%.l %/d1,%/d0\n"                              \
00550           "   move%.l       %/d0,%0"                                  \
00551           : "=g" ((USItype) (xh)),                             \
00552             "=g" ((USItype) (xl))                              \
00553           : "g" ((USItype) (a)),                               \
00554             "g" ((USItype) (b))                                \
00555           : "d0", "d1", "d2", "d3", "d4")
00556 #define UMUL_TIME 100
00557 #define UDIV_TIME 400
00558 
00559 #endif /* not mc68020 */
00560 
00561 /* The '020, '030, '040 and '060 have bitfield insns.
00562    cpu32 disguises as a 68020, but lacks them.  */
00563 #if defined (__mc68020__) && !defined (__mcpu32__)
00564 #define count_leading_zeros(count, x) \
00565   __asm__ ("bfffo %1{%b2:%b2},%0"                              \
00566           : "=d" ((USItype) (count))                                  \
00567           : "od" ((USItype) (x)), "n" (0))
00568 /* Some ColdFire architectures have a ff1 instruction supported via
00569    __builtin_clz. */
00570 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
00571 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
00572 #define COUNT_LEADING_ZEROS_0 32
00573 #endif
00574 #endif /* mc68000 */
00575 
00576 #if defined (__m88000__) && W_TYPE_SIZE == 32
00577 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00578   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"                 \
00579           : "=r" ((USItype) (sh)),                             \
00580             "=&r" ((USItype) (sl))                             \
00581           : "%rJ" ((USItype) (ah)),                                   \
00582             "rJ" ((USItype) (bh)),                             \
00583             "%rJ" ((USItype) (al)),                                   \
00584             "rJ" ((USItype) (bl)))
00585 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00586   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"                 \
00587           : "=r" ((USItype) (sh)),                             \
00588             "=&r" ((USItype) (sl))                             \
00589           : "rJ" ((USItype) (ah)),                             \
00590             "rJ" ((USItype) (bh)),                             \
00591             "rJ" ((USItype) (al)),                             \
00592             "rJ" ((USItype) (bl)))
00593 #define count_leading_zeros(count, x) \
00594   do {                                                         \
00595     USItype __cbtmp;                                           \
00596     __asm__ ("ff1 %0,%1"                                       \
00597             : "=r" (__cbtmp)                                          \
00598             : "r" ((USItype) (x)));                                   \
00599     (count) = __cbtmp ^ 31;                                    \
00600   } while (0)
00601 #define COUNT_LEADING_ZEROS_0 63 /* sic */
00602 #if defined (__mc88110__)
00603 #define umul_ppmm(wh, wl, u, v) \
00604   do {                                                         \
00605     union {UDItype __ll;                                       \
00606           struct {USItype __h, __l;} __i;                      \
00607          } __xx;                                               \
00608     __asm__ ("mulu.d %0,%1,%2"                                 \
00609             : "=r" (__xx.__ll)                                        \
00610             : "r" ((USItype) (u)),                             \
00611               "r" ((USItype) (v)));                                   \
00612     (wh) = __xx.__i.__h;                                       \
00613     (wl) = __xx.__i.__l;                                       \
00614   } while (0)
00615 #define udiv_qrnnd(q, r, n1, n0, d) \
00616   ({union {UDItype __ll;                                       \
00617           struct {USItype __h, __l;} __i;                      \
00618          } __xx;                                               \
00619   USItype __q;                                                        \
00620   __xx.__i.__h = (n1); __xx.__i.__l = (n0);                           \
00621   __asm__ ("divu.d %0,%1,%2"                                          \
00622           : "=r" (__q)                                                \
00623           : "r" (__xx.__ll),                                          \
00624             "r" ((USItype) (d)));                              \
00625   (r) = (n0) - __q * (d); (q) = __q; })
00626 #define UMUL_TIME 5
00627 #define UDIV_TIME 25
00628 #else
00629 #define UMUL_TIME 17
00630 #define UDIV_TIME 150
00631 #endif /* __mc88110__ */
00632 #endif /* __m88000__ */
00633 
00634 #if defined (__mips__) && W_TYPE_SIZE == 32
00635 #define umul_ppmm(w1, w0, u, v)                                       \
00636   do {                                                         \
00637     UDItype __x = (UDItype) (USItype) (u) * (USItype) (v);            \
00638     (w1) = (USItype) (__x >> 32);                              \
00639     (w0) = (USItype) (__x);                                    \
00640   } while (0)
00641 #define UMUL_TIME 10
00642 #define UDIV_TIME 100
00643 
00644 #if (__mips == 32 || __mips == 64) && ! __mips16
00645 #define count_leading_zeros(COUNT,X)      ((COUNT) = __builtin_clz (X))
00646 #define COUNT_LEADING_ZEROS_0 32
00647 #endif
00648 #endif /* __mips__ */
00649 
00650 #if defined (__ns32000__) && W_TYPE_SIZE == 32
00651 #define umul_ppmm(w1, w0, u, v) \
00652   ({union {UDItype __ll;                                       \
00653           struct {USItype __l, __h;} __i;                      \
00654          } __xx;                                               \
00655   __asm__ ("meid %2,%0"                                               \
00656           : "=g" (__xx.__ll)                                          \
00657           : "%0" ((USItype) (u)),                              \
00658             "g" ((USItype) (v)));                              \
00659   (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
00660 #define __umulsidi3(u, v) \
00661   ({UDItype __w;                                               \
00662     __asm__ ("meid %2,%0"                                      \
00663             : "=g" (__w)                                       \
00664             : "%0" ((USItype) (u)),                                   \
00665               "g" ((USItype) (v)));                                   \
00666     __w; })
00667 #define udiv_qrnnd(q, r, n1, n0, d) \
00668   ({union {UDItype __ll;                                       \
00669           struct {USItype __l, __h;} __i;                      \
00670          } __xx;                                               \
00671   __xx.__i.__h = (n1); __xx.__i.__l = (n0);                           \
00672   __asm__ ("deid %2,%0"                                               \
00673           : "=g" (__xx.__ll)                                          \
00674           : "0" (__xx.__ll),                                          \
00675             "g" ((USItype) (d)));                              \
00676   (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
00677 #define count_trailing_zeros(count,x) \
00678   do {                                                         \
00679     __asm__ ("ffsd     %2,%0"                                         \
00680             : "=r" ((USItype) (count))                                \
00681             : "0" ((USItype) 0),                               \
00682               "r" ((USItype) (x)));                                   \
00683   } while (0)
00684 #endif /* __ns32000__ */
00685 
00686 /* FIXME: We should test _IBMR2 here when we add assembly support for the
00687    system vendor compilers.
00688    FIXME: What's needed for gcc PowerPC VxWorks?  __vxworks__ is not good
00689    enough, since that hits ARM and m68k too.  */
00690 #if (defined (_ARCH_PPC)    /* AIX */                          \
00691      || defined (_ARCH_PWR) /* AIX */                          \
00692      || defined (_ARCH_COM) /* AIX */                          \
00693      || defined (__powerpc__)      /* gcc */                          \
00694      || defined (__POWERPC__)      /* BEOS */                         \
00695      || defined (__ppc__)   /* Darwin */                       \
00696      || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */    \
00697      || (defined (PPC) && defined (CPU_FAMILY)    /* VxWorks */               \
00698          && CPU_FAMILY == PPC)                                                \
00699      ) && W_TYPE_SIZE == 32
00700 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00701   do {                                                         \
00702     if (__builtin_constant_p (bh) && (bh) == 0)                       \
00703       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"         \
00704             : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00705     else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)              \
00706       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"         \
00707             : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00708     else                                                       \
00709       __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"        \
00710             : "=r" (sh), "=&r" (sl)                                   \
00711             : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));             \
00712   } while (0)
00713 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00714   do {                                                         \
00715     if (__builtin_constant_p (ah) && (ah) == 0)                       \
00716       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"     \
00717               : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00718     else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0)              \
00719       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"     \
00720               : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00721     else if (__builtin_constant_p (bh) && (bh) == 0)                  \
00722       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"              \
00723               : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00724     else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)              \
00725       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"              \
00726               : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00727     else                                                       \
00728       __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"    \
00729               : "=r" (sh), "=&r" (sl)                                 \
00730               : "r" (ah), "r" (bh), "rI" (al), "r" (bl));             \
00731   } while (0)
00732 #define count_leading_zeros(count, x) \
00733   __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
00734 #define COUNT_LEADING_ZEROS_0 32
00735 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
00736   || defined (__ppc__)                                                    \
00737   || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */       \
00738   || (defined (PPC) && defined (CPU_FAMILY)    /* VxWorks */                  \
00739          && CPU_FAMILY == PPC)
00740 #define umul_ppmm(ph, pl, m0, m1) \
00741   do {                                                         \
00742     USItype __m0 = (m0), __m1 = (m1);                                 \
00743     __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));    \
00744     (pl) = __m0 * __m1;                                               \
00745   } while (0)
00746 #define UMUL_TIME 15
00747 #define smul_ppmm(ph, pl, m0, m1) \
00748   do {                                                         \
00749     SItype __m0 = (m0), __m1 = (m1);                                  \
00750     __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));     \
00751     (pl) = __m0 * __m1;                                               \
00752   } while (0)
00753 #define SMUL_TIME 14
00754 #define UDIV_TIME 120
00755 #elif defined (_ARCH_PWR)
00756 #define UMUL_TIME 8
00757 #define smul_ppmm(xh, xl, m0, m1) \
00758   __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
00759 #define SMUL_TIME 4
00760 #define sdiv_qrnnd(q, r, nh, nl, d) \
00761   __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
00762 #define UDIV_TIME 100
00763 #endif
00764 #endif /* 32-bit POWER architecture variants.  */
00765 
00766 /* We should test _IBMR2 here when we add assembly support for the system
00767    vendor compilers.  */
00768 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
00769 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00770   do {                                                         \
00771     if (__builtin_constant_p (bh) && (bh) == 0)                       \
00772       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"         \
00773             : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00774     else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)              \
00775       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"         \
00776             : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00777     else                                                       \
00778       __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"        \
00779             : "=r" (sh), "=&r" (sl)                                   \
00780             : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));             \
00781   } while (0)
00782 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00783   do {                                                         \
00784     if (__builtin_constant_p (ah) && (ah) == 0)                       \
00785       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"     \
00786               : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00787     else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0)              \
00788       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"     \
00789               : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00790     else if (__builtin_constant_p (bh) && (bh) == 0)                  \
00791       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"              \
00792               : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00793     else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)              \
00794       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"              \
00795               : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00796     else                                                       \
00797       __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"    \
00798               : "=r" (sh), "=&r" (sl)                                 \
00799               : "r" (ah), "r" (bh), "rI" (al), "r" (bl));             \
00800   } while (0)
00801 #define count_leading_zeros(count, x) \
00802   __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
00803 #define COUNT_LEADING_ZEROS_0 64
00804 #define umul_ppmm(ph, pl, m0, m1) \
00805   do {                                                         \
00806     UDItype __m0 = (m0), __m1 = (m1);                                 \
00807     __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));    \
00808     (pl) = __m0 * __m1;                                               \
00809   } while (0)
00810 #define UMUL_TIME 15
00811 #define smul_ppmm(ph, pl, m0, m1) \
00812   do {                                                         \
00813     DItype __m0 = (m0), __m1 = (m1);                                  \
00814     __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));     \
00815     (pl) = __m0 * __m1;                                               \
00816   } while (0)
00817 #define SMUL_TIME 14  /* ??? */
00818 #define UDIV_TIME 120 /* ??? */
00819 #endif /* 64-bit PowerPC.  */
00820 
00821 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
00822 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00823   __asm__ ("a %1,%5\n\tae %0,%3"                               \
00824           : "=r" ((USItype) (sh)),                             \
00825             "=&r" ((USItype) (sl))                             \
00826           : "%0" ((USItype) (ah)),                             \
00827             "r" ((USItype) (bh)),                              \
00828             "%1" ((USItype) (al)),                             \
00829             "r" ((USItype) (bl)))
00830 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00831   __asm__ ("s %1,%5\n\tse %0,%3"                               \
00832           : "=r" ((USItype) (sh)),                             \
00833             "=&r" ((USItype) (sl))                             \
00834           : "0" ((USItype) (ah)),                              \
00835             "r" ((USItype) (bh)),                              \
00836             "1" ((USItype) (al)),                              \
00837             "r" ((USItype) (bl)))
00838 #define umul_ppmm(ph, pl, m0, m1) \
00839   do {                                                         \
00840     USItype __m0 = (m0), __m1 = (m1);                                 \
00841     __asm__ (                                                  \
00842        "s     r2,r2\n"                                         \
00843 "      mts    r10,%2\n"                                        \
00844 "      m      r2,%3\n"                                         \
00845 "      m      r2,%3\n"                                         \
00846 "      m      r2,%3\n"                                         \
00847 "      m      r2,%3\n"                                         \
00848 "      m      r2,%3\n"                                         \
00849 "      m      r2,%3\n"                                         \
00850 "      m      r2,%3\n"                                         \
00851 "      m      r2,%3\n"                                         \
00852 "      m      r2,%3\n"                                         \
00853 "      m      r2,%3\n"                                         \
00854 "      m      r2,%3\n"                                         \
00855 "      m      r2,%3\n"                                         \
00856 "      m      r2,%3\n"                                         \
00857 "      m      r2,%3\n"                                         \
00858 "      m      r2,%3\n"                                         \
00859 "      m      r2,%3\n"                                         \
00860 "      cas    %0,r2,r0\n"                                      \
00861 "      mfs    r10,%1"                                                 \
00862             : "=r" ((USItype) (ph)),                                  \
00863               "=r" ((USItype) (pl))                                   \
00864             : "%r" (__m0),                                     \
00865               "r" (__m1)                                       \
00866             : "r2");                                           \
00867     (ph) += ((((SItype) __m0 >> 31) & __m1)                           \
00868             + (((SItype) __m1 >> 31) & __m0));                        \
00869   } while (0)
00870 #define UMUL_TIME 20
00871 #define UDIV_TIME 200
00872 #define count_leading_zeros(count, x) \
00873   do {                                                         \
00874     if ((x) >= 0x10000)                                               \
00875       __asm__ ("clz  %0,%1"                                    \
00876               : "=r" ((USItype) (count))                       \
00877               : "r" ((USItype) (x) >> 16));                           \
00878     else                                                       \
00879       {                                                               \
00880        __asm__ ("clz %0,%1"                                    \
00881                : "=r" ((USItype) (count))                      \
00882                : "r" ((USItype) (x)));                                \
00883        (count) += 16;                                                 \
00884       }                                                               \
00885   } while (0)
00886 #endif
00887 
00888 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
00889 #ifndef __sh1__
00890 #define umul_ppmm(w1, w0, u, v) \
00891   __asm__ (                                                    \
00892        "dmulu.l      %2,%3\n\tsts%M1      macl,%1\n\tsts%M0    mach,%0"      \
00893           : "=r<" ((USItype)(w1)),                             \
00894             "=r<" ((USItype)(w0))                              \
00895           : "r" ((USItype)(u)),                                \
00896             "r" ((USItype)(v))                                        \
00897           : "macl", "mach")
00898 #define UMUL_TIME 5
00899 #endif
00900 
00901 /* This is the same algorithm as __udiv_qrnnd_c.  */
00902 #define UDIV_NEEDS_NORMALIZATION 1
00903 
00904 #define udiv_qrnnd(q, r, n1, n0, d) \
00905   do {                                                         \
00906     extern UWtype __udiv_qrnnd_16 (UWtype, UWtype)                    \
00907                         __attribute__ ((visibility ("hidden")));      \
00908     /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */       \
00909     __asm__ (                                                  \
00910        "mov%M4 %4,r5\n"                                        \
00911 "      swap.w %3,r4\n"                                                \
00912 "      swap.w r5,r6\n"                                                \
00913 "      jsr @%5\n"                                              \
00914 "      shll16 r6\n"                                            \
00915 "      swap.w r4,r4\n"                                                \
00916 "      jsr @%5\n"                                              \
00917 "      swap.w r1,%0\n"                                                \
00918 "      or r1,%0"                                               \
00919        : "=r" (q), "=&z" (r)                                          \
00920        : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16)         \
00921        : "r1", "r2", "r4", "r5", "r6", "pr");                         \
00922   } while (0)
00923 
00924 #define UDIV_TIME 80
00925 
00926 #define sub_ddmmss(sh, sl, ah, al, bh, bl)                            \
00927   __asm__ ("clrt;subc %5,%1; subc %4,%0"                       \
00928           : "=r" (sh), "=r" (sl)                               \
00929           : "0" (ah), "1" (al), "r" (bh), "r" (bl))
00930 
00931 #endif /* __sh__ */
00932 
00933 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
00934 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
00935 #define count_leading_zeros(count, x) \
00936   do                                                           \
00937     {                                                          \
00938       UDItype x_ = (USItype)(x);                               \
00939       SItype c_;                                               \
00940                                                                \
00941       __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_));                  \
00942       (count) = c_ - 31;                                       \
00943     }                                                          \
00944   while (0)
00945 #define COUNT_LEADING_ZEROS_0 32
00946 #endif
00947 
00948 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
00949     && W_TYPE_SIZE == 32
00950 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00951   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"                        \
00952           : "=r" ((USItype) (sh)),                             \
00953             "=&r" ((USItype) (sl))                             \
00954           : "%rJ" ((USItype) (ah)),                                   \
00955             "rI" ((USItype) (bh)),                             \
00956             "%rJ" ((USItype) (al)),                                   \
00957             "rI" ((USItype) (bl))                              \
00958           __CLOBBER_CC)
00959 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00960   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"                        \
00961           : "=r" ((USItype) (sh)),                             \
00962             "=&r" ((USItype) (sl))                             \
00963           : "rJ" ((USItype) (ah)),                             \
00964             "rI" ((USItype) (bh)),                             \
00965             "rJ" ((USItype) (al)),                             \
00966             "rI" ((USItype) (bl))                              \
00967           __CLOBBER_CC)
00968 #if defined (__sparc_v8__)
00969 #define umul_ppmm(w1, w0, u, v) \
00970   __asm__ ("umul %2,%3,%1;rd %%y,%0"                                  \
00971           : "=r" ((USItype) (w1)),                             \
00972             "=r" ((USItype) (w0))                              \
00973           : "r" ((USItype) (u)),                               \
00974             "r" ((USItype) (v)))
00975 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
00976   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
00977           : "=&r" ((USItype) (__q)),                                  \
00978             "=&r" ((USItype) (__r))                                   \
00979           : "r" ((USItype) (__n1)),                                   \
00980             "r" ((USItype) (__n0)),                                   \
00981             "r" ((USItype) (__d)))
00982 #else
00983 #if defined (__sparclite__)
00984 /* This has hardware multiply but not divide.  It also has two additional
00985    instructions scan (ffs from high bit) and divscc.  */
00986 #define umul_ppmm(w1, w0, u, v) \
00987   __asm__ ("umul %2,%3,%1;rd %%y,%0"                                  \
00988           : "=r" ((USItype) (w1)),                             \
00989             "=r" ((USItype) (w0))                              \
00990           : "r" ((USItype) (u)),                               \
00991             "r" ((USItype) (v)))
00992 #define udiv_qrnnd(q, r, n1, n0, d) \
00993   __asm__ ("! Inlined udiv_qrnnd\n"                                   \
00994 "      wr     %%g0,%2,%%y   ! Not a delayed write for sparclite\n"    \
00995 "      tst    %%g0\n"                                                 \
00996 "      divscc %3,%4,%%g1\n"                                    \
00997 "      divscc %%g1,%4,%%g1\n"                                         \
00998 "      divscc %%g1,%4,%%g1\n"                                         \
00999 "      divscc %%g1,%4,%%g1\n"                                         \
01000 "      divscc %%g1,%4,%%g1\n"                                         \
01001 "      divscc %%g1,%4,%%g1\n"                                         \
01002 "      divscc %%g1,%4,%%g1\n"                                         \
01003 "      divscc %%g1,%4,%%g1\n"                                         \
01004 "      divscc %%g1,%4,%%g1\n"                                         \
01005 "      divscc %%g1,%4,%%g1\n"                                         \
01006 "      divscc %%g1,%4,%%g1\n"                                         \
01007 "      divscc %%g1,%4,%%g1\n"                                         \
01008 "      divscc %%g1,%4,%%g1\n"                                         \
01009 "      divscc %%g1,%4,%%g1\n"                                         \
01010 "      divscc %%g1,%4,%%g1\n"                                         \
01011 "      divscc %%g1,%4,%%g1\n"                                         \
01012 "      divscc %%g1,%4,%%g1\n"                                         \
01013 "      divscc %%g1,%4,%%g1\n"                                         \
01014 "      divscc %%g1,%4,%%g1\n"                                         \
01015 "      divscc %%g1,%4,%%g1\n"                                         \
01016 "      divscc %%g1,%4,%%g1\n"                                         \
01017 "      divscc %%g1,%4,%%g1\n"                                         \
01018 "      divscc %%g1,%4,%%g1\n"                                         \
01019 "      divscc %%g1,%4,%%g1\n"                                         \
01020 "      divscc %%g1,%4,%%g1\n"                                         \
01021 "      divscc %%g1,%4,%%g1\n"                                         \
01022 "      divscc %%g1,%4,%%g1\n"                                         \
01023 "      divscc %%g1,%4,%%g1\n"                                         \
01024 "      divscc %%g1,%4,%%g1\n"                                         \
01025 "      divscc %%g1,%4,%%g1\n"                                         \
01026 "      divscc %%g1,%4,%%g1\n"                                         \
01027 "      divscc %%g1,%4,%0\n"                                    \
01028 "      rd     %%y,%1\n"                                        \
01029 "      bl,a 1f\n"                                              \
01030 "      add    %1,%4,%1\n"                                      \
01031 "1:    ! End of inline udiv_qrnnd"                             \
01032           : "=r" ((USItype) (q)),                              \
01033             "=r" ((USItype) (r))                               \
01034           : "r" ((USItype) (n1)),                              \
01035             "r" ((USItype) (n0)),                              \
01036             "rI" ((USItype) (d))                               \
01037           : "g1" __AND_CLOBBER_CC)
01038 #define UDIV_TIME 37
01039 #define count_leading_zeros(count, x) \
01040   do {                                                                  \
01041   __asm__ ("scan %1,1,%0"                                               \
01042            : "=r" ((USItype) (count))                                   \
01043            : "r" ((USItype) (x)));                             \
01044   } while (0)
01045 /* Early sparclites return 63 for an argument of 0, but they warn that future
01046    implementations might change this.  Therefore, leave COUNT_LEADING_ZEROS_0
01047    undefined.  */
01048 #else
01049 /* SPARC without integer multiplication and divide instructions.
01050    (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
01051 #define umul_ppmm(w1, w0, u, v) \
01052   __asm__ ("! Inlined umul_ppmm\n"                             \
01053 "      wr     %%g0,%2,%%y   ! SPARC has 0-3 delay insn after a wr\n"\
01054 "      sra    %3,31,%%o5    ! Don't move this insn\n"          \
01055 "      and    %2,%%o5,%%o5  ! Don't move this insn\n"          \
01056 "      andcc  %%g0,0,%%g1   ! Don't move this insn\n"          \
01057 "      mulscc %%g1,%3,%%g1\n"                                         \
01058 "      mulscc %%g1,%3,%%g1\n"                                         \
01059 "      mulscc %%g1,%3,%%g1\n"                                         \
01060 "      mulscc %%g1,%3,%%g1\n"                                         \
01061 "      mulscc %%g1,%3,%%g1\n"                                         \
01062 "      mulscc %%g1,%3,%%g1\n"                                         \
01063 "      mulscc %%g1,%3,%%g1\n"                                         \
01064 "      mulscc %%g1,%3,%%g1\n"                                         \
01065 "      mulscc %%g1,%3,%%g1\n"                                         \
01066 "      mulscc %%g1,%3,%%g1\n"                                         \
01067 "      mulscc %%g1,%3,%%g1\n"                                         \
01068 "      mulscc %%g1,%3,%%g1\n"                                         \
01069 "      mulscc %%g1,%3,%%g1\n"                                         \
01070 "      mulscc %%g1,%3,%%g1\n"                                         \
01071 "      mulscc %%g1,%3,%%g1\n"                                         \
01072 "      mulscc %%g1,%3,%%g1\n"                                         \
01073 "      mulscc %%g1,%3,%%g1\n"                                         \
01074 "      mulscc %%g1,%3,%%g1\n"                                         \
01075 "      mulscc %%g1,%3,%%g1\n"                                         \
01076 "      mulscc %%g1,%3,%%g1\n"                                         \
01077 "      mulscc %%g1,%3,%%g1\n"                                         \
01078 "      mulscc %%g1,%3,%%g1\n"                                         \
01079 "      mulscc %%g1,%3,%%g1\n"                                         \
01080 "      mulscc %%g1,%3,%%g1\n"                                         \
01081 "      mulscc %%g1,%3,%%g1\n"                                         \
01082 "      mulscc %%g1,%3,%%g1\n"                                         \
01083 "      mulscc %%g1,%3,%%g1\n"                                         \
01084 "      mulscc %%g1,%3,%%g1\n"                                         \
01085 "      mulscc %%g1,%3,%%g1\n"                                         \
01086 "      mulscc %%g1,%3,%%g1\n"                                         \
01087 "      mulscc %%g1,%3,%%g1\n"                                         \
01088 "      mulscc %%g1,%3,%%g1\n"                                         \
01089 "      mulscc %%g1,0,%%g1\n"                                          \
01090 "      add    %%g1,%%o5,%0\n"                                         \
01091 "      rd     %%y,%1"                                                 \
01092           : "=r" ((USItype) (w1)),                             \
01093             "=r" ((USItype) (w0))                              \
01094           : "%rI" ((USItype) (u)),                             \
01095             "r" ((USItype) (v))                                       \
01096           : "g1", "o5" __AND_CLOBBER_CC)
01097 #define UMUL_TIME 39        /* 39 instructions */
01098 /* It's quite necessary to add this much assembler for the sparc.
01099    The default udiv_qrnnd (in C) is more than 10 times slower!  */
01100 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
01101   __asm__ ("! Inlined udiv_qrnnd\n"                                   \
01102 "      mov    32,%%g1\n"                                       \
01103 "      subcc  %1,%2,%%g0\n"                                    \
01104 "1:    bcs    5f\n"                                            \
01105 "       addxcc %0,%0,%0     ! shift n1n0 and a q-bit in lsb\n" \
01106 "      sub    %1,%2,%1      ! this kills msb of n\n"           \
01107 "      addx   %1,%1,%1      ! so this can't give carry\n"             \
01108 "      subcc  %%g1,1,%%g1\n"                                          \
01109 "2:    bne    1b\n"                                            \
01110 "       subcc %1,%2,%%g0\n"                                    \
01111 "      bcs    3f\n"                                            \
01112 "       addxcc %0,%0,%0     ! shift n1n0 and a q-bit in lsb\n" \
01113 "      b      3f\n"                                            \
01114 "       sub   %1,%2,%1      ! this kills msb of n\n"           \
01115 "4:    sub    %1,%2,%1\n"                                      \
01116 "5:    addxcc %1,%1,%1\n"                                      \
01117 "      bcc    2b\n"                                            \
01118 "       subcc %%g1,1,%%g1\n"                                          \
01119 "! Got carry from n.  Subtract next step to cancel this carry.\n"     \
01120 "      bne    4b\n"                                            \
01121 "       addcc %0,%0,%0      ! shift n1n0 and a 0-bit in lsb\n" \
01122 "      sub    %1,%2,%1\n"                                      \
01123 "3:    xnor   %0,0,%0\n"                                       \
01124 "      ! End of inline udiv_qrnnd"                             \
01125           : "=&r" ((USItype) (__q)),                                  \
01126             "=&r" ((USItype) (__r))                                   \
01127           : "r" ((USItype) (__d)),                             \
01128             "1" ((USItype) (__n1)),                                   \
01129             "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
01130 #define UDIV_TIME (3+7*32)  /* 7 instructions/iteration. 32 iterations.  */
01131 #endif /* __sparclite__ */
01132 #endif /* __sparc_v8__ */
01133 #endif /* sparc32 */
01134 
01135 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
01136     && W_TYPE_SIZE == 64
01137 #define add_ssaaaa(sh, sl, ah, al, bh, bl)                            \
01138   __asm__ ("addcc %r4,%5,%1\n\t"                               \
01139           "add %r2,%3,%0\n\t"                                         \
01140           "bcs,a,pn %%xcc, 1f\n\t"                             \
01141           "add %0, 1, %0\n"                                    \
01142           "1:"                                                        \
01143           : "=r" ((UDItype)(sh)),                              \
01144             "=&r" ((UDItype)(sl))                              \
01145           : "%rJ" ((UDItype)(ah)),                             \
01146             "rI" ((UDItype)(bh)),                              \
01147             "%rJ" ((UDItype)(al)),                             \
01148             "rI" ((UDItype)(bl))                                      \
01149           __CLOBBER_CC)
01150 
01151 #define sub_ddmmss(sh, sl, ah, al, bh, bl)                            \
01152   __asm__ ("subcc %r4,%5,%1\n\t"                               \
01153           "sub %r2,%3,%0\n\t"                                         \
01154           "bcs,a,pn %%xcc, 1f\n\t"                             \
01155           "sub %0, 1, %0\n\t"                                         \
01156           "1:"                                                        \
01157           : "=r" ((UDItype)(sh)),                              \
01158             "=&r" ((UDItype)(sl))                              \
01159           : "rJ" ((UDItype)(ah)),                              \
01160             "rI" ((UDItype)(bh)),                              \
01161             "rJ" ((UDItype)(al)),                              \
01162             "rI" ((UDItype)(bl))                                      \
01163           __CLOBBER_CC)
01164 
01165 #define umul_ppmm(wh, wl, u, v)                                       \
01166   do {                                                         \
01167          UDItype tmp1, tmp2, tmp3, tmp4;                       \
01168          __asm__ __volatile__ (                                \
01169                  "srl %7,0,%3\n\t"                             \
01170                  "mulx %3,%6,%1\n\t"                                  \
01171                  "srlx %6,32,%2\n\t"                                  \
01172                  "mulx %2,%3,%4\n\t"                                  \
01173                  "sllx %4,32,%5\n\t"                                  \
01174                  "srl %6,0,%3\n\t"                             \
01175                  "sub %1,%5,%5\n\t"                                   \
01176                  "srlx %5,32,%5\n\t"                                  \
01177                  "addcc %4,%5,%4\n\t"                                 \
01178                  "srlx %7,32,%5\n\t"                                  \
01179                  "mulx %3,%5,%3\n\t"                                  \
01180                  "mulx %2,%5,%5\n\t"                                  \
01181                  "sethi %%hi(0x80000000),%2\n\t"               \
01182                  "addcc %4,%3,%4\n\t"                                 \
01183                  "srlx %4,32,%4\n\t"                                  \
01184                  "add %2,%2,%2\n\t"                                   \
01185                  "movcc %%xcc,%%g0,%2\n\t"                            \
01186                  "addcc %5,%4,%5\n\t"                                 \
01187                  "sllx %3,32,%3\n\t"                                  \
01188                  "add %1,%3,%1\n\t"                                   \
01189                  "add %5,%2,%0"                                \
01190           : "=r" ((UDItype)(wh)),                              \
01191             "=&r" ((UDItype)(wl)),                             \
01192             "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)    \
01193           : "r" ((UDItype)(u)),                                \
01194             "r" ((UDItype)(v))                                        \
01195           __CLOBBER_CC);                                       \
01196   } while (0)
01197 #define UMUL_TIME 96
01198 #define UDIV_TIME 230
01199 #endif /* sparc64 */
01200 
01201 #if defined (__vax__) && W_TYPE_SIZE == 32
01202 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
01203   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"                                \
01204           : "=g" ((USItype) (sh)),                             \
01205             "=&g" ((USItype) (sl))                             \
01206           : "%0" ((USItype) (ah)),                             \
01207             "g" ((USItype) (bh)),                              \
01208             "%1" ((USItype) (al)),                             \
01209             "g" ((USItype) (bl)))
01210 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
01211   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"                                \
01212           : "=g" ((USItype) (sh)),                             \
01213             "=&g" ((USItype) (sl))                             \
01214           : "0" ((USItype) (ah)),                              \
01215             "g" ((USItype) (bh)),                              \
01216             "1" ((USItype) (al)),                              \
01217             "g" ((USItype) (bl)))
01218 #define umul_ppmm(xh, xl, m0, m1) \
01219   do {                                                         \
01220     union {                                                    \
01221        UDItype __ll;                                           \
01222        struct {USItype __l, __h;} __i;                                \
01223       } __xx;                                                  \
01224     USItype __m0 = (m0), __m1 = (m1);                                 \
01225     __asm__ ("emul %1,%2,$0,%0"                                       \
01226             : "=r" (__xx.__ll)                                        \
01227             : "g" (__m0),                                      \
01228               "g" (__m1));                                     \
01229     (xh) = __xx.__i.__h;                                       \
01230     (xl) = __xx.__i.__l;                                       \
01231     (xh) += ((((SItype) __m0 >> 31) & __m1)                           \
01232             + (((SItype) __m1 >> 31) & __m0));                        \
01233   } while (0)
01234 #define sdiv_qrnnd(q, r, n1, n0, d) \
01235   do {                                                         \
01236     union {DItype __ll;                                               \
01237           struct {SItype __l, __h;} __i;                       \
01238          } __xx;                                               \
01239     __xx.__i.__h = n1; __xx.__i.__l = n0;                      \
01240     __asm__ ("ediv %3,%2,%0,%1"                                       \
01241             : "=g" (q), "=g" (r)                               \
01242             : "g" (__xx.__ll), "g" (d));                       \
01243   } while (0)
01244 #endif /* __vax__ */
01245 
01246 #if defined (__xtensa__) && W_TYPE_SIZE == 32
01247 /* This code is not Xtensa-configuration-specific, so rely on the compiler
01248    to expand builtin functions depending on what configuration features
01249    are available.  This avoids library calls when the operation can be
01250    performed in-line.  */
01251 #define umul_ppmm(w1, w0, u, v)                                       \
01252   do {                                                         \
01253     DWunion __w;                                               \
01254     __w.ll = __builtin_umulsidi3 (u, v);                       \
01255     w1 = __w.s.high;                                           \
01256     w0 = __w.s.low;                                            \
01257   } while (0)
01258 #define __umulsidi3(u, v)          __builtin_umulsidi3 (u, v)
01259 #define count_leading_zeros(COUNT, X)     ((COUNT) = __builtin_clz (X))
01260 #define count_trailing_zeros(COUNT, X)    ((COUNT) = __builtin_ctz (X))
01261 #endif /* __xtensa__ */
01262 
01263 #if defined (__z8000__) && W_TYPE_SIZE == 16
01264 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
01265   __asm__ ("add      %H1,%H5\n\tadc       %H0,%H3"                           \
01266           : "=r" ((unsigned int)(sh)),                                \
01267             "=&r" ((unsigned int)(sl))                                \
01268           : "%0" ((unsigned int)(ah)),                                \
01269             "r" ((unsigned int)(bh)),                                 \
01270             "%1" ((unsigned int)(al)),                                \
01271             "rQR" ((unsigned int)(bl)))
01272 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
01273   __asm__ ("sub      %H1,%H5\n\tsbc       %H0,%H3"                           \
01274           : "=r" ((unsigned int)(sh)),                                \
01275             "=&r" ((unsigned int)(sl))                                \
01276           : "0" ((unsigned int)(ah)),                                 \
01277             "r" ((unsigned int)(bh)),                                 \
01278             "1" ((unsigned int)(al)),                                 \
01279             "rQR" ((unsigned int)(bl)))
01280 #define umul_ppmm(xh, xl, m0, m1) \
01281   do {                                                         \
01282     union {long int __ll;                                      \
01283           struct {unsigned int __h, __l;} __i;                        \
01284          } __xx;                                               \
01285     unsigned int __m0 = (m0), __m1 = (m1);                            \
01286     __asm__ ("mult   %S0,%H3"                                  \
01287             : "=r" (__xx.__i.__h),                             \
01288               "=r" (__xx.__i.__l)                              \
01289             : "%1" (__m0),                                     \
01290               "rQR" (__m1));                                          \
01291     (xh) = __xx.__i.__h; (xl) = __xx.__i.__l;                         \
01292     (xh) += ((((signed int) __m0 >> 15) & __m1)                       \
01293             + (((signed int) __m1 >> 15) & __m0));                    \
01294   } while (0)
01295 #endif /* __z8000__ */
01296 
01297 #endif /* __GNUC__ */
01298 
01299 /* If this machine has no inline assembler, use C macros.  */
01300 
01301 #if !defined (add_ssaaaa)
01302 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
01303   do {                                                         \
01304     UWtype __x;                                                       \
01305     __x = (al) + (bl);                                                \
01306     (sh) = (ah) + (bh) + (__x < (al));                                \
01307     (sl) = __x;                                                       \
01308   } while (0)
01309 #endif
01310 
01311 #if !defined (sub_ddmmss)
01312 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
01313   do {                                                         \
01314     UWtype __x;                                                       \
01315     __x = (al) - (bl);                                                \
01316     (sh) = (ah) - (bh) - (__x > (al));                                \
01317     (sl) = __x;                                                       \
01318   } while (0)
01319 #endif
01320 
01321 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
01322    smul_ppmm.  */
01323 #if !defined (umul_ppmm) && defined (smul_ppmm)
01324 #define umul_ppmm(w1, w0, u, v)                                       \
01325   do {                                                         \
01326     UWtype __w1;                                               \
01327     UWtype __xm0 = (u), __xm1 = (v);                                  \
01328     smul_ppmm (__w1, w0, __xm0, __xm1);                               \
01329     (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1)             \
01330               + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0);              \
01331   } while (0)
01332 #endif
01333 
01334 /* If we still don't have umul_ppmm, define it using plain C.  */
01335 #if !defined (umul_ppmm)
01336 #define umul_ppmm(w1, w0, u, v)                                       \
01337   do {                                                         \
01338     UWtype __x0, __x1, __x2, __x3;                             \
01339     UHWtype __ul, __vl, __uh, __vh;                                   \
01340                                                                \
01341     __ul = __ll_lowpart (u);                                          \
01342     __uh = __ll_highpart (u);                                         \
01343     __vl = __ll_lowpart (v);                                          \
01344     __vh = __ll_highpart (v);                                         \
01345                                                                \
01346     __x0 = (UWtype) __ul * __vl;                               \
01347     __x1 = (UWtype) __ul * __vh;                               \
01348     __x2 = (UWtype) __uh * __vl;                               \
01349     __x3 = (UWtype) __uh * __vh;                               \
01350                                                                \
01351     __x1 += __ll_highpart (__x0);/* this can't give carry */          \
01352     __x1 += __x2;           /* but this indeed can */          \
01353     if (__x1 < __x2)        /* did we get it? */               \
01354       __x3 += __ll_B;              /* yes, add it in the proper pos.  */     \
01355                                                                \
01356     (w1) = __x3 + __ll_highpart (__x1);                               \
01357     (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);        \
01358   } while (0)
01359 #endif
01360 
01361 #if !defined (__umulsidi3)
01362 #define __umulsidi3(u, v) \
01363   ({DWunion __w;                                               \
01364     umul_ppmm (__w.s.high, __w.s.low, u, v);                          \
01365     __w.ll; })
01366 #endif
01367 
01368 /* Define this unconditionally, so it can be used for debugging.  */
01369 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
01370   do {                                                         \
01371     UWtype __d1, __d0, __q1, __q0;                             \
01372     UWtype __r1, __r0, __m;                                    \
01373     __d1 = __ll_highpart (d);                                         \
01374     __d0 = __ll_lowpart (d);                                          \
01375                                                                \
01376     __r1 = (n1) % __d1;                                               \
01377     __q1 = (n1) / __d1;                                               \
01378     __m = (UWtype) __q1 * __d0;                                       \
01379     __r1 = __r1 * __ll_B | __ll_highpart (n0);                        \
01380     if (__r1 < __m)                                            \
01381       {                                                               \
01382        __q1--, __r1 += (d);                                    \
01383        if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
01384          if (__r1 < __m)                                       \
01385            __q1--, __r1 += (d);                                \
01386       }                                                               \
01387     __r1 -= __m;                                               \
01388                                                                \
01389     __r0 = __r1 % __d1;                                               \
01390     __q0 = __r1 / __d1;                                               \
01391     __m = (UWtype) __q0 * __d0;                                       \
01392     __r0 = __r0 * __ll_B | __ll_lowpart (n0);                         \
01393     if (__r0 < __m)                                            \
01394       {                                                               \
01395        __q0--, __r0 += (d);                                    \
01396        if (__r0 >= (d))                                        \
01397          if (__r0 < __m)                                       \
01398            __q0--, __r0 += (d);                                \
01399       }                                                               \
01400     __r0 -= __m;                                               \
01401                                                                \
01402     (q) = (UWtype) __q1 * __ll_B | __q0;                       \
01403     (r) = __r0;                                                       \
01404   } while (0)
01405 
01406 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
01407    __udiv_w_sdiv (defined in libgcc or elsewhere).  */
01408 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
01409 #define udiv_qrnnd(q, r, nh, nl, d) \
01410   do {                                                         \
01411     USItype __r;                                               \
01412     (q) = __udiv_w_sdiv (&__r, nh, nl, d);                            \
01413     (r) = __r;                                                        \
01414   } while (0)
01415 #endif
01416 
01417 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
01418 #if !defined (udiv_qrnnd)
01419 #define UDIV_NEEDS_NORMALIZATION 1
01420 #define udiv_qrnnd __udiv_qrnnd_c
01421 #endif
01422 
01423 #if !defined (count_leading_zeros)
01424 #define count_leading_zeros(count, x) \
01425   do {                                                         \
01426     UWtype __xr = (x);                                                \
01427     UWtype __a;                                                       \
01428                                                                \
01429     if (W_TYPE_SIZE <= 32)                                     \
01430       {                                                               \
01431        __a = __xr < ((UWtype)1<<2*__BITS4)                            \
01432          ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4)                \
01433          : (__xr < ((UWtype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);  \
01434       }                                                               \
01435     else                                                       \
01436       {                                                               \
01437        for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8)                 \
01438          if (((__xr >> __a) & 0xff) != 0)                      \
01439            break;                                              \
01440       }                                                               \
01441                                                                \
01442     (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a);           \
01443   } while (0)
01444 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
01445 #endif
01446 
01447 #if !defined (count_trailing_zeros)
01448 /* Define count_trailing_zeros using count_leading_zeros.  The latter might be
01449    defined in asm, but if it is not, the C version above is good enough.  */
01450 #define count_trailing_zeros(count, x) \
01451   do {                                                         \
01452     UWtype __ctz_x = (x);                                      \
01453     UWtype __ctz_c;                                            \
01454     count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x);                \
01455     (count) = W_TYPE_SIZE - 1 - __ctz_c;                       \
01456   } while (0)
01457 #endif
01458 
01459 #ifndef UDIV_NEEDS_NORMALIZATION
01460 #define UDIV_NEEDS_NORMALIZATION 0
01461 #endif