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glibc  2.9
i960ca.h
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00001 /* Copyright (C) 1994, 1996, 1997 Free Software Foundation, Inc.
00002    This file is part of the GNU C Library.
00003    Contributed by Joel Sherrill (jsherril@redstone-emh2.army.mil),
00004    On-Line Applications Research Corporation.
00005 
00006    The GNU C Library is free software; you can redistribute it and/or
00007    modify it under the terms of the GNU Lesser General Public
00008    License as published by the Free Software Foundation; either
00009    version 2.1 of the License, or (at your option) any later version.
00010 
00011    The GNU C Library is distributed in the hope that it will be useful,
00012    but WITHOUT ANY WARRANTY; without even the implied warranty of
00013    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00014    Lesser General Public License for more details.
00015 
00016    You should have received a copy of the GNU Lesser General Public
00017    License along with the GNU C Library; if not, write to the Free
00018    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
00019    02111-1307 USA.  */
00020 
00021 /* i960ca.h
00022  *
00023  *  This file contains macros which are used to access i80960CA
00024  *  registers which are not addressable by C.  The functions
00025  *  in this file should be useful to the developer of target
00026  *  specific code.
00027  */
00028 
00029 #ifndef i960ca_h__
00030 #define i960ca_h__
00031 
00032 typedef unsigned char   unsigned8;
00033 typedef unsigned short  unsigned16;
00034 typedef unsigned int    unsigned32;
00035 
00036 /*
00037  *  Intel i80960CA Processor Control Block
00038  */
00039 
00040 struct i80960ca_prcb {
00041   unsigned32          *fault_tbl;     /* fault table base address     */
00042   struct i80960ca_ctltbl
00043                       *control_tbl;   /* control table base address   */
00044   unsigned32           initial_ac;    /* AC register initial value    */
00045   unsigned32           fault_config;  /* fault configuration word     */
00046   void                *intr_tbl;      /* interrupt table base address */
00047   void                *sys_proc_tbl;  /* system procedure table       */
00048                                       /*   base address               */
00049   unsigned32           reserved;      /* reserved                     */
00050   unsigned32          *intr_stack;    /* interrupt stack pointer      */
00051   unsigned32           ins_cache_cfg; /* instruction cache            */
00052                                       /*   configuration word         */
00053   unsigned32           reg_cache_cfg; /* register cache               */
00054                                       /*   configuration word         */
00055 };
00056 
00057 /*
00058  *  Intel i80960CA Control Table
00059  */
00060 
00061 struct i80960ca_ctltbl {
00062                             /* Control Group 0 */
00063   unsigned32       ipb0;              /* IP breakpoint 0 */
00064   unsigned32       ipb1;              /* IP breakpoint 1 */
00065   unsigned32       dab0;              /* data address breakpoint 0 */
00066   unsigned32       dab1;              /* data address breakpoint 1 */
00067                             /* Control Group 1 */
00068   unsigned32       imap0;             /* interrupt map 0 */
00069   unsigned32       imap1;             /* interrupt map 1 */
00070   unsigned32       imap2;             /* interrupt map 2 */
00071   unsigned32       icon;              /* interrupt control */
00072                             /* Control Group 2 */
00073   unsigned32       mcon0;             /* memory region 0 configuration */
00074   unsigned32       mcon1;             /* memory region 1 configuration */
00075   unsigned32       mcon2;             /* memory region 2 configuration */
00076   unsigned32       mcon3;             /* memory region 3 configuration */
00077                             /* Control Group 3 */
00078   unsigned32       mcon4;             /* memory region 4 configuration */
00079   unsigned32       mcon5;             /* memory region 5 configuration */
00080   unsigned32       mcon6;             /* memory region 6 configuration */
00081   unsigned32       mcon7;             /* memory region 7 configuration */
00082                             /* Control Group 4 */
00083   unsigned32       mcon8;             /* memory region 8 configuration */
00084   unsigned32       mcon9;             /* memory region 9 configuration */
00085   unsigned32       mcon10;            /* memory region 10 configuration */
00086   unsigned32       mcon11;            /* memory region 11 configuration */
00087                             /* Control Group 5 */
00088   unsigned32       mcon12;            /* memory region 12 configuration */
00089   unsigned32       mcon13;            /* memory region 13 configuration */
00090   unsigned32       mcon14;            /* memory region 14 configuration */
00091   unsigned32       mcon15;            /* memory region 15 configuration */
00092                             /* Control Group 6 */
00093   unsigned32       bpcon;             /* breakpoint control */
00094   unsigned32       tc;                /* trace control */
00095   unsigned32       bcon;              /* bus configuration control */
00096   unsigned32       reserved;          /* reserved */
00097 };
00098 
00099 #define disable_intr( oldlevel ) \
00100   { (oldlevel) = 0x1f0000; \
00101     asm volatile ( "modpc   0,%1,%1" \
00102                        : "=d" ((oldlevel)) \
00103                        : "0"  ((oldlevel)) ); \
00104   }
00105 
00106 #define enable_intr( oldlevel ) \
00107   { unsigned32 _mask = 0x1f0000; \
00108     asm volatile ( "modpc   0,%0,%1" \
00109                        : "=d" (_mask), "=d" ((oldlevel)) \
00110                        : "0"  (_mask), "1"  ((oldlevel)) ); \
00111   }
00112 
00113 #define flash_intr( oldlevel ) \
00114   { unsigned32 _mask = 0x1f0000; \
00115     asm volatile ( "modpc   0,%0,%1 ; \
00116                     mov     %0,%1 ; \
00117                     modpc   0,%0,%1"  \
00118                        : "=d" (_mask), "=d" ((oldlevel)) \
00119                        : "0"  (_mask), "1"  ((oldlevel)) ); \
00120   }
00121 
00122 #define atomic_modify( mask, addr, prev ) \
00123  { register unsigned32  _mask = (mask); \
00124    register unsigned32 *_addr = (unsigned32 *)(addr); \
00125    asm volatile( "atmod  %0,%1,%1" \
00126                   : "=d" (_addr), "=d" (_mask) \
00127                   : "0"  (_addr), "1"  (_mask) ); \
00128    (prev) = _mask; \
00129  }
00130 
00131 #define delay( microseconds ) \
00132   { register unsigned32 _delay=(microseconds); \
00133     register unsigned32 _tmp; \
00134     asm volatile( "delay0: \
00135                      remo      3,31,%0 ; \
00136                      cmpo      0,%0 ; \
00137                      subo      1,%1,%1 ; \
00138                      cmpobne.t 0,%1,delay0 " \
00139                   : "=d" (_tmp), "=d" (_delay) \
00140                   : "0"  (_tmp), "1"  (_delay) ); \
00141   }
00142 
00143 #define enable_tracing() \
00144  { register unsigned32 _pc = 0x1; \
00145    asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
00146  }
00147 
00148 #define unmask_intr( xint ) \
00149  { register unsigned32 _mask= (1<<(xint)); \
00150    asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
00151  }
00152 
00153 #define mask_intr( xint ) \
00154  { register unsigned32 _mask= (1<<(xint)); \
00155    asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
00156  }
00157 
00158 #define clear_intr( xint ) \
00159  { register unsigned32 _xint=(xint); \
00160    asm volatile( "loop_til_cleared:" \
00161                  "  clrbit %0,sf0,sf0 ;" \
00162                  "  bbs    %0,sf0,loop_til_cleared" \
00163                  : "=d" (_xint) : "0" (_xint) ); \
00164  }
00165 
00166 #define reload_ctl_group( group ) \
00167  { register int _cmd = ((group)|0x400) ; \
00168    asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
00169  }
00170 
00171 #define cause_intr( intr ) \
00172  { register int _intr = (intr); \
00173    asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
00174  }
00175 
00176 #define soft_reset( prcb ) \
00177  { register struct i80960ca_prcb *_prcb = (prcb); \
00178    register unsigned32         *_next=0; \
00179    register unsigned32          _cmd  = 0x30000; \
00180    asm volatile( "lda    next,%1; \
00181                   sysctl %0,%1,%2; \
00182             next: mov    g0,g0" \
00183                   : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
00184                   : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
00185  }
00186 
00187 static inline unsigned32 pend_intrs()
00188 { register unsigned32 _intr=0;
00189   asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
00190   return ( _intr );
00191 }
00192 
00193 static inline unsigned32 mask_intrs()
00194 { register unsigned32 _intr=0;
00195   asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
00196   return( _intr );
00197 }
00198 
00199 static inline unsigned32 get_fp()
00200 { register unsigned32 _fp=0;
00201   asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
00202   return ( _fp );
00203 }
00204 
00205 #endif
00206 /* end of include file */