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cell-binutils  2.17cvs20070401
xtensa.h
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00001 /* Xtensa ELF support for BFD.
00002    Copyright 2003, 2004 Free Software Foundation, Inc.
00003    Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
00004 
00005    This file is part of BFD, the Binary File Descriptor library.
00006 
00007    This program is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2 of the License, or
00010    (at your option) any later version.
00011 
00012    This program is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with this program; if not, write to the Free Software
00019    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
00020    USA.  */
00021 
00022 /* This file holds definitions specific to the Xtensa ELF ABI.  */
00023 
00024 #ifndef _ELF_XTENSA_H
00025 #define _ELF_XTENSA_H
00026 
00027 #include "elf/reloc-macros.h"
00028 
00029 /* Relocations.  */
00030 START_RELOC_NUMBERS (elf_xtensa_reloc_type)
00031      RELOC_NUMBER (R_XTENSA_NONE, 0)
00032      RELOC_NUMBER (R_XTENSA_32, 1)
00033      RELOC_NUMBER (R_XTENSA_RTLD, 2)
00034      RELOC_NUMBER (R_XTENSA_GLOB_DAT, 3)
00035      RELOC_NUMBER (R_XTENSA_JMP_SLOT, 4)
00036      RELOC_NUMBER (R_XTENSA_RELATIVE, 5)
00037      RELOC_NUMBER (R_XTENSA_PLT, 6)
00038      RELOC_NUMBER (R_XTENSA_OP0, 8)
00039      RELOC_NUMBER (R_XTENSA_OP1, 9)
00040      RELOC_NUMBER (R_XTENSA_OP2, 10) 
00041      RELOC_NUMBER (R_XTENSA_ASM_EXPAND, 11)
00042      RELOC_NUMBER (R_XTENSA_ASM_SIMPLIFY, 12)
00043      RELOC_NUMBER (R_XTENSA_GNU_VTINHERIT, 15)
00044      RELOC_NUMBER (R_XTENSA_GNU_VTENTRY, 16)
00045      RELOC_NUMBER (R_XTENSA_DIFF8, 17)
00046      RELOC_NUMBER (R_XTENSA_DIFF16, 18)
00047      RELOC_NUMBER (R_XTENSA_DIFF32, 19)
00048      RELOC_NUMBER (R_XTENSA_SLOT0_OP, 20)
00049      RELOC_NUMBER (R_XTENSA_SLOT1_OP, 21)
00050      RELOC_NUMBER (R_XTENSA_SLOT2_OP, 22)
00051      RELOC_NUMBER (R_XTENSA_SLOT3_OP, 23)
00052      RELOC_NUMBER (R_XTENSA_SLOT4_OP, 24)
00053      RELOC_NUMBER (R_XTENSA_SLOT5_OP, 25)
00054      RELOC_NUMBER (R_XTENSA_SLOT6_OP, 26)
00055      RELOC_NUMBER (R_XTENSA_SLOT7_OP, 27)
00056      RELOC_NUMBER (R_XTENSA_SLOT8_OP, 28)
00057      RELOC_NUMBER (R_XTENSA_SLOT9_OP, 29)
00058      RELOC_NUMBER (R_XTENSA_SLOT10_OP, 30)
00059      RELOC_NUMBER (R_XTENSA_SLOT11_OP, 31)
00060      RELOC_NUMBER (R_XTENSA_SLOT12_OP, 32)
00061      RELOC_NUMBER (R_XTENSA_SLOT13_OP, 33)
00062      RELOC_NUMBER (R_XTENSA_SLOT14_OP, 34)
00063      RELOC_NUMBER (R_XTENSA_SLOT0_ALT, 35)
00064      RELOC_NUMBER (R_XTENSA_SLOT1_ALT, 36)
00065      RELOC_NUMBER (R_XTENSA_SLOT2_ALT, 37)
00066      RELOC_NUMBER (R_XTENSA_SLOT3_ALT, 38)
00067      RELOC_NUMBER (R_XTENSA_SLOT4_ALT, 39)
00068      RELOC_NUMBER (R_XTENSA_SLOT5_ALT, 40)
00069      RELOC_NUMBER (R_XTENSA_SLOT6_ALT, 41)
00070      RELOC_NUMBER (R_XTENSA_SLOT7_ALT, 42)
00071      RELOC_NUMBER (R_XTENSA_SLOT8_ALT, 43)
00072      RELOC_NUMBER (R_XTENSA_SLOT9_ALT, 44)
00073      RELOC_NUMBER (R_XTENSA_SLOT10_ALT, 45)
00074      RELOC_NUMBER (R_XTENSA_SLOT11_ALT, 46)
00075      RELOC_NUMBER (R_XTENSA_SLOT12_ALT, 47)
00076      RELOC_NUMBER (R_XTENSA_SLOT13_ALT, 48)
00077      RELOC_NUMBER (R_XTENSA_SLOT14_ALT, 49)
00078 END_RELOC_NUMBERS (R_XTENSA_max)
00079 
00080 /* Processor-specific flags for the ELF header e_flags field.  */
00081 
00082 /* Four-bit Xtensa machine type field.  */
00083 #define EF_XTENSA_MACH                    0x0000000f
00084 
00085 /* Various CPU types.  */
00086 #define E_XTENSA_MACH                     0x00000000
00087 
00088 /* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
00089    Highly unlikely, but what the heck.  */
00090 
00091 #define EF_XTENSA_XT_INSN          0x00000100
00092 #define EF_XTENSA_XT_LIT           0x00000200
00093 
00094 
00095 /* Processor-specific dynamic array tags.  */
00096 
00097 /* Offset of the table that records the GOT location(s).  */
00098 #define DT_XTENSA_GOT_LOC_OFF             0x70000000
00099 
00100 /* Number of entries in the GOT location table.  */
00101 #define DT_XTENSA_GOT_LOC_SZ              0x70000001
00102 
00103 
00104 /* Definitions for instruction and literal property tables.  The
00105    tables for ".gnu.linkonce.*" sections are placed in the following
00106    sections:
00107 
00108    instruction tables:      .gnu.linkonce.x.*
00109    literal tables:   .gnu.linkonce.p.*
00110 */
00111 
00112 #define XTENSA_INSN_SEC_NAME ".xt.insn"
00113 #define XTENSA_LIT_SEC_NAME  ".xt.lit"
00114 #define XTENSA_PROP_SEC_NAME ".xt.prop"
00115 
00116 typedef struct property_table_entry_t
00117 {
00118   bfd_vma address;
00119   bfd_vma size;
00120   flagword flags;
00121 } property_table_entry;
00122 
00123 /* Flags in the property tables to specify whether blocks of memory are
00124    literals, instructions, data, or unreachable.  For instructions,
00125    blocks that begin loop targets and branch targets are designated.
00126    Blocks that do not allow density instructions, instruction reordering
00127    or transformation are also specified.  Finally, for branch targets,
00128    branch target alignment priority is included.  Alignment of the next
00129    block is specified in the current block and the size of the current
00130    block does not include any fill required to align to the next
00131    block.  */
00132    
00133 #define XTENSA_PROP_LITERAL        0x00000001
00134 #define XTENSA_PROP_INSN           0x00000002
00135 #define XTENSA_PROP_DATA           0x00000004
00136 #define XTENSA_PROP_UNREACHABLE           0x00000008
00137 /* Instruction-only properties at beginning of code. */
00138 #define XTENSA_PROP_INSN_LOOP_TARGET      0x00000010
00139 #define XTENSA_PROP_INSN_BRANCH_TARGET    0x00000020
00140 /* Instruction-only properties about code. */
00141 #define XTENSA_PROP_INSN_NO_DENSITY       0x00000040
00142 #define XTENSA_PROP_INSN_NO_REORDER       0x00000080
00143 #define XTENSA_PROP_INSN_NO_TRANSFORM     0x00000100
00144 
00145 /*  Branch target alignment information.  This transmits information
00146     to the linker optimization about the priority of aligning a
00147     particular block for branch target alignment: None, low priority,
00148     high priority, or required.  These only need to be checked in
00149     instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
00150     Common usage is:
00151 
00152     switch (GET_XTENSA_PROP_BT_ALIGN(flags))
00153     case XTENSA_PROP_BT_ALIGN_NONE:
00154     case XTENSA_PROP_BT_ALIGN_LOW:
00155     case XTENSA_PROP_BT_ALIGN_HIGH:
00156     case XTENSA_PROP_BT_ALIGN_REQUIRE:
00157 */
00158 #define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
00159 
00160 /* No branch target alignment.  */
00161 #define XTENSA_PROP_BT_ALIGN_NONE       0x0
00162 /* Low priority branch target alignment.  */
00163 #define XTENSA_PROP_BT_ALIGN_LOW        0x1
00164 /* High priority branch target alignment. */
00165 #define XTENSA_PROP_BT_ALIGN_HIGH       0x2
00166 /* Required branch target alignment.  */
00167 #define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
00168 
00169 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
00170   (((unsigned)((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
00171 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
00172   (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
00173     (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
00174 
00175 /* Alignment is specified in the block BEFORE the one that needs
00176    alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
00177    get the required alignment specified as a power of 2.  Use
00178    SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
00179    alignment.  Be careful of side effects since the SET will evaluate
00180    flags twice.  Also, note that the SIZE of a block in the property
00181    table does not include the alignment size, so the alignment fill
00182    must be calculated to determine if two blocks are contiguous.
00183    TEXT_ALIGN is not currently implemented but is a placeholder for a
00184    possible future implementation.  */
00185 
00186 #define XTENSA_PROP_ALIGN          0x00000800
00187 
00188 #define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
00189 
00190 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
00191   (((unsigned)((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
00192 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
00193   (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
00194     (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
00195 
00196 #define XTENSA_PROP_INSN_ABSLIT        0x00020000
00197 
00198 #endif /* _ELF_XTENSA_H */