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cell-binutils  2.17cvs20070401
xtensa-modules.c
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00001 /* Xtensa configuration-specific ISA information.
00002    Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
00003 
00004    This file is part of BFD, the Binary File Descriptor library.
00005 
00006    This program is free software; you can redistribute it and/or
00007    modify it under the terms of the GNU General Public License as
00008    published by the Free Software Foundation; either version 2 of the
00009    License, or (at your option) any later version.
00010 
00011    This program is distributed in the hope that it will be useful,
00012    but WITHOUT ANY WARRANTY; without even the implied warranty of
00013    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00014    General Public License for more details.
00015 
00016    You should have received a copy of the GNU General Public License
00017    along with this program; if not, write to the Free Software
00018    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
00019    02110-1301, USA.  */
00020 
00021 #include "ansidecl.h"
00022 #include <xtensa-isa.h>
00023 #include "xtensa-isa-internal.h"
00024 
00025 
00026 /* Sysregs.  */
00027 
00028 static xtensa_sysreg_internal sysregs[] = {
00029   { "LBEG", 0, 0 },
00030   { "LEND", 1, 0 },
00031   { "LCOUNT", 2, 0 },
00032   { "PTEVADDR", 83, 0 },
00033   { "DDR", 104, 0 },
00034   { "176", 176, 0 },
00035   { "208", 208, 0 },
00036   { "INTERRUPT", 226, 0 },
00037   { "INTCLEAR", 227, 0 },
00038   { "CCOUNT", 234, 0 },
00039   { "PRID", 235, 0 },
00040   { "ICOUNT", 236, 0 },
00041   { "CCOMPARE0", 240, 0 },
00042   { "CCOMPARE1", 241, 0 },
00043   { "CCOMPARE2", 242, 0 },
00044   { "EPC1", 177, 0 },
00045   { "EPC2", 178, 0 },
00046   { "EPC3", 179, 0 },
00047   { "EPC4", 180, 0 },
00048   { "EXCSAVE1", 209, 0 },
00049   { "EXCSAVE2", 210, 0 },
00050   { "EXCSAVE3", 211, 0 },
00051   { "EXCSAVE4", 212, 0 },
00052   { "EPS2", 194, 0 },
00053   { "EPS3", 195, 0 },
00054   { "EPS4", 196, 0 },
00055   { "EXCCAUSE", 232, 0 },
00056   { "DEPC", 192, 0 },
00057   { "EXCVADDR", 238, 0 },
00058   { "WINDOWBASE", 72, 0 },
00059   { "WINDOWSTART", 73, 0 },
00060   { "SAR", 3, 0 },
00061   { "LITBASE", 5, 0 },
00062   { "PS", 230, 0 },
00063   { "MISC0", 244, 0 },
00064   { "MISC1", 245, 0 },
00065   { "INTENABLE", 228, 0 },
00066   { "DBREAKA0", 144, 0 },
00067   { "DBREAKC0", 160, 0 },
00068   { "DBREAKA1", 145, 0 },
00069   { "DBREAKC1", 161, 0 },
00070   { "IBREAKA0", 128, 0 },
00071   { "IBREAKA1", 129, 0 },
00072   { "IBREAKENABLE", 96, 0 },
00073   { "ICOUNTLEVEL", 237, 0 },
00074   { "DEBUGCAUSE", 233, 0 },
00075   { "RASID", 90, 0 },
00076   { "ITLBCFG", 91, 0 },
00077   { "DTLBCFG", 92, 0 }
00078 };
00079 
00080 #define NUM_SYSREGS 49
00081 #define MAX_SPECIAL_REG 245
00082 #define MAX_USER_REG 0
00083 
00084 
00085 /* Processor states.  */
00086 
00087 static xtensa_state_internal states[] = {
00088   { "LCOUNT", 32, 0 },
00089   { "PC", 32, 0 },
00090   { "ICOUNT", 32, 0 },
00091   { "DDR", 32, 0 },
00092   { "INTERRUPT", 17, 0 },
00093   { "CCOUNT", 32, 0 },
00094   { "XTSYNC", 1, 0 },
00095   { "EPC1", 32, 0 },
00096   { "EPC2", 32, 0 },
00097   { "EPC3", 32, 0 },
00098   { "EPC4", 32, 0 },
00099   { "EXCSAVE1", 32, 0 },
00100   { "EXCSAVE2", 32, 0 },
00101   { "EXCSAVE3", 32, 0 },
00102   { "EXCSAVE4", 32, 0 },
00103   { "EPS2", 15, 0 },
00104   { "EPS3", 15, 0 },
00105   { "EPS4", 15, 0 },
00106   { "EXCCAUSE", 6, 0 },
00107   { "PSINTLEVEL", 4, 0 },
00108   { "PSUM", 1, 0 },
00109   { "PSWOE", 1, 0 },
00110   { "PSRING", 2, 0 },
00111   { "PSEXCM", 1, 0 },
00112   { "DEPC", 32, 0 },
00113   { "EXCVADDR", 32, 0 },
00114   { "WindowBase", 4, 0 },
00115   { "WindowStart", 16, 0 },
00116   { "PSCALLINC", 2, 0 },
00117   { "PSOWB", 4, 0 },
00118   { "LBEG", 32, 0 },
00119   { "LEND", 32, 0 },
00120   { "SAR", 6, 0 },
00121   { "LITBADDR", 20, 0 },
00122   { "LITBEN", 1, 0 },
00123   { "MISC0", 32, 0 },
00124   { "MISC1", 32, 0 },
00125   { "InOCDMode", 1, 0 },
00126   { "INTENABLE", 17, 0 },
00127   { "DBREAKA0", 32, 0 },
00128   { "DBREAKC0", 8, 0 },
00129   { "DBREAKA1", 32, 0 },
00130   { "DBREAKC1", 8, 0 },
00131   { "IBREAKA0", 32, 0 },
00132   { "IBREAKA1", 32, 0 },
00133   { "IBREAKENABLE", 2, 0 },
00134   { "ICOUNTLEVEL", 4, 0 },
00135   { "DEBUGCAUSE", 6, 0 },
00136   { "DBNUM", 4, 0 },
00137   { "CCOMPARE0", 32, 0 },
00138   { "CCOMPARE1", 32, 0 },
00139   { "CCOMPARE2", 32, 0 },
00140   { "ASID3", 8, 0 },
00141   { "ASID2", 8, 0 },
00142   { "ASID1", 8, 0 },
00143   { "INSTPGSZID4", 2, 0 },
00144   { "DATAPGSZID4", 2, 0 },
00145   { "PTBASE", 10, 0 }
00146 };
00147 
00148 #define NUM_STATES 58
00149 
00150 /* Macros for xtensa_state numbers (for use in iclasses because the
00151    state numbers are not available when the iclass table is generated).  */
00152 
00153 #define STATE_LCOUNT 0
00154 #define STATE_PC 1
00155 #define STATE_ICOUNT 2
00156 #define STATE_DDR 3
00157 #define STATE_INTERRUPT 4
00158 #define STATE_CCOUNT 5
00159 #define STATE_XTSYNC 6
00160 #define STATE_EPC1 7
00161 #define STATE_EPC2 8
00162 #define STATE_EPC3 9
00163 #define STATE_EPC4 10
00164 #define STATE_EXCSAVE1 11
00165 #define STATE_EXCSAVE2 12
00166 #define STATE_EXCSAVE3 13
00167 #define STATE_EXCSAVE4 14
00168 #define STATE_EPS2 15
00169 #define STATE_EPS3 16
00170 #define STATE_EPS4 17
00171 #define STATE_EXCCAUSE 18
00172 #define STATE_PSINTLEVEL 19
00173 #define STATE_PSUM 20
00174 #define STATE_PSWOE 21
00175 #define STATE_PSRING 22
00176 #define STATE_PSEXCM 23
00177 #define STATE_DEPC 24
00178 #define STATE_EXCVADDR 25
00179 #define STATE_WindowBase 26
00180 #define STATE_WindowStart 27
00181 #define STATE_PSCALLINC 28
00182 #define STATE_PSOWB 29
00183 #define STATE_LBEG 30
00184 #define STATE_LEND 31
00185 #define STATE_SAR 32
00186 #define STATE_LITBADDR 33
00187 #define STATE_LITBEN 34
00188 #define STATE_MISC0 35
00189 #define STATE_MISC1 36
00190 #define STATE_InOCDMode 37
00191 #define STATE_INTENABLE 38
00192 #define STATE_DBREAKA0 39
00193 #define STATE_DBREAKC0 40
00194 #define STATE_DBREAKA1 41
00195 #define STATE_DBREAKC1 42
00196 #define STATE_IBREAKA0 43
00197 #define STATE_IBREAKA1 44
00198 #define STATE_IBREAKENABLE 45
00199 #define STATE_ICOUNTLEVEL 46
00200 #define STATE_DEBUGCAUSE 47
00201 #define STATE_DBNUM 48
00202 #define STATE_CCOMPARE0 49
00203 #define STATE_CCOMPARE1 50
00204 #define STATE_CCOMPARE2 51
00205 #define STATE_ASID3 52
00206 #define STATE_ASID2 53
00207 #define STATE_ASID1 54
00208 #define STATE_INSTPGSZID4 55
00209 #define STATE_DATAPGSZID4 56
00210 #define STATE_PTBASE 57
00211 
00212 
00213 /* Field definitions.  */
00214 
00215 static unsigned
00216 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
00217 {
00218   unsigned tie_t = 0;
00219   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
00220   return tie_t;
00221 }
00222 
00223 static void
00224 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00225 {
00226   uint32 tie_t;
00227   tie_t = (val << 28) >> 28;
00228   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
00229 }
00230 
00231 static unsigned
00232 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
00233 {
00234   unsigned tie_t = 0;
00235   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00236   return tie_t;
00237 }
00238 
00239 static void
00240 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00241 {
00242   uint32 tie_t;
00243   tie_t = (val << 28) >> 28;
00244   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00245 }
00246 
00247 static unsigned
00248 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
00249 {
00250   unsigned tie_t = 0;
00251   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00252   return tie_t;
00253 }
00254 
00255 static void
00256 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00257 {
00258   uint32 tie_t;
00259   tie_t = (val << 28) >> 28;
00260   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00261 }
00262 
00263 static unsigned
00264 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
00265 {
00266   unsigned tie_t = 0;
00267   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00268   return tie_t;
00269 }
00270 
00271 static void
00272 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00273 {
00274   uint32 tie_t;
00275   tie_t = (val << 28) >> 28;
00276   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00277 }
00278 
00279 static unsigned
00280 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
00281 {
00282   unsigned tie_t = 0;
00283   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00284   return tie_t;
00285 }
00286 
00287 static void
00288 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00289 {
00290   uint32 tie_t;
00291   tie_t = (val << 28) >> 28;
00292   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00293 }
00294 
00295 static unsigned
00296 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
00297 {
00298   unsigned tie_t = 0;
00299   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
00300   return tie_t;
00301 }
00302 
00303 static void
00304 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00305 {
00306   uint32 tie_t;
00307   tie_t = (val << 28) >> 28;
00308   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
00309 }
00310 
00311 static unsigned
00312 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
00313 {
00314   unsigned tie_t = 0;
00315   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
00316   return tie_t;
00317 }
00318 
00319 static void
00320 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00321 {
00322   uint32 tie_t;
00323   tie_t = (val << 30) >> 30;
00324   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
00325 }
00326 
00327 static unsigned
00328 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
00329 {
00330   unsigned tie_t = 0;
00331   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
00332   return tie_t;
00333 }
00334 
00335 static void
00336 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00337 {
00338   uint32 tie_t;
00339   tie_t = (val << 30) >> 30;
00340   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
00341 }
00342 
00343 static unsigned
00344 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
00345 {
00346   unsigned tie_t = 0;
00347   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00348   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00349   return tie_t;
00350 }
00351 
00352 static void
00353 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00354 {
00355   uint32 tie_t;
00356   tie_t = (val << 28) >> 28;
00357   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00358   tie_t = (val << 24) >> 28;
00359   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00360 }
00361 
00362 static unsigned
00363 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
00364 {
00365   unsigned tie_t = 0;
00366   tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29);
00367   return tie_t;
00368 }
00369 
00370 static void
00371 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00372 {
00373   uint32 tie_t;
00374   tie_t = (val << 29) >> 29;
00375   insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
00376 }
00377 
00378 static unsigned
00379 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
00380 {
00381   unsigned tie_t = 0;
00382   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00383   return tie_t;
00384 }
00385 
00386 static void
00387 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00388 {
00389   uint32 tie_t;
00390   tie_t = (val << 28) >> 28;
00391   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00392 }
00393 
00394 static unsigned
00395 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
00396 {
00397   unsigned tie_t = 0;
00398   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00399   return tie_t;
00400 }
00401 
00402 static void
00403 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00404 {
00405   uint32 tie_t;
00406   tie_t = (val << 28) >> 28;
00407   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00408 }
00409 
00410 static unsigned
00411 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
00412 {
00413   unsigned tie_t = 0;
00414   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00415   return tie_t;
00416 }
00417 
00418 static void
00419 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00420 {
00421   uint32 tie_t;
00422   tie_t = (val << 28) >> 28;
00423   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00424 }
00425 
00426 static unsigned
00427 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
00428 {
00429   unsigned tie_t = 0;
00430   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00431   return tie_t;
00432 }
00433 
00434 static void
00435 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00436 {
00437   uint32 tie_t;
00438   tie_t = (val << 28) >> 28;
00439   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00440 }
00441 
00442 static unsigned
00443 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
00444 {
00445   unsigned tie_t = 0;
00446   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
00447   return tie_t;
00448 }
00449 
00450 static void
00451 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00452 {
00453   uint32 tie_t;
00454   tie_t = (val << 31) >> 31;
00455   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
00456 }
00457 
00458 static unsigned
00459 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
00460 {
00461   unsigned tie_t = 0;
00462   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
00463   return tie_t;
00464 }
00465 
00466 static void
00467 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00468 {
00469   uint32 tie_t;
00470   tie_t = (val << 31) >> 31;
00471   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
00472 }
00473 
00474 static unsigned
00475 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
00476 {
00477   unsigned tie_t = 0;
00478   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00479   return tie_t;
00480 }
00481 
00482 static void
00483 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00484 {
00485   uint32 tie_t;
00486   tie_t = (val << 28) >> 28;
00487   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00488 }
00489 
00490 static unsigned
00491 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
00492 {
00493   unsigned tie_t = 0;
00494   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00495   return tie_t;
00496 }
00497 
00498 static void
00499 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00500 {
00501   uint32 tie_t;
00502   tie_t = (val << 28) >> 28;
00503   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00504 }
00505 
00506 static unsigned
00507 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
00508 {
00509   unsigned tie_t = 0;
00510   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
00511   return tie_t;
00512 }
00513 
00514 static void
00515 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00516 {
00517   uint32 tie_t;
00518   tie_t = (val << 31) >> 31;
00519   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
00520 }
00521 
00522 static unsigned
00523 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
00524 {
00525   unsigned tie_t = 0;
00526   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
00527   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
00528   return tie_t;
00529 }
00530 
00531 static void
00532 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00533 {
00534   uint32 tie_t;
00535   tie_t = (val << 28) >> 28;
00536   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
00537   tie_t = (val << 27) >> 31;
00538   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
00539 }
00540 
00541 static unsigned
00542 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
00543 {
00544   unsigned tie_t = 0;
00545   tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20);
00546   return tie_t;
00547 }
00548 
00549 static void
00550 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00551 {
00552   uint32 tie_t;
00553   tie_t = (val << 20) >> 20;
00554   insn[0] = (insn[0] & ~0xfff) | (tie_t << 0);
00555 }
00556 
00557 static unsigned
00558 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
00559 {
00560   unsigned tie_t = 0;
00561   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
00562   return tie_t;
00563 }
00564 
00565 static void
00566 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00567 {
00568   uint32 tie_t;
00569   tie_t = (val << 24) >> 24;
00570   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
00571 }
00572 
00573 static unsigned
00574 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
00575 {
00576   unsigned tie_t = 0;
00577   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00578   return tie_t;
00579 }
00580 
00581 static void
00582 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00583 {
00584   uint32 tie_t;
00585   tie_t = (val << 28) >> 28;
00586   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00587 }
00588 
00589 static unsigned
00590 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
00591 {
00592   unsigned tie_t = 0;
00593   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00594   tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24);
00595   return tie_t;
00596 }
00597 
00598 static void
00599 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00600 {
00601   uint32 tie_t;
00602   tie_t = (val << 24) >> 24;
00603   insn[0] = (insn[0] & ~0xff) | (tie_t << 0);
00604   tie_t = (val << 20) >> 28;
00605   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00606 }
00607 
00608 static unsigned
00609 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
00610 {
00611   unsigned tie_t = 0;
00612   tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16);
00613   return tie_t;
00614 }
00615 
00616 static void
00617 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00618 {
00619   uint32 tie_t;
00620   tie_t = (val << 16) >> 16;
00621   insn[0] = (insn[0] & ~0xffff) | (tie_t << 0);
00622 }
00623 
00624 static unsigned
00625 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
00626 {
00627   unsigned tie_t = 0;
00628   tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14);
00629   return tie_t;
00630 }
00631 
00632 static void
00633 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00634 {
00635   uint32 tie_t;
00636   tie_t = (val << 14) >> 14;
00637   insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
00638 }
00639 
00640 static unsigned
00641 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
00642 {
00643   unsigned tie_t = 0;
00644   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00645   return tie_t;
00646 }
00647 
00648 static void
00649 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00650 {
00651   uint32 tie_t;
00652   tie_t = (val << 28) >> 28;
00653   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00654 }
00655 
00656 static unsigned
00657 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
00658 {
00659   unsigned tie_t = 0;
00660   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
00661   return tie_t;
00662 }
00663 
00664 static void
00665 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00666 {
00667   uint32 tie_t;
00668   tie_t = (val << 31) >> 31;
00669   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
00670 }
00671 
00672 static unsigned
00673 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
00674 {
00675   unsigned tie_t = 0;
00676   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
00677   return tie_t;
00678 }
00679 
00680 static void
00681 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00682 {
00683   uint32 tie_t;
00684   tie_t = (val << 31) >> 31;
00685   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
00686 }
00687 
00688 static unsigned
00689 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
00690 {
00691   unsigned tie_t = 0;
00692   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
00693   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00694   return tie_t;
00695 }
00696 
00697 static void
00698 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00699 {
00700   uint32 tie_t;
00701   tie_t = (val << 28) >> 28;
00702   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00703   tie_t = (val << 27) >> 31;
00704   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
00705 }
00706 
00707 static unsigned
00708 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
00709 {
00710   unsigned tie_t = 0;
00711   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
00712   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
00713   return tie_t;
00714 }
00715 
00716 static void
00717 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00718 {
00719   uint32 tie_t;
00720   tie_t = (val << 28) >> 28;
00721   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
00722   tie_t = (val << 27) >> 31;
00723   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
00724 }
00725 
00726 static unsigned
00727 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
00728 {
00729   unsigned tie_t = 0;
00730   tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31);
00731   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00732   return tie_t;
00733 }
00734 
00735 static void
00736 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00737 {
00738   uint32 tie_t;
00739   tie_t = (val << 28) >> 28;
00740   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00741   tie_t = (val << 27) >> 31;
00742   insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
00743 }
00744 
00745 static unsigned
00746 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
00747 {
00748   unsigned tie_t = 0;
00749   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
00750   return tie_t;
00751 }
00752 
00753 static void
00754 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00755 {
00756   uint32 tie_t;
00757   tie_t = (val << 31) >> 31;
00758   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
00759 }
00760 
00761 static unsigned
00762 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
00763 {
00764   unsigned tie_t = 0;
00765   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
00766   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00767   return tie_t;
00768 }
00769 
00770 static void
00771 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00772 {
00773   uint32 tie_t;
00774   tie_t = (val << 28) >> 28;
00775   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00776   tie_t = (val << 27) >> 31;
00777   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
00778 }
00779 
00780 static unsigned
00781 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
00782 {
00783   unsigned tie_t = 0;
00784   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00785   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00786   return tie_t;
00787 }
00788 
00789 static void
00790 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00791 {
00792   uint32 tie_t;
00793   tie_t = (val << 28) >> 28;
00794   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00795   tie_t = (val << 24) >> 28;
00796   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00797 }
00798 
00799 static unsigned
00800 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
00801 {
00802   unsigned tie_t = 0;
00803   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00804   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00805   return tie_t;
00806 }
00807 
00808 static void
00809 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00810 {
00811   uint32 tie_t;
00812   tie_t = (val << 28) >> 28;
00813   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00814   tie_t = (val << 24) >> 28;
00815   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00816 }
00817 
00818 static unsigned
00819 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
00820 {
00821   unsigned tie_t = 0;
00822   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
00823   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
00824   return tie_t;
00825 }
00826 
00827 static void
00828 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00829 {
00830   uint32 tie_t;
00831   tie_t = (val << 28) >> 28;
00832   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
00833   tie_t = (val << 24) >> 28;
00834   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
00835 }
00836 
00837 static unsigned
00838 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
00839 {
00840   unsigned tie_t = 0;
00841   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00842   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00843   return tie_t;
00844 }
00845 
00846 static void
00847 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00848 {
00849   uint32 tie_t;
00850   tie_t = (val << 28) >> 28;
00851   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00852   tie_t = (val << 24) >> 28;
00853   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00854 }
00855 
00856 static unsigned
00857 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
00858 {
00859   unsigned tie_t = 0;
00860   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
00861   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00862   return tie_t;
00863 }
00864 
00865 static void
00866 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00867 {
00868   uint32 tie_t;
00869   tie_t = (val << 28) >> 28;
00870   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00871   tie_t = (val << 24) >> 28;
00872   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
00873 }
00874 
00875 static unsigned
00876 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
00877 {
00878   unsigned tie_t = 0;
00879   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
00880   return tie_t;
00881 }
00882 
00883 static void
00884 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00885 {
00886   uint32 tie_t;
00887   tie_t = (val << 28) >> 28;
00888   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
00889 }
00890 
00891 static unsigned
00892 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
00893 {
00894   unsigned tie_t = 0;
00895   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00896   return tie_t;
00897 }
00898 
00899 static void
00900 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00901 {
00902   uint32 tie_t;
00903   tie_t = (val << 28) >> 28;
00904   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00905 }
00906 
00907 static unsigned
00908 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
00909 {
00910   unsigned tie_t = 0;
00911   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00912   return tie_t;
00913 }
00914 
00915 static void
00916 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00917 {
00918   uint32 tie_t;
00919   tie_t = (val << 28) >> 28;
00920   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00921 }
00922 
00923 static unsigned
00924 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
00925 {
00926   unsigned tie_t = 0;
00927   tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30);
00928   tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30);
00929   return tie_t;
00930 }
00931 
00932 static void
00933 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
00934 {
00935   uint32 tie_t;
00936   tie_t = (val << 30) >> 30;
00937   insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
00938   tie_t = (val << 28) >> 30;
00939   insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
00940 }
00941 
00942 static unsigned
00943 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
00944 {
00945   unsigned tie_t = 0;
00946   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
00947   return tie_t;
00948 }
00949 
00950 static void
00951 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00952 {
00953   uint32 tie_t;
00954   tie_t = (val << 31) >> 31;
00955   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
00956 }
00957 
00958 static unsigned
00959 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
00960 {
00961   unsigned tie_t = 0;
00962   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00963   return tie_t;
00964 }
00965 
00966 static void
00967 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
00968 {
00969   uint32 tie_t;
00970   tie_t = (val << 28) >> 28;
00971   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00972 }
00973 
00974 static unsigned
00975 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
00976 {
00977   unsigned tie_t = 0;
00978   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
00979   return tie_t;
00980 }
00981 
00982 static void
00983 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
00984 {
00985   uint32 tie_t;
00986   tie_t = (val << 28) >> 28;
00987   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
00988 }
00989 
00990 static unsigned
00991 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
00992 {
00993   unsigned tie_t = 0;
00994   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
00995   return tie_t;
00996 }
00997 
00998 static void
00999 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
01000 {
01001   uint32 tie_t;
01002   tie_t = (val << 30) >> 30;
01003   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
01004 }
01005 
01006 static unsigned
01007 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
01008 {
01009   unsigned tie_t = 0;
01010   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
01011   return tie_t;
01012 }
01013 
01014 static void
01015 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
01016 {
01017   uint32 tie_t;
01018   tie_t = (val << 30) >> 30;
01019   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
01020 }
01021 
01022 static unsigned
01023 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
01024 {
01025   unsigned tie_t = 0;
01026   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
01027   return tie_t;
01028 }
01029 
01030 static void
01031 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
01032 {
01033   uint32 tie_t;
01034   tie_t = (val << 28) >> 28;
01035   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
01036 }
01037 
01038 static unsigned
01039 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
01040 {
01041   unsigned tie_t = 0;
01042   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
01043   return tie_t;
01044 }
01045 
01046 static void
01047 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
01048 {
01049   uint32 tie_t;
01050   tie_t = (val << 28) >> 28;
01051   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
01052 }
01053 
01054 static unsigned
01055 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
01056 {
01057   unsigned tie_t = 0;
01058   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
01059   return tie_t;
01060 }
01061 
01062 static void
01063 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
01064 {
01065   uint32 tie_t;
01066   tie_t = (val << 29) >> 29;
01067   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
01068 }
01069 
01070 static unsigned
01071 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
01072 {
01073   unsigned tie_t = 0;
01074   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
01075   return tie_t;
01076 }
01077 
01078 static void
01079 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
01080 {
01081   uint32 tie_t;
01082   tie_t = (val << 29) >> 29;
01083   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
01084 }
01085 
01086 static unsigned
01087 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
01088 {
01089   unsigned tie_t = 0;
01090   tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31);
01091   return tie_t;
01092 }
01093 
01094 static void
01095 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
01096 {
01097   uint32 tie_t;
01098   tie_t = (val << 31) >> 31;
01099   insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
01100 }
01101 
01102 static unsigned
01103 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
01104 {
01105   unsigned tie_t = 0;
01106   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
01107   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
01108   return tie_t;
01109 }
01110 
01111 static void
01112 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
01113 {
01114   uint32 tie_t;
01115   tie_t = (val << 28) >> 28;
01116   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
01117   tie_t = (val << 26) >> 30;
01118   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
01119 }
01120 
01121 static unsigned
01122 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
01123 {
01124   unsigned tie_t = 0;
01125   tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30);
01126   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
01127   return tie_t;
01128 }
01129 
01130 static void
01131 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
01132 {
01133   uint32 tie_t;
01134   tie_t = (val << 28) >> 28;
01135   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
01136   tie_t = (val << 26) >> 30;
01137   insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
01138 }
01139 
01140 static unsigned
01141 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
01142 {
01143   unsigned tie_t = 0;
01144   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
01145   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
01146   return tie_t;
01147 }
01148 
01149 static void
01150 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
01151 {
01152   uint32 tie_t;
01153   tie_t = (val << 28) >> 28;
01154   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
01155   tie_t = (val << 25) >> 29;
01156   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
01157 }
01158 
01159 static unsigned
01160 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
01161 {
01162   unsigned tie_t = 0;
01163   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
01164   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
01165   return tie_t;
01166 }
01167 
01168 static void
01169 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
01170 {
01171   uint32 tie_t;
01172   tie_t = (val << 28) >> 28;
01173   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
01174   tie_t = (val << 25) >> 29;
01175   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
01176 }
01177 
01178 static void
01179 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
01180                   uint32 val ATTRIBUTE_UNUSED)
01181 {
01182   /* Do nothing.  */
01183 }
01184 
01185 static unsigned
01186 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
01187 {
01188   return 0;
01189 }
01190 
01191 static unsigned
01192 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
01193 {
01194   return 4;
01195 }
01196 
01197 static unsigned
01198 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
01199 {
01200   return 8;
01201 }
01202 
01203 static unsigned
01204 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
01205 {
01206   return 12;
01207 }
01208 
01209 
01210 /* Functional units.  */
01211 
01212 static xtensa_funcUnit_internal funcUnits[] = {
01213 
01214 };
01215 
01216 
01217 /* Register files.  */
01218 
01219 static xtensa_regfile_internal regfiles[] = {
01220   { "AR", "a", 0, 32, 64 }
01221 };
01222 
01223 
01224 /* Interfaces.  */
01225 
01226 static xtensa_interface_internal interfaces[] = {
01227 
01228 };
01229 
01230 
01231 /* Constant tables.  */
01232 
01233 /* constant table ai4c */
01234 static const unsigned CONST_TBL_ai4c_0[] = {
01235   0xffffffff,
01236   0x1,
01237   0x2,
01238   0x3,
01239   0x4,
01240   0x5,
01241   0x6,
01242   0x7,
01243   0x8,
01244   0x9,
01245   0xa,
01246   0xb,
01247   0xc,
01248   0xd,
01249   0xe,
01250   0xf,
01251   0
01252 };
01253 
01254 /* constant table b4c */
01255 static const unsigned CONST_TBL_b4c_0[] = {
01256   0xffffffff,
01257   0x1,
01258   0x2,
01259   0x3,
01260   0x4,
01261   0x5,
01262   0x6,
01263   0x7,
01264   0x8,
01265   0xa,
01266   0xc,
01267   0x10,
01268   0x20,
01269   0x40,
01270   0x80,
01271   0x100,
01272   0
01273 };
01274 
01275 /* constant table b4cu */
01276 static const unsigned CONST_TBL_b4cu_0[] = {
01277   0x8000,
01278   0x10000,
01279   0x2,
01280   0x3,
01281   0x4,
01282   0x5,
01283   0x6,
01284   0x7,
01285   0x8,
01286   0xa,
01287   0xc,
01288   0x10,
01289   0x20,
01290   0x40,
01291   0x80,
01292   0x100,
01293   0
01294 };
01295 
01296 
01297 /* Instruction operands.  */
01298 
01299 static int
01300 Operand_soffsetx4_decode (uint32 *valp)
01301 {
01302   unsigned soffsetx4_0, offset_0;
01303   offset_0 = *valp & 0x3ffff;
01304   soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
01305   *valp = soffsetx4_0;
01306   return 0;
01307 }
01308 
01309 static int
01310 Operand_soffsetx4_encode (uint32 *valp)
01311 {
01312   unsigned offset_0, soffsetx4_0;
01313   soffsetx4_0 = *valp;
01314   offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
01315   *valp = offset_0;
01316   return 0;
01317 }
01318 
01319 static int
01320 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
01321 {
01322   *valp -= (pc & ~0x3);
01323   return 0;
01324 }
01325 
01326 static int
01327 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
01328 {
01329   *valp += (pc & ~0x3);
01330   return 0;
01331 }
01332 
01333 static int
01334 Operand_uimm12x8_decode (uint32 *valp)
01335 {
01336   unsigned uimm12x8_0, imm12_0;
01337   imm12_0 = *valp & 0xfff;
01338   uimm12x8_0 = imm12_0 << 3;
01339   *valp = uimm12x8_0;
01340   return 0;
01341 }
01342 
01343 static int
01344 Operand_uimm12x8_encode (uint32 *valp)
01345 {
01346   unsigned imm12_0, uimm12x8_0;
01347   uimm12x8_0 = *valp;
01348   imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
01349   *valp = imm12_0;
01350   return 0;
01351 }
01352 
01353 static int
01354 Operand_simm4_decode (uint32 *valp)
01355 {
01356   unsigned simm4_0, mn_0;
01357   mn_0 = *valp & 0xf;
01358   simm4_0 = ((int) mn_0 << 28) >> 28;
01359   *valp = simm4_0;
01360   return 0;
01361 }
01362 
01363 static int
01364 Operand_simm4_encode (uint32 *valp)
01365 {
01366   unsigned mn_0, simm4_0;
01367   simm4_0 = *valp;
01368   mn_0 = (simm4_0 & 0xf);
01369   *valp = mn_0;
01370   return 0;
01371 }
01372 
01373 static int
01374 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
01375 {
01376   return 0;
01377 }
01378 
01379 static int
01380 Operand_arr_encode (uint32 *valp)
01381 {
01382   int error;
01383   error = (*valp & ~0xf) != 0;
01384   return error;
01385 }
01386 
01387 static int
01388 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
01389 {
01390   return 0;
01391 }
01392 
01393 static int
01394 Operand_ars_encode (uint32 *valp)
01395 {
01396   int error;
01397   error = (*valp & ~0xf) != 0;
01398   return error;
01399 }
01400 
01401 static int
01402 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
01403 {
01404   return 0;
01405 }
01406 
01407 static int
01408 Operand_art_encode (uint32 *valp)
01409 {
01410   int error;
01411   error = (*valp & ~0xf) != 0;
01412   return error;
01413 }
01414 
01415 static int
01416 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
01417 {
01418   return 0;
01419 }
01420 
01421 static int
01422 Operand_ar0_encode (uint32 *valp)
01423 {
01424   int error;
01425   error = (*valp & ~0x3f) != 0;
01426   return error;
01427 }
01428 
01429 static int
01430 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
01431 {
01432   return 0;
01433 }
01434 
01435 static int
01436 Operand_ar4_encode (uint32 *valp)
01437 {
01438   int error;
01439   error = (*valp & ~0x3f) != 0;
01440   return error;
01441 }
01442 
01443 static int
01444 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
01445 {
01446   return 0;
01447 }
01448 
01449 static int
01450 Operand_ar8_encode (uint32 *valp)
01451 {
01452   int error;
01453   error = (*valp & ~0x3f) != 0;
01454   return error;
01455 }
01456 
01457 static int
01458 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
01459 {
01460   return 0;
01461 }
01462 
01463 static int
01464 Operand_ar12_encode (uint32 *valp)
01465 {
01466   int error;
01467   error = (*valp & ~0x3f) != 0;
01468   return error;
01469 }
01470 
01471 static int
01472 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
01473 {
01474   return 0;
01475 }
01476 
01477 static int
01478 Operand_ars_entry_encode (uint32 *valp)
01479 {
01480   int error;
01481   error = (*valp & ~0x3f) != 0;
01482   return error;
01483 }
01484 
01485 static int
01486 Operand_immrx4_decode (uint32 *valp)
01487 {
01488   unsigned immrx4_0, r_0;
01489   r_0 = *valp & 0xf;
01490   immrx4_0 = ((((0xfffffff)) << 4) | r_0) << 2;
01491   *valp = immrx4_0;
01492   return 0;
01493 }
01494 
01495 static int
01496 Operand_immrx4_encode (uint32 *valp)
01497 {
01498   unsigned r_0, immrx4_0;
01499   immrx4_0 = *valp;
01500   r_0 = ((immrx4_0 >> 2) & 0xf);
01501   *valp = r_0;
01502   return 0;
01503 }
01504 
01505 static int
01506 Operand_lsi4x4_decode (uint32 *valp)
01507 {
01508   unsigned lsi4x4_0, r_0;
01509   r_0 = *valp & 0xf;
01510   lsi4x4_0 = r_0 << 2;
01511   *valp = lsi4x4_0;
01512   return 0;
01513 }
01514 
01515 static int
01516 Operand_lsi4x4_encode (uint32 *valp)
01517 {
01518   unsigned r_0, lsi4x4_0;
01519   lsi4x4_0 = *valp;
01520   r_0 = ((lsi4x4_0 >> 2) & 0xf);
01521   *valp = r_0;
01522   return 0;
01523 }
01524 
01525 static int
01526 Operand_simm7_decode (uint32 *valp)
01527 {
01528   unsigned simm7_0, imm7_0;
01529   imm7_0 = *valp & 0x7f;
01530   simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
01531   *valp = simm7_0;
01532   return 0;
01533 }
01534 
01535 static int
01536 Operand_simm7_encode (uint32 *valp)
01537 {
01538   unsigned imm7_0, simm7_0;
01539   simm7_0 = *valp;
01540   imm7_0 = (simm7_0 & 0x7f);
01541   *valp = imm7_0;
01542   return 0;
01543 }
01544 
01545 static int
01546 Operand_uimm6_decode (uint32 *valp)
01547 {
01548   unsigned uimm6_0, imm6_0;
01549   imm6_0 = *valp & 0x3f;
01550   uimm6_0 = 0x4 + ((((0)) << 6) | imm6_0);
01551   *valp = uimm6_0;
01552   return 0;
01553 }
01554 
01555 static int
01556 Operand_uimm6_encode (uint32 *valp)
01557 {
01558   unsigned imm6_0, uimm6_0;
01559   uimm6_0 = *valp;
01560   imm6_0 = (uimm6_0 - 0x4) & 0x3f;
01561   *valp = imm6_0;
01562   return 0;
01563 }
01564 
01565 static int
01566 Operand_uimm6_ator (uint32 *valp, uint32 pc)
01567 {
01568   *valp -= pc;
01569   return 0;
01570 }
01571 
01572 static int
01573 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
01574 {
01575   *valp += pc;
01576   return 0;
01577 }
01578 
01579 static int
01580 Operand_ai4const_decode (uint32 *valp)
01581 {
01582   unsigned ai4const_0, t_0;
01583   t_0 = *valp & 0xf;
01584   ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
01585   *valp = ai4const_0;
01586   return 0;
01587 }
01588 
01589 static int
01590 Operand_ai4const_encode (uint32 *valp)
01591 {
01592   unsigned t_0, ai4const_0;
01593   ai4const_0 = *valp;
01594   switch (ai4const_0)
01595     {
01596     case 0xffffffff: t_0 = 0; break;
01597     case 0x1: t_0 = 0x1; break;
01598     case 0x2: t_0 = 0x2; break;
01599     case 0x3: t_0 = 0x3; break;
01600     case 0x4: t_0 = 0x4; break;
01601     case 0x5: t_0 = 0x5; break;
01602     case 0x6: t_0 = 0x6; break;
01603     case 0x7: t_0 = 0x7; break;
01604     case 0x8: t_0 = 0x8; break;
01605     case 0x9: t_0 = 0x9; break;
01606     case 0xa: t_0 = 0xa; break;
01607     case 0xb: t_0 = 0xb; break;
01608     case 0xc: t_0 = 0xc; break;
01609     case 0xd: t_0 = 0xd; break;
01610     case 0xe: t_0 = 0xe; break;
01611     default: t_0 = 0xf; break;
01612     }
01613   *valp = t_0;
01614   return 0;
01615 }
01616 
01617 static int
01618 Operand_b4const_decode (uint32 *valp)
01619 {
01620   unsigned b4const_0, r_0;
01621   r_0 = *valp & 0xf;
01622   b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
01623   *valp = b4const_0;
01624   return 0;
01625 }
01626 
01627 static int
01628 Operand_b4const_encode (uint32 *valp)
01629 {
01630   unsigned r_0, b4const_0;
01631   b4const_0 = *valp;
01632   switch (b4const_0)
01633     {
01634     case 0xffffffff: r_0 = 0; break;
01635     case 0x1: r_0 = 0x1; break;
01636     case 0x2: r_0 = 0x2; break;
01637     case 0x3: r_0 = 0x3; break;
01638     case 0x4: r_0 = 0x4; break;
01639     case 0x5: r_0 = 0x5; break;
01640     case 0x6: r_0 = 0x6; break;
01641     case 0x7: r_0 = 0x7; break;
01642     case 0x8: r_0 = 0x8; break;
01643     case 0xa: r_0 = 0x9; break;
01644     case 0xc: r_0 = 0xa; break;
01645     case 0x10: r_0 = 0xb; break;
01646     case 0x20: r_0 = 0xc; break;
01647     case 0x40: r_0 = 0xd; break;
01648     case 0x80: r_0 = 0xe; break;
01649     default: r_0 = 0xf; break;
01650     }
01651   *valp = r_0;
01652   return 0;
01653 }
01654 
01655 static int
01656 Operand_b4constu_decode (uint32 *valp)
01657 {
01658   unsigned b4constu_0, r_0;
01659   r_0 = *valp & 0xf;
01660   b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
01661   *valp = b4constu_0;
01662   return 0;
01663 }
01664 
01665 static int
01666 Operand_b4constu_encode (uint32 *valp)
01667 {
01668   unsigned r_0, b4constu_0;
01669   b4constu_0 = *valp;
01670   switch (b4constu_0)
01671     {
01672     case 0x8000: r_0 = 0; break;
01673     case 0x10000: r_0 = 0x1; break;
01674     case 0x2: r_0 = 0x2; break;
01675     case 0x3: r_0 = 0x3; break;
01676     case 0x4: r_0 = 0x4; break;
01677     case 0x5: r_0 = 0x5; break;
01678     case 0x6: r_0 = 0x6; break;
01679     case 0x7: r_0 = 0x7; break;
01680     case 0x8: r_0 = 0x8; break;
01681     case 0xa: r_0 = 0x9; break;
01682     case 0xc: r_0 = 0xa; break;
01683     case 0x10: r_0 = 0xb; break;
01684     case 0x20: r_0 = 0xc; break;
01685     case 0x40: r_0 = 0xd; break;
01686     case 0x80: r_0 = 0xe; break;
01687     default: r_0 = 0xf; break;
01688     }
01689   *valp = r_0;
01690   return 0;
01691 }
01692 
01693 static int
01694 Operand_uimm8_decode (uint32 *valp)
01695 {
01696   unsigned uimm8_0, imm8_0;
01697   imm8_0 = *valp & 0xff;
01698   uimm8_0 = imm8_0;
01699   *valp = uimm8_0;
01700   return 0;
01701 }
01702 
01703 static int
01704 Operand_uimm8_encode (uint32 *valp)
01705 {
01706   unsigned imm8_0, uimm8_0;
01707   uimm8_0 = *valp;
01708   imm8_0 = (uimm8_0 & 0xff);
01709   *valp = imm8_0;
01710   return 0;
01711 }
01712 
01713 static int
01714 Operand_uimm8x2_decode (uint32 *valp)
01715 {
01716   unsigned uimm8x2_0, imm8_0;
01717   imm8_0 = *valp & 0xff;
01718   uimm8x2_0 = imm8_0 << 1;
01719   *valp = uimm8x2_0;
01720   return 0;
01721 }
01722 
01723 static int
01724 Operand_uimm8x2_encode (uint32 *valp)
01725 {
01726   unsigned imm8_0, uimm8x2_0;
01727   uimm8x2_0 = *valp;
01728   imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
01729   *valp = imm8_0;
01730   return 0;
01731 }
01732 
01733 static int
01734 Operand_uimm8x4_decode (uint32 *valp)
01735 {
01736   unsigned uimm8x4_0, imm8_0;
01737   imm8_0 = *valp & 0xff;
01738   uimm8x4_0 = imm8_0 << 2;
01739   *valp = uimm8x4_0;
01740   return 0;
01741 }
01742 
01743 static int
01744 Operand_uimm8x4_encode (uint32 *valp)
01745 {
01746   unsigned imm8_0, uimm8x4_0;
01747   uimm8x4_0 = *valp;
01748   imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
01749   *valp = imm8_0;
01750   return 0;
01751 }
01752 
01753 static int
01754 Operand_uimm4x16_decode (uint32 *valp)
01755 {
01756   unsigned uimm4x16_0, op2_0;
01757   op2_0 = *valp & 0xf;
01758   uimm4x16_0 = op2_0 << 4;
01759   *valp = uimm4x16_0;
01760   return 0;
01761 }
01762 
01763 static int
01764 Operand_uimm4x16_encode (uint32 *valp)
01765 {
01766   unsigned op2_0, uimm4x16_0;
01767   uimm4x16_0 = *valp;
01768   op2_0 = ((uimm4x16_0 >> 4) & 0xf);
01769   *valp = op2_0;
01770   return 0;
01771 }
01772 
01773 static int
01774 Operand_simm8_decode (uint32 *valp)
01775 {
01776   unsigned simm8_0, imm8_0;
01777   imm8_0 = *valp & 0xff;
01778   simm8_0 = ((int) imm8_0 << 24) >> 24;
01779   *valp = simm8_0;
01780   return 0;
01781 }
01782 
01783 static int
01784 Operand_simm8_encode (uint32 *valp)
01785 {
01786   unsigned imm8_0, simm8_0;
01787   simm8_0 = *valp;
01788   imm8_0 = (simm8_0 & 0xff);
01789   *valp = imm8_0;
01790   return 0;
01791 }
01792 
01793 static int
01794 Operand_simm8x256_decode (uint32 *valp)
01795 {
01796   unsigned simm8x256_0, imm8_0;
01797   imm8_0 = *valp & 0xff;
01798   simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
01799   *valp = simm8x256_0;
01800   return 0;
01801 }
01802 
01803 static int
01804 Operand_simm8x256_encode (uint32 *valp)
01805 {
01806   unsigned imm8_0, simm8x256_0;
01807   simm8x256_0 = *valp;
01808   imm8_0 = ((simm8x256_0 >> 8) & 0xff);
01809   *valp = imm8_0;
01810   return 0;
01811 }
01812 
01813 static int
01814 Operand_simm12b_decode (uint32 *valp)
01815 {
01816   unsigned simm12b_0, imm12b_0;
01817   imm12b_0 = *valp & 0xfff;
01818   simm12b_0 = ((int) imm12b_0 << 20) >> 20;
01819   *valp = simm12b_0;
01820   return 0;
01821 }
01822 
01823 static int
01824 Operand_simm12b_encode (uint32 *valp)
01825 {
01826   unsigned imm12b_0, simm12b_0;
01827   simm12b_0 = *valp;
01828   imm12b_0 = (simm12b_0 & 0xfff);
01829   *valp = imm12b_0;
01830   return 0;
01831 }
01832 
01833 static int
01834 Operand_msalp32_decode (uint32 *valp)
01835 {
01836   unsigned msalp32_0, sal_0;
01837   sal_0 = *valp & 0x1f;
01838   msalp32_0 = 0x20 - sal_0;
01839   *valp = msalp32_0;
01840   return 0;
01841 }
01842 
01843 static int
01844 Operand_msalp32_encode (uint32 *valp)
01845 {
01846   unsigned sal_0, msalp32_0;
01847   msalp32_0 = *valp;
01848   sal_0 = (0x20 - msalp32_0) & 0x1f;
01849   *valp = sal_0;
01850   return 0;
01851 }
01852 
01853 static int
01854 Operand_op2p1_decode (uint32 *valp)
01855 {
01856   unsigned op2p1_0, op2_0;
01857   op2_0 = *valp & 0xf;
01858   op2p1_0 = op2_0 + 0x1;
01859   *valp = op2p1_0;
01860   return 0;
01861 }
01862 
01863 static int
01864 Operand_op2p1_encode (uint32 *valp)
01865 {
01866   unsigned op2_0, op2p1_0;
01867   op2p1_0 = *valp;
01868   op2_0 = (op2p1_0 - 0x1) & 0xf;
01869   *valp = op2_0;
01870   return 0;
01871 }
01872 
01873 static int
01874 Operand_label8_decode (uint32 *valp)
01875 {
01876   unsigned label8_0, imm8_0;
01877   imm8_0 = *valp & 0xff;
01878   label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
01879   *valp = label8_0;
01880   return 0;
01881 }
01882 
01883 static int
01884 Operand_label8_encode (uint32 *valp)
01885 {
01886   unsigned imm8_0, label8_0;
01887   label8_0 = *valp;
01888   imm8_0 = (label8_0 - 0x4) & 0xff;
01889   *valp = imm8_0;
01890   return 0;
01891 }
01892 
01893 static int
01894 Operand_label8_ator (uint32 *valp, uint32 pc)
01895 {
01896   *valp -= pc;
01897   return 0;
01898 }
01899 
01900 static int
01901 Operand_label8_rtoa (uint32 *valp, uint32 pc)
01902 {
01903   *valp += pc;
01904   return 0;
01905 }
01906 
01907 static int
01908 Operand_ulabel8_decode (uint32 *valp)
01909 {
01910   unsigned ulabel8_0, imm8_0;
01911   imm8_0 = *valp & 0xff;
01912   ulabel8_0 = 0x4 + ((((0)) << 8) | imm8_0);
01913   *valp = ulabel8_0;
01914   return 0;
01915 }
01916 
01917 static int
01918 Operand_ulabel8_encode (uint32 *valp)
01919 {
01920   unsigned imm8_0, ulabel8_0;
01921   ulabel8_0 = *valp;
01922   imm8_0 = (ulabel8_0 - 0x4) & 0xff;
01923   *valp = imm8_0;
01924   return 0;
01925 }
01926 
01927 static int
01928 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
01929 {
01930   *valp -= pc;
01931   return 0;
01932 }
01933 
01934 static int
01935 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
01936 {
01937   *valp += pc;
01938   return 0;
01939 }
01940 
01941 static int
01942 Operand_label12_decode (uint32 *valp)
01943 {
01944   unsigned label12_0, imm12_0;
01945   imm12_0 = *valp & 0xfff;
01946   label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
01947   *valp = label12_0;
01948   return 0;
01949 }
01950 
01951 static int
01952 Operand_label12_encode (uint32 *valp)
01953 {
01954   unsigned imm12_0, label12_0;
01955   label12_0 = *valp;
01956   imm12_0 = (label12_0 - 0x4) & 0xfff;
01957   *valp = imm12_0;
01958   return 0;
01959 }
01960 
01961 static int
01962 Operand_label12_ator (uint32 *valp, uint32 pc)
01963 {
01964   *valp -= pc;
01965   return 0;
01966 }
01967 
01968 static int
01969 Operand_label12_rtoa (uint32 *valp, uint32 pc)
01970 {
01971   *valp += pc;
01972   return 0;
01973 }
01974 
01975 static int
01976 Operand_soffset_decode (uint32 *valp)
01977 {
01978   unsigned soffset_0, offset_0;
01979   offset_0 = *valp & 0x3ffff;
01980   soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
01981   *valp = soffset_0;
01982   return 0;
01983 }
01984 
01985 static int
01986 Operand_soffset_encode (uint32 *valp)
01987 {
01988   unsigned offset_0, soffset_0;
01989   soffset_0 = *valp;
01990   offset_0 = (soffset_0 - 0x4) & 0x3ffff;
01991   *valp = offset_0;
01992   return 0;
01993 }
01994 
01995 static int
01996 Operand_soffset_ator (uint32 *valp, uint32 pc)
01997 {
01998   *valp -= pc;
01999   return 0;
02000 }
02001 
02002 static int
02003 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
02004 {
02005   *valp += pc;
02006   return 0;
02007 }
02008 
02009 static int
02010 Operand_uimm16x4_decode (uint32 *valp)
02011 {
02012   unsigned uimm16x4_0, imm16_0;
02013   imm16_0 = *valp & 0xffff;
02014   uimm16x4_0 = ((((0xffff)) << 16) | imm16_0) << 2;
02015   *valp = uimm16x4_0;
02016   return 0;
02017 }
02018 
02019 static int
02020 Operand_uimm16x4_encode (uint32 *valp)
02021 {
02022   unsigned imm16_0, uimm16x4_0;
02023   uimm16x4_0 = *valp;
02024   imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
02025   *valp = imm16_0;
02026   return 0;
02027 }
02028 
02029 static int
02030 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
02031 {
02032   *valp -= ((pc + 3) & ~0x3);
02033   return 0;
02034 }
02035 
02036 static int
02037 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
02038 {
02039   *valp += ((pc + 3) & ~0x3);
02040   return 0;
02041 }
02042 
02043 static int
02044 Operand_immt_decode (uint32 *valp)
02045 {
02046   unsigned immt_0, t_0;
02047   t_0 = *valp & 0xf;
02048   immt_0 = t_0;
02049   *valp = immt_0;
02050   return 0;
02051 }
02052 
02053 static int
02054 Operand_immt_encode (uint32 *valp)
02055 {
02056   unsigned t_0, immt_0;
02057   immt_0 = *valp;
02058   t_0 = immt_0 & 0xf;
02059   *valp = t_0;
02060   return 0;
02061 }
02062 
02063 static int
02064 Operand_imms_decode (uint32 *valp)
02065 {
02066   unsigned imms_0, s_0;
02067   s_0 = *valp & 0xf;
02068   imms_0 = s_0;
02069   *valp = imms_0;
02070   return 0;
02071 }
02072 
02073 static int
02074 Operand_imms_encode (uint32 *valp)
02075 {
02076   unsigned s_0, imms_0;
02077   imms_0 = *valp;
02078   s_0 = imms_0 & 0xf;
02079   *valp = s_0;
02080   return 0;
02081 }
02082 
02083 static xtensa_operand_internal operands[] = {
02084   { "soffsetx4", 10, -1, 0,
02085     XTENSA_OPERAND_IS_PCRELATIVE,
02086     Operand_soffsetx4_encode, Operand_soffsetx4_decode,
02087     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
02088   { "uimm12x8", 3, -1, 0,
02089     0,
02090     Operand_uimm12x8_encode, Operand_uimm12x8_decode,
02091     0, 0 },
02092   { "simm4", 26, -1, 0,
02093     0,
02094     Operand_simm4_encode, Operand_simm4_decode,
02095     0, 0 },
02096   { "arr", 14, 0, 1,
02097     XTENSA_OPERAND_IS_REGISTER,
02098     Operand_arr_encode, Operand_arr_decode,
02099     0, 0 },
02100   { "ars", 5, 0, 1,
02101     XTENSA_OPERAND_IS_REGISTER,
02102     Operand_ars_encode, Operand_ars_decode,
02103     0, 0 },
02104   { "*ars_invisible", 5, 0, 1,
02105     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
02106     Operand_ars_encode, Operand_ars_decode,
02107     0, 0 },
02108   { "art", 0, 0, 1,
02109     XTENSA_OPERAND_IS_REGISTER,
02110     Operand_art_encode, Operand_art_decode,
02111     0, 0 },
02112   { "ar0", 35, 0, 1,
02113     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
02114     Operand_ar0_encode, Operand_ar0_decode,
02115     0, 0 },
02116   { "ar4", 36, 0, 1,
02117     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
02118     Operand_ar4_encode, Operand_ar4_decode,
02119     0, 0 },
02120   { "ar8", 37, 0, 1,
02121     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
02122     Operand_ar8_encode, Operand_ar8_decode,
02123     0, 0 },
02124   { "ar12", 38, 0, 1,
02125     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
02126     Operand_ar12_encode, Operand_ar12_decode,
02127     0, 0 },
02128   { "ars_entry", 5, 0, 1,
02129     XTENSA_OPERAND_IS_REGISTER,
02130     Operand_ars_entry_encode, Operand_ars_entry_decode,
02131     0, 0 },
02132   { "immrx4", 14, -1, 0,
02133     0,
02134     Operand_immrx4_encode, Operand_immrx4_decode,
02135     0, 0 },
02136   { "lsi4x4", 14, -1, 0,
02137     0,
02138     Operand_lsi4x4_encode, Operand_lsi4x4_decode,
02139     0, 0 },
02140   { "simm7", 34, -1, 0,
02141     0,
02142     Operand_simm7_encode, Operand_simm7_decode,
02143     0, 0 },
02144   { "uimm6", 33, -1, 0,
02145     XTENSA_OPERAND_IS_PCRELATIVE,
02146     Operand_uimm6_encode, Operand_uimm6_decode,
02147     Operand_uimm6_ator, Operand_uimm6_rtoa },
02148   { "ai4const", 0, -1, 0,
02149     0,
02150     Operand_ai4const_encode, Operand_ai4const_decode,
02151     0, 0 },
02152   { "b4const", 14, -1, 0,
02153     0,
02154     Operand_b4const_encode, Operand_b4const_decode,
02155     0, 0 },
02156   { "b4constu", 14, -1, 0,
02157     0,
02158     Operand_b4constu_encode, Operand_b4constu_decode,
02159     0, 0 },
02160   { "uimm8", 4, -1, 0,
02161     0,
02162     Operand_uimm8_encode, Operand_uimm8_decode,
02163     0, 0 },
02164   { "uimm8x2", 4, -1, 0,
02165     0,
02166     Operand_uimm8x2_encode, Operand_uimm8x2_decode,
02167     0, 0 },
02168   { "uimm8x4", 4, -1, 0,
02169     0,
02170     Operand_uimm8x4_encode, Operand_uimm8x4_decode,
02171     0, 0 },
02172   { "uimm4x16", 13, -1, 0,
02173     0,
02174     Operand_uimm4x16_encode, Operand_uimm4x16_decode,
02175     0, 0 },
02176   { "simm8", 4, -1, 0,
02177     0,
02178     Operand_simm8_encode, Operand_simm8_decode,
02179     0, 0 },
02180   { "simm8x256", 4, -1, 0,
02181     0,
02182     Operand_simm8x256_encode, Operand_simm8x256_decode,
02183     0, 0 },
02184   { "simm12b", 6, -1, 0,
02185     0,
02186     Operand_simm12b_encode, Operand_simm12b_decode,
02187     0, 0 },
02188   { "msalp32", 18, -1, 0,
02189     0,
02190     Operand_msalp32_encode, Operand_msalp32_decode,
02191     0, 0 },
02192   { "op2p1", 13, -1, 0,
02193     0,
02194     Operand_op2p1_encode, Operand_op2p1_decode,
02195     0, 0 },
02196   { "label8", 4, -1, 0,
02197     XTENSA_OPERAND_IS_PCRELATIVE,
02198     Operand_label8_encode, Operand_label8_decode,
02199     Operand_label8_ator, Operand_label8_rtoa },
02200   { "ulabel8", 4, -1, 0,
02201     XTENSA_OPERAND_IS_PCRELATIVE,
02202     Operand_ulabel8_encode, Operand_ulabel8_decode,
02203     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
02204   { "label12", 3, -1, 0,
02205     XTENSA_OPERAND_IS_PCRELATIVE,
02206     Operand_label12_encode, Operand_label12_decode,
02207     Operand_label12_ator, Operand_label12_rtoa },
02208   { "soffset", 10, -1, 0,
02209     XTENSA_OPERAND_IS_PCRELATIVE,
02210     Operand_soffset_encode, Operand_soffset_decode,
02211     Operand_soffset_ator, Operand_soffset_rtoa },
02212   { "uimm16x4", 7, -1, 0,
02213     XTENSA_OPERAND_IS_PCRELATIVE,
02214     Operand_uimm16x4_encode, Operand_uimm16x4_decode,
02215     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
02216   { "immt", 0, -1, 0,
02217     0,
02218     Operand_immt_encode, Operand_immt_decode,
02219     0, 0 },
02220   { "imms", 5, -1, 0,
02221     0,
02222     Operand_imms_encode, Operand_imms_decode,
02223     0, 0 },
02224   { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
02225   { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
02226   { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
02227   { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
02228   { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
02229   { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
02230   { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
02231   { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
02232   { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
02233   { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
02234   { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
02235   { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
02236   { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
02237   { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
02238   { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
02239   { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
02240   { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
02241   { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
02242   { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
02243   { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
02244   { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
02245   { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
02246   { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
02247   { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
02248   { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
02249   { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
02250   { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
02251   { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
02252   { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
02253   { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
02254   { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
02255   { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
02256   { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
02257   { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
02258   { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 }
02259 };
02260 
02261 
02262 /* Iclass table.  */
02263 
02264 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
02265   { { STATE_PSRING }, 'i' },
02266   { { STATE_PSEXCM }, 'm' },
02267   { { STATE_EPC1 }, 'i' }
02268 };
02269 
02270 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
02271   { { STATE_PSEXCM }, 'i' },
02272   { { STATE_PSRING }, 'i' },
02273   { { STATE_DEPC }, 'i' }
02274 };
02275 
02276 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
02277   { { 0 /* soffsetx4 */ }, 'i' },
02278   { { 10 /* ar12 */ }, 'o' }
02279 };
02280 
02281 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
02282   { { STATE_PSCALLINC }, 'o' }
02283 };
02284 
02285 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
02286   { { 0 /* soffsetx4 */ }, 'i' },
02287   { { 9 /* ar8 */ }, 'o' }
02288 };
02289 
02290 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
02291   { { STATE_PSCALLINC }, 'o' }
02292 };
02293 
02294 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
02295   { { 0 /* soffsetx4 */ }, 'i' },
02296   { { 8 /* ar4 */ }, 'o' }
02297 };
02298 
02299 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
02300   { { STATE_PSCALLINC }, 'o' }
02301 };
02302 
02303 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
02304   { { 4 /* ars */ }, 'i' },
02305   { { 10 /* ar12 */ }, 'o' }
02306 };
02307 
02308 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
02309   { { STATE_PSCALLINC }, 'o' }
02310 };
02311 
02312 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
02313   { { 4 /* ars */ }, 'i' },
02314   { { 9 /* ar8 */ }, 'o' }
02315 };
02316 
02317 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
02318   { { STATE_PSCALLINC }, 'o' }
02319 };
02320 
02321 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
02322   { { 4 /* ars */ }, 'i' },
02323   { { 8 /* ar4 */ }, 'o' }
02324 };
02325 
02326 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
02327   { { STATE_PSCALLINC }, 'o' }
02328 };
02329 
02330 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
02331   { { 11 /* ars_entry */ }, 's' },
02332   { { 4 /* ars */ }, 'i' },
02333   { { 1 /* uimm12x8 */ }, 'i' }
02334 };
02335 
02336 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
02337   { { STATE_PSCALLINC }, 'i' },
02338   { { STATE_PSEXCM }, 'i' },
02339   { { STATE_PSWOE }, 'i' },
02340   { { STATE_WindowBase }, 'm' },
02341   { { STATE_WindowStart }, 'm' }
02342 };
02343 
02344 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
02345   { { 6 /* art */ }, 'o' },
02346   { { 4 /* ars */ }, 'i' }
02347 };
02348 
02349 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
02350   { { STATE_WindowBase }, 'i' },
02351   { { STATE_WindowStart }, 'i' }
02352 };
02353 
02354 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
02355   { { 2 /* simm4 */ }, 'i' }
02356 };
02357 
02358 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
02359   { { STATE_PSEXCM }, 'i' },
02360   { { STATE_PSRING }, 'i' },
02361   { { STATE_WindowBase }, 'm' }
02362 };
02363 
02364 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
02365   { { 5 /* *ars_invisible */ }, 'i' }
02366 };
02367 
02368 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
02369   { { STATE_WindowBase }, 'm' },
02370   { { STATE_WindowStart }, 'm' },
02371   { { STATE_PSEXCM }, 'i' },
02372   { { STATE_PSWOE }, 'i' }
02373 };
02374 
02375 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
02376   { { STATE_EPC1 }, 'i' },
02377   { { STATE_PSEXCM }, 'm' },
02378   { { STATE_PSRING }, 'i' },
02379   { { STATE_WindowBase }, 'm' },
02380   { { STATE_WindowStart }, 'm' },
02381   { { STATE_PSOWB }, 'i' }
02382 };
02383 
02384 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
02385   { { 6 /* art */ }, 'o' },
02386   { { 4 /* ars */ }, 'i' },
02387   { { 12 /* immrx4 */ }, 'i' }
02388 };
02389 
02390 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
02391   { { STATE_PSEXCM }, 'i' },
02392   { { STATE_PSRING }, 'i' }
02393 };
02394 
02395 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
02396   { { 6 /* art */ }, 'i' },
02397   { { 4 /* ars */ }, 'i' },
02398   { { 12 /* immrx4 */ }, 'i' }
02399 };
02400 
02401 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
02402   { { STATE_PSEXCM }, 'i' },
02403   { { STATE_PSRING }, 'i' }
02404 };
02405 
02406 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
02407   { { 6 /* art */ }, 'o' }
02408 };
02409 
02410 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
02411   { { STATE_PSEXCM }, 'i' },
02412   { { STATE_PSRING }, 'i' },
02413   { { STATE_WindowBase }, 'i' }
02414 };
02415 
02416 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
02417   { { 6 /* art */ }, 'i' }
02418 };
02419 
02420 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
02421   { { STATE_PSEXCM }, 'i' },
02422   { { STATE_PSRING }, 'i' },
02423   { { STATE_WindowBase }, 'o' }
02424 };
02425 
02426 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
02427   { { 6 /* art */ }, 'm' }
02428 };
02429 
02430 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
02431   { { STATE_PSEXCM }, 'i' },
02432   { { STATE_PSRING }, 'i' },
02433   { { STATE_WindowBase }, 'm' }
02434 };
02435 
02436 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
02437   { { 6 /* art */ }, 'o' }
02438 };
02439 
02440 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
02441   { { STATE_PSEXCM }, 'i' },
02442   { { STATE_PSRING }, 'i' },
02443   { { STATE_WindowStart }, 'i' }
02444 };
02445 
02446 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
02447   { { 6 /* art */ }, 'i' }
02448 };
02449 
02450 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
02451   { { STATE_PSEXCM }, 'i' },
02452   { { STATE_PSRING }, 'i' },
02453   { { STATE_WindowStart }, 'o' }
02454 };
02455 
02456 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
02457   { { 6 /* art */ }, 'm' }
02458 };
02459 
02460 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
02461   { { STATE_PSEXCM }, 'i' },
02462   { { STATE_PSRING }, 'i' },
02463   { { STATE_WindowStart }, 'm' }
02464 };
02465 
02466 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
02467   { { 3 /* arr */ }, 'o' },
02468   { { 4 /* ars */ }, 'i' },
02469   { { 6 /* art */ }, 'i' }
02470 };
02471 
02472 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
02473   { { 3 /* arr */ }, 'o' },
02474   { { 4 /* ars */ }, 'i' },
02475   { { 16 /* ai4const */ }, 'i' }
02476 };
02477 
02478 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
02479   { { 4 /* ars */ }, 'i' },
02480   { { 15 /* uimm6 */ }, 'i' }
02481 };
02482 
02483 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
02484   { { 6 /* art */ }, 'o' },
02485   { { 4 /* ars */ }, 'i' },
02486   { { 13 /* lsi4x4 */ }, 'i' }
02487 };
02488 
02489 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
02490   { { 6 /* art */ }, 'o' },
02491   { { 4 /* ars */ }, 'i' }
02492 };
02493 
02494 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
02495   { { 4 /* ars */ }, 'o' },
02496   { { 14 /* simm7 */ }, 'i' }
02497 };
02498 
02499 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
02500   { { 5 /* *ars_invisible */ }, 'i' }
02501 };
02502 
02503 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
02504   { { 6 /* art */ }, 'i' },
02505   { { 4 /* ars */ }, 'i' },
02506   { { 13 /* lsi4x4 */ }, 'i' }
02507 };
02508 
02509 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
02510   { { 6 /* art */ }, 'o' },
02511   { { 4 /* ars */ }, 'i' },
02512   { { 23 /* simm8 */ }, 'i' }
02513 };
02514 
02515 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
02516   { { 6 /* art */ }, 'o' },
02517   { { 4 /* ars */ }, 'i' },
02518   { { 24 /* simm8x256 */ }, 'i' }
02519 };
02520 
02521 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
02522   { { 3 /* arr */ }, 'o' },
02523   { { 4 /* ars */ }, 'i' },
02524   { { 6 /* art */ }, 'i' }
02525 };
02526 
02527 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
02528   { { 3 /* arr */ }, 'o' },
02529   { { 4 /* ars */ }, 'i' },
02530   { { 6 /* art */ }, 'i' }
02531 };
02532 
02533 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
02534   { { 4 /* ars */ }, 'i' },
02535   { { 17 /* b4const */ }, 'i' },
02536   { { 28 /* label8 */ }, 'i' }
02537 };
02538 
02539 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
02540   { { 4 /* ars */ }, 'i' },
02541   { { 37 /* bbi */ }, 'i' },
02542   { { 28 /* label8 */ }, 'i' }
02543 };
02544 
02545 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
02546   { { 4 /* ars */ }, 'i' },
02547   { { 18 /* b4constu */ }, 'i' },
02548   { { 28 /* label8 */ }, 'i' }
02549 };
02550 
02551 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
02552   { { 4 /* ars */ }, 'i' },
02553   { { 6 /* art */ }, 'i' },
02554   { { 28 /* label8 */ }, 'i' }
02555 };
02556 
02557 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
02558   { { 4 /* ars */ }, 'i' },
02559   { { 30 /* label12 */ }, 'i' }
02560 };
02561 
02562 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
02563   { { 0 /* soffsetx4 */ }, 'i' },
02564   { { 7 /* ar0 */ }, 'o' }
02565 };
02566 
02567 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
02568   { { 4 /* ars */ }, 'i' },
02569   { { 7 /* ar0 */ }, 'o' }
02570 };
02571 
02572 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
02573   { { 3 /* arr */ }, 'o' },
02574   { { 6 /* art */ }, 'i' },
02575   { { 52 /* sae */ }, 'i' },
02576   { { 27 /* op2p1 */ }, 'i' }
02577 };
02578 
02579 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
02580   { { 31 /* soffset */ }, 'i' }
02581 };
02582 
02583 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
02584   { { 4 /* ars */ }, 'i' }
02585 };
02586 
02587 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
02588   { { 6 /* art */ }, 'o' },
02589   { { 4 /* ars */ }, 'i' },
02590   { { 20 /* uimm8x2 */ }, 'i' }
02591 };
02592 
02593 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
02594   { { 6 /* art */ }, 'o' },
02595   { { 4 /* ars */ }, 'i' },
02596   { { 20 /* uimm8x2 */ }, 'i' }
02597 };
02598 
02599 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
02600   { { 6 /* art */ }, 'o' },
02601   { { 4 /* ars */ }, 'i' },
02602   { { 21 /* uimm8x4 */ }, 'i' }
02603 };
02604 
02605 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
02606   { { 6 /* art */ }, 'o' },
02607   { { 32 /* uimm16x4 */ }, 'i' }
02608 };
02609 
02610 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
02611   { { STATE_LITBADDR }, 'i' },
02612   { { STATE_LITBEN }, 'i' }
02613 };
02614 
02615 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
02616   { { 6 /* art */ }, 'o' },
02617   { { 4 /* ars */ }, 'i' },
02618   { { 19 /* uimm8 */ }, 'i' }
02619 };
02620 
02621 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
02622   { { 4 /* ars */ }, 'i' },
02623   { { 29 /* ulabel8 */ }, 'i' }
02624 };
02625 
02626 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
02627   { { STATE_LBEG }, 'o' },
02628   { { STATE_LEND }, 'o' },
02629   { { STATE_LCOUNT }, 'o' }
02630 };
02631 
02632 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
02633   { { 4 /* ars */ }, 'i' },
02634   { { 29 /* ulabel8 */ }, 'i' }
02635 };
02636 
02637 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
02638   { { STATE_LBEG }, 'o' },
02639   { { STATE_LEND }, 'o' },
02640   { { STATE_LCOUNT }, 'o' }
02641 };
02642 
02643 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
02644   { { 6 /* art */ }, 'o' },
02645   { { 25 /* simm12b */ }, 'i' }
02646 };
02647 
02648 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
02649   { { 3 /* arr */ }, 'm' },
02650   { { 4 /* ars */ }, 'i' },
02651   { { 6 /* art */ }, 'i' }
02652 };
02653 
02654 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
02655   { { 3 /* arr */ }, 'o' },
02656   { { 6 /* art */ }, 'i' }
02657 };
02658 
02659 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
02660   { { 5 /* *ars_invisible */ }, 'i' }
02661 };
02662 
02663 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
02664   { { 6 /* art */ }, 'i' },
02665   { { 4 /* ars */ }, 'i' },
02666   { { 20 /* uimm8x2 */ }, 'i' }
02667 };
02668 
02669 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
02670   { { 6 /* art */ }, 'i' },
02671   { { 4 /* ars */ }, 'i' },
02672   { { 21 /* uimm8x4 */ }, 'i' }
02673 };
02674 
02675 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
02676   { { 6 /* art */ }, 'i' },
02677   { { 4 /* ars */ }, 'i' },
02678   { { 19 /* uimm8 */ }, 'i' }
02679 };
02680 
02681 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
02682   { { 4 /* ars */ }, 'i' }
02683 };
02684 
02685 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
02686   { { STATE_SAR }, 'o' }
02687 };
02688 
02689 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
02690   { { 56 /* sas */ }, 'i' }
02691 };
02692 
02693 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
02694   { { STATE_SAR }, 'o' }
02695 };
02696 
02697 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
02698   { { 3 /* arr */ }, 'o' },
02699   { { 4 /* ars */ }, 'i' }
02700 };
02701 
02702 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
02703   { { STATE_SAR }, 'i' }
02704 };
02705 
02706 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
02707   { { 3 /* arr */ }, 'o' },
02708   { { 4 /* ars */ }, 'i' },
02709   { { 6 /* art */ }, 'i' }
02710 };
02711 
02712 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
02713   { { STATE_SAR }, 'i' }
02714 };
02715 
02716 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
02717   { { 3 /* arr */ }, 'o' },
02718   { { 6 /* art */ }, 'i' }
02719 };
02720 
02721 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
02722   { { STATE_SAR }, 'i' }
02723 };
02724 
02725 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
02726   { { 3 /* arr */ }, 'o' },
02727   { { 4 /* ars */ }, 'i' },
02728   { { 26 /* msalp32 */ }, 'i' }
02729 };
02730 
02731 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
02732   { { 3 /* arr */ }, 'o' },
02733   { { 6 /* art */ }, 'i' },
02734   { { 54 /* sargt */ }, 'i' }
02735 };
02736 
02737 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
02738   { { 3 /* arr */ }, 'o' },
02739   { { 6 /* art */ }, 'i' },
02740   { { 40 /* s */ }, 'i' }
02741 };
02742 
02743 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
02744   { { STATE_XTSYNC }, 'i' }
02745 };
02746 
02747 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
02748   { { 6 /* art */ }, 'o' },
02749   { { 40 /* s */ }, 'i' }
02750 };
02751 
02752 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
02753   { { STATE_PSWOE }, 'i' },
02754   { { STATE_PSCALLINC }, 'i' },
02755   { { STATE_PSOWB }, 'i' },
02756   { { STATE_PSRING }, 'i' },
02757   { { STATE_PSUM }, 'i' },
02758   { { STATE_PSEXCM }, 'i' },
02759   { { STATE_PSINTLEVEL }, 'm' }
02760 };
02761 
02762 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
02763   { { 6 /* art */ }, 'o' }
02764 };
02765 
02766 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
02767   { { STATE_LEND }, 'i' }
02768 };
02769 
02770 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
02771   { { 6 /* art */ }, 'i' }
02772 };
02773 
02774 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
02775   { { STATE_LEND }, 'o' }
02776 };
02777 
02778 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
02779   { { 6 /* art */ }, 'm' }
02780 };
02781 
02782 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
02783   { { STATE_LEND }, 'm' }
02784 };
02785 
02786 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
02787   { { 6 /* art */ }, 'o' }
02788 };
02789 
02790 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
02791   { { STATE_LCOUNT }, 'i' }
02792 };
02793 
02794 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
02795   { { 6 /* art */ }, 'i' }
02796 };
02797 
02798 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
02799   { { STATE_XTSYNC }, 'o' },
02800   { { STATE_LCOUNT }, 'o' }
02801 };
02802 
02803 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
02804   { { 6 /* art */ }, 'm' }
02805 };
02806 
02807 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
02808   { { STATE_XTSYNC }, 'o' },
02809   { { STATE_LCOUNT }, 'm' }
02810 };
02811 
02812 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
02813   { { 6 /* art */ }, 'o' }
02814 };
02815 
02816 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
02817   { { STATE_LBEG }, 'i' }
02818 };
02819 
02820 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
02821   { { 6 /* art */ }, 'i' }
02822 };
02823 
02824 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
02825   { { STATE_LBEG }, 'o' }
02826 };
02827 
02828 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
02829   { { 6 /* art */ }, 'm' }
02830 };
02831 
02832 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
02833   { { STATE_LBEG }, 'm' }
02834 };
02835 
02836 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
02837   { { 6 /* art */ }, 'o' }
02838 };
02839 
02840 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
02841   { { STATE_SAR }, 'i' }
02842 };
02843 
02844 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
02845   { { 6 /* art */ }, 'i' }
02846 };
02847 
02848 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
02849   { { STATE_SAR }, 'o' },
02850   { { STATE_XTSYNC }, 'o' }
02851 };
02852 
02853 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
02854   { { 6 /* art */ }, 'm' }
02855 };
02856 
02857 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
02858   { { STATE_SAR }, 'm' }
02859 };
02860 
02861 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
02862   { { 6 /* art */ }, 'o' }
02863 };
02864 
02865 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
02866   { { STATE_LITBADDR }, 'i' },
02867   { { STATE_LITBEN }, 'i' }
02868 };
02869 
02870 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
02871   { { 6 /* art */ }, 'i' }
02872 };
02873 
02874 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
02875   { { STATE_LITBADDR }, 'o' },
02876   { { STATE_LITBEN }, 'o' }
02877 };
02878 
02879 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
02880   { { 6 /* art */ }, 'm' }
02881 };
02882 
02883 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
02884   { { STATE_LITBADDR }, 'm' },
02885   { { STATE_LITBEN }, 'm' }
02886 };
02887 
02888 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
02889   { { 6 /* art */ }, 'o' }
02890 };
02891 
02892 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
02893   { { STATE_PSEXCM }, 'i' },
02894   { { STATE_PSRING }, 'i' }
02895 };
02896 
02897 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
02898   { { 6 /* art */ }, 'o' }
02899 };
02900 
02901 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
02902   { { STATE_PSEXCM }, 'i' },
02903   { { STATE_PSRING }, 'i' }
02904 };
02905 
02906 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
02907   { { 6 /* art */ }, 'o' }
02908 };
02909 
02910 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
02911   { { STATE_PSWOE }, 'i' },
02912   { { STATE_PSCALLINC }, 'i' },
02913   { { STATE_PSOWB }, 'i' },
02914   { { STATE_PSRING }, 'i' },
02915   { { STATE_PSUM }, 'i' },
02916   { { STATE_PSEXCM }, 'i' },
02917   { { STATE_PSINTLEVEL }, 'i' }
02918 };
02919 
02920 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
02921   { { 6 /* art */ }, 'i' }
02922 };
02923 
02924 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
02925   { { STATE_PSWOE }, 'o' },
02926   { { STATE_PSCALLINC }, 'o' },
02927   { { STATE_PSOWB }, 'o' },
02928   { { STATE_PSRING }, 'm' },
02929   { { STATE_PSUM }, 'o' },
02930   { { STATE_PSEXCM }, 'm' },
02931   { { STATE_PSINTLEVEL }, 'o' }
02932 };
02933 
02934 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
02935   { { 6 /* art */ }, 'm' }
02936 };
02937 
02938 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
02939   { { STATE_PSWOE }, 'm' },
02940   { { STATE_PSCALLINC }, 'm' },
02941   { { STATE_PSOWB }, 'm' },
02942   { { STATE_PSRING }, 'm' },
02943   { { STATE_PSUM }, 'm' },
02944   { { STATE_PSEXCM }, 'm' },
02945   { { STATE_PSINTLEVEL }, 'm' }
02946 };
02947 
02948 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
02949   { { 6 /* art */ }, 'o' }
02950 };
02951 
02952 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
02953   { { STATE_PSEXCM }, 'i' },
02954   { { STATE_PSRING }, 'i' },
02955   { { STATE_EPC1 }, 'i' }
02956 };
02957 
02958 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
02959   { { 6 /* art */ }, 'i' }
02960 };
02961 
02962 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
02963   { { STATE_PSEXCM }, 'i' },
02964   { { STATE_PSRING }, 'i' },
02965   { { STATE_EPC1 }, 'o' }
02966 };
02967 
02968 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
02969   { { 6 /* art */ }, 'm' }
02970 };
02971 
02972 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
02973   { { STATE_PSEXCM }, 'i' },
02974   { { STATE_PSRING }, 'i' },
02975   { { STATE_EPC1 }, 'm' }
02976 };
02977 
02978 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
02979   { { 6 /* art */ }, 'o' }
02980 };
02981 
02982 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
02983   { { STATE_PSEXCM }, 'i' },
02984   { { STATE_PSRING }, 'i' },
02985   { { STATE_EXCSAVE1 }, 'i' }
02986 };
02987 
02988 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
02989   { { 6 /* art */ }, 'i' }
02990 };
02991 
02992 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
02993   { { STATE_PSEXCM }, 'i' },
02994   { { STATE_PSRING }, 'i' },
02995   { { STATE_EXCSAVE1 }, 'o' }
02996 };
02997 
02998 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
02999   { { 6 /* art */ }, 'm' }
03000 };
03001 
03002 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
03003   { { STATE_PSEXCM }, 'i' },
03004   { { STATE_PSRING }, 'i' },
03005   { { STATE_EXCSAVE1 }, 'm' }
03006 };
03007 
03008 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
03009   { { 6 /* art */ }, 'o' }
03010 };
03011 
03012 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
03013   { { STATE_PSEXCM }, 'i' },
03014   { { STATE_PSRING }, 'i' },
03015   { { STATE_EPC2 }, 'i' }
03016 };
03017 
03018 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
03019   { { 6 /* art */ }, 'i' }
03020 };
03021 
03022 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
03023   { { STATE_PSEXCM }, 'i' },
03024   { { STATE_PSRING }, 'i' },
03025   { { STATE_EPC2 }, 'o' }
03026 };
03027 
03028 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
03029   { { 6 /* art */ }, 'm' }
03030 };
03031 
03032 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
03033   { { STATE_PSEXCM }, 'i' },
03034   { { STATE_PSRING }, 'i' },
03035   { { STATE_EPC2 }, 'm' }
03036 };
03037 
03038 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
03039   { { 6 /* art */ }, 'o' }
03040 };
03041 
03042 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
03043   { { STATE_PSEXCM }, 'i' },
03044   { { STATE_PSRING }, 'i' },
03045   { { STATE_EXCSAVE2 }, 'i' }
03046 };
03047 
03048 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
03049   { { 6 /* art */ }, 'i' }
03050 };
03051 
03052 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
03053   { { STATE_PSEXCM }, 'i' },
03054   { { STATE_PSRING }, 'i' },
03055   { { STATE_EXCSAVE2 }, 'o' }
03056 };
03057 
03058 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
03059   { { 6 /* art */ }, 'm' }
03060 };
03061 
03062 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
03063   { { STATE_PSEXCM }, 'i' },
03064   { { STATE_PSRING }, 'i' },
03065   { { STATE_EXCSAVE2 }, 'm' }
03066 };
03067 
03068 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
03069   { { 6 /* art */ }, 'o' }
03070 };
03071 
03072 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
03073   { { STATE_PSEXCM }, 'i' },
03074   { { STATE_PSRING }, 'i' },
03075   { { STATE_EPC3 }, 'i' }
03076 };
03077 
03078 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
03079   { { 6 /* art */ }, 'i' }
03080 };
03081 
03082 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
03083   { { STATE_PSEXCM }, 'i' },
03084   { { STATE_PSRING }, 'i' },
03085   { { STATE_EPC3 }, 'o' }
03086 };
03087 
03088 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
03089   { { 6 /* art */ }, 'm' }
03090 };
03091 
03092 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
03093   { { STATE_PSEXCM }, 'i' },
03094   { { STATE_PSRING }, 'i' },
03095   { { STATE_EPC3 }, 'm' }
03096 };
03097 
03098 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
03099   { { 6 /* art */ }, 'o' }
03100 };
03101 
03102 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
03103   { { STATE_PSEXCM }, 'i' },
03104   { { STATE_PSRING }, 'i' },
03105   { { STATE_EXCSAVE3 }, 'i' }
03106 };
03107 
03108 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
03109   { { 6 /* art */ }, 'i' }
03110 };
03111 
03112 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
03113   { { STATE_PSEXCM }, 'i' },
03114   { { STATE_PSRING }, 'i' },
03115   { { STATE_EXCSAVE3 }, 'o' }
03116 };
03117 
03118 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
03119   { { 6 /* art */ }, 'm' }
03120 };
03121 
03122 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
03123   { { STATE_PSEXCM }, 'i' },
03124   { { STATE_PSRING }, 'i' },
03125   { { STATE_EXCSAVE3 }, 'm' }
03126 };
03127 
03128 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
03129   { { 6 /* art */ }, 'o' }
03130 };
03131 
03132 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
03133   { { STATE_PSEXCM }, 'i' },
03134   { { STATE_PSRING }, 'i' },
03135   { { STATE_EPC4 }, 'i' }
03136 };
03137 
03138 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
03139   { { 6 /* art */ }, 'i' }
03140 };
03141 
03142 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
03143   { { STATE_PSEXCM }, 'i' },
03144   { { STATE_PSRING }, 'i' },
03145   { { STATE_EPC4 }, 'o' }
03146 };
03147 
03148 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
03149   { { 6 /* art */ }, 'm' }
03150 };
03151 
03152 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
03153   { { STATE_PSEXCM }, 'i' },
03154   { { STATE_PSRING }, 'i' },
03155   { { STATE_EPC4 }, 'm' }
03156 };
03157 
03158 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
03159   { { 6 /* art */ }, 'o' }
03160 };
03161 
03162 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
03163   { { STATE_PSEXCM }, 'i' },
03164   { { STATE_PSRING }, 'i' },
03165   { { STATE_EXCSAVE4 }, 'i' }
03166 };
03167 
03168 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
03169   { { 6 /* art */ }, 'i' }
03170 };
03171 
03172 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
03173   { { STATE_PSEXCM }, 'i' },
03174   { { STATE_PSRING }, 'i' },
03175   { { STATE_EXCSAVE4 }, 'o' }
03176 };
03177 
03178 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
03179   { { 6 /* art */ }, 'm' }
03180 };
03181 
03182 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
03183   { { STATE_PSEXCM }, 'i' },
03184   { { STATE_PSRING }, 'i' },
03185   { { STATE_EXCSAVE4 }, 'm' }
03186 };
03187 
03188 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
03189   { { 6 /* art */ }, 'o' }
03190 };
03191 
03192 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
03193   { { STATE_PSEXCM }, 'i' },
03194   { { STATE_PSRING }, 'i' },
03195   { { STATE_EPS2 }, 'i' }
03196 };
03197 
03198 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
03199   { { 6 /* art */ }, 'i' }
03200 };
03201 
03202 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
03203   { { STATE_PSEXCM }, 'i' },
03204   { { STATE_PSRING }, 'i' },
03205   { { STATE_EPS2 }, 'o' }
03206 };
03207 
03208 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
03209   { { 6 /* art */ }, 'm' }
03210 };
03211 
03212 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
03213   { { STATE_PSEXCM }, 'i' },
03214   { { STATE_PSRING }, 'i' },
03215   { { STATE_EPS2 }, 'm' }
03216 };
03217 
03218 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
03219   { { 6 /* art */ }, 'o' }
03220 };
03221 
03222 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
03223   { { STATE_PSEXCM }, 'i' },
03224   { { STATE_PSRING }, 'i' },
03225   { { STATE_EPS3 }, 'i' }
03226 };
03227 
03228 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
03229   { { 6 /* art */ }, 'i' }
03230 };
03231 
03232 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
03233   { { STATE_PSEXCM }, 'i' },
03234   { { STATE_PSRING }, 'i' },
03235   { { STATE_EPS3 }, 'o' }
03236 };
03237 
03238 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
03239   { { 6 /* art */ }, 'm' }
03240 };
03241 
03242 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
03243   { { STATE_PSEXCM }, 'i' },
03244   { { STATE_PSRING }, 'i' },
03245   { { STATE_EPS3 }, 'm' }
03246 };
03247 
03248 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
03249   { { 6 /* art */ }, 'o' }
03250 };
03251 
03252 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
03253   { { STATE_PSEXCM }, 'i' },
03254   { { STATE_PSRING }, 'i' },
03255   { { STATE_EPS4 }, 'i' }
03256 };
03257 
03258 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
03259   { { 6 /* art */ }, 'i' }
03260 };
03261 
03262 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
03263   { { STATE_PSEXCM }, 'i' },
03264   { { STATE_PSRING }, 'i' },
03265   { { STATE_EPS4 }, 'o' }
03266 };
03267 
03268 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
03269   { { 6 /* art */ }, 'm' }
03270 };
03271 
03272 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
03273   { { STATE_PSEXCM }, 'i' },
03274   { { STATE_PSRING }, 'i' },
03275   { { STATE_EPS4 }, 'm' }
03276 };
03277 
03278 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
03279   { { 6 /* art */ }, 'o' }
03280 };
03281 
03282 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
03283   { { STATE_PSEXCM }, 'i' },
03284   { { STATE_PSRING }, 'i' },
03285   { { STATE_EXCVADDR }, 'i' }
03286 };
03287 
03288 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
03289   { { 6 /* art */ }, 'i' }
03290 };
03291 
03292 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
03293   { { STATE_PSEXCM }, 'i' },
03294   { { STATE_PSRING }, 'i' },
03295   { { STATE_EXCVADDR }, 'o' }
03296 };
03297 
03298 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
03299   { { 6 /* art */ }, 'm' }
03300 };
03301 
03302 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
03303   { { STATE_PSEXCM }, 'i' },
03304   { { STATE_PSRING }, 'i' },
03305   { { STATE_EXCVADDR }, 'm' }
03306 };
03307 
03308 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
03309   { { 6 /* art */ }, 'o' }
03310 };
03311 
03312 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
03313   { { STATE_PSEXCM }, 'i' },
03314   { { STATE_PSRING }, 'i' },
03315   { { STATE_DEPC }, 'i' }
03316 };
03317 
03318 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
03319   { { 6 /* art */ }, 'i' }
03320 };
03321 
03322 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
03323   { { STATE_PSEXCM }, 'i' },
03324   { { STATE_PSRING }, 'i' },
03325   { { STATE_DEPC }, 'o' }
03326 };
03327 
03328 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
03329   { { 6 /* art */ }, 'm' }
03330 };
03331 
03332 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
03333   { { STATE_PSEXCM }, 'i' },
03334   { { STATE_PSRING }, 'i' },
03335   { { STATE_DEPC }, 'm' }
03336 };
03337 
03338 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
03339   { { 6 /* art */ }, 'o' }
03340 };
03341 
03342 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
03343   { { STATE_PSEXCM }, 'i' },
03344   { { STATE_PSRING }, 'i' },
03345   { { STATE_EXCCAUSE }, 'i' },
03346   { { STATE_XTSYNC }, 'i' }
03347 };
03348 
03349 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
03350   { { 6 /* art */ }, 'i' }
03351 };
03352 
03353 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
03354   { { STATE_PSEXCM }, 'i' },
03355   { { STATE_PSRING }, 'i' },
03356   { { STATE_EXCCAUSE }, 'o' }
03357 };
03358 
03359 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
03360   { { 6 /* art */ }, 'm' }
03361 };
03362 
03363 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
03364   { { STATE_PSEXCM }, 'i' },
03365   { { STATE_PSRING }, 'i' },
03366   { { STATE_EXCCAUSE }, 'm' }
03367 };
03368 
03369 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
03370   { { 6 /* art */ }, 'o' }
03371 };
03372 
03373 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
03374   { { STATE_PSEXCM }, 'i' },
03375   { { STATE_PSRING }, 'i' },
03376   { { STATE_MISC0 }, 'i' }
03377 };
03378 
03379 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
03380   { { 6 /* art */ }, 'i' }
03381 };
03382 
03383 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
03384   { { STATE_PSEXCM }, 'i' },
03385   { { STATE_PSRING }, 'i' },
03386   { { STATE_MISC0 }, 'o' }
03387 };
03388 
03389 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
03390   { { 6 /* art */ }, 'm' }
03391 };
03392 
03393 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
03394   { { STATE_PSEXCM }, 'i' },
03395   { { STATE_PSRING }, 'i' },
03396   { { STATE_MISC0 }, 'm' }
03397 };
03398 
03399 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
03400   { { 6 /* art */ }, 'o' }
03401 };
03402 
03403 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
03404   { { STATE_PSEXCM }, 'i' },
03405   { { STATE_PSRING }, 'i' },
03406   { { STATE_MISC1 }, 'i' }
03407 };
03408 
03409 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
03410   { { 6 /* art */ }, 'i' }
03411 };
03412 
03413 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
03414   { { STATE_PSEXCM }, 'i' },
03415   { { STATE_PSRING }, 'i' },
03416   { { STATE_MISC1 }, 'o' }
03417 };
03418 
03419 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
03420   { { 6 /* art */ }, 'm' }
03421 };
03422 
03423 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
03424   { { STATE_PSEXCM }, 'i' },
03425   { { STATE_PSRING }, 'i' },
03426   { { STATE_MISC1 }, 'm' }
03427 };
03428 
03429 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
03430   { { 6 /* art */ }, 'o' }
03431 };
03432 
03433 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
03434   { { STATE_PSEXCM }, 'i' },
03435   { { STATE_PSRING }, 'i' }
03436 };
03437 
03438 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
03439   { { 40 /* s */ }, 'i' }
03440 };
03441 
03442 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
03443   { { STATE_PSWOE }, 'o' },
03444   { { STATE_PSCALLINC }, 'o' },
03445   { { STATE_PSOWB }, 'o' },
03446   { { STATE_PSRING }, 'm' },
03447   { { STATE_PSUM }, 'o' },
03448   { { STATE_PSEXCM }, 'm' },
03449   { { STATE_PSINTLEVEL }, 'o' },
03450   { { STATE_EPC1 }, 'i' },
03451   { { STATE_EPC2 }, 'i' },
03452   { { STATE_EPC3 }, 'i' },
03453   { { STATE_EPC4 }, 'i' },
03454   { { STATE_EPS2 }, 'i' },
03455   { { STATE_EPS3 }, 'i' },
03456   { { STATE_EPS4 }, 'i' },
03457   { { STATE_InOCDMode }, 'm' }
03458 };
03459 
03460 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
03461   { { 40 /* s */ }, 'i' }
03462 };
03463 
03464 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
03465   { { STATE_PSEXCM }, 'i' },
03466   { { STATE_PSRING }, 'i' },
03467   { { STATE_PSINTLEVEL }, 'o' }
03468 };
03469 
03470 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
03471   { { 6 /* art */ }, 'o' }
03472 };
03473 
03474 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
03475   { { STATE_PSEXCM }, 'i' },
03476   { { STATE_PSRING }, 'i' },
03477   { { STATE_INTERRUPT }, 'i' }
03478 };
03479 
03480 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
03481   { { 6 /* art */ }, 'i' }
03482 };
03483 
03484 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
03485   { { STATE_PSEXCM }, 'i' },
03486   { { STATE_PSRING }, 'i' },
03487   { { STATE_XTSYNC }, 'o' },
03488   { { STATE_INTERRUPT }, 'm' }
03489 };
03490 
03491 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
03492   { { 6 /* art */ }, 'i' }
03493 };
03494 
03495 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
03496   { { STATE_PSEXCM }, 'i' },
03497   { { STATE_PSRING }, 'i' },
03498   { { STATE_XTSYNC }, 'o' },
03499   { { STATE_INTERRUPT }, 'm' }
03500 };
03501 
03502 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
03503   { { 6 /* art */ }, 'o' }
03504 };
03505 
03506 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
03507   { { STATE_PSEXCM }, 'i' },
03508   { { STATE_PSRING }, 'i' },
03509   { { STATE_INTENABLE }, 'i' }
03510 };
03511 
03512 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
03513   { { 6 /* art */ }, 'i' }
03514 };
03515 
03516 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
03517   { { STATE_PSEXCM }, 'i' },
03518   { { STATE_PSRING }, 'i' },
03519   { { STATE_INTENABLE }, 'o' }
03520 };
03521 
03522 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
03523   { { 6 /* art */ }, 'm' }
03524 };
03525 
03526 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
03527   { { STATE_PSEXCM }, 'i' },
03528   { { STATE_PSRING }, 'i' },
03529   { { STATE_INTENABLE }, 'm' }
03530 };
03531 
03532 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
03533   { { 34 /* imms */ }, 'i' },
03534   { { 33 /* immt */ }, 'i' }
03535 };
03536 
03537 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
03538   { { STATE_PSEXCM }, 'i' },
03539   { { STATE_PSINTLEVEL }, 'i' }
03540 };
03541 
03542 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
03543   { { 34 /* imms */ }, 'i' }
03544 };
03545 
03546 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
03547   { { STATE_PSEXCM }, 'i' },
03548   { { STATE_PSINTLEVEL }, 'i' }
03549 };
03550 
03551 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
03552   { { 6 /* art */ }, 'o' }
03553 };
03554 
03555 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
03556   { { STATE_PSEXCM }, 'i' },
03557   { { STATE_PSRING }, 'i' },
03558   { { STATE_DBREAKA0 }, 'i' }
03559 };
03560 
03561 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
03562   { { 6 /* art */ }, 'i' }
03563 };
03564 
03565 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
03566   { { STATE_PSEXCM }, 'i' },
03567   { { STATE_PSRING }, 'i' },
03568   { { STATE_DBREAKA0 }, 'o' },
03569   { { STATE_XTSYNC }, 'o' }
03570 };
03571 
03572 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
03573   { { 6 /* art */ }, 'm' }
03574 };
03575 
03576 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
03577   { { STATE_PSEXCM }, 'i' },
03578   { { STATE_PSRING }, 'i' },
03579   { { STATE_DBREAKA0 }, 'm' },
03580   { { STATE_XTSYNC }, 'o' }
03581 };
03582 
03583 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
03584   { { 6 /* art */ }, 'o' }
03585 };
03586 
03587 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
03588   { { STATE_PSEXCM }, 'i' },
03589   { { STATE_PSRING }, 'i' },
03590   { { STATE_DBREAKC0 }, 'i' }
03591 };
03592 
03593 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
03594   { { 6 /* art */ }, 'i' }
03595 };
03596 
03597 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
03598   { { STATE_PSEXCM }, 'i' },
03599   { { STATE_PSRING }, 'i' },
03600   { { STATE_DBREAKC0 }, 'o' },
03601   { { STATE_XTSYNC }, 'o' }
03602 };
03603 
03604 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
03605   { { 6 /* art */ }, 'm' }
03606 };
03607 
03608 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
03609   { { STATE_PSEXCM }, 'i' },
03610   { { STATE_PSRING }, 'i' },
03611   { { STATE_DBREAKC0 }, 'm' },
03612   { { STATE_XTSYNC }, 'o' }
03613 };
03614 
03615 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
03616   { { 6 /* art */ }, 'o' }
03617 };
03618 
03619 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
03620   { { STATE_PSEXCM }, 'i' },
03621   { { STATE_PSRING }, 'i' },
03622   { { STATE_DBREAKA1 }, 'i' }
03623 };
03624 
03625 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
03626   { { 6 /* art */ }, 'i' }
03627 };
03628 
03629 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
03630   { { STATE_PSEXCM }, 'i' },
03631   { { STATE_PSRING }, 'i' },
03632   { { STATE_DBREAKA1 }, 'o' },
03633   { { STATE_XTSYNC }, 'o' }
03634 };
03635 
03636 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
03637   { { 6 /* art */ }, 'm' }
03638 };
03639 
03640 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
03641   { { STATE_PSEXCM }, 'i' },
03642   { { STATE_PSRING }, 'i' },
03643   { { STATE_DBREAKA1 }, 'm' },
03644   { { STATE_XTSYNC }, 'o' }
03645 };
03646 
03647 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
03648   { { 6 /* art */ }, 'o' }
03649 };
03650 
03651 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
03652   { { STATE_PSEXCM }, 'i' },
03653   { { STATE_PSRING }, 'i' },
03654   { { STATE_DBREAKC1 }, 'i' }
03655 };
03656 
03657 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
03658   { { 6 /* art */ }, 'i' }
03659 };
03660 
03661 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
03662   { { STATE_PSEXCM }, 'i' },
03663   { { STATE_PSRING }, 'i' },
03664   { { STATE_DBREAKC1 }, 'o' },
03665   { { STATE_XTSYNC }, 'o' }
03666 };
03667 
03668 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
03669   { { 6 /* art */ }, 'm' }
03670 };
03671 
03672 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
03673   { { STATE_PSEXCM }, 'i' },
03674   { { STATE_PSRING }, 'i' },
03675   { { STATE_DBREAKC1 }, 'm' },
03676   { { STATE_XTSYNC }, 'o' }
03677 };
03678 
03679 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
03680   { { 6 /* art */ }, 'o' }
03681 };
03682 
03683 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
03684   { { STATE_PSEXCM }, 'i' },
03685   { { STATE_PSRING }, 'i' },
03686   { { STATE_IBREAKA0 }, 'i' }
03687 };
03688 
03689 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
03690   { { 6 /* art */ }, 'i' }
03691 };
03692 
03693 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
03694   { { STATE_PSEXCM }, 'i' },
03695   { { STATE_PSRING }, 'i' },
03696   { { STATE_IBREAKA0 }, 'o' }
03697 };
03698 
03699 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
03700   { { 6 /* art */ }, 'm' }
03701 };
03702 
03703 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
03704   { { STATE_PSEXCM }, 'i' },
03705   { { STATE_PSRING }, 'i' },
03706   { { STATE_IBREAKA0 }, 'm' }
03707 };
03708 
03709 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
03710   { { 6 /* art */ }, 'o' }
03711 };
03712 
03713 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
03714   { { STATE_PSEXCM }, 'i' },
03715   { { STATE_PSRING }, 'i' },
03716   { { STATE_IBREAKA1 }, 'i' }
03717 };
03718 
03719 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
03720   { { 6 /* art */ }, 'i' }
03721 };
03722 
03723 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
03724   { { STATE_PSEXCM }, 'i' },
03725   { { STATE_PSRING }, 'i' },
03726   { { STATE_IBREAKA1 }, 'o' }
03727 };
03728 
03729 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
03730   { { 6 /* art */ }, 'm' }
03731 };
03732 
03733 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
03734   { { STATE_PSEXCM }, 'i' },
03735   { { STATE_PSRING }, 'i' },
03736   { { STATE_IBREAKA1 }, 'm' }
03737 };
03738 
03739 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
03740   { { 6 /* art */ }, 'o' }
03741 };
03742 
03743 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
03744   { { STATE_PSEXCM }, 'i' },
03745   { { STATE_PSRING }, 'i' },
03746   { { STATE_IBREAKENABLE }, 'i' }
03747 };
03748 
03749 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
03750   { { 6 /* art */ }, 'i' }
03751 };
03752 
03753 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
03754   { { STATE_PSEXCM }, 'i' },
03755   { { STATE_PSRING }, 'i' },
03756   { { STATE_IBREAKENABLE }, 'o' }
03757 };
03758 
03759 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
03760   { { 6 /* art */ }, 'm' }
03761 };
03762 
03763 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
03764   { { STATE_PSEXCM }, 'i' },
03765   { { STATE_PSRING }, 'i' },
03766   { { STATE_IBREAKENABLE }, 'm' }
03767 };
03768 
03769 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
03770   { { 6 /* art */ }, 'o' }
03771 };
03772 
03773 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
03774   { { STATE_PSEXCM }, 'i' },
03775   { { STATE_PSRING }, 'i' },
03776   { { STATE_DEBUGCAUSE }, 'i' },
03777   { { STATE_DBNUM }, 'i' }
03778 };
03779 
03780 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
03781   { { 6 /* art */ }, 'i' }
03782 };
03783 
03784 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
03785   { { STATE_PSEXCM }, 'i' },
03786   { { STATE_PSRING }, 'i' },
03787   { { STATE_DEBUGCAUSE }, 'o' },
03788   { { STATE_DBNUM }, 'o' }
03789 };
03790 
03791 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
03792   { { 6 /* art */ }, 'm' }
03793 };
03794 
03795 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
03796   { { STATE_PSEXCM }, 'i' },
03797   { { STATE_PSRING }, 'i' },
03798   { { STATE_DEBUGCAUSE }, 'm' },
03799   { { STATE_DBNUM }, 'm' }
03800 };
03801 
03802 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
03803   { { 6 /* art */ }, 'o' }
03804 };
03805 
03806 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
03807   { { STATE_PSEXCM }, 'i' },
03808   { { STATE_PSRING }, 'i' },
03809   { { STATE_ICOUNT }, 'i' }
03810 };
03811 
03812 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
03813   { { 6 /* art */ }, 'i' }
03814 };
03815 
03816 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
03817   { { STATE_PSEXCM }, 'i' },
03818   { { STATE_PSRING }, 'i' },
03819   { { STATE_XTSYNC }, 'o' },
03820   { { STATE_ICOUNT }, 'o' }
03821 };
03822 
03823 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
03824   { { 6 /* art */ }, 'm' }
03825 };
03826 
03827 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
03828   { { STATE_PSEXCM }, 'i' },
03829   { { STATE_PSRING }, 'i' },
03830   { { STATE_XTSYNC }, 'o' },
03831   { { STATE_ICOUNT }, 'm' }
03832 };
03833 
03834 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
03835   { { 6 /* art */ }, 'o' }
03836 };
03837 
03838 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
03839   { { STATE_PSEXCM }, 'i' },
03840   { { STATE_PSRING }, 'i' },
03841   { { STATE_ICOUNTLEVEL }, 'i' }
03842 };
03843 
03844 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
03845   { { 6 /* art */ }, 'i' }
03846 };
03847 
03848 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
03849   { { STATE_PSEXCM }, 'i' },
03850   { { STATE_PSRING }, 'i' },
03851   { { STATE_ICOUNTLEVEL }, 'o' }
03852 };
03853 
03854 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
03855   { { 6 /* art */ }, 'm' }
03856 };
03857 
03858 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
03859   { { STATE_PSEXCM }, 'i' },
03860   { { STATE_PSRING }, 'i' },
03861   { { STATE_ICOUNTLEVEL }, 'm' }
03862 };
03863 
03864 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
03865   { { 6 /* art */ }, 'o' }
03866 };
03867 
03868 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
03869   { { STATE_PSEXCM }, 'i' },
03870   { { STATE_PSRING }, 'i' },
03871   { { STATE_DDR }, 'i' }
03872 };
03873 
03874 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
03875   { { 6 /* art */ }, 'i' }
03876 };
03877 
03878 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
03879   { { STATE_PSEXCM }, 'i' },
03880   { { STATE_PSRING }, 'i' },
03881   { { STATE_XTSYNC }, 'o' },
03882   { { STATE_DDR }, 'o' }
03883 };
03884 
03885 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
03886   { { 6 /* art */ }, 'm' }
03887 };
03888 
03889 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
03890   { { STATE_PSEXCM }, 'i' },
03891   { { STATE_PSRING }, 'i' },
03892   { { STATE_XTSYNC }, 'o' },
03893   { { STATE_DDR }, 'm' }
03894 };
03895 
03896 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
03897   { { STATE_InOCDMode }, 'm' },
03898   { { STATE_EPC4 }, 'i' },
03899   { { STATE_PSWOE }, 'o' },
03900   { { STATE_PSCALLINC }, 'o' },
03901   { { STATE_PSOWB }, 'o' },
03902   { { STATE_PSRING }, 'o' },
03903   { { STATE_PSUM }, 'o' },
03904   { { STATE_PSEXCM }, 'o' },
03905   { { STATE_PSINTLEVEL }, 'o' },
03906   { { STATE_EPS4 }, 'i' }
03907 };
03908 
03909 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
03910   { { STATE_InOCDMode }, 'm' }
03911 };
03912 
03913 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
03914   { { 6 /* art */ }, 'o' }
03915 };
03916 
03917 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
03918   { { STATE_PSEXCM }, 'i' },
03919   { { STATE_PSRING }, 'i' },
03920   { { STATE_CCOUNT }, 'i' }
03921 };
03922 
03923 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
03924   { { 6 /* art */ }, 'i' }
03925 };
03926 
03927 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
03928   { { STATE_PSEXCM }, 'i' },
03929   { { STATE_PSRING }, 'i' },
03930   { { STATE_XTSYNC }, 'o' },
03931   { { STATE_CCOUNT }, 'o' }
03932 };
03933 
03934 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
03935   { { 6 /* art */ }, 'm' }
03936 };
03937 
03938 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
03939   { { STATE_PSEXCM }, 'i' },
03940   { { STATE_PSRING }, 'i' },
03941   { { STATE_XTSYNC }, 'o' },
03942   { { STATE_CCOUNT }, 'm' }
03943 };
03944 
03945 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
03946   { { 6 /* art */ }, 'o' }
03947 };
03948 
03949 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
03950   { { STATE_PSEXCM }, 'i' },
03951   { { STATE_PSRING }, 'i' },
03952   { { STATE_CCOMPARE0 }, 'i' }
03953 };
03954 
03955 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
03956   { { 6 /* art */ }, 'i' }
03957 };
03958 
03959 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
03960   { { STATE_PSEXCM }, 'i' },
03961   { { STATE_PSRING }, 'i' },
03962   { { STATE_CCOMPARE0 }, 'o' },
03963   { { STATE_INTERRUPT }, 'm' }
03964 };
03965 
03966 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
03967   { { 6 /* art */ }, 'm' }
03968 };
03969 
03970 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
03971   { { STATE_PSEXCM }, 'i' },
03972   { { STATE_PSRING }, 'i' },
03973   { { STATE_CCOMPARE0 }, 'm' },
03974   { { STATE_INTERRUPT }, 'm' }
03975 };
03976 
03977 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
03978   { { 6 /* art */ }, 'o' }
03979 };
03980 
03981 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
03982   { { STATE_PSEXCM }, 'i' },
03983   { { STATE_PSRING }, 'i' },
03984   { { STATE_CCOMPARE1 }, 'i' }
03985 };
03986 
03987 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
03988   { { 6 /* art */ }, 'i' }
03989 };
03990 
03991 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
03992   { { STATE_PSEXCM }, 'i' },
03993   { { STATE_PSRING }, 'i' },
03994   { { STATE_CCOMPARE1 }, 'o' },
03995   { { STATE_INTERRUPT }, 'm' }
03996 };
03997 
03998 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
03999   { { 6 /* art */ }, 'm' }
04000 };
04001 
04002 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
04003   { { STATE_PSEXCM }, 'i' },
04004   { { STATE_PSRING }, 'i' },
04005   { { STATE_CCOMPARE1 }, 'm' },
04006   { { STATE_INTERRUPT }, 'm' }
04007 };
04008 
04009 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
04010   { { 6 /* art */ }, 'o' }
04011 };
04012 
04013 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
04014   { { STATE_PSEXCM }, 'i' },
04015   { { STATE_PSRING }, 'i' },
04016   { { STATE_CCOMPARE2 }, 'i' }
04017 };
04018 
04019 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
04020   { { 6 /* art */ }, 'i' }
04021 };
04022 
04023 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
04024   { { STATE_PSEXCM }, 'i' },
04025   { { STATE_PSRING }, 'i' },
04026   { { STATE_CCOMPARE2 }, 'o' },
04027   { { STATE_INTERRUPT }, 'm' }
04028 };
04029 
04030 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
04031   { { 6 /* art */ }, 'm' }
04032 };
04033 
04034 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
04035   { { STATE_PSEXCM }, 'i' },
04036   { { STATE_PSRING }, 'i' },
04037   { { STATE_CCOMPARE2 }, 'm' },
04038   { { STATE_INTERRUPT }, 'm' }
04039 };
04040 
04041 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
04042   { { 4 /* ars */ }, 'i' },
04043   { { 21 /* uimm8x4 */ }, 'i' }
04044 };
04045 
04046 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
04047   { { 4 /* ars */ }, 'i' },
04048   { { 21 /* uimm8x4 */ }, 'i' }
04049 };
04050 
04051 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
04052   { { STATE_PSEXCM }, 'i' },
04053   { { STATE_PSRING }, 'i' }
04054 };
04055 
04056 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
04057   { { 6 /* art */ }, 'o' },
04058   { { 4 /* ars */ }, 'i' }
04059 };
04060 
04061 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
04062   { { STATE_PSEXCM }, 'i' },
04063   { { STATE_PSRING }, 'i' }
04064 };
04065 
04066 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
04067   { { 6 /* art */ }, 'i' },
04068   { { 4 /* ars */ }, 'i' }
04069 };
04070 
04071 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
04072   { { STATE_PSEXCM }, 'i' },
04073   { { STATE_PSRING }, 'i' }
04074 };
04075 
04076 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
04077   { { 4 /* ars */ }, 'i' },
04078   { { 21 /* uimm8x4 */ }, 'i' }
04079 };
04080 
04081 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
04082   { { 4 /* ars */ }, 'i' },
04083   { { 22 /* uimm4x16 */ }, 'i' }
04084 };
04085 
04086 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
04087   { { STATE_PSEXCM }, 'i' },
04088   { { STATE_PSRING }, 'i' }
04089 };
04090 
04091 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
04092   { { 4 /* ars */ }, 'i' },
04093   { { 21 /* uimm8x4 */ }, 'i' }
04094 };
04095 
04096 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
04097   { { STATE_PSEXCM }, 'i' },
04098   { { STATE_PSRING }, 'i' }
04099 };
04100 
04101 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
04102   { { 4 /* ars */ }, 'i' },
04103   { { 21 /* uimm8x4 */ }, 'i' }
04104 };
04105 
04106 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
04107   { { 6 /* art */ }, 'i' },
04108   { { 4 /* ars */ }, 'i' }
04109 };
04110 
04111 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
04112   { { STATE_PSEXCM }, 'i' },
04113   { { STATE_PSRING }, 'i' }
04114 };
04115 
04116 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
04117   { { 6 /* art */ }, 'o' },
04118   { { 4 /* ars */ }, 'i' }
04119 };
04120 
04121 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
04122   { { STATE_PSEXCM }, 'i' },
04123   { { STATE_PSRING }, 'i' }
04124 };
04125 
04126 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
04127   { { 6 /* art */ }, 'i' }
04128 };
04129 
04130 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
04131   { { STATE_PSEXCM }, 'i' },
04132   { { STATE_PSRING }, 'i' },
04133   { { STATE_PTBASE }, 'o' },
04134   { { STATE_XTSYNC }, 'o' }
04135 };
04136 
04137 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
04138   { { 6 /* art */ }, 'o' }
04139 };
04140 
04141 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
04142   { { STATE_PSEXCM }, 'i' },
04143   { { STATE_PSRING }, 'i' },
04144   { { STATE_PTBASE }, 'i' },
04145   { { STATE_EXCVADDR }, 'i' }
04146 };
04147 
04148 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
04149   { { 6 /* art */ }, 'm' }
04150 };
04151 
04152 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
04153   { { STATE_PSEXCM }, 'i' },
04154   { { STATE_PSRING }, 'i' },
04155   { { STATE_PTBASE }, 'm' },
04156   { { STATE_EXCVADDR }, 'i' },
04157   { { STATE_XTSYNC }, 'o' }
04158 };
04159 
04160 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
04161   { { 6 /* art */ }, 'o' }
04162 };
04163 
04164 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
04165   { { STATE_PSEXCM }, 'i' },
04166   { { STATE_PSRING }, 'i' },
04167   { { STATE_ASID3 }, 'i' },
04168   { { STATE_ASID2 }, 'i' },
04169   { { STATE_ASID1 }, 'i' }
04170 };
04171 
04172 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
04173   { { 6 /* art */ }, 'i' }
04174 };
04175 
04176 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
04177   { { STATE_XTSYNC }, 'o' },
04178   { { STATE_PSEXCM }, 'i' },
04179   { { STATE_PSRING }, 'i' },
04180   { { STATE_ASID3 }, 'o' },
04181   { { STATE_ASID2 }, 'o' },
04182   { { STATE_ASID1 }, 'o' }
04183 };
04184 
04185 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
04186   { { 6 /* art */ }, 'm' }
04187 };
04188 
04189 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
04190   { { STATE_XTSYNC }, 'o' },
04191   { { STATE_PSEXCM }, 'i' },
04192   { { STATE_PSRING }, 'i' },
04193   { { STATE_ASID3 }, 'm' },
04194   { { STATE_ASID2 }, 'm' },
04195   { { STATE_ASID1 }, 'm' }
04196 };
04197 
04198 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
04199   { { 6 /* art */ }, 'o' }
04200 };
04201 
04202 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
04203   { { STATE_PSEXCM }, 'i' },
04204   { { STATE_PSRING }, 'i' },
04205   { { STATE_INSTPGSZID4 }, 'i' }
04206 };
04207 
04208 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
04209   { { 6 /* art */ }, 'i' }
04210 };
04211 
04212 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
04213   { { STATE_XTSYNC }, 'o' },
04214   { { STATE_PSEXCM }, 'i' },
04215   { { STATE_PSRING }, 'i' },
04216   { { STATE_INSTPGSZID4 }, 'o' }
04217 };
04218 
04219 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
04220   { { 6 /* art */ }, 'm' }
04221 };
04222 
04223 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
04224   { { STATE_XTSYNC }, 'o' },
04225   { { STATE_PSEXCM }, 'i' },
04226   { { STATE_PSRING }, 'i' },
04227   { { STATE_INSTPGSZID4 }, 'm' }
04228 };
04229 
04230 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
04231   { { 6 /* art */ }, 'o' }
04232 };
04233 
04234 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
04235   { { STATE_PSEXCM }, 'i' },
04236   { { STATE_PSRING }, 'i' },
04237   { { STATE_DATAPGSZID4 }, 'i' }
04238 };
04239 
04240 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
04241   { { 6 /* art */ }, 'i' }
04242 };
04243 
04244 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
04245   { { STATE_XTSYNC }, 'o' },
04246   { { STATE_PSEXCM }, 'i' },
04247   { { STATE_PSRING }, 'i' },
04248   { { STATE_DATAPGSZID4 }, 'o' }
04249 };
04250 
04251 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
04252   { { 6 /* art */ }, 'm' }
04253 };
04254 
04255 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
04256   { { STATE_XTSYNC }, 'o' },
04257   { { STATE_PSEXCM }, 'i' },
04258   { { STATE_PSRING }, 'i' },
04259   { { STATE_DATAPGSZID4 }, 'm' }
04260 };
04261 
04262 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
04263   { { 4 /* ars */ }, 'i' }
04264 };
04265 
04266 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
04267   { { STATE_PSEXCM }, 'i' },
04268   { { STATE_PSRING }, 'i' },
04269   { { STATE_XTSYNC }, 'o' }
04270 };
04271 
04272 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
04273   { { 6 /* art */ }, 'o' },
04274   { { 4 /* ars */ }, 'i' }
04275 };
04276 
04277 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
04278   { { STATE_PSEXCM }, 'i' },
04279   { { STATE_PSRING }, 'i' }
04280 };
04281 
04282 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
04283   { { 6 /* art */ }, 'i' },
04284   { { 4 /* ars */ }, 'i' }
04285 };
04286 
04287 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
04288   { { STATE_PSEXCM }, 'i' },
04289   { { STATE_PSRING }, 'i' },
04290   { { STATE_XTSYNC }, 'o' }
04291 };
04292 
04293 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
04294   { { 4 /* ars */ }, 'i' }
04295 };
04296 
04297 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
04298   { { STATE_PSEXCM }, 'i' },
04299   { { STATE_PSRING }, 'i' }
04300 };
04301 
04302 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
04303   { { 6 /* art */ }, 'o' },
04304   { { 4 /* ars */ }, 'i' }
04305 };
04306 
04307 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
04308   { { STATE_PSEXCM }, 'i' },
04309   { { STATE_PSRING }, 'i' }
04310 };
04311 
04312 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
04313   { { 6 /* art */ }, 'i' },
04314   { { 4 /* ars */ }, 'i' }
04315 };
04316 
04317 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
04318   { { STATE_PSEXCM }, 'i' },
04319   { { STATE_PSRING }, 'i' }
04320 };
04321 
04322 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
04323   { { STATE_PTBASE }, 'i' },
04324   { { STATE_EXCVADDR }, 'i' }
04325 };
04326 
04327 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
04328   { { STATE_EXCVADDR }, 'i' }
04329 };
04330 
04331 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
04332   { { STATE_EXCVADDR }, 'i' }
04333 };
04334 
04335 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
04336   { { 6 /* art */ }, 'o' },
04337   { { 4 /* ars */ }, 'i' }
04338 };
04339 
04340 static xtensa_iclass_internal iclasses[] = {
04341   { 0, 0 /* xt_iclass_excw */,
04342     0, 0, 0, 0 },
04343   { 0, 0 /* xt_iclass_rfe */,
04344     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
04345   { 0, 0 /* xt_iclass_rfde */,
04346     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
04347   { 0, 0 /* xt_iclass_syscall */,
04348     0, 0, 0, 0 },
04349   { 0, 0 /* xt_iclass_simcall */,
04350     0, 0, 0, 0 },
04351   { 2, Iclass_xt_iclass_call12_args,
04352     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
04353   { 2, Iclass_xt_iclass_call8_args,
04354     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
04355   { 2, Iclass_xt_iclass_call4_args,
04356     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
04357   { 2, Iclass_xt_iclass_callx12_args,
04358     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
04359   { 2, Iclass_xt_iclass_callx8_args,
04360     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
04361   { 2, Iclass_xt_iclass_callx4_args,
04362     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
04363   { 3, Iclass_xt_iclass_entry_args,
04364     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
04365   { 2, Iclass_xt_iclass_movsp_args,
04366     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
04367   { 1, Iclass_xt_iclass_rotw_args,
04368     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
04369   { 1, Iclass_xt_iclass_retw_args,
04370     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
04371   { 0, 0 /* xt_iclass_rfwou */,
04372     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
04373   { 3, Iclass_xt_iclass_l32e_args,
04374     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
04375   { 3, Iclass_xt_iclass_s32e_args,
04376     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
04377   { 1, Iclass_xt_iclass_rsr_windowbase_args,
04378     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
04379   { 1, Iclass_xt_iclass_wsr_windowbase_args,
04380     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
04381   { 1, Iclass_xt_iclass_xsr_windowbase_args,
04382     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
04383   { 1, Iclass_xt_iclass_rsr_windowstart_args,
04384     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
04385   { 1, Iclass_xt_iclass_wsr_windowstart_args,
04386     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
04387   { 1, Iclass_xt_iclass_xsr_windowstart_args,
04388     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
04389   { 3, Iclass_xt_iclass_add_n_args,
04390     0, 0, 0, 0 },
04391   { 3, Iclass_xt_iclass_addi_n_args,
04392     0, 0, 0, 0 },
04393   { 2, Iclass_xt_iclass_bz6_args,
04394     0, 0, 0, 0 },
04395   { 0, 0 /* xt_iclass_ill_n */,
04396     0, 0, 0, 0 },
04397   { 3, Iclass_xt_iclass_loadi4_args,
04398     0, 0, 0, 0 },
04399   { 2, Iclass_xt_iclass_mov_n_args,
04400     0, 0, 0, 0 },
04401   { 2, Iclass_xt_iclass_movi_n_args,
04402     0, 0, 0, 0 },
04403   { 0, 0 /* xt_iclass_nopn */,
04404     0, 0, 0, 0 },
04405   { 1, Iclass_xt_iclass_retn_args,
04406     0, 0, 0, 0 },
04407   { 3, Iclass_xt_iclass_storei4_args,
04408     0, 0, 0, 0 },
04409   { 3, Iclass_xt_iclass_addi_args,
04410     0, 0, 0, 0 },
04411   { 3, Iclass_xt_iclass_addmi_args,
04412     0, 0, 0, 0 },
04413   { 3, Iclass_xt_iclass_addsub_args,
04414     0, 0, 0, 0 },
04415   { 3, Iclass_xt_iclass_bit_args,
04416     0, 0, 0, 0 },
04417   { 3, Iclass_xt_iclass_bsi8_args,
04418     0, 0, 0, 0 },
04419   { 3, Iclass_xt_iclass_bsi8b_args,
04420     0, 0, 0, 0 },
04421   { 3, Iclass_xt_iclass_bsi8u_args,
04422     0, 0, 0, 0 },
04423   { 3, Iclass_xt_iclass_bst8_args,
04424     0, 0, 0, 0 },
04425   { 2, Iclass_xt_iclass_bsz12_args,
04426     0, 0, 0, 0 },
04427   { 2, Iclass_xt_iclass_call0_args,
04428     0, 0, 0, 0 },
04429   { 2, Iclass_xt_iclass_callx0_args,
04430     0, 0, 0, 0 },
04431   { 4, Iclass_xt_iclass_exti_args,
04432     0, 0, 0, 0 },
04433   { 0, 0 /* xt_iclass_ill */,
04434     0, 0, 0, 0 },
04435   { 1, Iclass_xt_iclass_jump_args,
04436     0, 0, 0, 0 },
04437   { 1, Iclass_xt_iclass_jumpx_args,
04438     0, 0, 0, 0 },
04439   { 3, Iclass_xt_iclass_l16ui_args,
04440     0, 0, 0, 0 },
04441   { 3, Iclass_xt_iclass_l16si_args,
04442     0, 0, 0, 0 },
04443   { 3, Iclass_xt_iclass_l32i_args,
04444     0, 0, 0, 0 },
04445   { 2, Iclass_xt_iclass_l32r_args,
04446     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
04447   { 3, Iclass_xt_iclass_l8i_args,
04448     0, 0, 0, 0 },
04449   { 2, Iclass_xt_iclass_loop_args,
04450     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
04451   { 2, Iclass_xt_iclass_loopz_args,
04452     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
04453   { 2, Iclass_xt_iclass_movi_args,
04454     0, 0, 0, 0 },
04455   { 3, Iclass_xt_iclass_movz_args,
04456     0, 0, 0, 0 },
04457   { 2, Iclass_xt_iclass_neg_args,
04458     0, 0, 0, 0 },
04459   { 0, 0 /* xt_iclass_nop */,
04460     0, 0, 0, 0 },
04461   { 1, Iclass_xt_iclass_return_args,
04462     0, 0, 0, 0 },
04463   { 3, Iclass_xt_iclass_s16i_args,
04464     0, 0, 0, 0 },
04465   { 3, Iclass_xt_iclass_s32i_args,
04466     0, 0, 0, 0 },
04467   { 3, Iclass_xt_iclass_s8i_args,
04468     0, 0, 0, 0 },
04469   { 1, Iclass_xt_iclass_sar_args,
04470     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
04471   { 1, Iclass_xt_iclass_sari_args,
04472     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
04473   { 2, Iclass_xt_iclass_shifts_args,
04474     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
04475   { 3, Iclass_xt_iclass_shiftst_args,
04476     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
04477   { 2, Iclass_xt_iclass_shiftt_args,
04478     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
04479   { 3, Iclass_xt_iclass_slli_args,
04480     0, 0, 0, 0 },
04481   { 3, Iclass_xt_iclass_srai_args,
04482     0, 0, 0, 0 },
04483   { 3, Iclass_xt_iclass_srli_args,
04484     0, 0, 0, 0 },
04485   { 0, 0 /* xt_iclass_memw */,
04486     0, 0, 0, 0 },
04487   { 0, 0 /* xt_iclass_extw */,
04488     0, 0, 0, 0 },
04489   { 0, 0 /* xt_iclass_isync */,
04490     0, 0, 0, 0 },
04491   { 0, 0 /* xt_iclass_sync */,
04492     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
04493   { 2, Iclass_xt_iclass_rsil_args,
04494     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
04495   { 1, Iclass_xt_iclass_rsr_lend_args,
04496     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
04497   { 1, Iclass_xt_iclass_wsr_lend_args,
04498     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
04499   { 1, Iclass_xt_iclass_xsr_lend_args,
04500     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
04501   { 1, Iclass_xt_iclass_rsr_lcount_args,
04502     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
04503   { 1, Iclass_xt_iclass_wsr_lcount_args,
04504     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
04505   { 1, Iclass_xt_iclass_xsr_lcount_args,
04506     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
04507   { 1, Iclass_xt_iclass_rsr_lbeg_args,
04508     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
04509   { 1, Iclass_xt_iclass_wsr_lbeg_args,
04510     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
04511   { 1, Iclass_xt_iclass_xsr_lbeg_args,
04512     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
04513   { 1, Iclass_xt_iclass_rsr_sar_args,
04514     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
04515   { 1, Iclass_xt_iclass_wsr_sar_args,
04516     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
04517   { 1, Iclass_xt_iclass_xsr_sar_args,
04518     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
04519   { 1, Iclass_xt_iclass_rsr_litbase_args,
04520     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
04521   { 1, Iclass_xt_iclass_wsr_litbase_args,
04522     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
04523   { 1, Iclass_xt_iclass_xsr_litbase_args,
04524     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
04525   { 1, Iclass_xt_iclass_rsr_176_args,
04526     2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
04527   { 1, Iclass_xt_iclass_rsr_208_args,
04528     2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
04529   { 1, Iclass_xt_iclass_rsr_ps_args,
04530     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
04531   { 1, Iclass_xt_iclass_wsr_ps_args,
04532     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
04533   { 1, Iclass_xt_iclass_xsr_ps_args,
04534     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
04535   { 1, Iclass_xt_iclass_rsr_epc1_args,
04536     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
04537   { 1, Iclass_xt_iclass_wsr_epc1_args,
04538     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
04539   { 1, Iclass_xt_iclass_xsr_epc1_args,
04540     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
04541   { 1, Iclass_xt_iclass_rsr_excsave1_args,
04542     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
04543   { 1, Iclass_xt_iclass_wsr_excsave1_args,
04544     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
04545   { 1, Iclass_xt_iclass_xsr_excsave1_args,
04546     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
04547   { 1, Iclass_xt_iclass_rsr_epc2_args,
04548     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
04549   { 1, Iclass_xt_iclass_wsr_epc2_args,
04550     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
04551   { 1, Iclass_xt_iclass_xsr_epc2_args,
04552     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
04553   { 1, Iclass_xt_iclass_rsr_excsave2_args,
04554     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
04555   { 1, Iclass_xt_iclass_wsr_excsave2_args,
04556     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
04557   { 1, Iclass_xt_iclass_xsr_excsave2_args,
04558     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
04559   { 1, Iclass_xt_iclass_rsr_epc3_args,
04560     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
04561   { 1, Iclass_xt_iclass_wsr_epc3_args,
04562     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
04563   { 1, Iclass_xt_iclass_xsr_epc3_args,
04564     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
04565   { 1, Iclass_xt_iclass_rsr_excsave3_args,
04566     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
04567   { 1, Iclass_xt_iclass_wsr_excsave3_args,
04568     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
04569   { 1, Iclass_xt_iclass_xsr_excsave3_args,
04570     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
04571   { 1, Iclass_xt_iclass_rsr_epc4_args,
04572     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
04573   { 1, Iclass_xt_iclass_wsr_epc4_args,
04574     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
04575   { 1, Iclass_xt_iclass_xsr_epc4_args,
04576     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
04577   { 1, Iclass_xt_iclass_rsr_excsave4_args,
04578     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
04579   { 1, Iclass_xt_iclass_wsr_excsave4_args,
04580     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
04581   { 1, Iclass_xt_iclass_xsr_excsave4_args,
04582     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
04583   { 1, Iclass_xt_iclass_rsr_eps2_args,
04584     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
04585   { 1, Iclass_xt_iclass_wsr_eps2_args,
04586     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
04587   { 1, Iclass_xt_iclass_xsr_eps2_args,
04588     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
04589   { 1, Iclass_xt_iclass_rsr_eps3_args,
04590     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
04591   { 1, Iclass_xt_iclass_wsr_eps3_args,
04592     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
04593   { 1, Iclass_xt_iclass_xsr_eps3_args,
04594     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
04595   { 1, Iclass_xt_iclass_rsr_eps4_args,
04596     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
04597   { 1, Iclass_xt_iclass_wsr_eps4_args,
04598     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
04599   { 1, Iclass_xt_iclass_xsr_eps4_args,
04600     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
04601   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
04602     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
04603   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
04604     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
04605   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
04606     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
04607   { 1, Iclass_xt_iclass_rsr_depc_args,
04608     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
04609   { 1, Iclass_xt_iclass_wsr_depc_args,
04610     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
04611   { 1, Iclass_xt_iclass_xsr_depc_args,
04612     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
04613   { 1, Iclass_xt_iclass_rsr_exccause_args,
04614     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
04615   { 1, Iclass_xt_iclass_wsr_exccause_args,
04616     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
04617   { 1, Iclass_xt_iclass_xsr_exccause_args,
04618     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
04619   { 1, Iclass_xt_iclass_rsr_misc0_args,
04620     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
04621   { 1, Iclass_xt_iclass_wsr_misc0_args,
04622     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
04623   { 1, Iclass_xt_iclass_xsr_misc0_args,
04624     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
04625   { 1, Iclass_xt_iclass_rsr_misc1_args,
04626     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
04627   { 1, Iclass_xt_iclass_wsr_misc1_args,
04628     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
04629   { 1, Iclass_xt_iclass_xsr_misc1_args,
04630     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
04631   { 1, Iclass_xt_iclass_rsr_prid_args,
04632     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
04633   { 1, Iclass_xt_iclass_rfi_args,
04634     15, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
04635   { 1, Iclass_xt_iclass_wait_args,
04636     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
04637   { 1, Iclass_xt_iclass_rsr_interrupt_args,
04638     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
04639   { 1, Iclass_xt_iclass_wsr_intset_args,
04640     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
04641   { 1, Iclass_xt_iclass_wsr_intclear_args,
04642     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
04643   { 1, Iclass_xt_iclass_rsr_intenable_args,
04644     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
04645   { 1, Iclass_xt_iclass_wsr_intenable_args,
04646     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
04647   { 1, Iclass_xt_iclass_xsr_intenable_args,
04648     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
04649   { 2, Iclass_xt_iclass_break_args,
04650     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
04651   { 1, Iclass_xt_iclass_break_n_args,
04652     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
04653   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
04654     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
04655   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
04656     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
04657   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
04658     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
04659   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
04660     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
04661   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
04662     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
04663   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
04664     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
04665   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
04666     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
04667   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
04668     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
04669   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
04670     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
04671   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
04672     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
04673   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
04674     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
04675   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
04676     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
04677   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
04678     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
04679   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
04680     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
04681   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
04682     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
04683   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
04684     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
04685   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
04686     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
04687   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
04688     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
04689   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
04690     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
04691   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
04692     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
04693   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
04694     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
04695   { 1, Iclass_xt_iclass_rsr_debugcause_args,
04696     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
04697   { 1, Iclass_xt_iclass_wsr_debugcause_args,
04698     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
04699   { 1, Iclass_xt_iclass_xsr_debugcause_args,
04700     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
04701   { 1, Iclass_xt_iclass_rsr_icount_args,
04702     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
04703   { 1, Iclass_xt_iclass_wsr_icount_args,
04704     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
04705   { 1, Iclass_xt_iclass_xsr_icount_args,
04706     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
04707   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
04708     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
04709   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
04710     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
04711   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
04712     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
04713   { 1, Iclass_xt_iclass_rsr_ddr_args,
04714     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
04715   { 1, Iclass_xt_iclass_wsr_ddr_args,
04716     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
04717   { 1, Iclass_xt_iclass_xsr_ddr_args,
04718     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
04719   { 0, 0 /* xt_iclass_rfdo */,
04720     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
04721   { 0, 0 /* xt_iclass_rfdd */,
04722     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
04723   { 1, Iclass_xt_iclass_rsr_ccount_args,
04724     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
04725   { 1, Iclass_xt_iclass_wsr_ccount_args,
04726     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
04727   { 1, Iclass_xt_iclass_xsr_ccount_args,
04728     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
04729   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
04730     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
04731   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
04732     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
04733   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
04734     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
04735   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
04736     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
04737   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
04738     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
04739   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
04740     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
04741   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
04742     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
04743   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
04744     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
04745   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
04746     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
04747   { 2, Iclass_xt_iclass_icache_args,
04748     0, 0, 0, 0 },
04749   { 2, Iclass_xt_iclass_icache_inv_args,
04750     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
04751   { 2, Iclass_xt_iclass_licx_args,
04752     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
04753   { 2, Iclass_xt_iclass_sicx_args,
04754     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
04755   { 2, Iclass_xt_iclass_dcache_args,
04756     0, 0, 0, 0 },
04757   { 2, Iclass_xt_iclass_dcache_ind_args,
04758     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
04759   { 2, Iclass_xt_iclass_dcache_inv_args,
04760     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
04761   { 2, Iclass_xt_iclass_dpf_args,
04762     0, 0, 0, 0 },
04763   { 2, Iclass_xt_iclass_sdct_args,
04764     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
04765   { 2, Iclass_xt_iclass_ldct_args,
04766     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
04767   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
04768     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
04769   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
04770     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
04771   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
04772     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
04773   { 1, Iclass_xt_iclass_rsr_rasid_args,
04774     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
04775   { 1, Iclass_xt_iclass_wsr_rasid_args,
04776     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
04777   { 1, Iclass_xt_iclass_xsr_rasid_args,
04778     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
04779   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
04780     3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
04781   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
04782     4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
04783   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
04784     4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
04785   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
04786     3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
04787   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
04788     4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
04789   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
04790     4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
04791   { 1, Iclass_xt_iclass_idtlb_args,
04792     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
04793   { 2, Iclass_xt_iclass_rdtlb_args,
04794     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
04795   { 2, Iclass_xt_iclass_wdtlb_args,
04796     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
04797   { 1, Iclass_xt_iclass_iitlb_args,
04798     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
04799   { 2, Iclass_xt_iclass_ritlb_args,
04800     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
04801   { 2, Iclass_xt_iclass_witlb_args,
04802     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
04803   { 0, 0 /* xt_iclass_ldpte */,
04804     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
04805   { 0, 0 /* xt_iclass_hwwitlba */,
04806     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
04807   { 0, 0 /* xt_iclass_hwwdtlba */,
04808     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
04809   { 2, Iclass_xt_iclass_nsa_args,
04810     0, 0, 0, 0 }
04811 };
04812 
04813 
04814 /*  Opcode encodings.  */
04815 
04816 static void
04817 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
04818 {
04819   slotbuf[0] = 0x80200;
04820 }
04821 
04822 static void
04823 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
04824 {
04825   slotbuf[0] = 0x300;
04826 }
04827 
04828 static void
04829 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
04830 {
04831   slotbuf[0] = 0x2300;
04832 }
04833 
04834 static void
04835 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
04836 {
04837   slotbuf[0] = 0x500;
04838 }
04839 
04840 static void
04841 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
04842 {
04843   slotbuf[0] = 0x1500;
04844 }
04845 
04846 static void
04847 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
04848 {
04849   slotbuf[0] = 0x5c0000;
04850 }
04851 
04852 static void
04853 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
04854 {
04855   slotbuf[0] = 0x580000;
04856 }
04857 
04858 static void
04859 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
04860 {
04861   slotbuf[0] = 0x540000;
04862 }
04863 
04864 static void
04865 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
04866 {
04867   slotbuf[0] = 0xf0000;
04868 }
04869 
04870 static void
04871 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
04872 {
04873   slotbuf[0] = 0xb0000;
04874 }
04875 
04876 static void
04877 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
04878 {
04879   slotbuf[0] = 0x70000;
04880 }
04881 
04882 static void
04883 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
04884 {
04885   slotbuf[0] = 0x6c0000;
04886 }
04887 
04888 static void
04889 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
04890 {
04891   slotbuf[0] = 0x100;
04892 }
04893 
04894 static void
04895 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
04896 {
04897   slotbuf[0] = 0x804;
04898 }
04899 
04900 static void
04901 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
04902 {
04903   slotbuf[0] = 0x60000;
04904 }
04905 
04906 static void
04907 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
04908 {
04909   slotbuf[0] = 0xd10f;
04910 }
04911 
04912 static void
04913 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
04914 {
04915   slotbuf[0] = 0x4300;
04916 }
04917 
04918 static void
04919 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
04920 {
04921   slotbuf[0] = 0x5300;
04922 }
04923 
04924 static void
04925 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
04926 {
04927   slotbuf[0] = 0x90;
04928 }
04929 
04930 static void
04931 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
04932 {
04933   slotbuf[0] = 0x94;
04934 }
04935 
04936 static void
04937 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
04938 {
04939   slotbuf[0] = 0x4830;
04940 }
04941 
04942 static void
04943 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
04944 {
04945   slotbuf[0] = 0x4831;
04946 }
04947 
04948 static void
04949 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
04950 {
04951   slotbuf[0] = 0x4816;
04952 }
04953 
04954 static void
04955 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
04956 {
04957   slotbuf[0] = 0x4930;
04958 }
04959 
04960 static void
04961 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
04962 {
04963   slotbuf[0] = 0x4931;
04964 }
04965 
04966 static void
04967 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
04968 {
04969   slotbuf[0] = 0x4916;
04970 }
04971 
04972 static void
04973 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
04974 {
04975   slotbuf[0] = 0xa000;
04976 }
04977 
04978 static void
04979 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
04980 {
04981   slotbuf[0] = 0xb000;
04982 }
04983 
04984 static void
04985 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
04986 {
04987   slotbuf[0] = 0xc800;
04988 }
04989 
04990 static void
04991 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
04992 {
04993   slotbuf[0] = 0xcc00;
04994 }
04995 
04996 static void
04997 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
04998 {
04999   slotbuf[0] = 0xd60f;
05000 }
05001 
05002 static void
05003 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
05004 {
05005   slotbuf[0] = 0x8000;
05006 }
05007 
05008 static void
05009 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
05010 {
05011   slotbuf[0] = 0xd000;
05012 }
05013 
05014 static void
05015 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
05016 {
05017   slotbuf[0] = 0xc000;
05018 }
05019 
05020 static void
05021 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
05022 {
05023   slotbuf[0] = 0xd30f;
05024 }
05025 
05026 static void
05027 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
05028 {
05029   slotbuf[0] = 0xd00f;
05030 }
05031 
05032 static void
05033 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
05034 {
05035   slotbuf[0] = 0x9000;
05036 }
05037 
05038 static void
05039 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
05040 {
05041   slotbuf[0] = 0x200c00;
05042 }
05043 
05044 static void
05045 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
05046 {
05047   slotbuf[0] = 0x200d00;
05048 }
05049 
05050 static void
05051 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
05052 {
05053   slotbuf[0] = 0x8;
05054 }
05055 
05056 static void
05057 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
05058 {
05059   slotbuf[0] = 0xc;
05060 }
05061 
05062 static void
05063 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05064 {
05065   slotbuf[0] = 0x9;
05066 }
05067 
05068 static void
05069 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05070 {
05071   slotbuf[0] = 0xa;
05072 }
05073 
05074 static void
05075 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
05076 {
05077   slotbuf[0] = 0xb;
05078 }
05079 
05080 static void
05081 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05082 {
05083   slotbuf[0] = 0xd;
05084 }
05085 
05086 static void
05087 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05088 {
05089   slotbuf[0] = 0xe;
05090 }
05091 
05092 static void
05093 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
05094 {
05095   slotbuf[0] = 0xf;
05096 }
05097 
05098 static void
05099 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
05100 {
05101   slotbuf[0] = 0x1;
05102 }
05103 
05104 static void
05105 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
05106 {
05107   slotbuf[0] = 0x2;
05108 }
05109 
05110 static void
05111 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
05112 {
05113   slotbuf[0] = 0x3;
05114 }
05115 
05116 static void
05117 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
05118 {
05119   slotbuf[0] = 0x680000;
05120 }
05121 
05122 static void
05123 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
05124 {
05125   slotbuf[0] = 0x690000;
05126 }
05127 
05128 static void
05129 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
05130 {
05131   slotbuf[0] = 0x6b0000;
05132 }
05133 
05134 static void
05135 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
05136 {
05137   slotbuf[0] = 0x6a0000;
05138 }
05139 
05140 static void
05141 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
05142 {
05143   slotbuf[0] = 0x700600;
05144 }
05145 
05146 static void
05147 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
05148 {
05149   slotbuf[0] = 0x700e00;
05150 }
05151 
05152 static void
05153 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
05154 {
05155   slotbuf[0] = 0x6f0000;
05156 }
05157 
05158 static void
05159 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
05160 {
05161   slotbuf[0] = 0x6e0000;
05162 }
05163 
05164 static void
05165 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
05166 {
05167   slotbuf[0] = 0x700100;
05168 }
05169 
05170 static void
05171 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
05172 {
05173   slotbuf[0] = 0x700900;
05174 }
05175 
05176 static void
05177 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
05178 {
05179   slotbuf[0] = 0x700a00;
05180 }
05181 
05182 static void
05183 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
05184 {
05185   slotbuf[0] = 0x700200;
05186 }
05187 
05188 static void
05189 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
05190 {
05191   slotbuf[0] = 0x700b00;
05192 }
05193 
05194 static void
05195 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
05196 {
05197   slotbuf[0] = 0x700300;
05198 }
05199 
05200 static void
05201 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
05202 {
05203   slotbuf[0] = 0x700800;
05204 }
05205 
05206 static void
05207 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
05208 {
05209   slotbuf[0] = 0x700000;
05210 }
05211 
05212 static void
05213 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
05214 {
05215   slotbuf[0] = 0x700400;
05216 }
05217 
05218 static void
05219 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
05220 {
05221   slotbuf[0] = 0x700c00;
05222 }
05223 
05224 static void
05225 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
05226 {
05227   slotbuf[0] = 0x700500;
05228 }
05229 
05230 static void
05231 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
05232 {
05233   slotbuf[0] = 0x700d00;
05234 }
05235 
05236 static void
05237 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
05238 {
05239   slotbuf[0] = 0x640000;
05240 }
05241 
05242 static void
05243 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
05244 {
05245   slotbuf[0] = 0x650000;
05246 }
05247 
05248 static void
05249 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
05250 {
05251   slotbuf[0] = 0x670000;
05252 }
05253 
05254 static void
05255 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
05256 {
05257   slotbuf[0] = 0x660000;
05258 }
05259 
05260 static void
05261 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
05262 {
05263   slotbuf[0] = 0x500000;
05264 }
05265 
05266 static void
05267 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
05268 {
05269   slotbuf[0] = 0x30000;
05270 }
05271 
05272 static void
05273 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
05274 {
05275   slotbuf[0] = 0x40;
05276 }
05277 
05278 static void
05279 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
05280 {
05281   slotbuf[0] = 0;
05282 }
05283 
05284 static void
05285 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
05286 {
05287   slotbuf[0] = 0x600000;
05288 }
05289 
05290 static void
05291 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
05292 {
05293   slotbuf[0] = 0xa0000;
05294 }
05295 
05296 static void
05297 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
05298 {
05299   slotbuf[0] = 0x200100;
05300 }
05301 
05302 static void
05303 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
05304 {
05305   slotbuf[0] = 0x200900;
05306 }
05307 
05308 static void
05309 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
05310 {
05311   slotbuf[0] = 0x200200;
05312 }
05313 
05314 static void
05315 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
05316 {
05317   slotbuf[0] = 0x100000;
05318 }
05319 
05320 static void
05321 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
05322 {
05323   slotbuf[0] = 0x200000;
05324 }
05325 
05326 static void
05327 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
05328 {
05329   slotbuf[0] = 0x6d0800;
05330 }
05331 
05332 static void
05333 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
05334 {
05335   slotbuf[0] = 0x6d0900;
05336 }
05337 
05338 static void
05339 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
05340 {
05341   slotbuf[0] = 0x6d0a00;
05342 }
05343 
05344 static void
05345 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
05346 {
05347   slotbuf[0] = 0x200a00;
05348 }
05349 
05350 static void
05351 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
05352 {
05353   slotbuf[0] = 0x38;
05354 }
05355 
05356 static void
05357 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
05358 {
05359   slotbuf[0] = 0x39;
05360 }
05361 
05362 static void
05363 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
05364 {
05365   slotbuf[0] = 0x3a;
05366 }
05367 
05368 static void
05369 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
05370 {
05371   slotbuf[0] = 0x3b;
05372 }
05373 
05374 static void
05375 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
05376 {
05377   slotbuf[0] = 0x6;
05378 }
05379 
05380 static void
05381 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
05382 {
05383   slotbuf[0] = 0x1006;
05384 }
05385 
05386 static void
05387 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
05388 {
05389   slotbuf[0] = 0xf0200;
05390 }
05391 
05392 static void
05393 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
05394 {
05395   slotbuf[0] = 0x20000;
05396 }
05397 
05398 static void
05399 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
05400 {
05401   slotbuf[0] = 0x200500;
05402 }
05403 
05404 static void
05405 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
05406 {
05407   slotbuf[0] = 0x200600;
05408 }
05409 
05410 static void
05411 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
05412 {
05413   slotbuf[0] = 0x200400;
05414 }
05415 
05416 static void
05417 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
05418 {
05419   slotbuf[0] = 0x4;
05420 }
05421 
05422 static void
05423 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
05424 {
05425   slotbuf[0] = 0x104;
05426 }
05427 
05428 static void
05429 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
05430 {
05431   slotbuf[0] = 0x204;
05432 }
05433 
05434 static void
05435 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
05436 {
05437   slotbuf[0] = 0x304;
05438 }
05439 
05440 static void
05441 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
05442 {
05443   slotbuf[0] = 0x404;
05444 }
05445 
05446 static void
05447 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
05448 {
05449   slotbuf[0] = 0x1a;
05450 }
05451 
05452 static void
05453 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
05454 {
05455   slotbuf[0] = 0x18;
05456 }
05457 
05458 static void
05459 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
05460 {
05461   slotbuf[0] = 0x19;
05462 }
05463 
05464 static void
05465 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
05466 {
05467   slotbuf[0] = 0x1b;
05468 }
05469 
05470 static void
05471 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
05472 {
05473   slotbuf[0] = 0x10;
05474 }
05475 
05476 static void
05477 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
05478 {
05479   slotbuf[0] = 0x12;
05480 }
05481 
05482 static void
05483 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
05484 {
05485   slotbuf[0] = 0x14;
05486 }
05487 
05488 static void
05489 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
05490 {
05491   slotbuf[0] = 0xc0200;
05492 }
05493 
05494 static void
05495 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
05496 {
05497   slotbuf[0] = 0xd0200;
05498 }
05499 
05500 static void
05501 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
05502 {
05503   slotbuf[0] = 0x200;
05504 }
05505 
05506 static void
05507 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
05508 {
05509   slotbuf[0] = 0x10200;
05510 }
05511 
05512 static void
05513 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
05514 {
05515   slotbuf[0] = 0x20200;
05516 }
05517 
05518 static void
05519 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
05520 {
05521   slotbuf[0] = 0x30200;
05522 }
05523 
05524 static void
05525 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
05526 {
05527   slotbuf[0] = 0x600;
05528 }
05529 
05530 static void
05531 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
05532 {
05533   slotbuf[0] = 0x130;
05534 }
05535 
05536 static void
05537 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
05538 {
05539   slotbuf[0] = 0x131;
05540 }
05541 
05542 static void
05543 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
05544 {
05545   slotbuf[0] = 0x116;
05546 }
05547 
05548 static void
05549 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
05550 {
05551   slotbuf[0] = 0x230;
05552 }
05553 
05554 static void
05555 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
05556 {
05557   slotbuf[0] = 0x231;
05558 }
05559 
05560 static void
05561 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
05562 {
05563   slotbuf[0] = 0x216;
05564 }
05565 
05566 static void
05567 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
05568 {
05569   slotbuf[0] = 0x30;
05570 }
05571 
05572 static void
05573 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
05574 {
05575   slotbuf[0] = 0x31;
05576 }
05577 
05578 static void
05579 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
05580 {
05581   slotbuf[0] = 0x16;
05582 }
05583 
05584 static void
05585 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
05586 {
05587   slotbuf[0] = 0x330;
05588 }
05589 
05590 static void
05591 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
05592 {
05593   slotbuf[0] = 0x331;
05594 }
05595 
05596 static void
05597 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
05598 {
05599   slotbuf[0] = 0x316;
05600 }
05601 
05602 static void
05603 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
05604 {
05605   slotbuf[0] = 0x530;
05606 }
05607 
05608 static void
05609 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
05610 {
05611   slotbuf[0] = 0x531;
05612 }
05613 
05614 static void
05615 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
05616 {
05617   slotbuf[0] = 0x516;
05618 }
05619 
05620 static void
05621 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
05622 {
05623   slotbuf[0] = 0xb030;
05624 }
05625 
05626 static void
05627 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
05628 {
05629   slotbuf[0] = 0xd030;
05630 }
05631 
05632 static void
05633 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
05634 {
05635   slotbuf[0] = 0xe630;
05636 }
05637 
05638 static void
05639 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
05640 {
05641   slotbuf[0] = 0xe631;
05642 }
05643 
05644 static void
05645 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
05646 {
05647   slotbuf[0] = 0xe616;
05648 }
05649 
05650 static void
05651 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05652 {
05653   slotbuf[0] = 0xb130;
05654 }
05655 
05656 static void
05657 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05658 {
05659   slotbuf[0] = 0xb131;
05660 }
05661 
05662 static void
05663 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05664 {
05665   slotbuf[0] = 0xb116;
05666 }
05667 
05668 static void
05669 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05670 {
05671   slotbuf[0] = 0xd130;
05672 }
05673 
05674 static void
05675 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05676 {
05677   slotbuf[0] = 0xd131;
05678 }
05679 
05680 static void
05681 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05682 {
05683   slotbuf[0] = 0xd116;
05684 }
05685 
05686 static void
05687 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05688 {
05689   slotbuf[0] = 0xb230;
05690 }
05691 
05692 static void
05693 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05694 {
05695   slotbuf[0] = 0xb231;
05696 }
05697 
05698 static void
05699 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05700 {
05701   slotbuf[0] = 0xb216;
05702 }
05703 
05704 static void
05705 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05706 {
05707   slotbuf[0] = 0xd230;
05708 }
05709 
05710 static void
05711 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05712 {
05713   slotbuf[0] = 0xd231;
05714 }
05715 
05716 static void
05717 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05718 {
05719   slotbuf[0] = 0xd216;
05720 }
05721 
05722 static void
05723 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05724 {
05725   slotbuf[0] = 0xb330;
05726 }
05727 
05728 static void
05729 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05730 {
05731   slotbuf[0] = 0xb331;
05732 }
05733 
05734 static void
05735 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05736 {
05737   slotbuf[0] = 0xb316;
05738 }
05739 
05740 static void
05741 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05742 {
05743   slotbuf[0] = 0xd330;
05744 }
05745 
05746 static void
05747 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05748 {
05749   slotbuf[0] = 0xd331;
05750 }
05751 
05752 static void
05753 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05754 {
05755   slotbuf[0] = 0xd316;
05756 }
05757 
05758 static void
05759 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05760 {
05761   slotbuf[0] = 0xb430;
05762 }
05763 
05764 static void
05765 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05766 {
05767   slotbuf[0] = 0xb431;
05768 }
05769 
05770 static void
05771 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05772 {
05773   slotbuf[0] = 0xb416;
05774 }
05775 
05776 static void
05777 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05778 {
05779   slotbuf[0] = 0xd430;
05780 }
05781 
05782 static void
05783 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05784 {
05785   slotbuf[0] = 0xd431;
05786 }
05787 
05788 static void
05789 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05790 {
05791   slotbuf[0] = 0xd416;
05792 }
05793 
05794 static void
05795 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05796 {
05797   slotbuf[0] = 0xc230;
05798 }
05799 
05800 static void
05801 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05802 {
05803   slotbuf[0] = 0xc231;
05804 }
05805 
05806 static void
05807 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
05808 {
05809   slotbuf[0] = 0xc216;
05810 }
05811 
05812 static void
05813 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05814 {
05815   slotbuf[0] = 0xc330;
05816 }
05817 
05818 static void
05819 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05820 {
05821   slotbuf[0] = 0xc331;
05822 }
05823 
05824 static void
05825 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
05826 {
05827   slotbuf[0] = 0xc316;
05828 }
05829 
05830 static void
05831 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05832 {
05833   slotbuf[0] = 0xc430;
05834 }
05835 
05836 static void
05837 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05838 {
05839   slotbuf[0] = 0xc431;
05840 }
05841 
05842 static void
05843 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
05844 {
05845   slotbuf[0] = 0xc416;
05846 }
05847 
05848 static void
05849 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
05850 {
05851   slotbuf[0] = 0xee30;
05852 }
05853 
05854 static void
05855 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
05856 {
05857   slotbuf[0] = 0xee31;
05858 }
05859 
05860 static void
05861 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
05862 {
05863   slotbuf[0] = 0xee16;
05864 }
05865 
05866 static void
05867 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
05868 {
05869   slotbuf[0] = 0xc030;
05870 }
05871 
05872 static void
05873 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
05874 {
05875   slotbuf[0] = 0xc031;
05876 }
05877 
05878 static void
05879 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
05880 {
05881   slotbuf[0] = 0xc016;
05882 }
05883 
05884 static void
05885 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
05886 {
05887   slotbuf[0] = 0xe830;
05888 }
05889 
05890 static void
05891 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
05892 {
05893   slotbuf[0] = 0xe831;
05894 }
05895 
05896 static void
05897 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
05898 {
05899   slotbuf[0] = 0xe816;
05900 }
05901 
05902 static void
05903 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
05904 {
05905   slotbuf[0] = 0xf430;
05906 }
05907 
05908 static void
05909 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
05910 {
05911   slotbuf[0] = 0xf431;
05912 }
05913 
05914 static void
05915 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
05916 {
05917   slotbuf[0] = 0xf416;
05918 }
05919 
05920 static void
05921 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05922 {
05923   slotbuf[0] = 0xf530;
05924 }
05925 
05926 static void
05927 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05928 {
05929   slotbuf[0] = 0xf531;
05930 }
05931 
05932 static void
05933 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
05934 {
05935   slotbuf[0] = 0xf516;
05936 }
05937 
05938 static void
05939 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
05940 {
05941   slotbuf[0] = 0xeb30;
05942 }
05943 
05944 static void
05945 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
05946 {
05947   slotbuf[0] = 0x10300;
05948 }
05949 
05950 static void
05951 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
05952 {
05953   slotbuf[0] = 0x700;
05954 }
05955 
05956 static void
05957 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
05958 {
05959   slotbuf[0] = 0xe230;
05960 }
05961 
05962 static void
05963 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
05964 {
05965   slotbuf[0] = 0xe231;
05966 }
05967 
05968 static void
05969 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
05970 {
05971   slotbuf[0] = 0xe331;
05972 }
05973 
05974 static void
05975 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
05976 {
05977   slotbuf[0] = 0xe430;
05978 }
05979 
05980 static void
05981 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
05982 {
05983   slotbuf[0] = 0xe431;
05984 }
05985 
05986 static void
05987 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
05988 {
05989   slotbuf[0] = 0xe416;
05990 }
05991 
05992 static void
05993 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
05994 {
05995   slotbuf[0] = 0x400;
05996 }
05997 
05998 static void
05999 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
06000 {
06001   slotbuf[0] = 0xd20f;
06002 }
06003 
06004 static void
06005 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06006 {
06007   slotbuf[0] = 0x9030;
06008 }
06009 
06010 static void
06011 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06012 {
06013   slotbuf[0] = 0x9031;
06014 }
06015 
06016 static void
06017 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06018 {
06019   slotbuf[0] = 0x9016;
06020 }
06021 
06022 static void
06023 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06024 {
06025   slotbuf[0] = 0xa030;
06026 }
06027 
06028 static void
06029 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06030 {
06031   slotbuf[0] = 0xa031;
06032 }
06033 
06034 static void
06035 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06036 {
06037   slotbuf[0] = 0xa016;
06038 }
06039 
06040 static void
06041 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06042 {
06043   slotbuf[0] = 0x9130;
06044 }
06045 
06046 static void
06047 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06048 {
06049   slotbuf[0] = 0x9131;
06050 }
06051 
06052 static void
06053 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06054 {
06055   slotbuf[0] = 0x9116;
06056 }
06057 
06058 static void
06059 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06060 {
06061   slotbuf[0] = 0xa130;
06062 }
06063 
06064 static void
06065 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06066 {
06067   slotbuf[0] = 0xa131;
06068 }
06069 
06070 static void
06071 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06072 {
06073   slotbuf[0] = 0xa116;
06074 }
06075 
06076 static void
06077 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06078 {
06079   slotbuf[0] = 0x8030;
06080 }
06081 
06082 static void
06083 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06084 {
06085   slotbuf[0] = 0x8031;
06086 }
06087 
06088 static void
06089 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06090 {
06091   slotbuf[0] = 0x8016;
06092 }
06093 
06094 static void
06095 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06096 {
06097   slotbuf[0] = 0x8130;
06098 }
06099 
06100 static void
06101 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06102 {
06103   slotbuf[0] = 0x8131;
06104 }
06105 
06106 static void
06107 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06108 {
06109   slotbuf[0] = 0x8116;
06110 }
06111 
06112 static void
06113 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
06114 {
06115   slotbuf[0] = 0x6030;
06116 }
06117 
06118 static void
06119 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
06120 {
06121   slotbuf[0] = 0x6031;
06122 }
06123 
06124 static void
06125 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
06126 {
06127   slotbuf[0] = 0x6016;
06128 }
06129 
06130 static void
06131 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
06132 {
06133   slotbuf[0] = 0xe930;
06134 }
06135 
06136 static void
06137 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
06138 {
06139   slotbuf[0] = 0xe931;
06140 }
06141 
06142 static void
06143 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
06144 {
06145   slotbuf[0] = 0xe916;
06146 }
06147 
06148 static void
06149 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
06150 {
06151   slotbuf[0] = 0xec30;
06152 }
06153 
06154 static void
06155 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
06156 {
06157   slotbuf[0] = 0xec31;
06158 }
06159 
06160 static void
06161 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
06162 {
06163   slotbuf[0] = 0xec16;
06164 }
06165 
06166 static void
06167 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
06168 {
06169   slotbuf[0] = 0xed30;
06170 }
06171 
06172 static void
06173 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
06174 {
06175   slotbuf[0] = 0xed31;
06176 }
06177 
06178 static void
06179 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
06180 {
06181   slotbuf[0] = 0xed16;
06182 }
06183 
06184 static void
06185 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06186 {
06187   slotbuf[0] = 0x6830;
06188 }
06189 
06190 static void
06191 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06192 {
06193   slotbuf[0] = 0x6831;
06194 }
06195 
06196 static void
06197 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06198 {
06199   slotbuf[0] = 0x6816;
06200 }
06201 
06202 static void
06203 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
06204 {
06205   slotbuf[0] = 0xe1f;
06206 }
06207 
06208 static void
06209 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
06210 {
06211   slotbuf[0] = 0x10e1f;
06212 }
06213 
06214 static void
06215 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
06216 {
06217   slotbuf[0] = 0xea30;
06218 }
06219 
06220 static void
06221 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
06222 {
06223   slotbuf[0] = 0xea31;
06224 }
06225 
06226 static void
06227 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
06228 {
06229   slotbuf[0] = 0xea16;
06230 }
06231 
06232 static void
06233 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06234 {
06235   slotbuf[0] = 0xf030;
06236 }
06237 
06238 static void
06239 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06240 {
06241   slotbuf[0] = 0xf031;
06242 }
06243 
06244 static void
06245 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06246 {
06247   slotbuf[0] = 0xf016;
06248 }
06249 
06250 static void
06251 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06252 {
06253   slotbuf[0] = 0xf130;
06254 }
06255 
06256 static void
06257 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06258 {
06259   slotbuf[0] = 0xf131;
06260 }
06261 
06262 static void
06263 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06264 {
06265   slotbuf[0] = 0xf116;
06266 }
06267 
06268 static void
06269 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
06270 {
06271   slotbuf[0] = 0xf230;
06272 }
06273 
06274 static void
06275 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
06276 {
06277   slotbuf[0] = 0xf231;
06278 }
06279 
06280 static void
06281 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
06282 {
06283   slotbuf[0] = 0xf216;
06284 }
06285 
06286 static void
06287 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
06288 {
06289   slotbuf[0] = 0x2c0700;
06290 }
06291 
06292 static void
06293 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
06294 {
06295   slotbuf[0] = 0x2e0700;
06296 }
06297 
06298 static void
06299 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
06300 {
06301   slotbuf[0] = 0x2f0700;
06302 }
06303 
06304 static void
06305 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
06306 {
06307   slotbuf[0] = 0x1f;
06308 }
06309 
06310 static void
06311 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
06312 {
06313   slotbuf[0] = 0x21f;
06314 }
06315 
06316 static void
06317 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
06318 {
06319   slotbuf[0] = 0x11f;
06320 }
06321 
06322 static void
06323 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
06324 {
06325   slotbuf[0] = 0x31f;
06326 }
06327 
06328 static void
06329 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06330 {
06331   slotbuf[0] = 0x240700;
06332 }
06333 
06334 static void
06335 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
06336 {
06337   slotbuf[0] = 0x250700;
06338 }
06339 
06340 static void
06341 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06342 {
06343   slotbuf[0] = 0x280740;
06344 }
06345 
06346 static void
06347 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
06348 {
06349   slotbuf[0] = 0x280750;
06350 }
06351 
06352 static void
06353 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
06354 {
06355   slotbuf[0] = 0x260700;
06356 }
06357 
06358 static void
06359 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
06360 {
06361   slotbuf[0] = 0x270700;
06362 }
06363 
06364 static void
06365 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06366 {
06367   slotbuf[0] = 0x200700;
06368 }
06369 
06370 static void
06371 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
06372 {
06373   slotbuf[0] = 0x210700;
06374 }
06375 
06376 static void
06377 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
06378 {
06379   slotbuf[0] = 0x220700;
06380 }
06381 
06382 static void
06383 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
06384 {
06385   slotbuf[0] = 0x230700;
06386 }
06387 
06388 static void
06389 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
06390 {
06391   slotbuf[0] = 0x91f;
06392 }
06393 
06394 static void
06395 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
06396 {
06397   slotbuf[0] = 0x81f;
06398 }
06399 
06400 static void
06401 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06402 {
06403   slotbuf[0] = 0x5331;
06404 }
06405 
06406 static void
06407 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06408 {
06409   slotbuf[0] = 0x5330;
06410 }
06411 
06412 static void
06413 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
06414 {
06415   slotbuf[0] = 0x5316;
06416 }
06417 
06418 static void
06419 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
06420 {
06421   slotbuf[0] = 0x5a30;
06422 }
06423 
06424 static void
06425 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
06426 {
06427   slotbuf[0] = 0x5a31;
06428 }
06429 
06430 static void
06431 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
06432 {
06433   slotbuf[0] = 0x5a16;
06434 }
06435 
06436 static void
06437 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
06438 {
06439   slotbuf[0] = 0x5b30;
06440 }
06441 
06442 static void
06443 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
06444 {
06445   slotbuf[0] = 0x5b31;
06446 }
06447 
06448 static void
06449 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
06450 {
06451   slotbuf[0] = 0x5b16;
06452 }
06453 
06454 static void
06455 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
06456 {
06457   slotbuf[0] = 0x5c30;
06458 }
06459 
06460 static void
06461 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
06462 {
06463   slotbuf[0] = 0x5c31;
06464 }
06465 
06466 static void
06467 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
06468 {
06469   slotbuf[0] = 0x5c16;
06470 }
06471 
06472 static void
06473 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06474 {
06475   slotbuf[0] = 0xc05;
06476 }
06477 
06478 static void
06479 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06480 {
06481   slotbuf[0] = 0xd05;
06482 }
06483 
06484 static void
06485 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06486 {
06487   slotbuf[0] = 0xb05;
06488 }
06489 
06490 static void
06491 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06492 {
06493   slotbuf[0] = 0xf05;
06494 }
06495 
06496 static void
06497 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06498 {
06499   slotbuf[0] = 0xe05;
06500 }
06501 
06502 static void
06503 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06504 {
06505   slotbuf[0] = 0x405;
06506 }
06507 
06508 static void
06509 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06510 {
06511   slotbuf[0] = 0x505;
06512 }
06513 
06514 static void
06515 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
06516 {
06517   slotbuf[0] = 0x305;
06518 }
06519 
06520 static void
06521 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
06522 {
06523   slotbuf[0] = 0x705;
06524 }
06525 
06526 static void
06527 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
06528 {
06529   slotbuf[0] = 0x605;
06530 }
06531 
06532 static void
06533 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
06534 {
06535   slotbuf[0] = 0xf1f;
06536 }
06537 
06538 static void
06539 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
06540 {
06541   slotbuf[0] = 0x105;
06542 }
06543 
06544 static void
06545 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
06546 {
06547   slotbuf[0] = 0x905;
06548 }
06549 
06550 static void
06551 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
06552 {
06553   slotbuf[0] = 0xe04;
06554 }
06555 
06556 static void
06557 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
06558 {
06559   slotbuf[0] = 0xf04;
06560 }
06561 
06562 xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
06563   Opcode_excw_Slot_inst_encode, 0, 0
06564 };
06565 
06566 xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
06567   Opcode_rfe_Slot_inst_encode, 0, 0
06568 };
06569 
06570 xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
06571   Opcode_rfde_Slot_inst_encode, 0, 0
06572 };
06573 
06574 xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
06575   Opcode_syscall_Slot_inst_encode, 0, 0
06576 };
06577 
06578 xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
06579   Opcode_simcall_Slot_inst_encode, 0, 0
06580 };
06581 
06582 xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
06583   Opcode_call12_Slot_inst_encode, 0, 0
06584 };
06585 
06586 xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
06587   Opcode_call8_Slot_inst_encode, 0, 0
06588 };
06589 
06590 xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
06591   Opcode_call4_Slot_inst_encode, 0, 0
06592 };
06593 
06594 xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
06595   Opcode_callx12_Slot_inst_encode, 0, 0
06596 };
06597 
06598 xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
06599   Opcode_callx8_Slot_inst_encode, 0, 0
06600 };
06601 
06602 xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
06603   Opcode_callx4_Slot_inst_encode, 0, 0
06604 };
06605 
06606 xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
06607   Opcode_entry_Slot_inst_encode, 0, 0
06608 };
06609 
06610 xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
06611   Opcode_movsp_Slot_inst_encode, 0, 0
06612 };
06613 
06614 xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
06615   Opcode_rotw_Slot_inst_encode, 0, 0
06616 };
06617 
06618 xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
06619   Opcode_retw_Slot_inst_encode, 0, 0
06620 };
06621 
06622 xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
06623   0, 0, Opcode_retw_n_Slot_inst16b_encode
06624 };
06625 
06626 xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
06627   Opcode_rfwo_Slot_inst_encode, 0, 0
06628 };
06629 
06630 xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
06631   Opcode_rfwu_Slot_inst_encode, 0, 0
06632 };
06633 
06634 xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
06635   Opcode_l32e_Slot_inst_encode, 0, 0
06636 };
06637 
06638 xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
06639   Opcode_s32e_Slot_inst_encode, 0, 0
06640 };
06641 
06642 xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
06643   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
06644 };
06645 
06646 xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
06647   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
06648 };
06649 
06650 xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
06651   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
06652 };
06653 
06654 xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
06655   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
06656 };
06657 
06658 xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
06659   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
06660 };
06661 
06662 xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
06663   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
06664 };
06665 
06666 xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
06667   0, Opcode_add_n_Slot_inst16a_encode, 0
06668 };
06669 
06670 xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
06671   0, Opcode_addi_n_Slot_inst16a_encode, 0
06672 };
06673 
06674 xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
06675   0, 0, Opcode_beqz_n_Slot_inst16b_encode
06676 };
06677 
06678 xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
06679   0, 0, Opcode_bnez_n_Slot_inst16b_encode
06680 };
06681 
06682 xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
06683   0, 0, Opcode_ill_n_Slot_inst16b_encode
06684 };
06685 
06686 xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
06687   0, Opcode_l32i_n_Slot_inst16a_encode, 0
06688 };
06689 
06690 xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
06691   0, 0, Opcode_mov_n_Slot_inst16b_encode
06692 };
06693 
06694 xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
06695   0, 0, Opcode_movi_n_Slot_inst16b_encode
06696 };
06697 
06698 xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
06699   0, 0, Opcode_nop_n_Slot_inst16b_encode
06700 };
06701 
06702 xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
06703   0, 0, Opcode_ret_n_Slot_inst16b_encode
06704 };
06705 
06706 xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
06707   0, Opcode_s32i_n_Slot_inst16a_encode, 0
06708 };
06709 
06710 xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
06711   Opcode_addi_Slot_inst_encode, 0, 0
06712 };
06713 
06714 xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
06715   Opcode_addmi_Slot_inst_encode, 0, 0
06716 };
06717 
06718 xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
06719   Opcode_add_Slot_inst_encode, 0, 0
06720 };
06721 
06722 xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
06723   Opcode_sub_Slot_inst_encode, 0, 0
06724 };
06725 
06726 xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
06727   Opcode_addx2_Slot_inst_encode, 0, 0
06728 };
06729 
06730 xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
06731   Opcode_addx4_Slot_inst_encode, 0, 0
06732 };
06733 
06734 xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
06735   Opcode_addx8_Slot_inst_encode, 0, 0
06736 };
06737 
06738 xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
06739   Opcode_subx2_Slot_inst_encode, 0, 0
06740 };
06741 
06742 xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
06743   Opcode_subx4_Slot_inst_encode, 0, 0
06744 };
06745 
06746 xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
06747   Opcode_subx8_Slot_inst_encode, 0, 0
06748 };
06749 
06750 xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
06751   Opcode_and_Slot_inst_encode, 0, 0
06752 };
06753 
06754 xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
06755   Opcode_or_Slot_inst_encode, 0, 0
06756 };
06757 
06758 xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
06759   Opcode_xor_Slot_inst_encode, 0, 0
06760 };
06761 
06762 xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
06763   Opcode_beqi_Slot_inst_encode, 0, 0
06764 };
06765 
06766 xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
06767   Opcode_bnei_Slot_inst_encode, 0, 0
06768 };
06769 
06770 xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
06771   Opcode_bgei_Slot_inst_encode, 0, 0
06772 };
06773 
06774 xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
06775   Opcode_blti_Slot_inst_encode, 0, 0
06776 };
06777 
06778 xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
06779   Opcode_bbci_Slot_inst_encode, 0, 0
06780 };
06781 
06782 xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
06783   Opcode_bbsi_Slot_inst_encode, 0, 0
06784 };
06785 
06786 xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
06787   Opcode_bgeui_Slot_inst_encode, 0, 0
06788 };
06789 
06790 xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
06791   Opcode_bltui_Slot_inst_encode, 0, 0
06792 };
06793 
06794 xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
06795   Opcode_beq_Slot_inst_encode, 0, 0
06796 };
06797 
06798 xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
06799   Opcode_bne_Slot_inst_encode, 0, 0
06800 };
06801 
06802 xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
06803   Opcode_bge_Slot_inst_encode, 0, 0
06804 };
06805 
06806 xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
06807   Opcode_blt_Slot_inst_encode, 0, 0
06808 };
06809 
06810 xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
06811   Opcode_bgeu_Slot_inst_encode, 0, 0
06812 };
06813 
06814 xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
06815   Opcode_bltu_Slot_inst_encode, 0, 0
06816 };
06817 
06818 xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
06819   Opcode_bany_Slot_inst_encode, 0, 0
06820 };
06821 
06822 xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
06823   Opcode_bnone_Slot_inst_encode, 0, 0
06824 };
06825 
06826 xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
06827   Opcode_ball_Slot_inst_encode, 0, 0
06828 };
06829 
06830 xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
06831   Opcode_bnall_Slot_inst_encode, 0, 0
06832 };
06833 
06834 xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
06835   Opcode_bbc_Slot_inst_encode, 0, 0
06836 };
06837 
06838 xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
06839   Opcode_bbs_Slot_inst_encode, 0, 0
06840 };
06841 
06842 xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
06843   Opcode_beqz_Slot_inst_encode, 0, 0
06844 };
06845 
06846 xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
06847   Opcode_bnez_Slot_inst_encode, 0, 0
06848 };
06849 
06850 xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
06851   Opcode_bgez_Slot_inst_encode, 0, 0
06852 };
06853 
06854 xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
06855   Opcode_bltz_Slot_inst_encode, 0, 0
06856 };
06857 
06858 xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
06859   Opcode_call0_Slot_inst_encode, 0, 0
06860 };
06861 
06862 xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
06863   Opcode_callx0_Slot_inst_encode, 0, 0
06864 };
06865 
06866 xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
06867   Opcode_extui_Slot_inst_encode, 0, 0
06868 };
06869 
06870 xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
06871   Opcode_ill_Slot_inst_encode, 0, 0
06872 };
06873 
06874 xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
06875   Opcode_j_Slot_inst_encode, 0, 0
06876 };
06877 
06878 xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
06879   Opcode_jx_Slot_inst_encode, 0, 0
06880 };
06881 
06882 xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
06883   Opcode_l16ui_Slot_inst_encode, 0, 0
06884 };
06885 
06886 xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
06887   Opcode_l16si_Slot_inst_encode, 0, 0
06888 };
06889 
06890 xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
06891   Opcode_l32i_Slot_inst_encode, 0, 0
06892 };
06893 
06894 xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
06895   Opcode_l32r_Slot_inst_encode, 0, 0
06896 };
06897 
06898 xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
06899   Opcode_l8ui_Slot_inst_encode, 0, 0
06900 };
06901 
06902 xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
06903   Opcode_loop_Slot_inst_encode, 0, 0
06904 };
06905 
06906 xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
06907   Opcode_loopnez_Slot_inst_encode, 0, 0
06908 };
06909 
06910 xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
06911   Opcode_loopgtz_Slot_inst_encode, 0, 0
06912 };
06913 
06914 xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
06915   Opcode_movi_Slot_inst_encode, 0, 0
06916 };
06917 
06918 xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
06919   Opcode_moveqz_Slot_inst_encode, 0, 0
06920 };
06921 
06922 xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
06923   Opcode_movnez_Slot_inst_encode, 0, 0
06924 };
06925 
06926 xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
06927   Opcode_movltz_Slot_inst_encode, 0, 0
06928 };
06929 
06930 xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
06931   Opcode_movgez_Slot_inst_encode, 0, 0
06932 };
06933 
06934 xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
06935   Opcode_neg_Slot_inst_encode, 0, 0
06936 };
06937 
06938 xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
06939   Opcode_abs_Slot_inst_encode, 0, 0
06940 };
06941 
06942 xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
06943   Opcode_nop_Slot_inst_encode, 0, 0
06944 };
06945 
06946 xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
06947   Opcode_ret_Slot_inst_encode, 0, 0
06948 };
06949 
06950 xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
06951   Opcode_s16i_Slot_inst_encode, 0, 0
06952 };
06953 
06954 xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
06955   Opcode_s32i_Slot_inst_encode, 0, 0
06956 };
06957 
06958 xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
06959   Opcode_s8i_Slot_inst_encode, 0, 0
06960 };
06961 
06962 xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
06963   Opcode_ssr_Slot_inst_encode, 0, 0
06964 };
06965 
06966 xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
06967   Opcode_ssl_Slot_inst_encode, 0, 0
06968 };
06969 
06970 xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
06971   Opcode_ssa8l_Slot_inst_encode, 0, 0
06972 };
06973 
06974 xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
06975   Opcode_ssa8b_Slot_inst_encode, 0, 0
06976 };
06977 
06978 xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
06979   Opcode_ssai_Slot_inst_encode, 0, 0
06980 };
06981 
06982 xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
06983   Opcode_sll_Slot_inst_encode, 0, 0
06984 };
06985 
06986 xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
06987   Opcode_src_Slot_inst_encode, 0, 0
06988 };
06989 
06990 xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
06991   Opcode_srl_Slot_inst_encode, 0, 0
06992 };
06993 
06994 xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
06995   Opcode_sra_Slot_inst_encode, 0, 0
06996 };
06997 
06998 xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
06999   Opcode_slli_Slot_inst_encode, 0, 0
07000 };
07001 
07002 xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
07003   Opcode_srai_Slot_inst_encode, 0, 0
07004 };
07005 
07006 xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
07007   Opcode_srli_Slot_inst_encode, 0, 0
07008 };
07009 
07010 xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
07011   Opcode_memw_Slot_inst_encode, 0, 0
07012 };
07013 
07014 xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
07015   Opcode_extw_Slot_inst_encode, 0, 0
07016 };
07017 
07018 xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
07019   Opcode_isync_Slot_inst_encode, 0, 0
07020 };
07021 
07022 xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
07023   Opcode_rsync_Slot_inst_encode, 0, 0
07024 };
07025 
07026 xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
07027   Opcode_esync_Slot_inst_encode, 0, 0
07028 };
07029 
07030 xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
07031   Opcode_dsync_Slot_inst_encode, 0, 0
07032 };
07033 
07034 xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
07035   Opcode_rsil_Slot_inst_encode, 0, 0
07036 };
07037 
07038 xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
07039   Opcode_rsr_lend_Slot_inst_encode, 0, 0
07040 };
07041 
07042 xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
07043   Opcode_wsr_lend_Slot_inst_encode, 0, 0
07044 };
07045 
07046 xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
07047   Opcode_xsr_lend_Slot_inst_encode, 0, 0
07048 };
07049 
07050 xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
07051   Opcode_rsr_lcount_Slot_inst_encode, 0, 0
07052 };
07053 
07054 xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
07055   Opcode_wsr_lcount_Slot_inst_encode, 0, 0
07056 };
07057 
07058 xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
07059   Opcode_xsr_lcount_Slot_inst_encode, 0, 0
07060 };
07061 
07062 xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
07063   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
07064 };
07065 
07066 xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
07067   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
07068 };
07069 
07070 xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
07071   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
07072 };
07073 
07074 xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
07075   Opcode_rsr_sar_Slot_inst_encode, 0, 0
07076 };
07077 
07078 xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
07079   Opcode_wsr_sar_Slot_inst_encode, 0, 0
07080 };
07081 
07082 xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
07083   Opcode_xsr_sar_Slot_inst_encode, 0, 0
07084 };
07085 
07086 xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
07087   Opcode_rsr_litbase_Slot_inst_encode, 0, 0
07088 };
07089 
07090 xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
07091   Opcode_wsr_litbase_Slot_inst_encode, 0, 0
07092 };
07093 
07094 xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
07095   Opcode_xsr_litbase_Slot_inst_encode, 0, 0
07096 };
07097 
07098 xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
07099   Opcode_rsr_176_Slot_inst_encode, 0, 0
07100 };
07101 
07102 xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
07103   Opcode_rsr_208_Slot_inst_encode, 0, 0
07104 };
07105 
07106 xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
07107   Opcode_rsr_ps_Slot_inst_encode, 0, 0
07108 };
07109 
07110 xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
07111   Opcode_wsr_ps_Slot_inst_encode, 0, 0
07112 };
07113 
07114 xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
07115   Opcode_xsr_ps_Slot_inst_encode, 0, 0
07116 };
07117 
07118 xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
07119   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
07120 };
07121 
07122 xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
07123   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
07124 };
07125 
07126 xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
07127   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
07128 };
07129 
07130 xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
07131   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
07132 };
07133 
07134 xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
07135   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
07136 };
07137 
07138 xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
07139   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
07140 };
07141 
07142 xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
07143   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
07144 };
07145 
07146 xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
07147   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
07148 };
07149 
07150 xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
07151   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
07152 };
07153 
07154 xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
07155   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
07156 };
07157 
07158 xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
07159   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
07160 };
07161 
07162 xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
07163   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
07164 };
07165 
07166 xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
07167   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
07168 };
07169 
07170 xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
07171   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
07172 };
07173 
07174 xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
07175   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
07176 };
07177 
07178 xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
07179   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
07180 };
07181 
07182 xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
07183   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
07184 };
07185 
07186 xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
07187   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
07188 };
07189 
07190 xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
07191   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
07192 };
07193 
07194 xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
07195   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
07196 };
07197 
07198 xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
07199   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
07200 };
07201 
07202 xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
07203   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
07204 };
07205 
07206 xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
07207   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
07208 };
07209 
07210 xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
07211   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
07212 };
07213 
07214 xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
07215   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
07216 };
07217 
07218 xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
07219   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
07220 };
07221 
07222 xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
07223   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
07224 };
07225 
07226 xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
07227   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
07228 };
07229 
07230 xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
07231   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
07232 };
07233 
07234 xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
07235   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
07236 };
07237 
07238 xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
07239   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
07240 };
07241 
07242 xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
07243   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
07244 };
07245 
07246 xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
07247   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
07248 };
07249 
07250 xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
07251   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
07252 };
07253 
07254 xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
07255   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
07256 };
07257 
07258 xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
07259   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
07260 };
07261 
07262 xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
07263   Opcode_rsr_depc_Slot_inst_encode, 0, 0
07264 };
07265 
07266 xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
07267   Opcode_wsr_depc_Slot_inst_encode, 0, 0
07268 };
07269 
07270 xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
07271   Opcode_xsr_depc_Slot_inst_encode, 0, 0
07272 };
07273 
07274 xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
07275   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
07276 };
07277 
07278 xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
07279   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
07280 };
07281 
07282 xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
07283   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
07284 };
07285 
07286 xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
07287   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
07288 };
07289 
07290 xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
07291   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
07292 };
07293 
07294 xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
07295   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
07296 };
07297 
07298 xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
07299   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
07300 };
07301 
07302 xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
07303   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
07304 };
07305 
07306 xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
07307   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
07308 };
07309 
07310 xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
07311   Opcode_rsr_prid_Slot_inst_encode, 0, 0
07312 };
07313 
07314 xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
07315   Opcode_rfi_Slot_inst_encode, 0, 0
07316 };
07317 
07318 xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
07319   Opcode_waiti_Slot_inst_encode, 0, 0
07320 };
07321 
07322 xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
07323   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
07324 };
07325 
07326 xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
07327   Opcode_wsr_intset_Slot_inst_encode, 0, 0
07328 };
07329 
07330 xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
07331   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
07332 };
07333 
07334 xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
07335   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
07336 };
07337 
07338 xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
07339   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
07340 };
07341 
07342 xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
07343   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
07344 };
07345 
07346 xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
07347   Opcode_break_Slot_inst_encode, 0, 0
07348 };
07349 
07350 xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
07351   0, 0, Opcode_break_n_Slot_inst16b_encode
07352 };
07353 
07354 xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
07355   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
07356 };
07357 
07358 xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
07359   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
07360 };
07361 
07362 xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
07363   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
07364 };
07365 
07366 xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
07367   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
07368 };
07369 
07370 xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
07371   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
07372 };
07373 
07374 xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
07375   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
07376 };
07377 
07378 xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
07379   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
07380 };
07381 
07382 xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
07383   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
07384 };
07385 
07386 xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
07387   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
07388 };
07389 
07390 xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
07391   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
07392 };
07393 
07394 xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
07395   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
07396 };
07397 
07398 xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
07399   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
07400 };
07401 
07402 xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
07403   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
07404 };
07405 
07406 xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
07407   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
07408 };
07409 
07410 xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
07411   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
07412 };
07413 
07414 xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
07415   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
07416 };
07417 
07418 xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
07419   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
07420 };
07421 
07422 xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
07423   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
07424 };
07425 
07426 xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
07427   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
07428 };
07429 
07430 xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
07431   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
07432 };
07433 
07434 xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
07435   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
07436 };
07437 
07438 xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
07439   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
07440 };
07441 
07442 xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
07443   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
07444 };
07445 
07446 xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
07447   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
07448 };
07449 
07450 xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
07451   Opcode_rsr_icount_Slot_inst_encode, 0, 0
07452 };
07453 
07454 xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
07455   Opcode_wsr_icount_Slot_inst_encode, 0, 0
07456 };
07457 
07458 xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
07459   Opcode_xsr_icount_Slot_inst_encode, 0, 0
07460 };
07461 
07462 xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
07463   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
07464 };
07465 
07466 xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
07467   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
07468 };
07469 
07470 xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
07471   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
07472 };
07473 
07474 xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
07475   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
07476 };
07477 
07478 xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
07479   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
07480 };
07481 
07482 xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
07483   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
07484 };
07485 
07486 xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
07487   Opcode_rfdo_Slot_inst_encode, 0, 0
07488 };
07489 
07490 xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
07491   Opcode_rfdd_Slot_inst_encode, 0, 0
07492 };
07493 
07494 xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
07495   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
07496 };
07497 
07498 xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
07499   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
07500 };
07501 
07502 xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
07503   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
07504 };
07505 
07506 xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
07507   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
07508 };
07509 
07510 xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
07511   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
07512 };
07513 
07514 xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
07515   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
07516 };
07517 
07518 xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
07519   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
07520 };
07521 
07522 xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
07523   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
07524 };
07525 
07526 xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
07527   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
07528 };
07529 
07530 xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
07531   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
07532 };
07533 
07534 xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
07535   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
07536 };
07537 
07538 xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
07539   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
07540 };
07541 
07542 xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
07543   Opcode_ipf_Slot_inst_encode, 0, 0
07544 };
07545 
07546 xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
07547   Opcode_ihi_Slot_inst_encode, 0, 0
07548 };
07549 
07550 xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
07551   Opcode_iii_Slot_inst_encode, 0, 0
07552 };
07553 
07554 xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
07555   Opcode_lict_Slot_inst_encode, 0, 0
07556 };
07557 
07558 xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
07559   Opcode_licw_Slot_inst_encode, 0, 0
07560 };
07561 
07562 xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
07563   Opcode_sict_Slot_inst_encode, 0, 0
07564 };
07565 
07566 xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
07567   Opcode_sicw_Slot_inst_encode, 0, 0
07568 };
07569 
07570 xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
07571   Opcode_dhwb_Slot_inst_encode, 0, 0
07572 };
07573 
07574 xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
07575   Opcode_dhwbi_Slot_inst_encode, 0, 0
07576 };
07577 
07578 xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
07579   Opcode_diwb_Slot_inst_encode, 0, 0
07580 };
07581 
07582 xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
07583   Opcode_diwbi_Slot_inst_encode, 0, 0
07584 };
07585 
07586 xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
07587   Opcode_dhi_Slot_inst_encode, 0, 0
07588 };
07589 
07590 xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
07591   Opcode_dii_Slot_inst_encode, 0, 0
07592 };
07593 
07594 xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
07595   Opcode_dpfr_Slot_inst_encode, 0, 0
07596 };
07597 
07598 xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
07599   Opcode_dpfw_Slot_inst_encode, 0, 0
07600 };
07601 
07602 xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
07603   Opcode_dpfro_Slot_inst_encode, 0, 0
07604 };
07605 
07606 xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
07607   Opcode_dpfwo_Slot_inst_encode, 0, 0
07608 };
07609 
07610 xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
07611   Opcode_sdct_Slot_inst_encode, 0, 0
07612 };
07613 
07614 xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
07615   Opcode_ldct_Slot_inst_encode, 0, 0
07616 };
07617 
07618 xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
07619   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
07620 };
07621 
07622 xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
07623   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
07624 };
07625 
07626 xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
07627   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
07628 };
07629 
07630 xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
07631   Opcode_rsr_rasid_Slot_inst_encode, 0, 0
07632 };
07633 
07634 xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
07635   Opcode_wsr_rasid_Slot_inst_encode, 0, 0
07636 };
07637 
07638 xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
07639   Opcode_xsr_rasid_Slot_inst_encode, 0, 0
07640 };
07641 
07642 xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
07643   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
07644 };
07645 
07646 xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
07647   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
07648 };
07649 
07650 xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
07651   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
07652 };
07653 
07654 xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
07655   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
07656 };
07657 
07658 xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
07659   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
07660 };
07661 
07662 xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
07663   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
07664 };
07665 
07666 xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
07667   Opcode_idtlb_Slot_inst_encode, 0, 0
07668 };
07669 
07670 xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
07671   Opcode_pdtlb_Slot_inst_encode, 0, 0
07672 };
07673 
07674 xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
07675   Opcode_rdtlb0_Slot_inst_encode, 0, 0
07676 };
07677 
07678 xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
07679   Opcode_rdtlb1_Slot_inst_encode, 0, 0
07680 };
07681 
07682 xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
07683   Opcode_wdtlb_Slot_inst_encode, 0, 0
07684 };
07685 
07686 xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
07687   Opcode_iitlb_Slot_inst_encode, 0, 0
07688 };
07689 
07690 xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
07691   Opcode_pitlb_Slot_inst_encode, 0, 0
07692 };
07693 
07694 xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
07695   Opcode_ritlb0_Slot_inst_encode, 0, 0
07696 };
07697 
07698 xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
07699   Opcode_ritlb1_Slot_inst_encode, 0, 0
07700 };
07701 
07702 xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
07703   Opcode_witlb_Slot_inst_encode, 0, 0
07704 };
07705 
07706 xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
07707   Opcode_ldpte_Slot_inst_encode, 0, 0
07708 };
07709 
07710 xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
07711   Opcode_hwwitlba_Slot_inst_encode, 0, 0
07712 };
07713 
07714 xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
07715   Opcode_hwwdtlba_Slot_inst_encode, 0, 0
07716 };
07717 
07718 xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
07719   Opcode_nsa_Slot_inst_encode, 0, 0
07720 };
07721 
07722 xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
07723   Opcode_nsau_Slot_inst_encode, 0, 0
07724 };
07725 
07726 
07727 /* Opcode table.  */
07728 
07729 static xtensa_opcode_internal opcodes[] = {
07730   { "excw", 0 /* xt_iclass_excw */,
07731     0,
07732     Opcode_excw_encode_fns, 0, 0 },
07733   { "rfe", 1 /* xt_iclass_rfe */,
07734     XTENSA_OPCODE_IS_JUMP,
07735     Opcode_rfe_encode_fns, 0, 0 },
07736   { "rfde", 2 /* xt_iclass_rfde */,
07737     XTENSA_OPCODE_IS_JUMP,
07738     Opcode_rfde_encode_fns, 0, 0 },
07739   { "syscall", 3 /* xt_iclass_syscall */,
07740     0,
07741     Opcode_syscall_encode_fns, 0, 0 },
07742   { "simcall", 4 /* xt_iclass_simcall */,
07743     0,
07744     Opcode_simcall_encode_fns, 0, 0 },
07745   { "call12", 5 /* xt_iclass_call12 */,
07746     XTENSA_OPCODE_IS_CALL,
07747     Opcode_call12_encode_fns, 0, 0 },
07748   { "call8", 6 /* xt_iclass_call8 */,
07749     XTENSA_OPCODE_IS_CALL,
07750     Opcode_call8_encode_fns, 0, 0 },
07751   { "call4", 7 /* xt_iclass_call4 */,
07752     XTENSA_OPCODE_IS_CALL,
07753     Opcode_call4_encode_fns, 0, 0 },
07754   { "callx12", 8 /* xt_iclass_callx12 */,
07755     XTENSA_OPCODE_IS_CALL,
07756     Opcode_callx12_encode_fns, 0, 0 },
07757   { "callx8", 9 /* xt_iclass_callx8 */,
07758     XTENSA_OPCODE_IS_CALL,
07759     Opcode_callx8_encode_fns, 0, 0 },
07760   { "callx4", 10 /* xt_iclass_callx4 */,
07761     XTENSA_OPCODE_IS_CALL,
07762     Opcode_callx4_encode_fns, 0, 0 },
07763   { "entry", 11 /* xt_iclass_entry */,
07764     0,
07765     Opcode_entry_encode_fns, 0, 0 },
07766   { "movsp", 12 /* xt_iclass_movsp */,
07767     0,
07768     Opcode_movsp_encode_fns, 0, 0 },
07769   { "rotw", 13 /* xt_iclass_rotw */,
07770     0,
07771     Opcode_rotw_encode_fns, 0, 0 },
07772   { "retw", 14 /* xt_iclass_retw */,
07773     XTENSA_OPCODE_IS_JUMP,
07774     Opcode_retw_encode_fns, 0, 0 },
07775   { "retw.n", 14 /* xt_iclass_retw */,
07776     XTENSA_OPCODE_IS_JUMP,
07777     Opcode_retw_n_encode_fns, 0, 0 },
07778   { "rfwo", 15 /* xt_iclass_rfwou */,
07779     XTENSA_OPCODE_IS_JUMP,
07780     Opcode_rfwo_encode_fns, 0, 0 },
07781   { "rfwu", 15 /* xt_iclass_rfwou */,
07782     XTENSA_OPCODE_IS_JUMP,
07783     Opcode_rfwu_encode_fns, 0, 0 },
07784   { "l32e", 16 /* xt_iclass_l32e */,
07785     0,
07786     Opcode_l32e_encode_fns, 0, 0 },
07787   { "s32e", 17 /* xt_iclass_s32e */,
07788     0,
07789     Opcode_s32e_encode_fns, 0, 0 },
07790   { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
07791     0,
07792     Opcode_rsr_windowbase_encode_fns, 0, 0 },
07793   { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
07794     0,
07795     Opcode_wsr_windowbase_encode_fns, 0, 0 },
07796   { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
07797     0,
07798     Opcode_xsr_windowbase_encode_fns, 0, 0 },
07799   { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
07800     0,
07801     Opcode_rsr_windowstart_encode_fns, 0, 0 },
07802   { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
07803     0,
07804     Opcode_wsr_windowstart_encode_fns, 0, 0 },
07805   { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
07806     0,
07807     Opcode_xsr_windowstart_encode_fns, 0, 0 },
07808   { "add.n", 24 /* xt_iclass_add.n */,
07809     0,
07810     Opcode_add_n_encode_fns, 0, 0 },
07811   { "addi.n", 25 /* xt_iclass_addi.n */,
07812     0,
07813     Opcode_addi_n_encode_fns, 0, 0 },
07814   { "beqz.n", 26 /* xt_iclass_bz6 */,
07815     XTENSA_OPCODE_IS_BRANCH,
07816     Opcode_beqz_n_encode_fns, 0, 0 },
07817   { "bnez.n", 26 /* xt_iclass_bz6 */,
07818     XTENSA_OPCODE_IS_BRANCH,
07819     Opcode_bnez_n_encode_fns, 0, 0 },
07820   { "ill.n", 27 /* xt_iclass_ill.n */,
07821     0,
07822     Opcode_ill_n_encode_fns, 0, 0 },
07823   { "l32i.n", 28 /* xt_iclass_loadi4 */,
07824     0,
07825     Opcode_l32i_n_encode_fns, 0, 0 },
07826   { "mov.n", 29 /* xt_iclass_mov.n */,
07827     0,
07828     Opcode_mov_n_encode_fns, 0, 0 },
07829   { "movi.n", 30 /* xt_iclass_movi.n */,
07830     0,
07831     Opcode_movi_n_encode_fns, 0, 0 },
07832   { "nop.n", 31 /* xt_iclass_nopn */,
07833     0,
07834     Opcode_nop_n_encode_fns, 0, 0 },
07835   { "ret.n", 32 /* xt_iclass_retn */,
07836     XTENSA_OPCODE_IS_JUMP,
07837     Opcode_ret_n_encode_fns, 0, 0 },
07838   { "s32i.n", 33 /* xt_iclass_storei4 */,
07839     0,
07840     Opcode_s32i_n_encode_fns, 0, 0 },
07841   { "addi", 34 /* xt_iclass_addi */,
07842     0,
07843     Opcode_addi_encode_fns, 0, 0 },
07844   { "addmi", 35 /* xt_iclass_addmi */,
07845     0,
07846     Opcode_addmi_encode_fns, 0, 0 },
07847   { "add", 36 /* xt_iclass_addsub */,
07848     0,
07849     Opcode_add_encode_fns, 0, 0 },
07850   { "sub", 36 /* xt_iclass_addsub */,
07851     0,
07852     Opcode_sub_encode_fns, 0, 0 },
07853   { "addx2", 36 /* xt_iclass_addsub */,
07854     0,
07855     Opcode_addx2_encode_fns, 0, 0 },
07856   { "addx4", 36 /* xt_iclass_addsub */,
07857     0,
07858     Opcode_addx4_encode_fns, 0, 0 },
07859   { "addx8", 36 /* xt_iclass_addsub */,
07860     0,
07861     Opcode_addx8_encode_fns, 0, 0 },
07862   { "subx2", 36 /* xt_iclass_addsub */,
07863     0,
07864     Opcode_subx2_encode_fns, 0, 0 },
07865   { "subx4", 36 /* xt_iclass_addsub */,
07866     0,
07867     Opcode_subx4_encode_fns, 0, 0 },
07868   { "subx8", 36 /* xt_iclass_addsub */,
07869     0,
07870     Opcode_subx8_encode_fns, 0, 0 },
07871   { "and", 37 /* xt_iclass_bit */,
07872     0,
07873     Opcode_and_encode_fns, 0, 0 },
07874   { "or", 37 /* xt_iclass_bit */,
07875     0,
07876     Opcode_or_encode_fns, 0, 0 },
07877   { "xor", 37 /* xt_iclass_bit */,
07878     0,
07879     Opcode_xor_encode_fns, 0, 0 },
07880   { "beqi", 38 /* xt_iclass_bsi8 */,
07881     XTENSA_OPCODE_IS_BRANCH,
07882     Opcode_beqi_encode_fns, 0, 0 },
07883   { "bnei", 38 /* xt_iclass_bsi8 */,
07884     XTENSA_OPCODE_IS_BRANCH,
07885     Opcode_bnei_encode_fns, 0, 0 },
07886   { "bgei", 38 /* xt_iclass_bsi8 */,
07887     XTENSA_OPCODE_IS_BRANCH,
07888     Opcode_bgei_encode_fns, 0, 0 },
07889   { "blti", 38 /* xt_iclass_bsi8 */,
07890     XTENSA_OPCODE_IS_BRANCH,
07891     Opcode_blti_encode_fns, 0, 0 },
07892   { "bbci", 39 /* xt_iclass_bsi8b */,
07893     XTENSA_OPCODE_IS_BRANCH,
07894     Opcode_bbci_encode_fns, 0, 0 },
07895   { "bbsi", 39 /* xt_iclass_bsi8b */,
07896     XTENSA_OPCODE_IS_BRANCH,
07897     Opcode_bbsi_encode_fns, 0, 0 },
07898   { "bgeui", 40 /* xt_iclass_bsi8u */,
07899     XTENSA_OPCODE_IS_BRANCH,
07900     Opcode_bgeui_encode_fns, 0, 0 },
07901   { "bltui", 40 /* xt_iclass_bsi8u */,
07902     XTENSA_OPCODE_IS_BRANCH,
07903     Opcode_bltui_encode_fns, 0, 0 },
07904   { "beq", 41 /* xt_iclass_bst8 */,
07905     XTENSA_OPCODE_IS_BRANCH,
07906     Opcode_beq_encode_fns, 0, 0 },
07907   { "bne", 41 /* xt_iclass_bst8 */,
07908     XTENSA_OPCODE_IS_BRANCH,
07909     Opcode_bne_encode_fns, 0, 0 },
07910   { "bge", 41 /* xt_iclass_bst8 */,
07911     XTENSA_OPCODE_IS_BRANCH,
07912     Opcode_bge_encode_fns, 0, 0 },
07913   { "blt", 41 /* xt_iclass_bst8 */,
07914     XTENSA_OPCODE_IS_BRANCH,
07915     Opcode_blt_encode_fns, 0, 0 },
07916   { "bgeu", 41 /* xt_iclass_bst8 */,
07917     XTENSA_OPCODE_IS_BRANCH,
07918     Opcode_bgeu_encode_fns, 0, 0 },
07919   { "bltu", 41 /* xt_iclass_bst8 */,
07920     XTENSA_OPCODE_IS_BRANCH,
07921     Opcode_bltu_encode_fns, 0, 0 },
07922   { "bany", 41 /* xt_iclass_bst8 */,
07923     XTENSA_OPCODE_IS_BRANCH,
07924     Opcode_bany_encode_fns, 0, 0 },
07925   { "bnone", 41 /* xt_iclass_bst8 */,
07926     XTENSA_OPCODE_IS_BRANCH,
07927     Opcode_bnone_encode_fns, 0, 0 },
07928   { "ball", 41 /* xt_iclass_bst8 */,
07929     XTENSA_OPCODE_IS_BRANCH,
07930     Opcode_ball_encode_fns, 0, 0 },
07931   { "bnall", 41 /* xt_iclass_bst8 */,
07932     XTENSA_OPCODE_IS_BRANCH,
07933     Opcode_bnall_encode_fns, 0, 0 },
07934   { "bbc", 41 /* xt_iclass_bst8 */,
07935     XTENSA_OPCODE_IS_BRANCH,
07936     Opcode_bbc_encode_fns, 0, 0 },
07937   { "bbs", 41 /* xt_iclass_bst8 */,
07938     XTENSA_OPCODE_IS_BRANCH,
07939     Opcode_bbs_encode_fns, 0, 0 },
07940   { "beqz", 42 /* xt_iclass_bsz12 */,
07941     XTENSA_OPCODE_IS_BRANCH,
07942     Opcode_beqz_encode_fns, 0, 0 },
07943   { "bnez", 42 /* xt_iclass_bsz12 */,
07944     XTENSA_OPCODE_IS_BRANCH,
07945     Opcode_bnez_encode_fns, 0, 0 },
07946   { "bgez", 42 /* xt_iclass_bsz12 */,
07947     XTENSA_OPCODE_IS_BRANCH,
07948     Opcode_bgez_encode_fns, 0, 0 },
07949   { "bltz", 42 /* xt_iclass_bsz12 */,
07950     XTENSA_OPCODE_IS_BRANCH,
07951     Opcode_bltz_encode_fns, 0, 0 },
07952   { "call0", 43 /* xt_iclass_call0 */,
07953     XTENSA_OPCODE_IS_CALL,
07954     Opcode_call0_encode_fns, 0, 0 },
07955   { "callx0", 44 /* xt_iclass_callx0 */,
07956     XTENSA_OPCODE_IS_CALL,
07957     Opcode_callx0_encode_fns, 0, 0 },
07958   { "extui", 45 /* xt_iclass_exti */,
07959     0,
07960     Opcode_extui_encode_fns, 0, 0 },
07961   { "ill", 46 /* xt_iclass_ill */,
07962     0,
07963     Opcode_ill_encode_fns, 0, 0 },
07964   { "j", 47 /* xt_iclass_jump */,
07965     XTENSA_OPCODE_IS_JUMP,
07966     Opcode_j_encode_fns, 0, 0 },
07967   { "jx", 48 /* xt_iclass_jumpx */,
07968     XTENSA_OPCODE_IS_JUMP,
07969     Opcode_jx_encode_fns, 0, 0 },
07970   { "l16ui", 49 /* xt_iclass_l16ui */,
07971     0,
07972     Opcode_l16ui_encode_fns, 0, 0 },
07973   { "l16si", 50 /* xt_iclass_l16si */,
07974     0,
07975     Opcode_l16si_encode_fns, 0, 0 },
07976   { "l32i", 51 /* xt_iclass_l32i */,
07977     0,
07978     Opcode_l32i_encode_fns, 0, 0 },
07979   { "l32r", 52 /* xt_iclass_l32r */,
07980     0,
07981     Opcode_l32r_encode_fns, 0, 0 },
07982   { "l8ui", 53 /* xt_iclass_l8i */,
07983     0,
07984     Opcode_l8ui_encode_fns, 0, 0 },
07985   { "loop", 54 /* xt_iclass_loop */,
07986     XTENSA_OPCODE_IS_LOOP,
07987     Opcode_loop_encode_fns, 0, 0 },
07988   { "loopnez", 55 /* xt_iclass_loopz */,
07989     XTENSA_OPCODE_IS_LOOP,
07990     Opcode_loopnez_encode_fns, 0, 0 },
07991   { "loopgtz", 55 /* xt_iclass_loopz */,
07992     XTENSA_OPCODE_IS_LOOP,
07993     Opcode_loopgtz_encode_fns, 0, 0 },
07994   { "movi", 56 /* xt_iclass_movi */,
07995     0,
07996     Opcode_movi_encode_fns, 0, 0 },
07997   { "moveqz", 57 /* xt_iclass_movz */,
07998     0,
07999     Opcode_moveqz_encode_fns, 0, 0 },
08000   { "movnez", 57 /* xt_iclass_movz */,
08001     0,
08002     Opcode_movnez_encode_fns, 0, 0 },
08003   { "movltz", 57 /* xt_iclass_movz */,
08004     0,
08005     Opcode_movltz_encode_fns, 0, 0 },
08006   { "movgez", 57 /* xt_iclass_movz */,
08007     0,
08008     Opcode_movgez_encode_fns, 0, 0 },
08009   { "neg", 58 /* xt_iclass_neg */,
08010     0,
08011     Opcode_neg_encode_fns, 0, 0 },
08012   { "abs", 58 /* xt_iclass_neg */,
08013     0,
08014     Opcode_abs_encode_fns, 0, 0 },
08015   { "nop", 59 /* xt_iclass_nop */,
08016     0,
08017     Opcode_nop_encode_fns, 0, 0 },
08018   { "ret", 60 /* xt_iclass_return */,
08019     XTENSA_OPCODE_IS_JUMP,
08020     Opcode_ret_encode_fns, 0, 0 },
08021   { "s16i", 61 /* xt_iclass_s16i */,
08022     0,
08023     Opcode_s16i_encode_fns, 0, 0 },
08024   { "s32i", 62 /* xt_iclass_s32i */,
08025     0,
08026     Opcode_s32i_encode_fns, 0, 0 },
08027   { "s8i", 63 /* xt_iclass_s8i */,
08028     0,
08029     Opcode_s8i_encode_fns, 0, 0 },
08030   { "ssr", 64 /* xt_iclass_sar */,
08031     0,
08032     Opcode_ssr_encode_fns, 0, 0 },
08033   { "ssl", 64 /* xt_iclass_sar */,
08034     0,
08035     Opcode_ssl_encode_fns, 0, 0 },
08036   { "ssa8l", 64 /* xt_iclass_sar */,
08037     0,
08038     Opcode_ssa8l_encode_fns, 0, 0 },
08039   { "ssa8b", 64 /* xt_iclass_sar */,
08040     0,
08041     Opcode_ssa8b_encode_fns, 0, 0 },
08042   { "ssai", 65 /* xt_iclass_sari */,
08043     0,
08044     Opcode_ssai_encode_fns, 0, 0 },
08045   { "sll", 66 /* xt_iclass_shifts */,
08046     0,
08047     Opcode_sll_encode_fns, 0, 0 },
08048   { "src", 67 /* xt_iclass_shiftst */,
08049     0,
08050     Opcode_src_encode_fns, 0, 0 },
08051   { "srl", 68 /* xt_iclass_shiftt */,
08052     0,
08053     Opcode_srl_encode_fns, 0, 0 },
08054   { "sra", 68 /* xt_iclass_shiftt */,
08055     0,
08056     Opcode_sra_encode_fns, 0, 0 },
08057   { "slli", 69 /* xt_iclass_slli */,
08058     0,
08059     Opcode_slli_encode_fns, 0, 0 },
08060   { "srai", 70 /* xt_iclass_srai */,
08061     0,
08062     Opcode_srai_encode_fns, 0, 0 },
08063   { "srli", 71 /* xt_iclass_srli */,
08064     0,
08065     Opcode_srli_encode_fns, 0, 0 },
08066   { "memw", 72 /* xt_iclass_memw */,
08067     0,
08068     Opcode_memw_encode_fns, 0, 0 },
08069   { "extw", 73 /* xt_iclass_extw */,
08070     0,
08071     Opcode_extw_encode_fns, 0, 0 },
08072   { "isync", 74 /* xt_iclass_isync */,
08073     0,
08074     Opcode_isync_encode_fns, 0, 0 },
08075   { "rsync", 75 /* xt_iclass_sync */,
08076     0,
08077     Opcode_rsync_encode_fns, 0, 0 },
08078   { "esync", 75 /* xt_iclass_sync */,
08079     0,
08080     Opcode_esync_encode_fns, 0, 0 },
08081   { "dsync", 75 /* xt_iclass_sync */,
08082     0,
08083     Opcode_dsync_encode_fns, 0, 0 },
08084   { "rsil", 76 /* xt_iclass_rsil */,
08085     0,
08086     Opcode_rsil_encode_fns, 0, 0 },
08087   { "rsr.lend", 77 /* xt_iclass_rsr.lend */,
08088     0,
08089     Opcode_rsr_lend_encode_fns, 0, 0 },
08090   { "wsr.lend", 78 /* xt_iclass_wsr.lend */,
08091     0,
08092     Opcode_wsr_lend_encode_fns, 0, 0 },
08093   { "xsr.lend", 79 /* xt_iclass_xsr.lend */,
08094     0,
08095     Opcode_xsr_lend_encode_fns, 0, 0 },
08096   { "rsr.lcount", 80 /* xt_iclass_rsr.lcount */,
08097     0,
08098     Opcode_rsr_lcount_encode_fns, 0, 0 },
08099   { "wsr.lcount", 81 /* xt_iclass_wsr.lcount */,
08100     0,
08101     Opcode_wsr_lcount_encode_fns, 0, 0 },
08102   { "xsr.lcount", 82 /* xt_iclass_xsr.lcount */,
08103     0,
08104     Opcode_xsr_lcount_encode_fns, 0, 0 },
08105   { "rsr.lbeg", 83 /* xt_iclass_rsr.lbeg */,
08106     0,
08107     Opcode_rsr_lbeg_encode_fns, 0, 0 },
08108   { "wsr.lbeg", 84 /* xt_iclass_wsr.lbeg */,
08109     0,
08110     Opcode_wsr_lbeg_encode_fns, 0, 0 },
08111   { "xsr.lbeg", 85 /* xt_iclass_xsr.lbeg */,
08112     0,
08113     Opcode_xsr_lbeg_encode_fns, 0, 0 },
08114   { "rsr.sar", 86 /* xt_iclass_rsr.sar */,
08115     0,
08116     Opcode_rsr_sar_encode_fns, 0, 0 },
08117   { "wsr.sar", 87 /* xt_iclass_wsr.sar */,
08118     0,
08119     Opcode_wsr_sar_encode_fns, 0, 0 },
08120   { "xsr.sar", 88 /* xt_iclass_xsr.sar */,
08121     0,
08122     Opcode_xsr_sar_encode_fns, 0, 0 },
08123   { "rsr.litbase", 89 /* xt_iclass_rsr.litbase */,
08124     0,
08125     Opcode_rsr_litbase_encode_fns, 0, 0 },
08126   { "wsr.litbase", 90 /* xt_iclass_wsr.litbase */,
08127     0,
08128     Opcode_wsr_litbase_encode_fns, 0, 0 },
08129   { "xsr.litbase", 91 /* xt_iclass_xsr.litbase */,
08130     0,
08131     Opcode_xsr_litbase_encode_fns, 0, 0 },
08132   { "rsr.176", 92 /* xt_iclass_rsr.176 */,
08133     0,
08134     Opcode_rsr_176_encode_fns, 0, 0 },
08135   { "rsr.208", 93 /* xt_iclass_rsr.208 */,
08136     0,
08137     Opcode_rsr_208_encode_fns, 0, 0 },
08138   { "rsr.ps", 94 /* xt_iclass_rsr.ps */,
08139     0,
08140     Opcode_rsr_ps_encode_fns, 0, 0 },
08141   { "wsr.ps", 95 /* xt_iclass_wsr.ps */,
08142     0,
08143     Opcode_wsr_ps_encode_fns, 0, 0 },
08144   { "xsr.ps", 96 /* xt_iclass_xsr.ps */,
08145     0,
08146     Opcode_xsr_ps_encode_fns, 0, 0 },
08147   { "rsr.epc1", 97 /* xt_iclass_rsr.epc1 */,
08148     0,
08149     Opcode_rsr_epc1_encode_fns, 0, 0 },
08150   { "wsr.epc1", 98 /* xt_iclass_wsr.epc1 */,
08151     0,
08152     Opcode_wsr_epc1_encode_fns, 0, 0 },
08153   { "xsr.epc1", 99 /* xt_iclass_xsr.epc1 */,
08154     0,
08155     Opcode_xsr_epc1_encode_fns, 0, 0 },
08156   { "rsr.excsave1", 100 /* xt_iclass_rsr.excsave1 */,
08157     0,
08158     Opcode_rsr_excsave1_encode_fns, 0, 0 },
08159   { "wsr.excsave1", 101 /* xt_iclass_wsr.excsave1 */,
08160     0,
08161     Opcode_wsr_excsave1_encode_fns, 0, 0 },
08162   { "xsr.excsave1", 102 /* xt_iclass_xsr.excsave1 */,
08163     0,
08164     Opcode_xsr_excsave1_encode_fns, 0, 0 },
08165   { "rsr.epc2", 103 /* xt_iclass_rsr.epc2 */,
08166     0,
08167     Opcode_rsr_epc2_encode_fns, 0, 0 },
08168   { "wsr.epc2", 104 /* xt_iclass_wsr.epc2 */,
08169     0,
08170     Opcode_wsr_epc2_encode_fns, 0, 0 },
08171   { "xsr.epc2", 105 /* xt_iclass_xsr.epc2 */,
08172     0,
08173     Opcode_xsr_epc2_encode_fns, 0, 0 },
08174   { "rsr.excsave2", 106 /* xt_iclass_rsr.excsave2 */,
08175     0,
08176     Opcode_rsr_excsave2_encode_fns, 0, 0 },
08177   { "wsr.excsave2", 107 /* xt_iclass_wsr.excsave2 */,
08178     0,
08179     Opcode_wsr_excsave2_encode_fns, 0, 0 },
08180   { "xsr.excsave2", 108 /* xt_iclass_xsr.excsave2 */,
08181     0,
08182     Opcode_xsr_excsave2_encode_fns, 0, 0 },
08183   { "rsr.epc3", 109 /* xt_iclass_rsr.epc3 */,
08184     0,
08185     Opcode_rsr_epc3_encode_fns, 0, 0 },
08186   { "wsr.epc3", 110 /* xt_iclass_wsr.epc3 */,
08187     0,
08188     Opcode_wsr_epc3_encode_fns, 0, 0 },
08189   { "xsr.epc3", 111 /* xt_iclass_xsr.epc3 */,
08190     0,
08191     Opcode_xsr_epc3_encode_fns, 0, 0 },
08192   { "rsr.excsave3", 112 /* xt_iclass_rsr.excsave3 */,
08193     0,
08194     Opcode_rsr_excsave3_encode_fns, 0, 0 },
08195   { "wsr.excsave3", 113 /* xt_iclass_wsr.excsave3 */,
08196     0,
08197     Opcode_wsr_excsave3_encode_fns, 0, 0 },
08198   { "xsr.excsave3", 114 /* xt_iclass_xsr.excsave3 */,
08199     0,
08200     Opcode_xsr_excsave3_encode_fns, 0, 0 },
08201   { "rsr.epc4", 115 /* xt_iclass_rsr.epc4 */,
08202     0,
08203     Opcode_rsr_epc4_encode_fns, 0, 0 },
08204   { "wsr.epc4", 116 /* xt_iclass_wsr.epc4 */,
08205     0,
08206     Opcode_wsr_epc4_encode_fns, 0, 0 },
08207   { "xsr.epc4", 117 /* xt_iclass_xsr.epc4 */,
08208     0,
08209     Opcode_xsr_epc4_encode_fns, 0, 0 },
08210   { "rsr.excsave4", 118 /* xt_iclass_rsr.excsave4 */,
08211     0,
08212     Opcode_rsr_excsave4_encode_fns, 0, 0 },
08213   { "wsr.excsave4", 119 /* xt_iclass_wsr.excsave4 */,
08214     0,
08215     Opcode_wsr_excsave4_encode_fns, 0, 0 },
08216   { "xsr.excsave4", 120 /* xt_iclass_xsr.excsave4 */,
08217     0,
08218     Opcode_xsr_excsave4_encode_fns, 0, 0 },
08219   { "rsr.eps2", 121 /* xt_iclass_rsr.eps2 */,
08220     0,
08221     Opcode_rsr_eps2_encode_fns, 0, 0 },
08222   { "wsr.eps2", 122 /* xt_iclass_wsr.eps2 */,
08223     0,
08224     Opcode_wsr_eps2_encode_fns, 0, 0 },
08225   { "xsr.eps2", 123 /* xt_iclass_xsr.eps2 */,
08226     0,
08227     Opcode_xsr_eps2_encode_fns, 0, 0 },
08228   { "rsr.eps3", 124 /* xt_iclass_rsr.eps3 */,
08229     0,
08230     Opcode_rsr_eps3_encode_fns, 0, 0 },
08231   { "wsr.eps3", 125 /* xt_iclass_wsr.eps3 */,
08232     0,
08233     Opcode_wsr_eps3_encode_fns, 0, 0 },
08234   { "xsr.eps3", 126 /* xt_iclass_xsr.eps3 */,
08235     0,
08236     Opcode_xsr_eps3_encode_fns, 0, 0 },
08237   { "rsr.eps4", 127 /* xt_iclass_rsr.eps4 */,
08238     0,
08239     Opcode_rsr_eps4_encode_fns, 0, 0 },
08240   { "wsr.eps4", 128 /* xt_iclass_wsr.eps4 */,
08241     0,
08242     Opcode_wsr_eps4_encode_fns, 0, 0 },
08243   { "xsr.eps4", 129 /* xt_iclass_xsr.eps4 */,
08244     0,
08245     Opcode_xsr_eps4_encode_fns, 0, 0 },
08246   { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */,
08247     0,
08248     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
08249   { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */,
08250     0,
08251     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
08252   { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */,
08253     0,
08254     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
08255   { "rsr.depc", 133 /* xt_iclass_rsr.depc */,
08256     0,
08257     Opcode_rsr_depc_encode_fns, 0, 0 },
08258   { "wsr.depc", 134 /* xt_iclass_wsr.depc */,
08259     0,
08260     Opcode_wsr_depc_encode_fns, 0, 0 },
08261   { "xsr.depc", 135 /* xt_iclass_xsr.depc */,
08262     0,
08263     Opcode_xsr_depc_encode_fns, 0, 0 },
08264   { "rsr.exccause", 136 /* xt_iclass_rsr.exccause */,
08265     0,
08266     Opcode_rsr_exccause_encode_fns, 0, 0 },
08267   { "wsr.exccause", 137 /* xt_iclass_wsr.exccause */,
08268     0,
08269     Opcode_wsr_exccause_encode_fns, 0, 0 },
08270   { "xsr.exccause", 138 /* xt_iclass_xsr.exccause */,
08271     0,
08272     Opcode_xsr_exccause_encode_fns, 0, 0 },
08273   { "rsr.misc0", 139 /* xt_iclass_rsr.misc0 */,
08274     0,
08275     Opcode_rsr_misc0_encode_fns, 0, 0 },
08276   { "wsr.misc0", 140 /* xt_iclass_wsr.misc0 */,
08277     0,
08278     Opcode_wsr_misc0_encode_fns, 0, 0 },
08279   { "xsr.misc0", 141 /* xt_iclass_xsr.misc0 */,
08280     0,
08281     Opcode_xsr_misc0_encode_fns, 0, 0 },
08282   { "rsr.misc1", 142 /* xt_iclass_rsr.misc1 */,
08283     0,
08284     Opcode_rsr_misc1_encode_fns, 0, 0 },
08285   { "wsr.misc1", 143 /* xt_iclass_wsr.misc1 */,
08286     0,
08287     Opcode_wsr_misc1_encode_fns, 0, 0 },
08288   { "xsr.misc1", 144 /* xt_iclass_xsr.misc1 */,
08289     0,
08290     Opcode_xsr_misc1_encode_fns, 0, 0 },
08291   { "rsr.prid", 145 /* xt_iclass_rsr.prid */,
08292     0,
08293     Opcode_rsr_prid_encode_fns, 0, 0 },
08294   { "rfi", 146 /* xt_iclass_rfi */,
08295     XTENSA_OPCODE_IS_JUMP,
08296     Opcode_rfi_encode_fns, 0, 0 },
08297   { "waiti", 147 /* xt_iclass_wait */,
08298     0,
08299     Opcode_waiti_encode_fns, 0, 0 },
08300   { "rsr.interrupt", 148 /* xt_iclass_rsr.interrupt */,
08301     0,
08302     Opcode_rsr_interrupt_encode_fns, 0, 0 },
08303   { "wsr.intset", 149 /* xt_iclass_wsr.intset */,
08304     0,
08305     Opcode_wsr_intset_encode_fns, 0, 0 },
08306   { "wsr.intclear", 150 /* xt_iclass_wsr.intclear */,
08307     0,
08308     Opcode_wsr_intclear_encode_fns, 0, 0 },
08309   { "rsr.intenable", 151 /* xt_iclass_rsr.intenable */,
08310     0,
08311     Opcode_rsr_intenable_encode_fns, 0, 0 },
08312   { "wsr.intenable", 152 /* xt_iclass_wsr.intenable */,
08313     0,
08314     Opcode_wsr_intenable_encode_fns, 0, 0 },
08315   { "xsr.intenable", 153 /* xt_iclass_xsr.intenable */,
08316     0,
08317     Opcode_xsr_intenable_encode_fns, 0, 0 },
08318   { "break", 154 /* xt_iclass_break */,
08319     0,
08320     Opcode_break_encode_fns, 0, 0 },
08321   { "break.n", 155 /* xt_iclass_break.n */,
08322     0,
08323     Opcode_break_n_encode_fns, 0, 0 },
08324   { "rsr.dbreaka0", 156 /* xt_iclass_rsr.dbreaka0 */,
08325     0,
08326     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
08327   { "wsr.dbreaka0", 157 /* xt_iclass_wsr.dbreaka0 */,
08328     0,
08329     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
08330   { "xsr.dbreaka0", 158 /* xt_iclass_xsr.dbreaka0 */,
08331     0,
08332     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
08333   { "rsr.dbreakc0", 159 /* xt_iclass_rsr.dbreakc0 */,
08334     0,
08335     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
08336   { "wsr.dbreakc0", 160 /* xt_iclass_wsr.dbreakc0 */,
08337     0,
08338     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
08339   { "xsr.dbreakc0", 161 /* xt_iclass_xsr.dbreakc0 */,
08340     0,
08341     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
08342   { "rsr.dbreaka1", 162 /* xt_iclass_rsr.dbreaka1 */,
08343     0,
08344     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
08345   { "wsr.dbreaka1", 163 /* xt_iclass_wsr.dbreaka1 */,
08346     0,
08347     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
08348   { "xsr.dbreaka1", 164 /* xt_iclass_xsr.dbreaka1 */,
08349     0,
08350     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
08351   { "rsr.dbreakc1", 165 /* xt_iclass_rsr.dbreakc1 */,
08352     0,
08353     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
08354   { "wsr.dbreakc1", 166 /* xt_iclass_wsr.dbreakc1 */,
08355     0,
08356     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
08357   { "xsr.dbreakc1", 167 /* xt_iclass_xsr.dbreakc1 */,
08358     0,
08359     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
08360   { "rsr.ibreaka0", 168 /* xt_iclass_rsr.ibreaka0 */,
08361     0,
08362     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
08363   { "wsr.ibreaka0", 169 /* xt_iclass_wsr.ibreaka0 */,
08364     0,
08365     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
08366   { "xsr.ibreaka0", 170 /* xt_iclass_xsr.ibreaka0 */,
08367     0,
08368     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
08369   { "rsr.ibreaka1", 171 /* xt_iclass_rsr.ibreaka1 */,
08370     0,
08371     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
08372   { "wsr.ibreaka1", 172 /* xt_iclass_wsr.ibreaka1 */,
08373     0,
08374     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
08375   { "xsr.ibreaka1", 173 /* xt_iclass_xsr.ibreaka1 */,
08376     0,
08377     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
08378   { "rsr.ibreakenable", 174 /* xt_iclass_rsr.ibreakenable */,
08379     0,
08380     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
08381   { "wsr.ibreakenable", 175 /* xt_iclass_wsr.ibreakenable */,
08382     0,
08383     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
08384   { "xsr.ibreakenable", 176 /* xt_iclass_xsr.ibreakenable */,
08385     0,
08386     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
08387   { "rsr.debugcause", 177 /* xt_iclass_rsr.debugcause */,
08388     0,
08389     Opcode_rsr_debugcause_encode_fns, 0, 0 },
08390   { "wsr.debugcause", 178 /* xt_iclass_wsr.debugcause */,
08391     0,
08392     Opcode_wsr_debugcause_encode_fns, 0, 0 },
08393   { "xsr.debugcause", 179 /* xt_iclass_xsr.debugcause */,
08394     0,
08395     Opcode_xsr_debugcause_encode_fns, 0, 0 },
08396   { "rsr.icount", 180 /* xt_iclass_rsr.icount */,
08397     0,
08398     Opcode_rsr_icount_encode_fns, 0, 0 },
08399   { "wsr.icount", 181 /* xt_iclass_wsr.icount */,
08400     0,
08401     Opcode_wsr_icount_encode_fns, 0, 0 },
08402   { "xsr.icount", 182 /* xt_iclass_xsr.icount */,
08403     0,
08404     Opcode_xsr_icount_encode_fns, 0, 0 },
08405   { "rsr.icountlevel", 183 /* xt_iclass_rsr.icountlevel */,
08406     0,
08407     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
08408   { "wsr.icountlevel", 184 /* xt_iclass_wsr.icountlevel */,
08409     0,
08410     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
08411   { "xsr.icountlevel", 185 /* xt_iclass_xsr.icountlevel */,
08412     0,
08413     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
08414   { "rsr.ddr", 186 /* xt_iclass_rsr.ddr */,
08415     0,
08416     Opcode_rsr_ddr_encode_fns, 0, 0 },
08417   { "wsr.ddr", 187 /* xt_iclass_wsr.ddr */,
08418     0,
08419     Opcode_wsr_ddr_encode_fns, 0, 0 },
08420   { "xsr.ddr", 188 /* xt_iclass_xsr.ddr */,
08421     0,
08422     Opcode_xsr_ddr_encode_fns, 0, 0 },
08423   { "rfdo", 189 /* xt_iclass_rfdo */,
08424     XTENSA_OPCODE_IS_JUMP,
08425     Opcode_rfdo_encode_fns, 0, 0 },
08426   { "rfdd", 190 /* xt_iclass_rfdd */,
08427     XTENSA_OPCODE_IS_JUMP,
08428     Opcode_rfdd_encode_fns, 0, 0 },
08429   { "rsr.ccount", 191 /* xt_iclass_rsr.ccount */,
08430     0,
08431     Opcode_rsr_ccount_encode_fns, 0, 0 },
08432   { "wsr.ccount", 192 /* xt_iclass_wsr.ccount */,
08433     0,
08434     Opcode_wsr_ccount_encode_fns, 0, 0 },
08435   { "xsr.ccount", 193 /* xt_iclass_xsr.ccount */,
08436     0,
08437     Opcode_xsr_ccount_encode_fns, 0, 0 },
08438   { "rsr.ccompare0", 194 /* xt_iclass_rsr.ccompare0 */,
08439     0,
08440     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
08441   { "wsr.ccompare0", 195 /* xt_iclass_wsr.ccompare0 */,
08442     0,
08443     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
08444   { "xsr.ccompare0", 196 /* xt_iclass_xsr.ccompare0 */,
08445     0,
08446     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
08447   { "rsr.ccompare1", 197 /* xt_iclass_rsr.ccompare1 */,
08448     0,
08449     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
08450   { "wsr.ccompare1", 198 /* xt_iclass_wsr.ccompare1 */,
08451     0,
08452     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
08453   { "xsr.ccompare1", 199 /* xt_iclass_xsr.ccompare1 */,
08454     0,
08455     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
08456   { "rsr.ccompare2", 200 /* xt_iclass_rsr.ccompare2 */,
08457     0,
08458     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
08459   { "wsr.ccompare2", 201 /* xt_iclass_wsr.ccompare2 */,
08460     0,
08461     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
08462   { "xsr.ccompare2", 202 /* xt_iclass_xsr.ccompare2 */,
08463     0,
08464     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
08465   { "ipf", 203 /* xt_iclass_icache */,
08466     0,
08467     Opcode_ipf_encode_fns, 0, 0 },
08468   { "ihi", 203 /* xt_iclass_icache */,
08469     0,
08470     Opcode_ihi_encode_fns, 0, 0 },
08471   { "iii", 204 /* xt_iclass_icache_inv */,
08472     0,
08473     Opcode_iii_encode_fns, 0, 0 },
08474   { "lict", 205 /* xt_iclass_licx */,
08475     0,
08476     Opcode_lict_encode_fns, 0, 0 },
08477   { "licw", 205 /* xt_iclass_licx */,
08478     0,
08479     Opcode_licw_encode_fns, 0, 0 },
08480   { "sict", 206 /* xt_iclass_sicx */,
08481     0,
08482     Opcode_sict_encode_fns, 0, 0 },
08483   { "sicw", 206 /* xt_iclass_sicx */,
08484     0,
08485     Opcode_sicw_encode_fns, 0, 0 },
08486   { "dhwb", 207 /* xt_iclass_dcache */,
08487     0,
08488     Opcode_dhwb_encode_fns, 0, 0 },
08489   { "dhwbi", 207 /* xt_iclass_dcache */,
08490     0,
08491     Opcode_dhwbi_encode_fns, 0, 0 },
08492   { "diwb", 208 /* xt_iclass_dcache_ind */,
08493     0,
08494     Opcode_diwb_encode_fns, 0, 0 },
08495   { "diwbi", 208 /* xt_iclass_dcache_ind */,
08496     0,
08497     Opcode_diwbi_encode_fns, 0, 0 },
08498   { "dhi", 209 /* xt_iclass_dcache_inv */,
08499     0,
08500     Opcode_dhi_encode_fns, 0, 0 },
08501   { "dii", 209 /* xt_iclass_dcache_inv */,
08502     0,
08503     Opcode_dii_encode_fns, 0, 0 },
08504   { "dpfr", 210 /* xt_iclass_dpf */,
08505     0,
08506     Opcode_dpfr_encode_fns, 0, 0 },
08507   { "dpfw", 210 /* xt_iclass_dpf */,
08508     0,
08509     Opcode_dpfw_encode_fns, 0, 0 },
08510   { "dpfro", 210 /* xt_iclass_dpf */,
08511     0,
08512     Opcode_dpfro_encode_fns, 0, 0 },
08513   { "dpfwo", 210 /* xt_iclass_dpf */,
08514     0,
08515     Opcode_dpfwo_encode_fns, 0, 0 },
08516   { "sdct", 211 /* xt_iclass_sdct */,
08517     0,
08518     Opcode_sdct_encode_fns, 0, 0 },
08519   { "ldct", 212 /* xt_iclass_ldct */,
08520     0,
08521     Opcode_ldct_encode_fns, 0, 0 },
08522   { "wsr.ptevaddr", 213 /* xt_iclass_wsr.ptevaddr */,