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cell-binutils  2.17cvs20070401
xtensa-config.h
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00001 /* Xtensa configuration settings.
00002    Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006
00003    Free Software Foundation, Inc.
00004    Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
00005 
00006    This program is free software; you can redistribute it and/or modify
00007    it under the terms of the GNU General Public License as published by
00008    the Free Software Foundation; either version 2, or (at your option)
00009    any later version.
00010 
00011    This program is distributed in the hope that it will be useful, but
00012    WITHOUT ANY WARRANTY; without even the implied warranty of
00013    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00014    General Public License for more details.
00015 
00016    You should have received a copy of the GNU General Public License
00017    along with this program; if not, write to the Free Software
00018    Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00019 
00020 #ifndef XTENSA_CONFIG_H
00021 #define XTENSA_CONFIG_H
00022 
00023 /* The macros defined here match those with the same names in the Xtensa
00024    compile-time HAL (Hardware Abstraction Layer).  Please refer to the
00025    Xtensa System Software Reference Manual for documentation of these
00026    macros.  */
00027 
00028 #undef XCHAL_HAVE_BE
00029 #define XCHAL_HAVE_BE                     1
00030 
00031 #undef XCHAL_HAVE_DENSITY
00032 #define XCHAL_HAVE_DENSITY         1
00033 
00034 #undef XCHAL_HAVE_CONST16
00035 #define XCHAL_HAVE_CONST16         0
00036 
00037 #undef XCHAL_HAVE_ABS
00038 #define XCHAL_HAVE_ABS                    1
00039 
00040 #undef XCHAL_HAVE_ADDX
00041 #define XCHAL_HAVE_ADDX                   1
00042 
00043 #undef XCHAL_HAVE_L32R
00044 #define XCHAL_HAVE_L32R                   1
00045 
00046 #undef XSHAL_USE_ABSOLUTE_LITERALS
00047 #define XSHAL_USE_ABSOLUTE_LITERALS       0
00048 
00049 #undef XCHAL_HAVE_MAC16
00050 #define XCHAL_HAVE_MAC16           0
00051 
00052 #undef XCHAL_HAVE_MUL16
00053 #define XCHAL_HAVE_MUL16           0
00054 
00055 #undef XCHAL_HAVE_MUL32
00056 #define XCHAL_HAVE_MUL32           0
00057 
00058 #undef XCHAL_HAVE_MUL32_HIGH
00059 #define XCHAL_HAVE_MUL32_HIGH             0
00060 
00061 #undef XCHAL_HAVE_DIV32
00062 #define XCHAL_HAVE_DIV32           0
00063 
00064 #undef XCHAL_HAVE_NSA
00065 #define XCHAL_HAVE_NSA                    1
00066 
00067 #undef XCHAL_HAVE_MINMAX
00068 #define XCHAL_HAVE_MINMAX          0
00069 
00070 #undef XCHAL_HAVE_SEXT
00071 #define XCHAL_HAVE_SEXT                   0
00072 
00073 #undef XCHAL_HAVE_LOOPS
00074 #define XCHAL_HAVE_LOOPS           1
00075 
00076 #undef XCHAL_HAVE_BOOLEANS
00077 #define XCHAL_HAVE_BOOLEANS        0
00078 
00079 #undef XCHAL_HAVE_FP
00080 #define XCHAL_HAVE_FP                     0
00081 
00082 #undef XCHAL_HAVE_FP_DIV
00083 #define XCHAL_HAVE_FP_DIV          0
00084 
00085 #undef XCHAL_HAVE_FP_RECIP
00086 #define XCHAL_HAVE_FP_RECIP        0
00087 
00088 #undef XCHAL_HAVE_FP_SQRT
00089 #define XCHAL_HAVE_FP_SQRT         0
00090 
00091 #undef XCHAL_HAVE_FP_RSQRT
00092 #define XCHAL_HAVE_FP_RSQRT        0
00093 
00094 #undef XCHAL_HAVE_WINDOWED
00095 #define XCHAL_HAVE_WINDOWED        1
00096 
00097 #undef XCHAL_HAVE_WIDE_BRANCHES
00098 #define XCHAL_HAVE_WIDE_BRANCHES   0
00099 
00100 #undef XCHAL_HAVE_PREDICTED_BRANCHES
00101 #define XCHAL_HAVE_PREDICTED_BRANCHES     0
00102 
00103 
00104 #undef XCHAL_ICACHE_SIZE
00105 #define XCHAL_ICACHE_SIZE          8192
00106 
00107 #undef XCHAL_DCACHE_SIZE
00108 #define XCHAL_DCACHE_SIZE          8192
00109 
00110 #undef XCHAL_ICACHE_LINESIZE
00111 #define XCHAL_ICACHE_LINESIZE             16
00112 
00113 #undef XCHAL_DCACHE_LINESIZE
00114 #define XCHAL_DCACHE_LINESIZE             16
00115 
00116 #undef XCHAL_ICACHE_LINEWIDTH
00117 #define XCHAL_ICACHE_LINEWIDTH            4
00118 
00119 #undef XCHAL_DCACHE_LINEWIDTH
00120 #define XCHAL_DCACHE_LINEWIDTH            4
00121 
00122 #undef XCHAL_DCACHE_IS_WRITEBACK
00123 #define XCHAL_DCACHE_IS_WRITEBACK  0
00124 
00125 
00126 #undef XCHAL_HAVE_MMU
00127 #define XCHAL_HAVE_MMU                    1
00128 
00129 #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
00130 #define XCHAL_MMU_MIN_PTE_PAGE_SIZE       12
00131 
00132 
00133 #undef XCHAL_HAVE_DEBUG
00134 #define XCHAL_HAVE_DEBUG           1
00135 
00136 #undef XCHAL_NUM_IBREAK
00137 #define XCHAL_NUM_IBREAK           2
00138 
00139 #undef XCHAL_NUM_DBREAK
00140 #define XCHAL_NUM_DBREAK           2
00141 
00142 #undef XCHAL_DEBUGLEVEL
00143 #define XCHAL_DEBUGLEVEL           4
00144 
00145 
00146 #undef XCHAL_INST_FETCH_WIDTH
00147 #define XCHAL_INST_FETCH_WIDTH            4
00148 
00149 
00150 #undef XSHAL_ABI
00151 #undef XTHAL_ABI_WINDOWED
00152 #undef XTHAL_ABI_CALL0
00153 #define XSHAL_ABI                  XTHAL_ABI_WINDOWED
00154 #define XTHAL_ABI_WINDOWED         0
00155 #define XTHAL_ABI_CALL0                   1
00156 
00157 #endif /* !XTENSA_CONFIG_H */