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cell-binutils  2.17cvs20070401
xstormy16-desc.h
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00001 /* CPU data header for xstormy16.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef XSTORMY16_CPU_H
00026 #define XSTORMY16_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH xstormy16
00031 
00032 /* Given symbol S, return xstormy16_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) xstormy16##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) xstormy16_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_XSTORMY16
00042 
00043 #define CGEN_INSN_LSB0_P 0
00044 
00045 /* Minimum size of any insn (in bytes).  */
00046 #define CGEN_MIN_INSN_SIZE 2
00047 
00048 /* Maximum size of any insn (in bytes).  */
00049 #define CGEN_MAX_INSN_SIZE 4
00050 
00051 #define CGEN_INT_INSN_P 1
00052 
00053 /* Maximum number of syntax elements in an instruction.  */
00054 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
00055 
00056 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00057    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00058    we can't hash on everything up to the space.  */
00059 #define CGEN_MNEMONIC_OPERANDS
00060 
00061 /* Maximum number of fields in an instruction.  */
00062 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
00063 
00064 /* Enums.  */
00065 
00066 /* Enum declaration for .  */
00067 typedef enum gr_names {
00068   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
00069  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
00070  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
00071  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
00072  , H_GR_PSW = 14, H_GR_SP = 15
00073 } GR_NAMES;
00074 
00075 /* Enum declaration for .  */
00076 typedef enum gr_rb_names {
00077   H_RBJ_R8 = 0, H_RBJ_R9 = 1, H_RBJ_R10 = 2, H_RBJ_R11 = 3
00078  , H_RBJ_R12 = 4, H_RBJ_R13 = 5, H_RBJ_R14 = 6, H_RBJ_R15 = 7
00079  , H_RBJ_PSW = 6, H_RBJ_SP = 7
00080 } GR_RB_NAMES;
00081 
00082 /* Enum declaration for insn op enums.  */
00083 typedef enum insn_op1 {
00084   OP1_0, OP1_1, OP1_2, OP1_3
00085  , OP1_4, OP1_5, OP1_6, OP1_7
00086  , OP1_8, OP1_9, OP1_A, OP1_B
00087  , OP1_C, OP1_D, OP1_E, OP1_F
00088 } INSN_OP1;
00089 
00090 /* Enum declaration for insn op enums.  */
00091 typedef enum insn_op2 {
00092   OP2_0, OP2_1, OP2_2, OP2_3
00093  , OP2_4, OP2_5, OP2_6, OP2_7
00094  , OP2_8, OP2_9, OP2_A, OP2_B
00095  , OP2_C, OP2_D, OP2_E, OP2_F
00096 } INSN_OP2;
00097 
00098 /* Enum declaration for insn op enums.  */
00099 typedef enum insn_op2a {
00100   OP2A_0, OP2A_2, OP2A_4, OP2A_6
00101  , OP2A_8, OP2A_A, OP2A_C, OP2A_E
00102 } INSN_OP2A;
00103 
00104 /* Enum declaration for insn op enums.  */
00105 typedef enum insn_op2m {
00106   OP2M_0, OP2M_1
00107 } INSN_OP2M;
00108 
00109 /* Enum declaration for insn op enums.  */
00110 typedef enum insn_op3 {
00111   OP3_0, OP3_1, OP3_2, OP3_3
00112  , OP3_4, OP3_5, OP3_6, OP3_7
00113  , OP3_8, OP3_9, OP3_A, OP3_B
00114  , OP3_C, OP3_D, OP3_E, OP3_F
00115 } INSN_OP3;
00116 
00117 /* Enum declaration for insn op enums.  */
00118 typedef enum insn_op3a {
00119   OP3A_0, OP3A_1, OP3A_2, OP3A_3
00120 } INSN_OP3A;
00121 
00122 /* Enum declaration for insn op enums.  */
00123 typedef enum insn_op3b {
00124   OP3B_0, OP3B_2, OP3B_4, OP3B_6
00125  , OP3B_8, OP3B_A, OP3B_C, OP3B_E
00126 } INSN_OP3B;
00127 
00128 /* Enum declaration for insn op enums.  */
00129 typedef enum insn_op4 {
00130   OP4_0, OP4_1, OP4_2, OP4_3
00131  , OP4_4, OP4_5, OP4_6, OP4_7
00132  , OP4_8, OP4_9, OP4_A, OP4_B
00133  , OP4_C, OP4_D, OP4_E, OP4_F
00134 } INSN_OP4;
00135 
00136 /* Enum declaration for insn op enums.  */
00137 typedef enum insn_op4m {
00138   OP4M_0, OP4M_1
00139 } INSN_OP4M;
00140 
00141 /* Enum declaration for insn op enums.  */
00142 typedef enum insn_op4b {
00143   OP4B_0, OP4B_1
00144 } INSN_OP4B;
00145 
00146 /* Enum declaration for insn op enums.  */
00147 typedef enum insn_op5 {
00148   OP5_0, OP5_1, OP5_2, OP5_3
00149  , OP5_4, OP5_5, OP5_6, OP5_7
00150  , OP5_8, OP5_9, OP5_A, OP5_B
00151  , OP5_C, OP5_D, OP5_E, OP5_F
00152 } INSN_OP5;
00153 
00154 /* Enum declaration for insn op enums.  */
00155 typedef enum insn_op5a {
00156   OP5A_0, OP5A_1
00157 } INSN_OP5A;
00158 
00159 /* Attributes.  */
00160 
00161 /* Enum declaration for machine type selection.  */
00162 typedef enum mach_attr {
00163   MACH_BASE, MACH_XSTORMY16, MACH_MAX
00164 } MACH_ATTR;
00165 
00166 /* Enum declaration for instruction set selection.  */
00167 typedef enum isa_attr {
00168   ISA_XSTORMY16, ISA_MAX
00169 } ISA_ATTR;
00170 
00171 /* Number of architecture variants.  */
00172 #define MAX_ISAS  1
00173 #define MAX_MACHS ((int) MACH_MAX)
00174 
00175 /* Ifield support.  */
00176 
00177 /* Ifield attribute indices.  */
00178 
00179 /* Enum declaration for cgen_ifld attrs.  */
00180 typedef enum cgen_ifld_attr {
00181   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00182  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00183  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00184 } CGEN_IFLD_ATTR;
00185 
00186 /* Number of non-boolean elements in cgen_ifld_attr.  */
00187 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00188 
00189 /* cgen_ifld attribute accessor macros.  */
00190 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00191 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00192 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00193 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00194 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00195 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00196 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00197 
00198 /* Enum declaration for xstormy16 ifield types.  */
00199 typedef enum ifield_type {
00200   XSTORMY16_F_NIL, XSTORMY16_F_ANYOF, XSTORMY16_F_RD, XSTORMY16_F_RDM
00201  , XSTORMY16_F_RM, XSTORMY16_F_RS, XSTORMY16_F_RB, XSTORMY16_F_RBJ
00202  , XSTORMY16_F_OP1, XSTORMY16_F_OP2, XSTORMY16_F_OP2A, XSTORMY16_F_OP2M
00203  , XSTORMY16_F_OP3, XSTORMY16_F_OP3A, XSTORMY16_F_OP3B, XSTORMY16_F_OP4
00204  , XSTORMY16_F_OP4M, XSTORMY16_F_OP4B, XSTORMY16_F_OP5, XSTORMY16_F_OP5A
00205  , XSTORMY16_F_OP, XSTORMY16_F_IMM2, XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B
00206  , XSTORMY16_F_IMM4, XSTORMY16_F_IMM8, XSTORMY16_F_IMM12, XSTORMY16_F_IMM16
00207  , XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8, XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4
00208  , XSTORMY16_F_REL12, XSTORMY16_F_REL12A, XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2
00209  , XSTORMY16_F_ABS24, XSTORMY16_F_MAX
00210 } IFIELD_TYPE;
00211 
00212 #define MAX_IFLD ((int) XSTORMY16_F_MAX)
00213 
00214 /* Hardware attribute indices.  */
00215 
00216 /* Enum declaration for cgen_hw attrs.  */
00217 typedef enum cgen_hw_attr {
00218   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00219  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00220 } CGEN_HW_ATTR;
00221 
00222 /* Number of non-boolean elements in cgen_hw_attr.  */
00223 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00224 
00225 /* cgen_hw attribute accessor macros.  */
00226 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00227 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00228 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00229 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00230 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00231 
00232 /* Enum declaration for xstormy16 hardware types.  */
00233 typedef enum cgen_hw_type {
00234   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00235  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_RB
00236  , HW_H_RBJ, HW_H_RPSW, HW_H_Z8, HW_H_Z16
00237  , HW_H_CY, HW_H_HC, HW_H_OV, HW_H_PT
00238  , HW_H_S, HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX
00239 } CGEN_HW_TYPE;
00240 
00241 #define MAX_HW ((int) HW_MAX)
00242 
00243 /* Operand attribute indices.  */
00244 
00245 /* Enum declaration for cgen_operand attrs.  */
00246 typedef enum cgen_operand_attr {
00247   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00248  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00249  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00250 } CGEN_OPERAND_ATTR;
00251 
00252 /* Number of non-boolean elements in cgen_operand_attr.  */
00253 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00254 
00255 /* cgen_operand attribute accessor macros.  */
00256 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00257 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00258 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00259 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00260 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00261 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00262 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00263 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00264 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00265 
00266 /* Enum declaration for xstormy16 operand types.  */
00267 typedef enum cgen_operand_type {
00268   XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8, XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY
00269  , XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV, XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S
00270  , XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM, XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS
00271  , XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ, XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2
00272  , XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2, XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B
00273  , XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8, XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12
00274  , XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8, XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2
00275  , XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12, XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24
00276  , XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW, XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0
00277  , XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2, XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX
00278 } CGEN_OPERAND_TYPE;
00279 
00280 /* Number of operands types.  */
00281 #define MAX_OPERANDS 39
00282 
00283 /* Maximum number of operands referenced by any insn.  */
00284 #define MAX_OPERAND_INSTANCES 8
00285 
00286 /* Insn attribute indices.  */
00287 
00288 /* Enum declaration for cgen_insn attrs.  */
00289 typedef enum cgen_insn_attr {
00290   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00291  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00292  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
00293  , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
00294 } CGEN_INSN_ATTR;
00295 
00296 /* Number of non-boolean elements in cgen_insn_attr.  */
00297 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00298 
00299 /* cgen_insn attribute accessor macros.  */
00300 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00301 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00302 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00303 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00304 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00305 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00306 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00307 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00308 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00309 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00310 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00311 
00312 /* cgen.h uses things we just defined.  */
00313 #include "opcode/cgen.h"
00314 
00315 extern const struct cgen_ifld xstormy16_cgen_ifld_table[];
00316 
00317 /* Attributes.  */
00318 extern const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[];
00319 extern const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[];
00320 extern const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[];
00321 extern const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[];
00322 
00323 /* Hardware decls.  */
00324 
00325 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_names;
00326 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names;
00327 extern CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names;
00328 extern CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond;
00329 extern CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize;
00330 
00331 extern const CGEN_HW_ENTRY xstormy16_cgen_hw_table[];
00332 
00333 
00334 
00335 #endif /* XSTORMY16_CPU_H */