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cell-binutils  2.17cvs20070401
xstormy16-desc.c
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00001 /* CPU data for xstormy16.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "xstormy16-desc.h"
00032 #include "xstormy16-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "xstormy16", MACH_XSTORMY16 },
00050   { "max", MACH_MAX },
00051   { 0, 0 }
00052 };
00053 
00054 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00055 {
00056   { "xstormy16", ISA_XSTORMY16 },
00057   { "max", ISA_MAX },
00058   { 0, 0 }
00059 };
00060 
00061 const CGEN_ATTR_TABLE xstormy16_cgen_ifield_attr_table[] =
00062 {
00063   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00064   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00065   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00066   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00067   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00068   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00069   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00070   { 0, 0, 0 }
00071 };
00072 
00073 const CGEN_ATTR_TABLE xstormy16_cgen_hardware_attr_table[] =
00074 {
00075   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00076   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00077   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00078   { "PC", &bool_attr[0], &bool_attr[0] },
00079   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00080   { 0, 0, 0 }
00081 };
00082 
00083 const CGEN_ATTR_TABLE xstormy16_cgen_operand_attr_table[] =
00084 {
00085   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00086   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00087   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00088   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00089   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00090   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00091   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00092   { "RELAX", &bool_attr[0], &bool_attr[0] },
00093   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00094   { 0, 0, 0 }
00095 };
00096 
00097 const CGEN_ATTR_TABLE xstormy16_cgen_insn_attr_table[] =
00098 {
00099   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00100   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00101   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00102   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00103   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00104   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00105   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00106   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00107   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00108   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00109   { "PBB", &bool_attr[0], &bool_attr[0] },
00110   { 0, 0, 0 }
00111 };
00112 
00113 /* Instruction set variants.  */
00114 
00115 static const CGEN_ISA xstormy16_cgen_isa_table[] = {
00116   { "xstormy16", 32, 32, 16, 32 },
00117   { 0, 0, 0, 0, 0 }
00118 };
00119 
00120 /* Machine variants.  */
00121 
00122 static const CGEN_MACH xstormy16_cgen_mach_table[] = {
00123   { "xstormy16", "xstormy16", MACH_XSTORMY16, 16 },
00124   { 0, 0, 0, 0 }
00125 };
00126 
00127 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_names_entries[] =
00128 {
00129   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00130   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
00131   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
00132   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
00133   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
00134   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
00135   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
00136   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
00137   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
00138   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
00139   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
00140   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
00141   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
00142   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
00143   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
00144   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
00145   { "psw", 14, {0, {{{0, 0}}}}, 0, 0 },
00146   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
00147 };
00148 
00149 CGEN_KEYWORD xstormy16_cgen_opval_gr_names =
00150 {
00151   & xstormy16_cgen_opval_gr_names_entries[0],
00152   18,
00153   0, 0, 0, 0, ""
00154 };
00155 
00156 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_gr_Rb_names_entries[] =
00157 {
00158   { "r8", 0, {0, {{{0, 0}}}}, 0, 0 },
00159   { "r9", 1, {0, {{{0, 0}}}}, 0, 0 },
00160   { "r10", 2, {0, {{{0, 0}}}}, 0, 0 },
00161   { "r11", 3, {0, {{{0, 0}}}}, 0, 0 },
00162   { "r12", 4, {0, {{{0, 0}}}}, 0, 0 },
00163   { "r13", 5, {0, {{{0, 0}}}}, 0, 0 },
00164   { "r14", 6, {0, {{{0, 0}}}}, 0, 0 },
00165   { "r15", 7, {0, {{{0, 0}}}}, 0, 0 },
00166   { "psw", 6, {0, {{{0, 0}}}}, 0, 0 },
00167   { "sp", 7, {0, {{{0, 0}}}}, 0, 0 }
00168 };
00169 
00170 CGEN_KEYWORD xstormy16_cgen_opval_gr_Rb_names =
00171 {
00172   & xstormy16_cgen_opval_gr_Rb_names_entries[0],
00173   10,
00174   0, 0, 0, 0, ""
00175 };
00176 
00177 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_branchcond_entries[] =
00178 {
00179   { "ge", 0, {0, {{{0, 0}}}}, 0, 0 },
00180   { "nc", 1, {0, {{{0, 0}}}}, 0, 0 },
00181   { "lt", 2, {0, {{{0, 0}}}}, 0, 0 },
00182   { "c", 3, {0, {{{0, 0}}}}, 0, 0 },
00183   { "gt", 4, {0, {{{0, 0}}}}, 0, 0 },
00184   { "hi", 5, {0, {{{0, 0}}}}, 0, 0 },
00185   { "le", 6, {0, {{{0, 0}}}}, 0, 0 },
00186   { "ls", 7, {0, {{{0, 0}}}}, 0, 0 },
00187   { "pl", 8, {0, {{{0, 0}}}}, 0, 0 },
00188   { "nv", 9, {0, {{{0, 0}}}}, 0, 0 },
00189   { "mi", 10, {0, {{{0, 0}}}}, 0, 0 },
00190   { "v", 11, {0, {{{0, 0}}}}, 0, 0 },
00191   { "nz.b", 12, {0, {{{0, 0}}}}, 0, 0 },
00192   { "nz", 13, {0, {{{0, 0}}}}, 0, 0 },
00193   { "z.b", 14, {0, {{{0, 0}}}}, 0, 0 },
00194   { "z", 15, {0, {{{0, 0}}}}, 0, 0 }
00195 };
00196 
00197 CGEN_KEYWORD xstormy16_cgen_opval_h_branchcond =
00198 {
00199   & xstormy16_cgen_opval_h_branchcond_entries[0],
00200   16,
00201   0, 0, 0, 0, ""
00202 };
00203 
00204 static CGEN_KEYWORD_ENTRY xstormy16_cgen_opval_h_wordsize_entries[] =
00205 {
00206   { ".b", 0, {0, {{{0, 0}}}}, 0, 0 },
00207   { ".w", 1, {0, {{{0, 0}}}}, 0, 0 },
00208   { "", 1, {0, {{{0, 0}}}}, 0, 0 }
00209 };
00210 
00211 CGEN_KEYWORD xstormy16_cgen_opval_h_wordsize =
00212 {
00213   & xstormy16_cgen_opval_h_wordsize_entries[0],
00214   3,
00215   0, 0, 0, 0, ""
00216 };
00217 
00218 
00219 /* The hardware table.  */
00220 
00221 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00222 #define A(a) (1 << CGEN_HW_##a)
00223 #else
00224 #define A(a) (1 << CGEN_HW_a)
00225 #endif
00226 
00227 const CGEN_HW_ENTRY xstormy16_cgen_hw_table[] =
00228 {
00229   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00230   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00231   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00232   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00233   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00234   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00235   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00236   { "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00237   { "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00238   { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00239   { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00240   { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00241   { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00242   { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00243   { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00244   { "h-pt", HW_H_PT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00245   { "h-s", HW_H_S, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
00246   { "h-branchcond", HW_H_BRANCHCOND, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_branchcond, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00247   { "h-wordsize", HW_H_WORDSIZE, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_h_wordsize, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00248   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00249 };
00250 
00251 #undef A
00252 
00253 
00254 /* The instruction field table.  */
00255 
00256 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00257 #define A(a) (1 << CGEN_IFLD_##a)
00258 #else
00259 #define A(a) (1 << CGEN_IFLD_a)
00260 #endif
00261 
00262 const CGEN_IFLD xstormy16_cgen_ifld_table[] =
00263 {
00264   { XSTORMY16_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00265   { XSTORMY16_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00266   { XSTORMY16_F_RD, "f-Rd", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00267   { XSTORMY16_F_RDM, "f-Rdm", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00268   { XSTORMY16_F_RM, "f-Rm", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00269   { XSTORMY16_F_RS, "f-Rs", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00270   { XSTORMY16_F_RB, "f-Rb", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00271   { XSTORMY16_F_RBJ, "f-Rbj", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00272   { XSTORMY16_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00273   { XSTORMY16_F_OP2, "f-op2", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00274   { XSTORMY16_F_OP2A, "f-op2a", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00275   { XSTORMY16_F_OP2M, "f-op2m", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00276   { XSTORMY16_F_OP3, "f-op3", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00277   { XSTORMY16_F_OP3A, "f-op3a", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00278   { XSTORMY16_F_OP3B, "f-op3b", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00279   { XSTORMY16_F_OP4, "f-op4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00280   { XSTORMY16_F_OP4M, "f-op4m", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00281   { XSTORMY16_F_OP4B, "f-op4b", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00282   { XSTORMY16_F_OP5, "f-op5", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00283   { XSTORMY16_F_OP5A, "f-op5a", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00284   { XSTORMY16_F_OP, "f-op", 0, 32, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00285   { XSTORMY16_F_IMM2, "f-imm2", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00286   { XSTORMY16_F_IMM3, "f-imm3", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00287   { XSTORMY16_F_IMM3B, "f-imm3b", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00288   { XSTORMY16_F_IMM4, "f-imm4", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00289   { XSTORMY16_F_IMM8, "f-imm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00290   { XSTORMY16_F_IMM12, "f-imm12", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00291   { XSTORMY16_F_IMM16, "f-imm16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00292   { XSTORMY16_F_LMEM8, "f-lmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00293   { XSTORMY16_F_HMEM8, "f-hmem8", 0, 32, 8, 8, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00294   { XSTORMY16_F_REL8_2, "f-rel8-2", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00295   { XSTORMY16_F_REL8_4, "f-rel8-4", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00296   { XSTORMY16_F_REL12, "f-rel12", 0, 32, 20, 12, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00297   { XSTORMY16_F_REL12A, "f-rel12a", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00298   { XSTORMY16_F_ABS24_1, "f-abs24-1", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00299   { XSTORMY16_F_ABS24_2, "f-abs24-2", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00300   { XSTORMY16_F_ABS24, "f-abs24", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00301   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00302 };
00303 
00304 #undef A
00305 
00306 
00307 
00308 /* multi ifield declarations */
00309 
00310 const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
00311 
00312 
00313 /* multi ifield definitions */
00314 
00315 const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
00316 {
00317     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_1] } },
00318     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_ABS24_2] } },
00319     { 0, { (const PTR) 0 } }
00320 };
00321 
00322 /* The operand table.  */
00323 
00324 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00325 #define A(a) (1 << CGEN_OPERAND_##a)
00326 #else
00327 #define A(a) (1 << CGEN_OPERAND_a)
00328 #endif
00329 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00330 #define OPERAND(op) XSTORMY16_OPERAND_##op
00331 #else
00332 #define OPERAND(op) XSTORMY16_OPERAND_op
00333 #endif
00334 
00335 const CGEN_OPERAND xstormy16_cgen_operand_table[] =
00336 {
00337 /* pc: program counter */
00338   { "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
00339     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_NIL] } }, 
00340     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00341 /* psw-z8:  */
00342   { "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
00343     { 0, { (const PTR) 0 } }, 
00344     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00345 /* psw-z16:  */
00346   { "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
00347     { 0, { (const PTR) 0 } }, 
00348     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00349 /* psw-cy:  */
00350   { "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
00351     { 0, { (const PTR) 0 } }, 
00352     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00353 /* psw-hc:  */
00354   { "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
00355     { 0, { (const PTR) 0 } }, 
00356     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00357 /* psw-ov:  */
00358   { "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
00359     { 0, { (const PTR) 0 } }, 
00360     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00361 /* psw-pt:  */
00362   { "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
00363     { 0, { (const PTR) 0 } }, 
00364     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00365 /* psw-s:  */
00366   { "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
00367     { 0, { (const PTR) 0 } }, 
00368     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00369 /* Rd: general register destination */
00370   { "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
00371     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RD] } }, 
00372     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00373 /* Rdm: general register destination */
00374   { "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
00375     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RDM] } }, 
00376     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00377 /* Rm: general register for memory */
00378   { "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
00379     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RM] } }, 
00380     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00381 /* Rs: general register source */
00382   { "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
00383     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RS] } }, 
00384     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00385 /* Rb: base register */
00386   { "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
00387     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RB] } }, 
00388     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00389 /* Rbj: base register for jump */
00390   { "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
00391     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_RBJ] } }, 
00392     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00393 /* bcond2: branch condition opcode */
00394   { "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
00395     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2] } }, 
00396     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00397 /* ws2: word size opcode */
00398   { "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
00399     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP2M] } }, 
00400     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00401 /* bcond5: branch condition opcode */
00402   { "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
00403     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_OP5] } }, 
00404     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00405 /* imm2: 2 bit unsigned immediate */
00406   { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
00407     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM2] } }, 
00408     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00409 /* imm3: 3 bit unsigned immediate */
00410   { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
00411     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3] } }, 
00412     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00413 /* imm3b: 3 bit unsigned immediate for bit tests */
00414   { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
00415     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM3B] } }, 
00416     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00417 /* imm4: 4 bit unsigned immediate */
00418   { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
00419     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM4] } }, 
00420     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00421 /* imm8: 8 bit unsigned immediate */
00422   { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
00423     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, 
00424     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00425 /* imm8small: 8 bit unsigned immediate */
00426   { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
00427     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM8] } }, 
00428     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00429 /* imm12: 12 bit signed immediate */
00430   { "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
00431     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM12] } }, 
00432     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00433 /* imm16: 16 bit immediate */
00434   { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
00435     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_IMM16] } }, 
00436     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00437 /* lmem8: 8 bit unsigned immediate low memory */
00438   { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
00439     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_LMEM8] } }, 
00440     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00441 /* hmem8: 8 bit unsigned immediate high memory */
00442   { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
00443     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_HMEM8] } }, 
00444     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00445 /* rel8-2: 8 bit relative address */
00446   { "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
00447     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_2] } }, 
00448     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00449 /* rel8-4: 8 bit relative address */
00450   { "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
00451     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL8_4] } }, 
00452     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00453 /* rel12: 12 bit relative address */
00454   { "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
00455     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12] } }, 
00456     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00457 /* rel12a: 12 bit relative address */
00458   { "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
00459     { 0, { (const PTR) &xstormy16_cgen_ifld_table[XSTORMY16_F_REL12A] } }, 
00460     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00461 /* abs24: 24 bit absolute address */
00462   { "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
00463     { 2, { (const PTR) &XSTORMY16_F_ABS24_MULTI_IFIELD[0] } }, 
00464     { 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00465 /* psw: program status word */
00466   { "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
00467     { 0, { (const PTR) 0 } }, 
00468     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00469 /* Rpsw: N0-N3 of the program status word */
00470   { "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
00471     { 0, { (const PTR) 0 } }, 
00472     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00473 /* sp: stack pointer */
00474   { "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
00475     { 0, { (const PTR) 0 } }, 
00476     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00477 /* R0: R0 */
00478   { "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
00479     { 0, { (const PTR) 0 } }, 
00480     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00481 /* R1: R1 */
00482   { "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
00483     { 0, { (const PTR) 0 } }, 
00484     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00485 /* R2: R2 */
00486   { "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
00487     { 0, { (const PTR) 0 } }, 
00488     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00489 /* R8: R8 */
00490   { "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
00491     { 0, { (const PTR) 0 } }, 
00492     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00493 /* sentinel */
00494   { 0, 0, 0, 0, 0,
00495     { 0, { (const PTR) 0 } },
00496     { 0, { { { (1<<MACH_BASE), 0 } } } } }
00497 };
00498 
00499 #undef A
00500 
00501 
00502 /* The instruction table.  */
00503 
00504 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00505 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00506 #define A(a) (1 << CGEN_INSN_##a)
00507 #else
00508 #define A(a) (1 << CGEN_INSN_a)
00509 #endif
00510 
00511 static const CGEN_IBASE xstormy16_cgen_insn_table[MAX_INSNS] =
00512 {
00513   /* Special null first entry.
00514      A `num' value of zero is thus invalid.
00515      Also, the special `invalid' insn resides here.  */
00516   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00517 /* mov$ws2 $lmem8,#$imm16 */
00518   {
00519     XSTORMY16_INSN_MOVLMEMIMM, "movlmemimm", "mov", 32,
00520     { 0, { { { (1<<MACH_BASE), 0 } } } }
00521   },
00522 /* mov$ws2 $hmem8,#$imm16 */
00523   {
00524     XSTORMY16_INSN_MOVHMEMIMM, "movhmemimm", "mov", 32,
00525     { 0, { { { (1<<MACH_BASE), 0 } } } }
00526   },
00527 /* mov$ws2 $Rm,$lmem8 */
00528   {
00529     XSTORMY16_INSN_MOVLGRMEM, "movlgrmem", "mov", 16,
00530     { 0, { { { (1<<MACH_BASE), 0 } } } }
00531   },
00532 /* mov$ws2 $Rm,$hmem8 */
00533   {
00534     XSTORMY16_INSN_MOVHGRMEM, "movhgrmem", "mov", 16,
00535     { 0, { { { (1<<MACH_BASE), 0 } } } }
00536   },
00537 /* mov$ws2 $lmem8,$Rm */
00538   {
00539     XSTORMY16_INSN_MOVLMEMGR, "movlmemgr", "mov", 16,
00540     { 0, { { { (1<<MACH_BASE), 0 } } } }
00541   },
00542 /* mov$ws2 $hmem8,$Rm */
00543   {
00544     XSTORMY16_INSN_MOVHMEMGR, "movhmemgr", "mov", 16,
00545     { 0, { { { (1<<MACH_BASE), 0 } } } }
00546   },
00547 /* mov$ws2 $Rdm,($Rs) */
00548   {
00549     XSTORMY16_INSN_MOVGRGRI, "movgrgri", "mov", 16,
00550     { 0, { { { (1<<MACH_BASE), 0 } } } }
00551   },
00552 /* mov$ws2 $Rdm,($Rs++) */
00553   {
00554     XSTORMY16_INSN_MOVGRGRIPOSTINC, "movgrgripostinc", "mov", 16,
00555     { 0, { { { (1<<MACH_BASE), 0 } } } }
00556   },
00557 /* mov$ws2 $Rdm,(--$Rs) */
00558   {
00559     XSTORMY16_INSN_MOVGRGRIPREDEC, "movgrgripredec", "mov", 16,
00560     { 0, { { { (1<<MACH_BASE), 0 } } } }
00561   },
00562 /* mov$ws2 ($Rs),$Rdm */
00563   {
00564     XSTORMY16_INSN_MOVGRIGR, "movgrigr", "mov", 16,
00565     { 0, { { { (1<<MACH_BASE), 0 } } } }
00566   },
00567 /* mov$ws2 ($Rs++),$Rdm */
00568   {
00569     XSTORMY16_INSN_MOVGRIPOSTINCGR, "movgripostincgr", "mov", 16,
00570     { 0, { { { (1<<MACH_BASE), 0 } } } }
00571   },
00572 /* mov$ws2 (--$Rs),$Rdm */
00573   {
00574     XSTORMY16_INSN_MOVGRIPREDECGR, "movgripredecgr", "mov", 16,
00575     { 0, { { { (1<<MACH_BASE), 0 } } } }
00576   },
00577 /* mov$ws2 $Rdm,($Rs,$imm12) */
00578   {
00579     XSTORMY16_INSN_MOVGRGRII, "movgrgrii", "mov", 32,
00580     { 0, { { { (1<<MACH_BASE), 0 } } } }
00581   },
00582 /* mov$ws2 $Rdm,($Rs++,$imm12) */
00583   {
00584     XSTORMY16_INSN_MOVGRGRIIPOSTINC, "movgrgriipostinc", "mov", 32,
00585     { 0, { { { (1<<MACH_BASE), 0 } } } }
00586   },
00587 /* mov$ws2 $Rdm,(--$Rs,$imm12) */
00588   {
00589     XSTORMY16_INSN_MOVGRGRIIPREDEC, "movgrgriipredec", "mov", 32,
00590     { 0, { { { (1<<MACH_BASE), 0 } } } }
00591   },
00592 /* mov$ws2 ($Rs,$imm12),$Rdm */
00593   {
00594     XSTORMY16_INSN_MOVGRIIGR, "movgriigr", "mov", 32,
00595     { 0, { { { (1<<MACH_BASE), 0 } } } }
00596   },
00597 /* mov$ws2 ($Rs++,$imm12),$Rdm */
00598   {
00599     XSTORMY16_INSN_MOVGRIIPOSTINCGR, "movgriipostincgr", "mov", 32,
00600     { 0, { { { (1<<MACH_BASE), 0 } } } }
00601   },
00602 /* mov$ws2 (--$Rs,$imm12),$Rdm */
00603   {
00604     XSTORMY16_INSN_MOVGRIIPREDECGR, "movgriipredecgr", "mov", 32,
00605     { 0, { { { (1<<MACH_BASE), 0 } } } }
00606   },
00607 /* mov $Rd,$Rs */
00608   {
00609     XSTORMY16_INSN_MOVGRGR, "movgrgr", "mov", 16,
00610     { 0, { { { (1<<MACH_BASE), 0 } } } }
00611   },
00612 /* mov.w Rx,#$imm8 */
00613   {
00614     XSTORMY16_INSN_MOVWIMM8, "movwimm8", "mov.w", 16,
00615     { 0, { { { (1<<MACH_BASE), 0 } } } }
00616   },
00617 /* mov.w $Rm,#$imm8small */
00618   {
00619     XSTORMY16_INSN_MOVWGRIMM8, "movwgrimm8", "mov.w", 16,
00620     { 0, { { { (1<<MACH_BASE), 0 } } } }
00621   },
00622 /* mov.w $Rd,#$imm16 */
00623   {
00624     XSTORMY16_INSN_MOVWGRIMM16, "movwgrimm16", "mov.w", 32,
00625     { 0, { { { (1<<MACH_BASE), 0 } } } }
00626   },
00627 /* mov.b $Rd,RxL */
00628   {
00629     XSTORMY16_INSN_MOVLOWGR, "movlowgr", "mov.b", 16,
00630     { 0, { { { (1<<MACH_BASE), 0 } } } }
00631   },
00632 /* mov.b $Rd,RxH */
00633   {
00634     XSTORMY16_INSN_MOVHIGHGR, "movhighgr", "mov.b", 16,
00635     { 0, { { { (1<<MACH_BASE), 0 } } } }
00636   },
00637 /* movf$ws2 $Rdm,($Rs) */
00638   {
00639     XSTORMY16_INSN_MOVFGRGRI, "movfgrgri", "movf", 16,
00640     { 0, { { { (1<<MACH_BASE), 0 } } } }
00641   },
00642 /* movf$ws2 $Rdm,($Rs++) */
00643   {
00644     XSTORMY16_INSN_MOVFGRGRIPOSTINC, "movfgrgripostinc", "movf", 16,
00645     { 0, { { { (1<<MACH_BASE), 0 } } } }
00646   },
00647 /* movf$ws2 $Rdm,(--$Rs) */
00648   {
00649     XSTORMY16_INSN_MOVFGRGRIPREDEC, "movfgrgripredec", "movf", 16,
00650     { 0, { { { (1<<MACH_BASE), 0 } } } }
00651   },
00652 /* movf$ws2 ($Rs),$Rdm */
00653   {
00654     XSTORMY16_INSN_MOVFGRIGR, "movfgrigr", "movf", 16,
00655     { 0, { { { (1<<MACH_BASE), 0 } } } }
00656   },
00657 /* movf$ws2 ($Rs++),$Rdm */
00658   {
00659     XSTORMY16_INSN_MOVFGRIPOSTINCGR, "movfgripostincgr", "movf", 16,
00660     { 0, { { { (1<<MACH_BASE), 0 } } } }
00661   },
00662 /* movf$ws2 (--$Rs),$Rdm */
00663   {
00664     XSTORMY16_INSN_MOVFGRIPREDECGR, "movfgripredecgr", "movf", 16,
00665     { 0, { { { (1<<MACH_BASE), 0 } } } }
00666   },
00667 /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
00668   {
00669     XSTORMY16_INSN_MOVFGRGRII, "movfgrgrii", "movf", 32,
00670     { 0, { { { (1<<MACH_BASE), 0 } } } }
00671   },
00672 /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
00673   {
00674     XSTORMY16_INSN_MOVFGRGRIIPOSTINC, "movfgrgriipostinc", "movf", 32,
00675     { 0, { { { (1<<MACH_BASE), 0 } } } }
00676   },
00677 /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
00678   {
00679     XSTORMY16_INSN_MOVFGRGRIIPREDEC, "movfgrgriipredec", "movf", 32,
00680     { 0, { { { (1<<MACH_BASE), 0 } } } }
00681   },
00682 /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
00683   {
00684     XSTORMY16_INSN_MOVFGRIIGR, "movfgriigr", "movf", 32,
00685     { 0, { { { (1<<MACH_BASE), 0 } } } }
00686   },
00687 /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
00688   {
00689     XSTORMY16_INSN_MOVFGRIIPOSTINCGR, "movfgriipostincgr", "movf", 32,
00690     { 0, { { { (1<<MACH_BASE), 0 } } } }
00691   },
00692 /* movf$ws2 ($Rb,--$Rs,$imm12),$Rdm */
00693   {
00694     XSTORMY16_INSN_MOVFGRIIPREDECGR, "movfgriipredecgr", "movf", 32,
00695     { 0, { { { (1<<MACH_BASE), 0 } } } }
00696   },
00697 /* mask $Rd,$Rs */
00698   {
00699     XSTORMY16_INSN_MASKGRGR, "maskgrgr", "mask", 16,
00700     { 0, { { { (1<<MACH_BASE), 0 } } } }
00701   },
00702 /* mask $Rd,#$imm16 */
00703   {
00704     XSTORMY16_INSN_MASKGRIMM16, "maskgrimm16", "mask", 32,
00705     { 0, { { { (1<<MACH_BASE), 0 } } } }
00706   },
00707 /* push $Rd */
00708   {
00709     XSTORMY16_INSN_PUSHGR, "pushgr", "push", 16,
00710     { 0, { { { (1<<MACH_BASE), 0 } } } }
00711   },
00712 /* pop $Rd */
00713   {
00714     XSTORMY16_INSN_POPGR, "popgr", "pop", 16,
00715     { 0, { { { (1<<MACH_BASE), 0 } } } }
00716   },
00717 /* swpn $Rd */
00718   {
00719     XSTORMY16_INSN_SWPN, "swpn", "swpn", 16,
00720     { 0, { { { (1<<MACH_BASE), 0 } } } }
00721   },
00722 /* swpb $Rd */
00723   {
00724     XSTORMY16_INSN_SWPB, "swpb", "swpb", 16,
00725     { 0, { { { (1<<MACH_BASE), 0 } } } }
00726   },
00727 /* swpw $Rd,$Rs */
00728   {
00729     XSTORMY16_INSN_SWPW, "swpw", "swpw", 16,
00730     { 0, { { { (1<<MACH_BASE), 0 } } } }
00731   },
00732 /* and $Rd,$Rs */
00733   {
00734     XSTORMY16_INSN_ANDGRGR, "andgrgr", "and", 16,
00735     { 0, { { { (1<<MACH_BASE), 0 } } } }
00736   },
00737 /* and Rx,#$imm8 */
00738   {
00739     XSTORMY16_INSN_ANDIMM8, "andimm8", "and", 16,
00740     { 0, { { { (1<<MACH_BASE), 0 } } } }
00741   },
00742 /* and $Rd,#$imm16 */
00743   {
00744     XSTORMY16_INSN_ANDGRIMM16, "andgrimm16", "and", 32,
00745     { 0, { { { (1<<MACH_BASE), 0 } } } }
00746   },
00747 /* or $Rd,$Rs */
00748   {
00749     XSTORMY16_INSN_ORGRGR, "orgrgr", "or", 16,
00750     { 0, { { { (1<<MACH_BASE), 0 } } } }
00751   },
00752 /* or Rx,#$imm8 */
00753   {
00754     XSTORMY16_INSN_ORIMM8, "orimm8", "or", 16,
00755     { 0, { { { (1<<MACH_BASE), 0 } } } }
00756   },
00757 /* or $Rd,#$imm16 */
00758   {
00759     XSTORMY16_INSN_ORGRIMM16, "orgrimm16", "or", 32,
00760     { 0, { { { (1<<MACH_BASE), 0 } } } }
00761   },
00762 /* xor $Rd,$Rs */
00763   {
00764     XSTORMY16_INSN_XORGRGR, "xorgrgr", "xor", 16,
00765     { 0, { { { (1<<MACH_BASE), 0 } } } }
00766   },
00767 /* xor Rx,#$imm8 */
00768   {
00769     XSTORMY16_INSN_XORIMM8, "xorimm8", "xor", 16,
00770     { 0, { { { (1<<MACH_BASE), 0 } } } }
00771   },
00772 /* xor $Rd,#$imm16 */
00773   {
00774     XSTORMY16_INSN_XORGRIMM16, "xorgrimm16", "xor", 32,
00775     { 0, { { { (1<<MACH_BASE), 0 } } } }
00776   },
00777 /* not $Rd */
00778   {
00779     XSTORMY16_INSN_NOTGR, "notgr", "not", 16,
00780     { 0, { { { (1<<MACH_BASE), 0 } } } }
00781   },
00782 /* add $Rd,$Rs */
00783   {
00784     XSTORMY16_INSN_ADDGRGR, "addgrgr", "add", 16,
00785     { 0, { { { (1<<MACH_BASE), 0 } } } }
00786   },
00787 /* add $Rd,#$imm4 */
00788   {
00789     XSTORMY16_INSN_ADDGRIMM4, "addgrimm4", "add", 16,
00790     { 0, { { { (1<<MACH_BASE), 0 } } } }
00791   },
00792 /* add Rx,#$imm8 */
00793   {
00794     XSTORMY16_INSN_ADDIMM8, "addimm8", "add", 16,
00795     { 0, { { { (1<<MACH_BASE), 0 } } } }
00796   },
00797 /* add $Rd,#$imm16 */
00798   {
00799     XSTORMY16_INSN_ADDGRIMM16, "addgrimm16", "add", 32,
00800     { 0, { { { (1<<MACH_BASE), 0 } } } }
00801   },
00802 /* adc $Rd,$Rs */
00803   {
00804     XSTORMY16_INSN_ADCGRGR, "adcgrgr", "adc", 16,
00805     { 0, { { { (1<<MACH_BASE), 0 } } } }
00806   },
00807 /* adc $Rd,#$imm4 */
00808   {
00809     XSTORMY16_INSN_ADCGRIMM4, "adcgrimm4", "adc", 16,
00810     { 0, { { { (1<<MACH_BASE), 0 } } } }
00811   },
00812 /* adc Rx,#$imm8 */
00813   {
00814     XSTORMY16_INSN_ADCIMM8, "adcimm8", "adc", 16,
00815     { 0, { { { (1<<MACH_BASE), 0 } } } }
00816   },
00817 /* adc $Rd,#$imm16 */
00818   {
00819     XSTORMY16_INSN_ADCGRIMM16, "adcgrimm16", "adc", 32,
00820     { 0, { { { (1<<MACH_BASE), 0 } } } }
00821   },
00822 /* sub $Rd,$Rs */
00823   {
00824     XSTORMY16_INSN_SUBGRGR, "subgrgr", "sub", 16,
00825     { 0, { { { (1<<MACH_BASE), 0 } } } }
00826   },
00827 /* sub $Rd,#$imm4 */
00828   {
00829     XSTORMY16_INSN_SUBGRIMM4, "subgrimm4", "sub", 16,
00830     { 0, { { { (1<<MACH_BASE), 0 } } } }
00831   },
00832 /* sub Rx,#$imm8 */
00833   {
00834     XSTORMY16_INSN_SUBIMM8, "subimm8", "sub", 16,
00835     { 0, { { { (1<<MACH_BASE), 0 } } } }
00836   },
00837 /* sub $Rd,#$imm16 */
00838   {
00839     XSTORMY16_INSN_SUBGRIMM16, "subgrimm16", "sub", 32,
00840     { 0, { { { (1<<MACH_BASE), 0 } } } }
00841   },
00842 /* sbc $Rd,$Rs */
00843   {
00844     XSTORMY16_INSN_SBCGRGR, "sbcgrgr", "sbc", 16,
00845     { 0, { { { (1<<MACH_BASE), 0 } } } }
00846   },
00847 /* sbc $Rd,#$imm4 */
00848   {
00849     XSTORMY16_INSN_SBCGRIMM4, "sbcgrimm4", "sbc", 16,
00850     { 0, { { { (1<<MACH_BASE), 0 } } } }
00851   },
00852 /* sbc Rx,#$imm8 */
00853   {
00854     XSTORMY16_INSN_SBCGRIMM8, "sbcgrimm8", "sbc", 16,
00855     { 0, { { { (1<<MACH_BASE), 0 } } } }
00856   },
00857 /* sbc $Rd,#$imm16 */
00858   {
00859     XSTORMY16_INSN_SBCGRIMM16, "sbcgrimm16", "sbc", 32,
00860     { 0, { { { (1<<MACH_BASE), 0 } } } }
00861   },
00862 /* inc $Rd,#$imm2 */
00863   {
00864     XSTORMY16_INSN_INCGRIMM2, "incgrimm2", "inc", 16,
00865     { 0, { { { (1<<MACH_BASE), 0 } } } }
00866   },
00867 /* dec $Rd,#$imm2 */
00868   {
00869     XSTORMY16_INSN_DECGRIMM2, "decgrimm2", "dec", 16,
00870     { 0, { { { (1<<MACH_BASE), 0 } } } }
00871   },
00872 /* rrc $Rd,$Rs */
00873   {
00874     XSTORMY16_INSN_RRCGRGR, "rrcgrgr", "rrc", 16,
00875     { 0, { { { (1<<MACH_BASE), 0 } } } }
00876   },
00877 /* rrc $Rd,#$imm4 */
00878   {
00879     XSTORMY16_INSN_RRCGRIMM4, "rrcgrimm4", "rrc", 16,
00880     { 0, { { { (1<<MACH_BASE), 0 } } } }
00881   },
00882 /* rlc $Rd,$Rs */
00883   {
00884     XSTORMY16_INSN_RLCGRGR, "rlcgrgr", "rlc", 16,
00885     { 0, { { { (1<<MACH_BASE), 0 } } } }
00886   },
00887 /* rlc $Rd,#$imm4 */
00888   {
00889     XSTORMY16_INSN_RLCGRIMM4, "rlcgrimm4", "rlc", 16,
00890     { 0, { { { (1<<MACH_BASE), 0 } } } }
00891   },
00892 /* shr $Rd,$Rs */
00893   {
00894     XSTORMY16_INSN_SHRGRGR, "shrgrgr", "shr", 16,
00895     { 0, { { { (1<<MACH_BASE), 0 } } } }
00896   },
00897 /* shr $Rd,#$imm4 */
00898   {
00899     XSTORMY16_INSN_SHRGRIMM, "shrgrimm", "shr", 16,
00900     { 0, { { { (1<<MACH_BASE), 0 } } } }
00901   },
00902 /* shl $Rd,$Rs */
00903   {
00904     XSTORMY16_INSN_SHLGRGR, "shlgrgr", "shl", 16,
00905     { 0, { { { (1<<MACH_BASE), 0 } } } }
00906   },
00907 /* shl $Rd,#$imm4 */
00908   {
00909     XSTORMY16_INSN_SHLGRIMM, "shlgrimm", "shl", 16,
00910     { 0, { { { (1<<MACH_BASE), 0 } } } }
00911   },
00912 /* asr $Rd,$Rs */
00913   {
00914     XSTORMY16_INSN_ASRGRGR, "asrgrgr", "asr", 16,
00915     { 0, { { { (1<<MACH_BASE), 0 } } } }
00916   },
00917 /* asr $Rd,#$imm4 */
00918   {
00919     XSTORMY16_INSN_ASRGRIMM, "asrgrimm", "asr", 16,
00920     { 0, { { { (1<<MACH_BASE), 0 } } } }
00921   },
00922 /* set1 $Rd,#$imm4 */
00923   {
00924     XSTORMY16_INSN_SET1GRIMM, "set1grimm", "set1", 16,
00925     { 0, { { { (1<<MACH_BASE), 0 } } } }
00926   },
00927 /* set1 $Rd,$Rs */
00928   {
00929     XSTORMY16_INSN_SET1GRGR, "set1grgr", "set1", 16,
00930     { 0, { { { (1<<MACH_BASE), 0 } } } }
00931   },
00932 /* set1 $lmem8,#$imm3 */
00933   {
00934     XSTORMY16_INSN_SET1LMEMIMM, "set1lmemimm", "set1", 16,
00935     { 0, { { { (1<<MACH_BASE), 0 } } } }
00936   },
00937 /* set1 $hmem8,#$imm3 */
00938   {
00939     XSTORMY16_INSN_SET1HMEMIMM, "set1hmemimm", "set1", 16,
00940     { 0, { { { (1<<MACH_BASE), 0 } } } }
00941   },
00942 /* clr1 $Rd,#$imm4 */
00943   {
00944     XSTORMY16_INSN_CLR1GRIMM, "clr1grimm", "clr1", 16,
00945     { 0, { { { (1<<MACH_BASE), 0 } } } }
00946   },
00947 /* clr1 $Rd,$Rs */
00948   {
00949     XSTORMY16_INSN_CLR1GRGR, "clr1grgr", "clr1", 16,
00950     { 0, { { { (1<<MACH_BASE), 0 } } } }
00951   },
00952 /* clr1 $lmem8,#$imm3 */
00953   {
00954     XSTORMY16_INSN_CLR1LMEMIMM, "clr1lmemimm", "clr1", 16,
00955     { 0, { { { (1<<MACH_BASE), 0 } } } }
00956   },
00957 /* clr1 $hmem8,#$imm3 */
00958   {
00959     XSTORMY16_INSN_CLR1HMEMIMM, "clr1hmemimm", "clr1", 16,
00960     { 0, { { { (1<<MACH_BASE), 0 } } } }
00961   },
00962 /* cbw $Rd */
00963   {
00964     XSTORMY16_INSN_CBWGR, "cbwgr", "cbw", 16,
00965     { 0, { { { (1<<MACH_BASE), 0 } } } }
00966   },
00967 /* rev $Rd */
00968   {
00969     XSTORMY16_INSN_REVGR, "revgr", "rev", 16,
00970     { 0, { { { (1<<MACH_BASE), 0 } } } }
00971   },
00972 /* b$bcond5 $Rd,$Rs,$rel12 */
00973   {
00974     XSTORMY16_INSN_BCCGRGR, "bccgrgr", "b", 32,
00975     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
00976   },
00977 /* b$bcond5 $Rm,#$imm8,$rel12 */
00978   {
00979     XSTORMY16_INSN_BCCGRIMM8, "bccgrimm8", "b", 32,
00980     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
00981   },
00982 /* b$bcond2 Rx,#$imm16,${rel8-4} */
00983   {
00984     XSTORMY16_INSN_BCCIMM16, "bccimm16", "b", 32,
00985     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
00986   },
00987 /* bn $Rd,#$imm4,$rel12 */
00988   {
00989     XSTORMY16_INSN_BNGRIMM4, "bngrimm4", "bn", 32,
00990     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
00991   },
00992 /* bn $Rd,$Rs,$rel12 */
00993   {
00994     XSTORMY16_INSN_BNGRGR, "bngrgr", "bn", 32,
00995     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
00996   },
00997 /* bn $lmem8,#$imm3b,$rel12 */
00998   {
00999     XSTORMY16_INSN_BNLMEMIMM, "bnlmemimm", "bn", 32,
01000     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01001   },
01002 /* bn $hmem8,#$imm3b,$rel12 */
01003   {
01004     XSTORMY16_INSN_BNHMEMIMM, "bnhmemimm", "bn", 32,
01005     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01006   },
01007 /* bp $Rd,#$imm4,$rel12 */
01008   {
01009     XSTORMY16_INSN_BPGRIMM4, "bpgrimm4", "bp", 32,
01010     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01011   },
01012 /* bp $Rd,$Rs,$rel12 */
01013   {
01014     XSTORMY16_INSN_BPGRGR, "bpgrgr", "bp", 32,
01015     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01016   },
01017 /* bp $lmem8,#$imm3b,$rel12 */
01018   {
01019     XSTORMY16_INSN_BPLMEMIMM, "bplmemimm", "bp", 32,
01020     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01021   },
01022 /* bp $hmem8,#$imm3b,$rel12 */
01023   {
01024     XSTORMY16_INSN_BPHMEMIMM, "bphmemimm", "bp", 32,
01025     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01026   },
01027 /* b$bcond2 ${rel8-2} */
01028   {
01029     XSTORMY16_INSN_BCC, "bcc", "b", 16,
01030     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01031   },
01032 /* br $Rd */
01033   {
01034     XSTORMY16_INSN_BGR, "bgr", "br", 16,
01035     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01036   },
01037 /* br $rel12a */
01038   {
01039     XSTORMY16_INSN_BR, "br", "br", 16,
01040     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01041   },
01042 /* jmp $Rbj,$Rd */
01043   {
01044     XSTORMY16_INSN_JMP, "jmp", "jmp", 16,
01045     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01046   },
01047 /* jmpf $abs24 */
01048   {
01049     XSTORMY16_INSN_JMPF, "jmpf", "jmpf", 32,
01050     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01051   },
01052 /* callr $Rd */
01053   {
01054     XSTORMY16_INSN_CALLRGR, "callrgr", "callr", 16,
01055     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01056   },
01057 /* callr $rel12a */
01058   {
01059     XSTORMY16_INSN_CALLRIMM, "callrimm", "callr", 16,
01060     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01061   },
01062 /* call $Rbj,$Rd */
01063   {
01064     XSTORMY16_INSN_CALLGR, "callgr", "call", 16,
01065     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01066   },
01067 /* callf $abs24 */
01068   {
01069     XSTORMY16_INSN_CALLFIMM, "callfimm", "callf", 32,
01070     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01071   },
01072 /* icallr $Rd */
01073   {
01074     XSTORMY16_INSN_ICALLRGR, "icallrgr", "icallr", 16,
01075     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01076   },
01077 /* icall $Rbj,$Rd */
01078   {
01079     XSTORMY16_INSN_ICALLGR, "icallgr", "icall", 16,
01080     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01081   },
01082 /* icallf $abs24 */
01083   {
01084     XSTORMY16_INSN_ICALLFIMM, "icallfimm", "icallf", 32,
01085     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01086   },
01087 /* iret */
01088   {
01089     XSTORMY16_INSN_IRET, "iret", "iret", 16,
01090     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01091   },
01092 /* ret */
01093   {
01094     XSTORMY16_INSN_RET, "ret", "ret", 16,
01095     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01096   },
01097 /* mul */
01098   {
01099     XSTORMY16_INSN_MUL, "mul", "mul", 16,
01100     { 0, { { { (1<<MACH_BASE), 0 } } } }
01101   },
01102 /* div */
01103   {
01104     XSTORMY16_INSN_DIV, "div", "div", 16,
01105     { 0, { { { (1<<MACH_BASE), 0 } } } }
01106   },
01107 /* sdiv */
01108   {
01109     XSTORMY16_INSN_SDIV, "sdiv", "sdiv", 16,
01110     { 0, { { { (1<<MACH_BASE), 0 } } } }
01111   },
01112 /* sdivlh */
01113   {
01114     XSTORMY16_INSN_SDIVLH, "sdivlh", "sdivlh", 16,
01115     { 0, { { { (1<<MACH_BASE), 0 } } } }
01116   },
01117 /* divlh */
01118   {
01119     XSTORMY16_INSN_DIVLH, "divlh", "divlh", 16,
01120     { 0, { { { (1<<MACH_BASE), 0 } } } }
01121   },
01122 /* reset */
01123   {
01124     XSTORMY16_INSN_RESET, "reset", "reset", 16,
01125     { 0, { { { (1<<MACH_BASE), 0 } } } }
01126   },
01127 /* nop */
01128   {
01129     XSTORMY16_INSN_NOP, "nop", "nop", 16,
01130     { 0, { { { (1<<MACH_BASE), 0 } } } }
01131   },
01132 /* halt */
01133   {
01134     XSTORMY16_INSN_HALT, "halt", "halt", 16,
01135     { 0, { { { (1<<MACH_BASE), 0 } } } }
01136   },
01137 /* hold */
01138   {
01139     XSTORMY16_INSN_HOLD, "hold", "hold", 16,
01140     { 0, { { { (1<<MACH_BASE), 0 } } } }
01141   },
01142 /* holdx */
01143   {
01144     XSTORMY16_INSN_HOLDX, "holdx", "holdx", 16,
01145     { 0, { { { (1<<MACH_BASE), 0 } } } }
01146   },
01147 /* brk */
01148   {
01149     XSTORMY16_INSN_BRK, "brk", "brk", 16,
01150     { 0, { { { (1<<MACH_BASE), 0 } } } }
01151   },
01152 /* --unused-- */
01153   {
01154     XSTORMY16_INSN_SYSCALL, "syscall", "--unused--", 16,
01155     { 0, { { { (1<<MACH_BASE), 0 } } } }
01156   },
01157 };
01158 
01159 #undef OP
01160 #undef A
01161 
01162 /* Initialize anything needed to be done once, before any cpu_open call.  */
01163 
01164 static void
01165 init_tables (void)
01166 {
01167 }
01168 
01169 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
01170 static void build_hw_table      (CGEN_CPU_TABLE *);
01171 static void build_ifield_table  (CGEN_CPU_TABLE *);
01172 static void build_operand_table (CGEN_CPU_TABLE *);
01173 static void build_insn_table    (CGEN_CPU_TABLE *);
01174 static void xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *);
01175 
01176 /* Subroutine of xstormy16_cgen_cpu_open to look up a mach via its bfd name.  */
01177 
01178 static const CGEN_MACH *
01179 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
01180 {
01181   while (table->name)
01182     {
01183       if (strcmp (name, table->bfd_name) == 0)
01184        return table;
01185       ++table;
01186     }
01187   abort ();
01188 }
01189 
01190 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
01191 
01192 static void
01193 build_hw_table (CGEN_CPU_TABLE *cd)
01194 {
01195   int i;
01196   int machs = cd->machs;
01197   const CGEN_HW_ENTRY *init = & xstormy16_cgen_hw_table[0];
01198   /* MAX_HW is only an upper bound on the number of selected entries.
01199      However each entry is indexed by it's enum so there can be holes in
01200      the table.  */
01201   const CGEN_HW_ENTRY **selected =
01202     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01203 
01204   cd->hw_table.init_entries = init;
01205   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01206   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01207   /* ??? For now we just use machs to determine which ones we want.  */
01208   for (i = 0; init[i].name != NULL; ++i)
01209     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01210        & machs)
01211       selected[init[i].type] = &init[i];
01212   cd->hw_table.entries = selected;
01213   cd->hw_table.num_entries = MAX_HW;
01214 }
01215 
01216 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
01217 
01218 static void
01219 build_ifield_table (CGEN_CPU_TABLE *cd)
01220 {
01221   cd->ifld_table = & xstormy16_cgen_ifld_table[0];
01222 }
01223 
01224 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.  */
01225 
01226 static void
01227 build_operand_table (CGEN_CPU_TABLE *cd)
01228 {
01229   int i;
01230   int machs = cd->machs;
01231   const CGEN_OPERAND *init = & xstormy16_cgen_operand_table[0];
01232   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01233      However each entry is indexed by it's enum so there can be holes in
01234      the table.  */
01235   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
01236 
01237   cd->operand_table.init_entries = init;
01238   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01239   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01240   /* ??? For now we just use mach to determine which ones we want.  */
01241   for (i = 0; init[i].name != NULL; ++i)
01242     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01243        & machs)
01244       selected[init[i].type] = &init[i];
01245   cd->operand_table.entries = selected;
01246   cd->operand_table.num_entries = MAX_OPERANDS;
01247 }
01248 
01249 /* Subroutine of xstormy16_cgen_cpu_open to build the hardware table.
01250    ??? This could leave out insns not supported by the specified mach/isa,
01251    but that would cause errors like "foo only supported by bar" to become
01252    "unknown insn", so for now we include all insns and require the app to
01253    do the checking later.
01254    ??? On the other hand, parsing of such insns may require their hardware or
01255    operand elements to be in the table [which they mightn't be].  */
01256 
01257 static void
01258 build_insn_table (CGEN_CPU_TABLE *cd)
01259 {
01260   int i;
01261   const CGEN_IBASE *ib = & xstormy16_cgen_insn_table[0];
01262   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01263 
01264   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01265   for (i = 0; i < MAX_INSNS; ++i)
01266     insns[i].base = &ib[i];
01267   cd->insn_table.init_entries = insns;
01268   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01269   cd->insn_table.num_init_entries = MAX_INSNS;
01270 }
01271 
01272 /* Subroutine of xstormy16_cgen_cpu_open to rebuild the tables.  */
01273 
01274 static void
01275 xstormy16_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
01276 {
01277   int i;
01278   CGEN_BITSET *isas = cd->isas;
01279   unsigned int machs = cd->machs;
01280 
01281   cd->int_insn_p = CGEN_INT_INSN_P;
01282 
01283   /* Data derived from the isa spec.  */
01284 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01285   cd->default_insn_bitsize = UNSET;
01286   cd->base_insn_bitsize = UNSET;
01287   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
01288   cd->max_insn_bitsize = 0;
01289   for (i = 0; i < MAX_ISAS; ++i)
01290     if (cgen_bitset_contains (isas, i))
01291       {
01292        const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
01293 
01294        /* Default insn sizes of all selected isas must be
01295           equal or we set the result to 0, meaning "unknown".  */
01296        if (cd->default_insn_bitsize == UNSET)
01297          cd->default_insn_bitsize = isa->default_insn_bitsize;
01298        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
01299          ; /* This is ok.  */
01300        else
01301          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
01302 
01303        /* Base insn sizes of all selected isas must be equal
01304           or we set the result to 0, meaning "unknown".  */
01305        if (cd->base_insn_bitsize == UNSET)
01306          cd->base_insn_bitsize = isa->base_insn_bitsize;
01307        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
01308          ; /* This is ok.  */
01309        else
01310          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
01311 
01312        /* Set min,max insn sizes.  */
01313        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
01314          cd->min_insn_bitsize = isa->min_insn_bitsize;
01315        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
01316          cd->max_insn_bitsize = isa->max_insn_bitsize;
01317       }
01318 
01319   /* Data derived from the mach spec.  */
01320   for (i = 0; i < MAX_MACHS; ++i)
01321     if (((1 << i) & machs) != 0)
01322       {
01323        const CGEN_MACH *mach = & xstormy16_cgen_mach_table[i];
01324 
01325        if (mach->insn_chunk_bitsize != 0)
01326        {
01327          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
01328            {
01329              fprintf (stderr, "xstormy16_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
01330                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
01331              abort ();
01332            }
01333 
01334          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
01335        }
01336       }
01337 
01338   /* Determine which hw elements are used by MACH.  */
01339   build_hw_table (cd);
01340 
01341   /* Build the ifield table.  */
01342   build_ifield_table (cd);
01343 
01344   /* Determine which operands are used by MACH/ISA.  */
01345   build_operand_table (cd);
01346 
01347   /* Build the instruction table.  */
01348   build_insn_table (cd);
01349 }
01350 
01351 /* Initialize a cpu table and return a descriptor.
01352    It's much like opening a file, and must be the first function called.
01353    The arguments are a set of (type/value) pairs, terminated with
01354    CGEN_CPU_OPEN_END.
01355 
01356    Currently supported values:
01357    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
01358    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
01359    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
01360    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
01361    CGEN_CPU_OPEN_END:     terminates arguments
01362 
01363    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
01364    precluded.
01365 
01366    ??? We only support ISO C stdargs here, not K&R.
01367    Laziness, plus experiment to see if anything requires K&R - eventually
01368    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01369 
01370 CGEN_CPU_DESC
01371 xstormy16_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
01372 {
01373   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
01374   static int init_p;
01375   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
01376   unsigned int machs = 0; /* 0 = "unspecified" */
01377   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
01378   va_list ap;
01379 
01380   if (! init_p)
01381     {
01382       init_tables ();
01383       init_p = 1;
01384     }
01385 
01386   memset (cd, 0, sizeof (*cd));
01387 
01388   va_start (ap, arg_type);
01389   while (arg_type != CGEN_CPU_OPEN_END)
01390     {
01391       switch (arg_type)
01392        {
01393        case CGEN_CPU_OPEN_ISAS :
01394          isas = va_arg (ap, CGEN_BITSET *);
01395          break;
01396        case CGEN_CPU_OPEN_MACHS :
01397          machs = va_arg (ap, unsigned int);
01398          break;
01399        case CGEN_CPU_OPEN_BFDMACH :
01400          {
01401            const char *name = va_arg (ap, const char *);
01402            const CGEN_MACH *mach =
01403              lookup_mach_via_bfd_name (xstormy16_cgen_mach_table, name);
01404 
01405            machs |= 1 << mach->num;
01406            break;
01407          }
01408        case CGEN_CPU_OPEN_ENDIAN :
01409          endian = va_arg (ap, enum cgen_endian);
01410          break;
01411        default :
01412          fprintf (stderr, "xstormy16_cgen_cpu_open: unsupported argument `%d'\n",
01413                  arg_type);
01414          abort (); /* ??? return NULL? */
01415        }
01416       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
01417     }
01418   va_end (ap);
01419 
01420   /* Mach unspecified means "all".  */
01421   if (machs == 0)
01422     machs = (1 << MAX_MACHS) - 1;
01423   /* Base mach is always selected.  */
01424   machs |= 1;
01425   if (endian == CGEN_ENDIAN_UNKNOWN)
01426     {
01427       /* ??? If target has only one, could have a default.  */
01428       fprintf (stderr, "xstormy16_cgen_cpu_open: no endianness specified\n");
01429       abort ();
01430     }
01431 
01432   cd->isas = cgen_bitset_copy (isas);
01433   cd->machs = machs;
01434   cd->endian = endian;
01435   /* FIXME: for the sparc case we can determine insn-endianness statically.
01436      The worry here is where both data and insn endian can be independently
01437      chosen, in which case this function will need another argument.
01438      Actually, will want to allow for more arguments in the future anyway.  */
01439   cd->insn_endian = endian;
01440 
01441   /* Table (re)builder.  */
01442   cd->rebuild_tables = xstormy16_cgen_rebuild_tables;
01443   xstormy16_cgen_rebuild_tables (cd);
01444 
01445   /* Default to not allowing signed overflow.  */
01446   cd->signed_overflow_ok_p = 0;
01447   
01448   return (CGEN_CPU_DESC) cd;
01449 }
01450 
01451 /* Cover fn to xstormy16_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01452    MACH_NAME is the bfd name of the mach.  */
01453 
01454 CGEN_CPU_DESC
01455 xstormy16_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
01456 {
01457   return xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01458                             CGEN_CPU_OPEN_ENDIAN, endian,
01459                             CGEN_CPU_OPEN_END);
01460 }
01461 
01462 /* Close a cpu table.
01463    ??? This can live in a machine independent file, but there's currently
01464    no place to put this file (there's no libcgen).  libopcodes is the wrong
01465    place as some simulator ports use this but they don't use libopcodes.  */
01466 
01467 void
01468 xstormy16_cgen_cpu_close (CGEN_CPU_DESC cd)
01469 {
01470   unsigned int i;
01471   const CGEN_INSN *insns;
01472 
01473   if (cd->macro_insn_table.init_entries)
01474     {
01475       insns = cd->macro_insn_table.init_entries;
01476       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01477        if (CGEN_INSN_RX ((insns)))
01478          regfree (CGEN_INSN_RX (insns));
01479     }
01480 
01481   if (cd->insn_table.init_entries)
01482     {
01483       insns = cd->insn_table.init_entries;
01484       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01485        if (CGEN_INSN_RX (insns))
01486          regfree (CGEN_INSN_RX (insns));
01487     }  
01488 
01489   if (cd->macro_insn_table.init_entries)
01490     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01491 
01492   if (cd->insn_table.init_entries)
01493     free ((CGEN_INSN *) cd->insn_table.init_entries);
01494 
01495   if (cd->hw_table.entries)
01496     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01497 
01498   if (cd->operand_table.entries)
01499     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01500 
01501   free (cd);
01502 }
01503