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cell-binutils  2.17cvs20070401
xc16x-desc.h
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00001 /* CPU data header for xc16x.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef XC16X_CPU_H
00026 #define XC16X_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH xc16x
00031 
00032 /* Given symbol S, return xc16x_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) xc16x##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) xc16x_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_XC16XBF
00042 
00043 #define CGEN_INSN_LSB0_P 1
00044 
00045 /* Minimum size of any insn (in bytes).  */
00046 #define CGEN_MIN_INSN_SIZE 2
00047 
00048 /* Maximum size of any insn (in bytes).  */
00049 #define CGEN_MAX_INSN_SIZE 4
00050 
00051 #define CGEN_INT_INSN_P 1
00052 
00053 /* Maximum number of syntax elements in an instruction.  */
00054 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
00055 
00056 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00057    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00058    we can't hash on everything up to the space.  */
00059 #define CGEN_MNEMONIC_OPERANDS
00060 
00061 /* Maximum number of fields in an instruction.  */
00062 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
00063 
00064 /* Enums.  */
00065 
00066 /* Enum declaration for insn format enums.  */
00067 typedef enum insn_op1 {
00068   OP1_0, OP1_1, OP1_2, OP1_3
00069  , OP1_4, OP1_5, OP1_6, OP1_7
00070  , OP1_8, OP1_9, OP1_10, OP1_11
00071  , OP1_12, OP1_13, OP1_14, OP1_15
00072 } INSN_OP1;
00073 
00074 /* Enum declaration for op2 enums.  */
00075 typedef enum insn_op2 {
00076   OP2_0, OP2_1, OP2_2, OP2_3
00077  , OP2_4, OP2_5, OP2_6, OP2_7
00078  , OP2_8, OP2_9, OP2_10, OP2_11
00079  , OP2_12, OP2_13, OP2_14, OP2_15
00080 } INSN_OP2;
00081 
00082 /* Enum declaration for bit set/clear enums.  */
00083 typedef enum insn_qcond {
00084   QBIT_0, QBIT_1, QBIT_2, QBIT_3
00085  , QBIT_4, QBIT_5, QBIT_6, QBIT_7
00086  , QBIT_8, QBIT_9, QBIT_10, QBIT_11
00087  , QBIT_12, QBIT_13, QBIT_14, QBIT_15
00088 } INSN_QCOND;
00089 
00090 /* Enum declaration for relative jump condition code op2 enums.  */
00091 typedef enum insn_rcond {
00092   COND_UC = 0, COND_NET = 1, COND_Z = 2, COND_NE_NZ = 3
00093  , COND_V = 4, COND_NV = 5, COND_N = 6, COND_NN = 7
00094  , COND_C = 8, COND_NC = 9, COND_SGT = 10, COND_SLE = 11
00095  , COND_SLT = 12, COND_SGE = 13, COND_UGT = 14, COND_ULE = 15
00096  , COND_EQ = 2, COND_NE = 3, COND_ULT = 8, COND_UGE = 9
00097 } INSN_RCOND;
00098 
00099 /* Enum declaration for .  */
00100 typedef enum gr_names {
00101   H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3
00102  , H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7
00103  , H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11
00104  , H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15
00105 } GR_NAMES;
00106 
00107 /* Enum declaration for .  */
00108 typedef enum ext_names {
00109   H_EXT_0X1 = 0, H_EXT_0X2 = 1, H_EXT_0X3 = 2, H_EXT_0X4 = 3
00110  , H_EXT_1 = 0, H_EXT_2 = 1, H_EXT_3 = 2, H_EXT_4 = 3
00111 } EXT_NAMES;
00112 
00113 /* Enum declaration for .  */
00114 typedef enum psw_names {
00115   H_PSW_IEN = 136, H_PSW_R0_11 = 240, H_PSW_R1_11 = 241, H_PSW_R2_11 = 242
00116  , H_PSW_R3_11 = 243, H_PSW_R4_11 = 244, H_PSW_R5_11 = 245, H_PSW_R6_11 = 246
00117  , H_PSW_R7_11 = 247, H_PSW_R8_11 = 248, H_PSW_R9_11 = 249, H_PSW_R10_11 = 250
00118  , H_PSW_R11_11 = 251, H_PSW_R12_11 = 252, H_PSW_R13_11 = 253, H_PSW_R14_11 = 254
00119  , H_PSW_R15_11 = 255
00120 } PSW_NAMES;
00121 
00122 /* Enum declaration for .  */
00123 typedef enum grb_names {
00124   H_GRB_RL0, H_GRB_RH0, H_GRB_RL1, H_GRB_RH1
00125  , H_GRB_RL2, H_GRB_RH2, H_GRB_RL3, H_GRB_RH3
00126  , H_GRB_RL4, H_GRB_RH4, H_GRB_RL5, H_GRB_RH5
00127  , H_GRB_RL6, H_GRB_RH6, H_GRB_RL7, H_GRB_RH7
00128 } GRB_NAMES;
00129 
00130 /* Enum declaration for .  */
00131 typedef enum conditioncode_names {
00132   H_CC_CC_UC = 0, H_CC_CC_NET = 1, H_CC_CC_Z = 2, H_CC_CC_EQ = 2
00133  , H_CC_CC_NZ = 3, H_CC_CC_NE = 3, H_CC_CC_V = 4, H_CC_CC_NV = 5
00134  , H_CC_CC_N = 6, H_CC_CC_NN = 7, H_CC_CC_ULT = 8, H_CC_CC_UGE = 9
00135  , H_CC_CC_C = 8, H_CC_CC_NC = 9, H_CC_CC_SGT = 10, H_CC_CC_SLE = 11
00136  , H_CC_CC_SLT = 12, H_CC_CC_SGE = 13, H_CC_CC_UGT = 14, H_CC_CC_ULE = 15
00137 } CONDITIONCODE_NAMES;
00138 
00139 /* Enum declaration for .  */
00140 typedef enum extconditioncode_names {
00141   H_ECC_CC_UC = 0, H_ECC_CC_NET = 2, H_ECC_CC_Z = 4, H_ECC_CC_EQ = 4
00142  , H_ECC_CC_NZ = 6, H_ECC_CC_NE = 6, H_ECC_CC_V = 8, H_ECC_CC_NV = 10
00143  , H_ECC_CC_N = 12, H_ECC_CC_NN = 14, H_ECC_CC_ULT = 16, H_ECC_CC_UGE = 18
00144  , H_ECC_CC_C = 16, H_ECC_CC_NC = 18, H_ECC_CC_SGT = 20, H_ECC_CC_SLE = 22
00145  , H_ECC_CC_SLT = 24, H_ECC_CC_SGE = 26, H_ECC_CC_UGT = 28, H_ECC_CC_ULE = 30
00146  , H_ECC_CC_NUSR0 = 1, H_ECC_CC_NUSR1 = 3, H_ECC_CC_USR0 = 5, H_ECC_CC_USR1 = 7
00147 } EXTCONDITIONCODE_NAMES;
00148 
00149 /* Enum declaration for .  */
00150 typedef enum grb8_names {
00151   H_GRB8_DPP0 = 0, H_GRB8_DPP1 = 1, H_GRB8_DPP2 = 2, H_GRB8_DPP3 = 3
00152  , H_GRB8_PSW = 136, H_GRB8_CP = 8, H_GRB8_MDL = 7, H_GRB8_MDH = 6
00153  , H_GRB8_MDC = 135, H_GRB8_SP = 9, H_GRB8_CSP = 4, H_GRB8_VECSEG = 137
00154  , H_GRB8_STKOV = 10, H_GRB8_STKUN = 11, H_GRB8_CPUCON1 = 12, H_GRB8_CPUCON2 = 13
00155  , H_GRB8_ZEROS = 142, H_GRB8_ONES = 143, H_GRB8_SPSEG = 134, H_GRB8_TFR = 214
00156  , H_GRB8_RL0 = 240, H_GRB8_RH0 = 241, H_GRB8_RL1 = 242, H_GRB8_RH1 = 243
00157  , H_GRB8_RL2 = 244, H_GRB8_RH2 = 245, H_GRB8_RL3 = 246, H_GRB8_RH3 = 247
00158  , H_GRB8_RL4 = 248, H_GRB8_RH4 = 249, H_GRB8_RL5 = 250, H_GRB8_RH5 = 251
00159  , H_GRB8_RL6 = 252, H_GRB8_RH6 = 253, H_GRB8_RL7 = 254, H_GRB8_RH7 = 255
00160 } GRB8_NAMES;
00161 
00162 /* Enum declaration for .  */
00163 typedef enum r8_names {
00164   H_R8_DPP0 = 0, H_R8_DPP1 = 1, H_R8_DPP2 = 2, H_R8_DPP3 = 3
00165  , H_R8_PSW = 136, H_R8_CP = 8, H_R8_MDL = 7, H_R8_MDH = 6
00166  , H_R8_MDC = 135, H_R8_SP = 9, H_R8_CSP = 4, H_R8_VECSEG = 137
00167  , H_R8_STKOV = 10, H_R8_STKUN = 11, H_R8_CPUCON1 = 12, H_R8_CPUCON2 = 13
00168  , H_R8_ZEROS = 142, H_R8_ONES = 143, H_R8_SPSEG = 134, H_R8_TFR = 214
00169  , H_R8_R0 = 240, H_R8_R1 = 241, H_R8_R2 = 242, H_R8_R3 = 243
00170  , H_R8_R4 = 244, H_R8_R5 = 245, H_R8_R6 = 246, H_R8_R7 = 247
00171  , H_R8_R8 = 248, H_R8_R9 = 249, H_R8_R10 = 250, H_R8_R11 = 251
00172  , H_R8_R12 = 252, H_R8_R13 = 253, H_R8_R14 = 254, H_R8_R15 = 255
00173 } R8_NAMES;
00174 
00175 /* Enum declaration for .  */
00176 typedef enum regmem8_names {
00177   H_REGMEM8_DPP0 = 0, H_REGMEM8_DPP1 = 1, H_REGMEM8_DPP2 = 2, H_REGMEM8_DPP3 = 3
00178  , H_REGMEM8_PSW = 136, H_REGMEM8_CP = 8, H_REGMEM8_MDL = 7, H_REGMEM8_MDH = 6
00179  , H_REGMEM8_MDC = 135, H_REGMEM8_SP = 9, H_REGMEM8_CSP = 4, H_REGMEM8_VECSEG = 137
00180  , H_REGMEM8_STKOV = 10, H_REGMEM8_STKUN = 11, H_REGMEM8_CPUCON1 = 12, H_REGMEM8_CPUCON2 = 13
00181  , H_REGMEM8_ZEROS = 142, H_REGMEM8_ONES = 143, H_REGMEM8_SPSEG = 134, H_REGMEM8_TFR = 214
00182  , H_REGMEM8_R0 = 240, H_REGMEM8_R1 = 241, H_REGMEM8_R2 = 242, H_REGMEM8_R3 = 243
00183  , H_REGMEM8_R4 = 244, H_REGMEM8_R5 = 245, H_REGMEM8_R6 = 246, H_REGMEM8_R7 = 247
00184  , H_REGMEM8_R8 = 248, H_REGMEM8_R9 = 249, H_REGMEM8_R10 = 250, H_REGMEM8_R11 = 251
00185  , H_REGMEM8_R12 = 252, H_REGMEM8_R13 = 253, H_REGMEM8_R14 = 254, H_REGMEM8_R15 = 255
00186 } REGMEM8_NAMES;
00187 
00188 /* Enum declaration for .  */
00189 typedef enum regdiv8_names {
00190   H_REGDIV8_R0 = 0, H_REGDIV8_R1 = 17, H_REGDIV8_R2 = 34, H_REGDIV8_R3 = 51
00191  , H_REGDIV8_R4 = 68, H_REGDIV8_R5 = 85, H_REGDIV8_R6 = 102, H_REGDIV8_R7 = 119
00192  , H_REGDIV8_R8 = 136, H_REGDIV8_R9 = 153, H_REGDIV8_R10 = 170, H_REGDIV8_R11 = 187
00193  , H_REGDIV8_R12 = 204, H_REGDIV8_R13 = 221, H_REGDIV8_R14 = 238, H_REGDIV8_R15 = 255
00194 } REGDIV8_NAMES;
00195 
00196 /* Enum declaration for .  */
00197 typedef enum reg0_name {
00198   H_REG0_0X1 = 1, H_REG0_0X2 = 2, H_REG0_0X3 = 3, H_REG0_0X4 = 4
00199  , H_REG0_0X5 = 5, H_REG0_0X6 = 6, H_REG0_0X7 = 7, H_REG0_0X8 = 8
00200  , H_REG0_0X9 = 9, H_REG0_0XA = 10, H_REG0_0XB = 11, H_REG0_0XC = 12
00201  , H_REG0_0XD = 13, H_REG0_0XE = 14, H_REG0_0XF = 15, H_REG0_1 = 1
00202  , H_REG0_2 = 2, H_REG0_3 = 3, H_REG0_4 = 4, H_REG0_5 = 5
00203  , H_REG0_6 = 6, H_REG0_7 = 7, H_REG0_8 = 8, H_REG0_9 = 9
00204  , H_REG0_10 = 10, H_REG0_11 = 11, H_REG0_12 = 12, H_REG0_13 = 13
00205  , H_REG0_14 = 14, H_REG0_15 = 15
00206 } REG0_NAME;
00207 
00208 /* Enum declaration for .  */
00209 typedef enum reg0_name1 {
00210   H_REG01_0X1 = 1, H_REG01_0X2 = 2, H_REG01_0X3 = 3, H_REG01_0X4 = 4
00211  , H_REG01_0X5 = 5, H_REG01_0X6 = 6, H_REG01_0X7 = 7, H_REG01_1 = 1
00212  , H_REG01_2 = 2, H_REG01_3 = 3, H_REG01_4 = 4, H_REG01_5 = 5
00213  , H_REG01_6 = 6, H_REG01_7 = 7
00214 } REG0_NAME1;
00215 
00216 /* Enum declaration for .  */
00217 typedef enum regbmem8_names {
00218   H_REGBMEM8_DPP0 = 0, H_REGBMEM8_DPP1 = 1, H_REGBMEM8_DPP2 = 2, H_REGBMEM8_DPP3 = 3
00219  , H_REGBMEM8_PSW = 136, H_REGBMEM8_CP = 8, H_REGBMEM8_MDL = 7, H_REGBMEM8_MDH = 6
00220  , H_REGBMEM8_MDC = 135, H_REGBMEM8_SP = 9, H_REGBMEM8_CSP = 4, H_REGBMEM8_VECSEG = 137
00221  , H_REGBMEM8_STKOV = 10, H_REGBMEM8_STKUN = 11, H_REGBMEM8_CPUCON1 = 12, H_REGBMEM8_CPUCON2 = 13
00222  , H_REGBMEM8_ZEROS = 142, H_REGBMEM8_ONES = 143, H_REGBMEM8_SPSEG = 134, H_REGBMEM8_TFR = 214
00223  , H_REGBMEM8_RL0 = 240, H_REGBMEM8_RH0 = 241, H_REGBMEM8_RL1 = 242, H_REGBMEM8_RH1 = 243
00224  , H_REGBMEM8_RL2 = 244, H_REGBMEM8_RH2 = 245, H_REGBMEM8_RL3 = 246, H_REGBMEM8_RH3 = 247
00225  , H_REGBMEM8_RL4 = 248, H_REGBMEM8_RH4 = 249, H_REGBMEM8_RL5 = 250, H_REGBMEM8_RH5 = 251
00226  , H_REGBMEM8_RL6 = 252, H_REGBMEM8_RH6 = 253, H_REGBMEM8_RL7 = 254, H_REGBMEM8_RH7 = 255
00227 } REGBMEM8_NAMES;
00228 
00229 /* Enum declaration for .  */
00230 typedef enum memgr8_names {
00231   H_MEMGR8_DPP0 = 65024, H_MEMGR8_DPP1 = 65026, H_MEMGR8_DPP2 = 65028, H_MEMGR8_DPP3 = 65030
00232  , H_MEMGR8_PSW = 65296, H_MEMGR8_CP = 65040, H_MEMGR8_MDL = 65038, H_MEMGR8_MDH = 65036
00233  , H_MEMGR8_MDC = 65294, H_MEMGR8_SP = 65042, H_MEMGR8_CSP = 65032, H_MEMGR8_VECSEG = 65298
00234  , H_MEMGR8_STKOV = 65044, H_MEMGR8_STKUN = 65046, H_MEMGR8_CPUCON1 = 65048, H_MEMGR8_CPUCON2 = 65050
00235  , H_MEMGR8_ZEROS = 65308, H_MEMGR8_ONES = 65310, H_MEMGR8_SPSEG = 65292, H_MEMGR8_TFR = 65452
00236 } MEMGR8_NAMES;
00237 
00238 /* Attributes.  */
00239 
00240 /* Enum declaration for machine type selection.  */
00241 typedef enum mach_attr {
00242   MACH_BASE, MACH_XC16X, MACH_MAX
00243 } MACH_ATTR;
00244 
00245 /* Enum declaration for instruction set selection.  */
00246 typedef enum isa_attr {
00247   ISA_XC16X, ISA_MAX
00248 } ISA_ATTR;
00249 
00250 /* Enum declaration for parallel execution pipeline selection.  */
00251 typedef enum pipe_attr {
00252   PIPE_NONE, PIPE_OS
00253 } PIPE_ATTR;
00254 
00255 /* Number of architecture variants.  */
00256 #define MAX_ISAS  1
00257 #define MAX_MACHS ((int) MACH_MAX)
00258 
00259 /* Ifield support.  */
00260 
00261 /* Ifield attribute indices.  */
00262 
00263 /* Enum declaration for cgen_ifld attrs.  */
00264 typedef enum cgen_ifld_attr {
00265   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00266  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
00267  , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00268 } CGEN_IFLD_ATTR;
00269 
00270 /* Number of non-boolean elements in cgen_ifld_attr.  */
00271 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00272 
00273 /* cgen_ifld attribute accessor macros.  */
00274 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00275 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00276 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00277 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00278 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00279 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00280 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00281 #define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)
00282 
00283 /* Enum declaration for xc16x ifield types.  */
00284 typedef enum ifield_type {
00285   XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2
00286  , XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND
00287  , XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2
00288  , XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3
00289  , XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16
00290  , XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8
00291  , XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8
00292  , XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8
00293  , XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16
00294  , XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3
00295  , XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT
00296  , XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16
00297  , XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2
00298  , XC16X_F_POF, XC16X_F_MAX
00299 } IFIELD_TYPE;
00300 
00301 #define MAX_IFLD ((int) XC16X_F_MAX)
00302 
00303 /* Hardware attribute indices.  */
00304 
00305 /* Enum declaration for cgen_hw attrs.  */
00306 typedef enum cgen_hw_attr {
00307   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00308  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00309 } CGEN_HW_ATTR;
00310 
00311 /* Number of non-boolean elements in cgen_hw_attr.  */
00312 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00313 
00314 /* cgen_hw attribute accessor macros.  */
00315 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00316 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00317 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00318 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00319 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00320 
00321 /* Enum declaration for xc16x hardware types.  */
00322 typedef enum cgen_hw_type {
00323   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00324  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_EXT
00325  , HW_H_PSW, HW_H_GRB, HW_H_CC, HW_H_ECC
00326  , HW_H_GRB8, HW_H_R8, HW_H_REGMEM8, HW_H_REGDIV8
00327  , HW_H_R0, HW_H_R01, HW_H_REGBMEM8, HW_H_MEMGR8
00328  , HW_H_COND, HW_H_CBIT, HW_H_SGTDIS, HW_MAX
00329 } CGEN_HW_TYPE;
00330 
00331 #define MAX_HW ((int) HW_MAX)
00332 
00333 /* Operand attribute indices.  */
00334 
00335 /* Enum declaration for cgen_operand attrs.  */
00336 typedef enum cgen_operand_attr {
00337   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00338  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00339  , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX
00340  , CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX, CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS
00341  , CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00342 } CGEN_OPERAND_ATTR;
00343 
00344 /* Number of non-boolean elements in cgen_operand_attr.  */
00345 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00346 
00347 /* cgen_operand attribute accessor macros.  */
00348 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00349 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00350 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00351 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00352 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00353 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00354 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00355 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00356 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00357 #define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)
00358 #define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
00359 #define CGEN_ATTR_CGEN_OPERAND_DOT_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_DOT_PREFIX)) != 0)
00360 #define CGEN_ATTR_CGEN_OPERAND_POF_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_POF_PREFIX)) != 0)
00361 #define CGEN_ATTR_CGEN_OPERAND_PAG_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PAG_PREFIX)) != 0)
00362 #define CGEN_ATTR_CGEN_OPERAND_SOF_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SOF_PREFIX)) != 0)
00363 #define CGEN_ATTR_CGEN_OPERAND_SEG_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEG_PREFIX)) != 0)
00364 
00365 /* Enum declaration for xc16x operand types.  */
00366 typedef enum cgen_operand_type {
00367   XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI
00368  , XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1
00369  , XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2
00370  , XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8
00371  , XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8
00372  , XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8
00373  , XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR
00374  , XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1
00375  , XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2
00376  , XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01
00377  , XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY
00378  , XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT
00379  , XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM
00380  , XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16
00381  , XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH
00382  , XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF
00383  , XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX
00384 } CGEN_OPERAND_TYPE;
00385 
00386 /* Number of operands types.  */
00387 #define MAX_OPERANDS 65
00388 
00389 /* Maximum number of operands referenced by any insn.  */
00390 #define MAX_OPERAND_INSTANCES 8
00391 
00392 /* Insn attribute indices.  */
00393 
00394 /* Enum declaration for cgen_insn attrs.  */
00395 typedef enum cgen_insn_attr {
00396   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00397  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00398  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
00399  , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
00400 } CGEN_INSN_ATTR;
00401 
00402 /* Number of non-boolean elements in cgen_insn_attr.  */
00403 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00404 
00405 /* cgen_insn attribute accessor macros.  */
00406 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00407 #define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
00408 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00409 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00410 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00411 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00412 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00413 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00414 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00415 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00416 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00417 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00418 
00419 /* cgen.h uses things we just defined.  */
00420 #include "opcode/cgen.h"
00421 
00422 extern const struct cgen_ifld xc16x_cgen_ifld_table[];
00423 
00424 /* Attributes.  */
00425 extern const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[];
00426 extern const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[];
00427 extern const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[];
00428 extern const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[];
00429 
00430 /* Hardware decls.  */
00431 
00432 extern CGEN_KEYWORD xc16x_cgen_opval_gr_names;
00433 extern CGEN_KEYWORD xc16x_cgen_opval_ext_names;
00434 extern CGEN_KEYWORD xc16x_cgen_opval_psw_names;
00435 extern CGEN_KEYWORD xc16x_cgen_opval_grb_names;
00436 extern CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names;
00437 extern CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names;
00438 extern CGEN_KEYWORD xc16x_cgen_opval_grb8_names;
00439 extern CGEN_KEYWORD xc16x_cgen_opval_r8_names;
00440 extern CGEN_KEYWORD xc16x_cgen_opval_regmem8_names;
00441 extern CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names;
00442 extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name;
00443 extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name1;
00444 extern CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names;
00445 extern CGEN_KEYWORD xc16x_cgen_opval_memgr8_names;
00446 
00447 extern const CGEN_HW_ENTRY xc16x_cgen_hw_table[];
00448 
00449 
00450 
00451 #endif /* XC16X_CPU_H */