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cell-binutils  2.17cvs20070401
xc16x-desc.c
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00001 /* CPU data for xc16x.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "xc16x-desc.h"
00032 #include "xc16x-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "xc16x", MACH_XC16X },
00050   { "max", MACH_MAX },
00051   { 0, 0 }
00052 };
00053 
00054 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00055 {
00056   { "xc16x", ISA_XC16X },
00057   { "max", ISA_MAX },
00058   { 0, 0 }
00059 };
00060 
00061 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
00062 {
00063   { "NONE", PIPE_NONE },
00064   { "OS", PIPE_OS },
00065   { 0, 0 }
00066 };
00067 
00068 const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
00069 {
00070   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00071   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00072   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00073   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00074   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00075   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00076   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00077   { "RELOC", &bool_attr[0], &bool_attr[0] },
00078   { 0, 0, 0 }
00079 };
00080 
00081 const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
00082 {
00083   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00084   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00085   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00086   { "PC", &bool_attr[0], &bool_attr[0] },
00087   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00088   { 0, 0, 0 }
00089 };
00090 
00091 const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
00092 {
00093   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00094   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00095   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00096   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00097   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00098   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00099   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00100   { "RELAX", &bool_attr[0], &bool_attr[0] },
00101   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00102   { "RELOC", &bool_attr[0], &bool_attr[0] },
00103   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
00104   { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
00105   { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
00106   { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
00107   { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
00108   { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
00109   { 0, 0, 0 }
00110 };
00111 
00112 const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
00113 {
00114   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00115   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
00116   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00117   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00118   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00119   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00120   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00121   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00122   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00123   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00124   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00125   { "PBB", &bool_attr[0], &bool_attr[0] },
00126   { 0, 0, 0 }
00127 };
00128 
00129 /* Instruction set variants.  */
00130 
00131 static const CGEN_ISA xc16x_cgen_isa_table[] = {
00132   { "xc16x", 16, 32, 16, 32 },
00133   { 0, 0, 0, 0, 0 }
00134 };
00135 
00136 /* Machine variants.  */
00137 
00138 static const CGEN_MACH xc16x_cgen_mach_table[] = {
00139   { "xc16x", "xc16x", MACH_XC16X, 32 },
00140   { 0, 0, 0, 0 }
00141 };
00142 
00143 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
00144 {
00145   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00146   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
00147   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
00148   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
00149   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
00150   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
00151   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
00152   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
00153   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
00154   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
00155   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
00156   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
00157   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
00158   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
00159   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
00160   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
00161 };
00162 
00163 CGEN_KEYWORD xc16x_cgen_opval_gr_names =
00164 {
00165   & xc16x_cgen_opval_gr_names_entries[0],
00166   16,
00167   0, 0, 0, 0, ""
00168 };
00169 
00170 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
00171 {
00172   { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
00173   { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
00174   { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
00175   { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
00176   { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
00177   { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
00178   { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
00179   { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
00180 };
00181 
00182 CGEN_KEYWORD xc16x_cgen_opval_ext_names =
00183 {
00184   & xc16x_cgen_opval_ext_names_entries[0],
00185   8,
00186   0, 0, 0, 0, ""
00187 };
00188 
00189 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
00190 {
00191   { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
00192   { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
00193   { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
00194   { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
00195   { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
00196   { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
00197   { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
00198   { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
00199   { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
00200   { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
00201   { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
00202   { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
00203   { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
00204   { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
00205   { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
00206   { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
00207   { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
00208 };
00209 
00210 CGEN_KEYWORD xc16x_cgen_opval_psw_names =
00211 {
00212   & xc16x_cgen_opval_psw_names_entries[0],
00213   17,
00214   0, 0, 0, 0, ""
00215 };
00216 
00217 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
00218 {
00219   { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
00220   { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
00221   { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
00222   { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
00223   { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
00224   { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
00225   { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
00226   { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
00227   { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
00228   { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
00229   { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
00230   { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
00231   { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
00232   { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
00233   { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
00234   { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
00235 };
00236 
00237 CGEN_KEYWORD xc16x_cgen_opval_grb_names =
00238 {
00239   & xc16x_cgen_opval_grb_names_entries[0],
00240   16,
00241   0, 0, 0, 0, ""
00242 };
00243 
00244 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
00245 {
00246   { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
00247   { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
00248   { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
00249   { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
00250   { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
00251   { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
00252   { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
00253   { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
00254   { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
00255   { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
00256   { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
00257   { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
00258   { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
00259   { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
00260   { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
00261   { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
00262   { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
00263   { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
00264   { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
00265   { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
00266 };
00267 
00268 CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
00269 {
00270   & xc16x_cgen_opval_conditioncode_names_entries[0],
00271   20,
00272   0, 0, 0, 0, ""
00273 };
00274 
00275 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
00276 {
00277   { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
00278   { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
00279   { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
00280   { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
00281   { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
00282   { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
00283   { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
00284   { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
00285   { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
00286   { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
00287   { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
00288   { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
00289   { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
00290   { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
00291   { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
00292   { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
00293   { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
00294   { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
00295   { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
00296   { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
00297   { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
00298   { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
00299   { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
00300   { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
00301 };
00302 
00303 CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
00304 {
00305   & xc16x_cgen_opval_extconditioncode_names_entries[0],
00306   24,
00307   0, 0, 0, 0, ""
00308 };
00309 
00310 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
00311 {
00312   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
00313   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
00314   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
00315   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
00316   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
00317   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
00318   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
00319   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
00320   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
00321   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
00322   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
00323   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
00324   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
00325   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
00326   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
00327   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
00328   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
00329   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
00330   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
00331   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
00332   { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
00333   { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
00334   { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
00335   { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
00336   { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
00337   { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
00338   { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
00339   { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
00340   { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
00341   { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
00342   { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
00343   { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
00344   { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
00345   { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
00346   { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
00347   { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
00348 };
00349 
00350 CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
00351 {
00352   & xc16x_cgen_opval_grb8_names_entries[0],
00353   36,
00354   0, 0, 0, 0, ""
00355 };
00356 
00357 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
00358 {
00359   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
00360   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
00361   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
00362   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
00363   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
00364   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
00365   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
00366   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
00367   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
00368   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
00369   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
00370   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
00371   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
00372   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
00373   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
00374   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
00375   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
00376   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
00377   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
00378   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
00379   { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
00380   { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
00381   { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
00382   { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
00383   { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
00384   { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
00385   { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
00386   { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
00387   { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
00388   { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
00389   { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
00390   { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
00391   { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
00392   { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
00393   { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
00394   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
00395 };
00396 
00397 CGEN_KEYWORD xc16x_cgen_opval_r8_names =
00398 {
00399   & xc16x_cgen_opval_r8_names_entries[0],
00400   36,
00401   0, 0, 0, 0, ""
00402 };
00403 
00404 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
00405 {
00406   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
00407   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
00408   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
00409   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
00410   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
00411   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
00412   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
00413   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
00414   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
00415   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
00416   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
00417   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
00418   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
00419   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
00420   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
00421   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
00422   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
00423   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
00424   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
00425   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
00426   { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
00427   { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
00428   { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
00429   { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
00430   { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
00431   { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
00432   { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
00433   { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
00434   { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
00435   { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
00436   { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
00437   { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
00438   { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
00439   { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
00440   { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
00441   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
00442 };
00443 
00444 CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
00445 {
00446   & xc16x_cgen_opval_regmem8_names_entries[0],
00447   36,
00448   0, 0, 0, 0, ""
00449 };
00450 
00451 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
00452 {
00453   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00454   { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
00455   { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
00456   { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
00457   { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
00458   { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
00459   { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
00460   { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
00461   { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
00462   { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
00463   { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
00464   { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
00465   { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
00466   { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
00467   { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
00468   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
00469 };
00470 
00471 CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
00472 {
00473   & xc16x_cgen_opval_regdiv8_names_entries[0],
00474   16,
00475   0, 0, 0, 0, ""
00476 };
00477 
00478 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
00479 {
00480   { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
00481   { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
00482   { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
00483   { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
00484   { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
00485   { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
00486   { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
00487   { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
00488   { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
00489   { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
00490   { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
00491   { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
00492   { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
00493   { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
00494   { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
00495   { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
00496   { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
00497   { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
00498   { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
00499   { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
00500   { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
00501   { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
00502   { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
00503   { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
00504   { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
00505   { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
00506   { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
00507   { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
00508   { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
00509   { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
00510 };
00511 
00512 CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
00513 {
00514   & xc16x_cgen_opval_reg0_name_entries[0],
00515   30,
00516   0, 0, 0, 0, ""
00517 };
00518 
00519 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
00520 {
00521   { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
00522   { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
00523   { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
00524   { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
00525   { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
00526   { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
00527   { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
00528   { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
00529   { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
00530   { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
00531   { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
00532   { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
00533   { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
00534   { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
00535 };
00536 
00537 CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
00538 {
00539   & xc16x_cgen_opval_reg0_name1_entries[0],
00540   14,
00541   0, 0, 0, 0, ""
00542 };
00543 
00544 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
00545 {
00546   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
00547   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
00548   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
00549   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
00550   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
00551   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
00552   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
00553   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
00554   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
00555   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
00556   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
00557   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
00558   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
00559   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
00560   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
00561   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
00562   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
00563   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
00564   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
00565   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
00566   { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
00567   { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
00568   { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
00569   { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
00570   { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
00571   { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
00572   { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
00573   { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
00574   { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
00575   { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
00576   { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
00577   { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
00578   { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
00579   { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
00580   { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
00581   { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
00582 };
00583 
00584 CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
00585 {
00586   & xc16x_cgen_opval_regbmem8_names_entries[0],
00587   36,
00588   0, 0, 0, 0, ""
00589 };
00590 
00591 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
00592 {
00593   { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
00594   { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
00595   { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
00596   { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
00597   { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
00598   { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
00599   { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
00600   { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
00601   { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
00602   { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
00603   { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
00604   { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
00605   { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
00606   { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
00607   { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
00608   { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
00609   { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
00610   { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
00611   { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
00612   { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
00613 };
00614 
00615 CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
00616 {
00617   & xc16x_cgen_opval_memgr8_names_entries[0],
00618   20,
00619   0, 0, 0, 0, ""
00620 };
00621 
00622 
00623 /* The hardware table.  */
00624 
00625 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00626 #define A(a) (1 << CGEN_HW_##a)
00627 #else
00628 #define A(a) (1 << CGEN_HW_a)
00629 #endif
00630 
00631 const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
00632 {
00633   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00634   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00635   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00636   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00637   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00638   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00639   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00640   { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00641   { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00642   { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00643   { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00644   { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00645   { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00646   { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00647   { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00648   { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00649   { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00650   { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00651   { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00652   { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00653   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00654   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00655   { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00656   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00657 };
00658 
00659 #undef A
00660 
00661 
00662 /* The instruction field table.  */
00663 
00664 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00665 #define A(a) (1 << CGEN_IFLD_##a)
00666 #else
00667 #define A(a) (1 << CGEN_IFLD_a)
00668 #endif
00669 
00670 const CGEN_IFLD xc16x_cgen_ifld_table[] =
00671 {
00672   { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00673   { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00674   { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00675   { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00676   { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00677   { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00678   { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00679   { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00680   { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00681   { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00682   { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00683   { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00684   { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00685   { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00686   { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00687   { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00688   { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00689   { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00690   { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00691   { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00692   { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00693   { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00694   { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00695   { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00696   { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00697   { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00698   { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00699   { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00700   { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00701   { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00702   { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00703   { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00704   { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00705   { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00706   { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00707   { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00708   { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00709   { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00710   { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00711   { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00712   { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00713   { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00714   { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00715   { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00716   { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00717   { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00718   { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00719   { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00720   { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00721   { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00722   { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00723   { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00724   { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00725   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00726 };
00727 
00728 #undef A
00729 
00730 
00731 
00732 /* multi ifield declarations */
00733 
00734 
00735 
00736 /* multi ifield definitions */
00737 
00738 
00739 /* The operand table.  */
00740 
00741 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00742 #define A(a) (1 << CGEN_OPERAND_##a)
00743 #else
00744 #define A(a) (1 << CGEN_OPERAND_a)
00745 #endif
00746 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00747 #define OPERAND(op) XC16X_OPERAND_##op
00748 #else
00749 #define OPERAND(op) XC16X_OPERAND_op
00750 #endif
00751 
00752 const CGEN_OPERAND xc16x_cgen_operand_table[] =
00753 {
00754 /* pc: program counter */
00755   { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
00756     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } }, 
00757     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00758 /* sr: source register */
00759   { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
00760     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 
00761     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00762 /* dr: destination register */
00763   { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
00764     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 
00765     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00766 /* dri: destination register */
00767   { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
00768     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } }, 
00769     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00770 /* srb: source register */
00771   { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
00772     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 
00773     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00774 /* drb: destination register */
00775   { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
00776     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 
00777     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00778 /* sr2: 2 bit source register */
00779   { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
00780     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } }, 
00781     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00782 /* src1: source register 1 */
00783   { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
00784     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 
00785     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00786 /* src2: source register 2 */
00787   { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
00788     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 
00789     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00790 /* srdiv: source register 2 */
00791   { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
00792     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 
00793     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00794 /* RegNam: PSW bits */
00795   { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
00796     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 
00797     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00798 /* uimm2: 2 bit unsigned number */
00799   { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
00800     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } }, 
00801     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00802 /* uimm3: 3 bit unsigned number */
00803   { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
00804     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } }, 
00805     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00806 /* uimm4: 4 bit unsigned number */
00807   { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
00808     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } }, 
00809     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00810 /* uimm7: 7 bit trap number */
00811   { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
00812     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } }, 
00813     { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00814 /* uimm8: 8 bit unsigned immediate */
00815   { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
00816     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } }, 
00817     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00818 /* uimm16: 16 bit unsigned immediate */
00819   { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
00820     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } }, 
00821     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00822 /* upof16: 16 bit unsigned immediate */
00823   { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
00824     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } }, 
00825     { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00826 /* reg8: 8 bit word register number */
00827   { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
00828     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 
00829     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00830 /* regmem8: 8 bit word register number */
00831   { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
00832     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } }, 
00833     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00834 /* regbmem8: 8 bit byte register number */
00835   { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
00836     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } }, 
00837     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00838 /* regoff8: 8 bit word register number */
00839   { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
00840     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } }, 
00841     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00842 /* reghi8: 8 bit word register number */
00843   { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
00844     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } }, 
00845     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00846 /* regb8: 8 bit byte register number */
00847   { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
00848     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } }, 
00849     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00850 /* genreg: 8 bit word register number */
00851   { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
00852     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } }, 
00853     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00854 /* seg: 8 bit segment number */
00855   { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
00856     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } }, 
00857     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00858 /* seghi8: 8 bit hi segment number */
00859   { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
00860     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } }, 
00861     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00862 /* caddr: 16 bit address offset */
00863   { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
00864     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 
00865     { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00866 /* rel: 8 bit signed relative offset */
00867   { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
00868     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } }, 
00869     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00870 /* relhi: hi 8 bit signed relative offset */
00871   { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
00872     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } }, 
00873     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00874 /* condbit: condition bit */
00875   { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
00876     { 0, { (const PTR) 0 } }, 
00877     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00878 /* bit1: gap of 1 bit */
00879   { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
00880     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } }, 
00881     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00882 /* bit2: gap of 2 bits */
00883   { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
00884     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } }, 
00885     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00886 /* bit4: gap of 4 bits */
00887   { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
00888     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } }, 
00889     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00890 /* lbit4: gap of 4 bits */
00891   { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
00892     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } }, 
00893     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00894 /* lbit2: gap of 2 bits */
00895   { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
00896     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } }, 
00897     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00898 /* bit8: gap of 8 bits */
00899   { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
00900     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } }, 
00901     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00902 /* u4: gap of 4 bits */
00903   { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
00904     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } }, 
00905     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00906 /* bitone: field of 1 bit */
00907   { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
00908     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } }, 
00909     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00910 /* bit01: field of 1 bit */
00911   { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
00912     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } }, 
00913     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00914 /* cond: condition code */
00915   { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
00916     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } }, 
00917     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00918 /* icond: indirect condition code */
00919   { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
00920     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } }, 
00921     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00922 /* extcond: extended condition code */
00923   { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
00924     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } }, 
00925     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00926 /* memory: 16 bit memory */
00927   { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
00928     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } }, 
00929     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00930 /* memgr8: 16 bit memory */
00931   { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
00932     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } }, 
00933     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00934 /* cbit: carry bit */
00935   { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
00936     { 0, { (const PTR) 0 } }, 
00937     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00938 /* qbit: bit addr */
00939   { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
00940     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } }, 
00941     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00942 /* qlobit: bit addr */
00943   { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
00944     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } }, 
00945     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00946 /* qhibit: bit addr */
00947   { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
00948     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } }, 
00949     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00950 /* mask8: 8 bit mask */
00951   { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
00952     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } }, 
00953     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00954 /* masklo8: 8 bit mask */
00955   { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
00956     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } }, 
00957     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00958 /* pagenum: 10 bit page number */
00959   { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
00960     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } }, 
00961     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00962 /* data8: 8 bit data */
00963   { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
00964     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } }, 
00965     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00966 /* datahi8: 8 bit data */
00967   { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
00968     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } }, 
00969     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00970 /* sgtdisbit: segmentation enable bit */
00971   { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
00972     { 0, { (const PTR) 0 } }, 
00973     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00974 /* upag16: 16 bit unsigned immediate */
00975   { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
00976     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } }, 
00977     { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00978 /* useg8: 8 bit segment  */
00979   { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
00980     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } }, 
00981     { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00982 /* useg16: 16 bit address offset */
00983   { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
00984     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 
00985     { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00986 /* usof16: 16 bit address offset */
00987   { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
00988     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 
00989     { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00990 /* hash: # prefix */
00991   { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
00992     { 0, { (const PTR) 0 } }, 
00993     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00994 /* dot: . prefix */
00995   { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
00996     { 0, { (const PTR) 0 } }, 
00997     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00998 /* pof: pof: prefix */
00999   { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
01000     { 0, { (const PTR) 0 } }, 
01001     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
01002 /* pag: pag: prefix */
01003   { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
01004     { 0, { (const PTR) 0 } }, 
01005     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
01006 /* sof: sof: prefix */
01007   { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
01008     { 0, { (const PTR) 0 } }, 
01009     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
01010 /* segm: seg: prefix */
01011   { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
01012     { 0, { (const PTR) 0 } }, 
01013     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
01014 /* sentinel */
01015   { 0, 0, 0, 0, 0,
01016     { 0, { (const PTR) 0 } },
01017     { 0, { { { (1<<MACH_BASE), 0 } } } } }
01018 };
01019 
01020 #undef A
01021 
01022 
01023 /* The instruction table.  */
01024 
01025 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
01026 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01027 #define A(a) (1 << CGEN_INSN_##a)
01028 #else
01029 #define A(a) (1 << CGEN_INSN_a)
01030 #endif
01031 
01032 static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
01033 {
01034   /* Special null first entry.
01035      A `num' value of zero is thus invalid.
01036      Also, the special `invalid' insn resides here.  */
01037   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
01038 /* add $reg8,$pof$upof16 */
01039   {
01040     XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
01041     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01042   },
01043 /* sub $reg8,$pof$upof16 */
01044   {
01045     XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
01046     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01047   },
01048 /* addb $regb8,$pof$upof16 */
01049   {
01050     XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
01051     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01052   },
01053 /* subb $regb8,$pof$upof16 */
01054   {
01055     XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
01056     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01057   },
01058 /* add $reg8,$pag$upag16 */
01059   {
01060     XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
01061     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01062   },
01063 /* sub $reg8,$pag$upag16 */
01064   {
01065     XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
01066     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01067   },
01068 /* addb $regb8,$pag$upag16 */
01069   {
01070     XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
01071     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01072   },
01073 /* subb $regb8,$pag$upag16 */
01074   {
01075     XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
01076     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01077   },
01078 /* addc $reg8,$pof$upof16 */
01079   {
01080     XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
01081     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01082   },
01083 /* subc $reg8,$pof$upof16 */
01084   {
01085     XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
01086     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01087   },
01088 /* addcb $regb8,$pof$upof16 */
01089   {
01090     XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
01091     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01092   },
01093 /* subcb $regb8,$pof$upof16 */
01094   {
01095     XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
01096     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01097   },
01098 /* addc $reg8,$pag$upag16 */
01099   {
01100     XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
01101     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01102   },
01103 /* subc $reg8,$pag$upag16 */
01104   {
01105     XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
01106     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01107   },
01108 /* addcb $regb8,$pag$upag16 */
01109   {
01110     XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
01111     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01112   },
01113 /* subcb $regb8,$pag$upag16 */
01114   {
01115     XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
01116     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01117   },
01118 /* add $pof$upof16,$reg8 */
01119   {
01120     XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
01121     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01122   },
01123 /* sub $pof$upof16,$reg8 */
01124   {
01125     XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
01126     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01127   },
01128 /* addb $pof$upof16,$regb8 */
01129   {
01130     XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
01131     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01132   },
01133 /* subb $pof$upof16,$regb8 */
01134   {
01135     XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
01136     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01137   },
01138 /* addc $pof$upof16,$reg8 */
01139   {
01140     XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
01141     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01142   },
01143 /* subc $pof$upof16,$reg8 */
01144   {
01145     XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
01146     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01147   },
01148 /* addcb $pof$upof16,$regb8 */
01149   {
01150     XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
01151     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01152   },
01153 /* subcb $pof$upof16,$regb8 */
01154   {
01155     XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
01156     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01157   },
01158 /* add $reg8,$hash$pof$uimm16 */
01159   {
01160     XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
01161     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01162   },
01163 /* sub $reg8,$hash$pof$uimm16 */
01164   {
01165     XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
01166     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01167   },
01168 /* add $reg8,$hash$pag$uimm16 */
01169   {
01170     XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
01171     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01172   },
01173 /* sub $reg8,$hash$pag$uimm16 */
01174   {
01175     XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
01176     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01177   },
01178 /* add $dr,$hash$pof$uimm3 */
01179   {
01180     XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
01181     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01182   },
01183 /* sub $dr,$hash$pof$uimm3 */
01184   {
01185     XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
01186     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01187   },
01188 /* addb $drb,$hash$pag$uimm3 */
01189   {
01190     XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
01191     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01192   },
01193 /* subb $drb,$hash$pag$uimm3 */
01194   {
01195     XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
01196     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01197   },
01198 /* add $dr,$hash$pag$uimm3 */
01199   {
01200     XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
01201     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01202   },
01203 /* sub $dr,$hash$pag$uimm3 */
01204   {
01205     XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
01206     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01207   },
01208 /* addb $drb,$hash$pof$uimm3 */
01209   {
01210     XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
01211     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01212   },
01213 /* subb $drb,$hash$pof$uimm3 */
01214   {
01215     XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
01216     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01217   },
01218 /* addb $regb8,$hash$pof$uimm8 */
01219   {
01220     XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
01221     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01222   },
01223 /* subb $regb8,$hash$pof$uimm8 */
01224   {
01225     XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
01226     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01227   },
01228 /* addb $regb8,$hash$pag$uimm8 */
01229   {
01230     XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
01231     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01232   },
01233 /* subb $regb8,$hash$pag$uimm8 */
01234   {
01235     XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
01236     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01237   },
01238 /* addc $reg8,$hash$pof$uimm16 */
01239   {
01240     XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
01241     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01242   },
01243 /* subc $reg8,$hash$pof$uimm16 */
01244   {
01245     XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
01246     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01247   },
01248 /* addc $reg8,$hash$pag$uimm16 */
01249   {
01250     XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
01251     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01252   },
01253 /* subc $reg8,$hash$pag$uimm16 */
01254   {
01255     XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
01256     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01257   },
01258 /* addc $dr,$hash$pof$uimm3 */
01259   {
01260     XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
01261     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01262   },
01263 /* subc $dr,$hash$pof$uimm3 */
01264   {
01265     XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
01266     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01267   },
01268 /* addcb $drb,$hash$pag$uimm3 */
01269   {
01270     XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
01271     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01272   },
01273 /* subcb $drb,$hash$pag$uimm3 */
01274   {
01275     XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
01276     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01277   },
01278 /* addc $dr,$hash$pag$uimm3 */
01279   {
01280     XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
01281     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01282   },
01283 /* subc $dr,$hash$pag$uimm3 */
01284   {
01285     XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
01286     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01287   },
01288 /* addcb $drb,$hash$pof$uimm3 */
01289   {
01290     XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
01291     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01292   },
01293 /* subcb $drb,$hash$pof$uimm3 */
01294   {
01295     XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
01296     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01297   },
01298 /* addcb $regb8,$hash$pof$uimm8 */
01299   {
01300     XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
01301     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01302   },
01303 /* subcb $regb8,$hash$pof$uimm8 */
01304   {
01305     XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
01306     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01307   },
01308 /* addcb $regb8,$hash$pag$uimm8 */
01309   {
01310     XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
01311     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01312   },
01313 /* subcb $regb8,$hash$pag$uimm8 */
01314   {
01315     XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
01316     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01317   },
01318 /* add $dr,$hash$uimm3 */
01319   {
01320     XC16X_INSN_ADDRI, "addri", "add", 16,
01321     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01322   },
01323 /* sub $dr,$hash$uimm3 */
01324   {
01325     XC16X_INSN_SUBRI, "subri", "sub", 16,
01326     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01327   },
01328 /* addb $drb,$hash$uimm3 */
01329   {
01330     XC16X_INSN_ADDBRI, "addbri", "addb", 16,
01331     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01332   },
01333 /* subb $drb,$hash$uimm3 */
01334   {
01335     XC16X_INSN_SUBBRI, "subbri", "subb", 16,
01336     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01337   },
01338 /* add $reg8,$hash$uimm16 */
01339   {
01340     XC16X_INSN_ADDRIM, "addrim", "add", 32,
01341     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01342   },
01343 /* sub $reg8,$hash$uimm16 */
01344   {
01345     XC16X_INSN_SUBRIM, "subrim", "sub", 32,
01346     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01347   },
01348 /* addb $regb8,$hash$uimm8 */
01349   {
01350     XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
01351     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01352   },
01353 /* subb $regb8,$hash$uimm8 */
01354   {
01355     XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
01356     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01357   },
01358 /* addc $dr,$hash$uimm3 */
01359   {
01360     XC16X_INSN_ADDCRI, "addcri", "addc", 16,
01361     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01362   },
01363 /* subc $dr,$hash$uimm3 */
01364   {
01365     XC16X_INSN_SUBCRI, "subcri", "subc", 16,
01366     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01367   },
01368 /* addcb $drb,$hash$uimm3 */
01369   {
01370     XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
01371     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01372   },
01373 /* subcb $drb,$hash$uimm3 */
01374   {
01375     XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
01376     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01377   },
01378 /* addc $reg8,$hash$uimm16 */
01379   {
01380     XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
01381     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01382   },
01383 /* subc $reg8,$hash$uimm16 */
01384   {
01385     XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
01386     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01387   },
01388 /* addcb $regb8,$hash$uimm8 */
01389   {
01390     XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
01391     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01392   },
01393 /* subcb $regb8,$hash$uimm8 */
01394   {
01395     XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
01396     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01397   },
01398 /* add $dr,$sr */
01399   {
01400     XC16X_INSN_ADDR, "addr", "add", 16,
01401     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01402   },
01403 /* sub $dr,$sr */
01404   {
01405     XC16X_INSN_SUBR, "subr", "sub", 16,
01406     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01407   },
01408 /* addb $drb,$srb */
01409   {
01410     XC16X_INSN_ADDBR, "addbr", "addb", 16,
01411     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01412   },
01413 /* subb $drb,$srb */
01414   {
01415     XC16X_INSN_SUBBR, "subbr", "subb", 16,
01416     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01417   },
01418 /* add $dr,[$sr2] */
01419   {
01420     XC16X_INSN_ADD2, "add2", "add", 16,
01421     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01422   },
01423 /* sub $dr,[$sr2] */
01424   {
01425     XC16X_INSN_SUB2, "sub2", "sub", 16,
01426     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01427   },
01428 /* addb $drb,[$sr2] */
01429   {
01430     XC16X_INSN_ADDB2, "addb2", "addb", 16,
01431     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01432   },
01433 /* subb $drb,[$sr2] */
01434   {
01435     XC16X_INSN_SUBB2, "subb2", "subb", 16,
01436     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01437   },
01438 /* add $dr,[$sr2+] */
01439   {
01440     XC16X_INSN_ADD2I, "add2i", "add", 16,
01441     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01442   },
01443 /* sub $dr,[$sr2+] */
01444   {
01445     XC16X_INSN_SUB2I, "sub2i", "sub", 16,
01446     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01447   },
01448 /* addb $drb,[$sr2+] */
01449   {
01450     XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
01451     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01452   },
01453 /* subb $drb,[$sr2+] */
01454   {
01455     XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
01456     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01457   },
01458 /* addc $dr,$sr */
01459   {
01460     XC16X_INSN_ADDCR, "addcr", "addc", 16,
01461     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01462   },
01463 /* subc $dr,$sr */
01464   {
01465     XC16X_INSN_SUBCR, "subcr", "subc", 16,
01466     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01467   },
01468 /* addcb $drb,$srb */
01469   {
01470     XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
01471     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01472   },
01473 /* subcb $drb,$srb */
01474   {
01475     XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
01476     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01477   },
01478 /* addc $dr,[$sr2] */
01479   {
01480     XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
01481     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01482   },
01483 /* subc $dr,[$sr2] */
01484   {
01485     XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
01486     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01487   },
01488 /* addcb $drb,[$sr2] */
01489   {
01490     XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
01491     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01492   },
01493 /* subcb $drb,[$sr2] */
01494   {
01495     XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
01496     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01497   },
01498 /* addc $dr,[$sr2+] */
01499   {
01500     XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
01501     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01502   },
01503 /* subc $dr,[$sr2+] */
01504   {
01505     XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
01506     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01507   },
01508 /* addcb $drb,[$sr2+] */
01509   {
01510     XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
01511     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01512   },
01513 /* subcb $drb,[$sr2+] */
01514   {
01515     XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
01516     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01517   },
01518 /* add $regmem8,$memgr8 */
01519   {
01520     XC16X_INSN_ADDRM2, "addrm2", "add", 32,
01521     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01522   },
01523 /* add $memgr8,$regmem8 */
01524   {
01525     XC16X_INSN_ADDRM3, "addrm3", "add", 32,
01526     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01527   },
01528 /* add $reg8,$memory */
01529   {
01530     XC16X_INSN_ADDRM, "addrm", "add", 32,
01531     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01532   },
01533 /* add $memory,$reg8 */
01534   {
01535     XC16X_INSN_ADDRM1, "addrm1", "add", 32,
01536     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01537   },
01538 /* sub $regmem8,$memgr8 */
01539   {
01540     XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
01541     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01542   },
01543 /* sub $memgr8,$regmem8 */
01544   {
01545     XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
01546     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01547   },
01548 /* sub $reg8,$memory */
01549   {
01550     XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
01551     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01552   },
01553 /* sub $memory,$reg8 */
01554   {
01555     XC16X_INSN_SUBRM, "subrm", "sub", 32,
01556     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01557   },
01558 /* addb $regbmem8,$memgr8 */
01559   {
01560     XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
01561     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01562   },
01563 /* addb $memgr8,$regbmem8 */
01564   {
01565     XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
01566     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01567   },
01568 /* addb $regb8,$memory */
01569   {
01570     XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
01571     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01572   },
01573 /* addb $memory,$regb8 */
01574   {
01575     XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
01576     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01577   },
01578 /* subb $regbmem8,$memgr8 */
01579   {
01580     XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
01581     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01582   },
01583 /* subb $memgr8,$regbmem8 */
01584   {
01585     XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
01586     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01587   },
01588 /* subb $regb8,$memory */
01589   {
01590     XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
01591     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01592   },
01593 /* subb $memory,$regb8 */
01594   {
01595     XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
01596     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01597   },
01598 /* addc $regmem8,$memgr8 */
01599   {
01600     XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
01601     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01602   },
01603 /* addc $memgr8,$regmem8 */
01604   {
01605     XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
01606     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01607   },
01608 /* addc $reg8,$memory */
01609   {
01610     XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
01611     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01612   },
01613 /* addc $memory,$reg8 */
01614   {
01615     XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
01616     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01617   },
01618 /* subc $regmem8,$memgr8 */
01619   {
01620     XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
01621     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01622   },
01623 /* subc $memgr8,$regmem8 */
01624   {
01625     XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
01626     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01627   },
01628 /* subc $reg8,$memory */
01629   {
01630     XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
01631     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01632   },
01633 /* subc $memory,$reg8 */
01634   {
01635     XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
01636     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01637   },
01638 /* addcb $regbmem8,$memgr8 */
01639   {
01640     XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
01641     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01642   },
01643 /* addcb $memgr8,$regbmem8 */
01644   {
01645     XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
01646     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01647   },
01648 /* addcb $regb8,$memory */
01649   {
01650     XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
01651     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01652   },
01653 /* addcb $memory,$regb8 */
01654   {
01655     XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
01656     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01657   },
01658 /* subcb $regbmem8,$memgr8 */
01659   {
01660     XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
01661     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01662   },
01663 /* subcb $memgr8,$regbmem8 */
01664   {
01665     XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
01666     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01667   },
01668 /* subcb $regb8,$memory */
01669   {
01670     XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
01671     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01672   },
01673 /* subcb $memory,$regb8 */
01674   {
01675     XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
01676     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01677   },
01678 /* mul $src1,$src2 */
01679   {
01680     XC16X_INSN_MULS, "muls", "mul", 16,
01681     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01682   },
01683 /* mulu $src1,$src2 */
01684   {
01685     XC16X_INSN_MULU, "mulu", "mulu", 16,
01686     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01687   },
01688 /* div $srdiv */
01689   {
01690     XC16X_INSN_DIV, "div", "div", 16,
01691     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01692   },
01693 /* divl $srdiv */
01694   {
01695     XC16X_INSN_DIVL, "divl", "divl", 16,
01696     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01697   },
01698 /* divlu $srdiv */
01699   {
01700     XC16X_INSN_DIVLU, "divlu", "divlu", 16,
01701     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01702   },
01703 /* divu $srdiv */
01704   {
01705     XC16X_INSN_DIVU, "divu", "divu", 16,
01706     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01707   },
01708 /* cpl $dr */
01709   {
01710     XC16X_INSN_CPL, "cpl", "cpl", 16,
01711     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01712   },
01713 /* cplb $drb */
01714   {
01715     XC16X_INSN_CPLB, "cplb", "cplb", 16,
01716     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01717   },
01718 /* neg $dr */
01719   {
01720     XC16X_INSN_NEG, "neg", "neg", 16,
01721     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01722   },
01723 /* negb $drb */
01724   {
01725     XC16X_INSN_NEGB, "negb", "negb", 16,
01726     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01727   },
01728 /* and $dr,$sr */
01729   {
01730     XC16X_INSN_ANDR, "andr", "and", 16,
01731     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01732   },
01733 /* or $dr,$sr */
01734   {
01735     XC16X_INSN_ORR, "orr", "or", 16,
01736     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01737   },
01738 /* xor $dr,$sr */
01739   {
01740     XC16X_INSN_XORR, "xorr", "xor", 16,
01741     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01742   },
01743 /* andb $drb,$srb */
01744   {
01745     XC16X_INSN_ANDBR, "andbr", "andb", 16,
01746     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01747   },
01748 /* orb $drb,$srb */
01749   {
01750     XC16X_INSN_ORBR, "orbr", "orb", 16,
01751     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01752   },
01753 /* xorb $drb,$srb */
01754   {
01755     XC16X_INSN_XORBR, "xorbr", "xorb", 16,
01756     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01757   },
01758 /* and $dr,$hash$uimm3 */
01759   {
01760     XC16X_INSN_ANDRI, "andri", "and", 16,
01761     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01762   },
01763 /* or $dr,$hash$uimm3 */
01764   {
01765     XC16X_INSN_ORRI, "orri", "or", 16,
01766     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01767   },
01768 /* xor $dr,$hash$uimm3 */
01769   {
01770     XC16X_INSN_XORRI, "xorri", "xor", 16,
01771     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01772   },
01773 /* andb $drb,$hash$uimm3 */
01774   {
01775     XC16X_INSN_ANDBRI, "andbri", "andb", 16,
01776     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01777   },
01778 /* orb $drb,$hash$uimm3 */
01779   {
01780     XC16X_INSN_ORBRI, "orbri", "orb", 16,
01781     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01782   },
01783 /* xorb $drb,$hash$uimm3 */
01784   {
01785     XC16X_INSN_XORBRI, "xorbri", "xorb", 16,
01786     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01787   },
01788 /* and $reg8,$hash$uimm16 */
01789   {
01790     XC16X_INSN_ANDRIM, "andrim", "and", 32,
01791     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01792   },
01793 /* or $reg8,$hash$uimm16 */
01794   {
01795     XC16X_INSN_ORRIM, "orrim", "or", 32,
01796     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01797   },
01798 /* xor $reg8,$hash$uimm16 */
01799   {
01800     XC16X_INSN_XORRIM, "xorrim", "xor", 32,
01801     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01802   },
01803 /* andb $regb8,$hash$uimm8 */
01804   {
01805     XC16X_INSN_ANDBRIM, "andbrim", "andb", 32,
01806     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01807   },
01808 /* orb $regb8,$hash$uimm8 */
01809   {
01810     XC16X_INSN_ORBRIM, "orbrim", "orb", 32,
01811     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01812   },
01813 /* xorb $regb8,$hash$uimm8 */
01814   {
01815     XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32,
01816     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01817   },
01818 /* and $dr,[$sr2] */
01819   {
01820     XC16X_INSN_AND2, "and2", "and", 16,
01821     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01822   },
01823 /* or $dr,[$sr2] */
01824   {
01825     XC16X_INSN_OR2, "or2", "or", 16,
01826     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01827   },
01828 /* xor $dr,[$sr2] */
01829   {
01830     XC16X_INSN_XOR2, "xor2", "xor", 16,
01831     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01832   },
01833 /* andb $drb,[$sr2] */
01834   {
01835     XC16X_INSN_ANDB2, "andb2", "andb", 16,
01836     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01837   },
01838 /* orb $drb,[$sr2] */
01839   {
01840     XC16X_INSN_ORB2, "orb2", "orb", 16,
01841     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01842   },
01843 /* xorb $drb,[$sr2] */
01844   {
01845     XC16X_INSN_XORB2, "xorb2", "xorb", 16,
01846     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01847   },
01848 /* and $dr,[$sr2+] */
01849   {
01850     XC16X_INSN_AND2I, "and2i", "and", 16,
01851     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01852   },
01853 /* or $dr,[$sr2+] */
01854   {
01855     XC16X_INSN_OR2I, "or2i", "or", 16,
01856     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01857   },
01858 /* xor $dr,[$sr2+] */
01859   {
01860     XC16X_INSN_XOR2I, "xor2i", "xor", 16,
01861     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01862   },
01863 /* andb $drb,[$sr2+] */
01864   {
01865     XC16X_INSN_ANDB2I, "andb2i", "andb", 16,
01866     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01867   },
01868 /* orb $drb,[$sr2+] */
01869   {
01870     XC16X_INSN_ORB2I, "orb2i", "orb", 16,
01871     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01872   },
01873 /* xorb $drb,[$sr2+] */
01874   {
01875     XC16X_INSN_XORB2I, "xorb2i", "xorb", 16,
01876     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01877   },
01878 /* and $pof$reg8,$upof16 */
01879   {
01880     XC16X_INSN_ANDPOFR, "andpofr", "and", 32,
01881     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01882   },
01883 /* or $pof$reg8,$upof16 */
01884   {
01885     XC16X_INSN_ORPOFR, "orpofr", "or", 32,
01886     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01887   },
01888 /* xor $pof$reg8,$upof16 */
01889   {
01890     XC16X_INSN_XORPOFR, "xorpofr", "xor", 32,
01891     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01892   },
01893 /* andb $pof$regb8,$upof16 */
01894   {
01895     XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32,
01896     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01897   },
01898 /* orb $pof$regb8,$upof16 */
01899   {
01900     XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32,
01901     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01902   },
01903 /* xorb $pof$regb8,$upof16 */
01904   {
01905     XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32,
01906     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01907   },
01908 /* and $pof$upof16,$reg8 */
01909   {
01910     XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32,
01911     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01912   },
01913 /* or $pof$upof16,$reg8 */
01914   {
01915     XC16X_INSN_ORRPOFR, "orrpofr", "or", 32,
01916     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01917   },
01918 /* xor $pof$upof16,$reg8 */
01919   {
01920     XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32,
01921     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01922   },
01923 /* andb $pof$upof16,$regb8 */
01924   {
01925     XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32,
01926     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01927   },
01928 /* orb $pof$upof16,$regb8 */
01929   {
01930     XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32,
01931     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01932   },
01933 /* xorb $pof$upof16,$regb8 */
01934   {
01935     XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32,
01936     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01937   },
01938 /* and $regmem8,$memgr8 */
01939   {
01940     XC16X_INSN_ANDRM2, "andrm2", "and", 32,
01941     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01942   },
01943 /* and $memgr8,$regmem8 */
01944   {
01945     XC16X_INSN_ANDRM3, "andrm3", "and", 32,
01946     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01947   },
01948 /* and $reg8,$memory */
01949   {
01950     XC16X_INSN_ANDRM, "andrm", "and", 32,
01951     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01952   },
01953 /* and $memory,$reg8 */
01954   {
01955     XC16X_INSN_ANDRM1, "andrm1", "and", 32,
01956     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01957   },
01958 /* or $regmem8,$memgr8 */
01959   {
01960     XC16X_INSN_ORRM3, "orrm3", "or", 32,
01961     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01962   },
01963 /* or $memgr8,$regmem8 */
01964   {
01965     XC16X_INSN_ORRM2, "orrm2", "or", 32,
01966     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01967   },
01968 /* or $reg8,$memory */
01969   {
01970     XC16X_INSN_ORRM1, "orrm1", "or", 32,
01971     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01972   },
01973 /* or $memory,$reg8 */
01974   {
01975     XC16X_INSN_ORRM, "orrm", "or", 32,
01976     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01977   },
01978 /* xor $regmem8,$memgr8 */
01979   {
01980     XC16X_INSN_XORRM3, "xorrm3", "xor", 32,
01981     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01982   },
01983 /* xor $memgr8,$regmem8 */
01984   {
01985     XC16X_INSN_XORRM2, "xorrm2", "xor", 32,
01986     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01987   },
01988 /* xor $reg8,$memory */
01989   {
01990     XC16X_INSN_XORRM1, "xorrm1", "xor", 32,
01991     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01992   },
01993 /* xor $memory,$reg8 */
01994   {
01995     XC16X_INSN_XORRM, "xorrm", "xor", 32,
01996     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
01997   },
01998 /* andb $regbmem8,$memgr8 */
01999   {
02000     XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32,
02001     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02002   },
02003 /* andb $memgr8,$regbmem8 */
02004   {
02005     XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32,
02006     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02007   },
02008 /* andb $regb8,$memory */
02009   {
02010     XC16X_INSN_ANDBRM, "andbrm", "andb", 32,
02011     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02012   },
02013 /* andb $memory,$regb8 */
02014   {
02015     XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32,
02016     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02017   },
02018 /* orb $regbmem8,$memgr8 */
02019   {
02020     XC16X_INSN_ORBRM3, "orbrm3", "orb", 32,
02021     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02022   },
02023 /* orb $memgr8,$regbmem8 */
02024   {
02025     XC16X_INSN_ORBRM2, "orbrm2", "orb", 32,
02026     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02027   },
02028 /* orb $regb8,$memory */
02029   {
02030     XC16X_INSN_ORBRM1, "orbrm1", "orb", 32,
02031     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02032   },
02033 /* orb $memory,$regb8 */
02034   {
02035     XC16X_INSN_ORBRM, "orbrm", "orb", 32,
02036     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02037   },
02038 /* xorb $regbmem8,$memgr8 */
02039   {
02040     XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32,
02041     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02042   },
02043 /* xorb $memgr8,$regbmem8 */
02044   {
02045     XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32,
02046     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02047   },
02048 /* xorb $regb8,$memory */
02049   {
02050     XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32,
02051     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02052   },
02053 /* xorb $memory,$regb8 */
02054   {
02055     XC16X_INSN_XORBRM, "xorbrm", "xorb", 32,
02056     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02057   },
02058 /* mov $dr,$sr */
02059   {
02060     XC16X_INSN_MOVR, "movr", "mov", 16,
02061     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02062   },
02063 /* movb $drb,$srb */
02064   {
02065     XC16X_INSN_MOVRB, "movrb", "movb", 16,
02066     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02067   },
02068 /* mov $dri,$hash$u4 */
02069   {
02070     XC16X_INSN_MOVRI, "movri", "mov", 16,
02071     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02072   },
02073 /* movb $srb,$hash$u4 */
02074   {
02075     XC16X_INSN_MOVBRI, "movbri", "movb", 16,
02076     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02077   },
02078 /* mov $reg8,$hash$uimm16 */
02079   {
02080     XC16X_INSN_MOVI, "movi", "mov", 32,
02081     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02082   },
02083 /* movb $regb8,$hash$uimm8 */
02084   {
02085     XC16X_INSN_MOVBI, "movbi", "movb", 32,
02086     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02087   },
02088 /* mov $dr,[$sr] */
02089   {
02090     XC16X_INSN_MOVR2, "movr2", "mov", 16,
02091     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02092   },
02093 /* movb $drb,[$sr] */
02094   {
02095     XC16X_INSN_MOVBR2, "movbr2", "movb", 16,
02096     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02097   },
02098 /* mov [$sr],$dr */
02099   {
02100     XC16X_INSN_MOVRI2, "movri2", "mov", 16,
02101     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02102   },
02103 /* movb [$sr],$drb */
02104   {
02105     XC16X_INSN_MOVBRI2, "movbri2", "movb", 16,
02106     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02107   },
02108 /* mov [-$sr],$dr */
02109   {
02110     XC16X_INSN_MOVRI3, "movri3", "mov", 16,
02111     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02112   },
02113 /* movb [-$sr],$drb */
02114   {
02115     XC16X_INSN_MOVBRI3, "movbri3", "movb", 16,
02116     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02117   },
02118 /* mov $dr,[$sr+] */
02119   {
02120     XC16X_INSN_MOV2I, "mov2i", "mov", 16,
02121     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02122   },
02123 /* movb $drb,[$sr+] */
02124   {
02125     XC16X_INSN_MOVB2I, "movb2i", "movb", 16,
02126     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02127   },
02128 /* mov [$dr],[$sr] */
02129   {
02130     XC16X_INSN_MOV6I, "mov6i", "mov", 16,
02131     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02132   },
02133 /* movb [$dr],[$sr] */
02134   {
02135     XC16X_INSN_MOVB6I, "movb6i", "movb", 16,
02136     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02137   },
02138 /* mov [$dr+],[$sr] */
02139   {
02140     XC16X_INSN_MOV7I, "mov7i", "mov", 16,
02141     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02142   },
02143 /* movb [$dr+],[$sr] */
02144   {
02145     XC16X_INSN_MOVB7I, "movb7i", "movb", 16,
02146     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02147   },
02148 /* mov [$dr],[$sr+] */
02149   {
02150     XC16X_INSN_MOV8I, "mov8i", "mov", 16,
02151     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02152   },
02153 /* movb [$dr],[$sr+] */
02154   {
02155     XC16X_INSN_MOVB8I, "movb8i", "movb", 16,
02156     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02157   },
02158 /* mov $dr,[$sr+$hash$uimm16] */
02159   {
02160     XC16X_INSN_MOV9I, "mov9i", "mov", 32,
02161     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02162   },
02163 /* movb $drb,[$sr+$hash$uimm16] */
02164   {
02165     XC16X_INSN_MOVB9I, "movb9i", "movb", 32,
02166     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02167   },
02168 /* mov [$sr+$hash$uimm16],$dr */
02169   {
02170     XC16X_INSN_MOV10I, "mov10i", "mov", 32,
02171     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02172   },
02173 /* movb [$sr+$hash$uimm16],$drb */
02174   {
02175     XC16X_INSN_MOVB10I, "movb10i", "movb", 32,
02176     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02177   },
02178 /* mov [$src2],$memory */
02179   {
02180     XC16X_INSN_MOVRI11, "movri11", "mov", 32,
02181     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02182   },
02183 /* movb [$src2],$memory */
02184   {
02185     XC16X_INSN_MOVBRI11, "movbri11", "movb", 32,
02186     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02187   },
02188 /* mov $memory,[$src2] */
02189   {
02190     XC16X_INSN_MOVRI12, "movri12", "mov", 32,
02191     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02192   },
02193 /* movb $memory,[$src2] */
02194   {
02195     XC16X_INSN_MOVBRI12, "movbri12", "movb", 32,
02196     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02197   },
02198 /* mov $regoff8,$hash$pof$upof16 */
02199   {
02200     XC16X_INSN_MOVEHM5, "movehm5", "mov", 32,
02201     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02202   },
02203 /* mov $regoff8,$hash$pag$upag16 */
02204   {
02205     XC16X_INSN_MOVEHM6, "movehm6", "mov", 32,
02206     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02207   },
02208 /* mov $regoff8,$hash$segm$useg16 */
02209   {
02210     XC16X_INSN_MOVEHM7, "movehm7", "mov", 32,
02211     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02212   },
02213 /* mov $regoff8,$hash$sof$usof16 */
02214   {
02215     XC16X_INSN_MOVEHM8, "movehm8", "mov", 32,
02216     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02217   },
02218 /* movb $regb8,$hash$pof$uimm8 */
02219   {
02220     XC16X_INSN_MOVEHM9, "movehm9", "movb", 32,
02221     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02222   },
02223 /* movb $regoff8,$hash$pag$uimm8 */
02224   {
02225     XC16X_INSN_MOVEHM10, "movehm10", "movb", 32,
02226     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02227   },
02228 /* mov $regoff8,$pof$upof16 */
02229   {
02230     XC16X_INSN_MOVRMP, "movrmp", "mov", 32,
02231     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02232   },
02233 /* movb $regb8,$pof$upof16 */
02234   {
02235     XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32,
02236     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02237   },
02238 /* mov $regoff8,$pag$upag16 */
02239   {
02240     XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32,
02241     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02242   },
02243 /* movb $regb8,$pag$upag16 */
02244   {
02245     XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32,
02246     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02247   },
02248 /* mov $pof$upof16,$regoff8 */
02249   {
02250     XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32,
02251     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02252   },
02253 /* movb $pof$upof16,$regb8 */
02254   {
02255     XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32,
02256     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02257   },
02258 /* mov $dri,$hash$pof$u4 */
02259   {
02260     XC16X_INSN_MOVEHM1, "movehm1", "mov", 16,
02261     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02262   },
02263 /* movb $srb,$hash$pof$u4 */
02264   {
02265     XC16X_INSN_MOVEHM2, "movehm2", "movb", 16,
02266     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02267   },
02268 /* mov $dri,$hash$pag$u4 */
02269   {
02270     XC16X_INSN_MOVEHM3, "movehm3", "mov", 16,
02271     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02272   },
02273 /* movb $srb,$hash$pag$u4 */
02274   {
02275     XC16X_INSN_MOVEHM4, "movehm4", "movb", 16,
02276     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02277   },
02278 /* mov $regmem8,$memgr8 */
02279   {
02280     XC16X_INSN_MVE12, "mve12", "mov", 32,
02281     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02282   },
02283 /* mov $memgr8,$regmem8 */
02284   {
02285     XC16X_INSN_MVE13, "mve13", "mov", 32,
02286     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02287   },
02288 /* mov $reg8,$memory */
02289   {
02290     XC16X_INSN_MOVER12, "mover12", "mov", 32,
02291     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02292   },
02293 /* mov $memory,$reg8 */
02294   {
02295     XC16X_INSN_MVR13, "mvr13", "mov", 32,
02296     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02297   },
02298 /* movb $regbmem8,$memgr8 */
02299   {
02300     XC16X_INSN_MVER12, "mver12", "movb", 32,
02301     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02302   },
02303 /* movb $memgr8,$regbmem8 */
02304   {
02305     XC16X_INSN_MVER13, "mver13", "movb", 32,
02306     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02307   },
02308 /* movb $regb8,$memory */
02309   {
02310     XC16X_INSN_MOVR12, "movr12", "movb", 32,
02311     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02312   },
02313 /* movb $memory,$regb8 */
02314   {
02315     XC16X_INSN_MOVR13, "movr13", "movb", 32,
02316     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02317   },
02318 /* movbs $sr,$drb */
02319   {
02320     XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16,
02321     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02322   },
02323 /* movbz $sr,$drb */
02324   {
02325     XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16,
02326     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02327   },
02328 /* movbs $regmem8,$pof$upof16 */
02329   {
02330     XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32,
02331     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02332   },
02333 /* movbs $pof$upof16,$regbmem8 */
02334   {
02335     XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32,
02336     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02337   },
02338 /* movbz $reg8,$pof$upof16 */
02339   {
02340     XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32,
02341     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02342   },
02343 /* movbz $pof$upof16,$regb8 */
02344   {
02345     XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32,
02346     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02347   },
02348 /* movbs $regmem8,$memgr8 */
02349   {
02350     XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32,
02351     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02352   },
02353 /* movbs $memgr8,$regbmem8 */
02354   {
02355     XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32,
02356     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02357   },
02358 /* movbs $reg8,$memory */
02359   {
02360     XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32,
02361     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02362   },
02363 /* movbs $memory,$regb8 */
02364   {
02365     XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32,
02366     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02367   },
02368 /* movbz $regmem8,$memgr8 */
02369   {
02370     XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32,
02371     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02372   },
02373 /* movbz $memgr8,$regbmem8 */
02374   {
02375     XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32,
02376     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02377   },
02378 /* movbz $reg8,$memory */
02379   {
02380     XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32,
02381     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02382   },
02383 /* movbz $memory,$regb8 */
02384   {
02385     XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32,
02386     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02387   },
02388 /* movbs $sr,$drb */
02389   {
02390     XC16X_INSN_MOVRBS, "movrbs", "movbs", 16,
02391     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02392   },
02393 /* movbz $sr,$drb */
02394   {
02395     XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16,
02396     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02397   },
02398 /* jmpa+ $extcond,$caddr */
02399   {
02400     XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32,
02401     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02402   },
02403 /* jmpa $extcond,$caddr */
02404   {
02405     XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32,
02406     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02407   },
02408 /* jmpa- $extcond,$caddr */
02409   {
02410     XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32,
02411     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02412   },
02413 /* jmpi $icond,[$sr] */
02414   {
02415     XC16X_INSN_JMPI, "jmpi", "jmpi", 16,
02416     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02417   },
02418 /* jmpr $cond,$rel */
02419   {
02420     XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16,
02421     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02422   },
02423 /* jmpr $cond,$rel */
02424   {
02425     XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16,
02426     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02427   },
02428 /* jmpr $cond,$rel */
02429   {
02430     XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16,
02431     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02432   },
02433 /* jmpr $cond,$rel */
02434   {
02435     XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16,
02436     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02437   },
02438 /* jmpr $cond,$rel */
02439   {
02440     XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16,
02441     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02442   },
02443 /* jmpr $cond,$rel */
02444   {
02445     XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16,
02446     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02447   },
02448 /* jmpr $cond,$rel */
02449   {
02450     XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16,
02451     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02452   },
02453 /* jmpr $cond,$rel */
02454   {
02455     XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16,
02456     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02457   },
02458 /* jmpr $cond,$rel */
02459   {
02460     XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16,
02461     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02462   },
02463 /* jmpr $cond,$rel */
02464   {
02465     XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16,
02466     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02467   },
02468 /* jmpr $cond,$rel */
02469   {
02470     XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16,
02471     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02472   },
02473 /* jmpr $cond,$rel */
02474   {
02475     XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16,
02476     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02477   },
02478 /* jmpr $cond,$rel */
02479   {
02480     XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16,
02481     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02482   },
02483 /* jmpr $cond,$rel */
02484   {
02485     XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16,
02486     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02487   },
02488 /* jmpr $cond,$rel */
02489   {
02490     XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16,
02491     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02492   },
02493 /* jmpr $cond,$rel */
02494   {
02495     XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16,
02496     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02497   },
02498 /* jmpr $cond,$rel */
02499   {
02500     XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16,
02501     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02502   },
02503 /* jmpr $cond,$rel */
02504   {
02505     XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16,
02506     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02507   },
02508 /* jmpr $cond,$rel */
02509   {
02510     XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16,
02511     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02512   },
02513 /* jmpr $cond,$rel */
02514   {
02515     XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16,
02516     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02517   },
02518 /* jmps $hash$segm$useg8,$hash$sof$usof16 */
02519   {
02520     XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32,
02521     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02522   },
02523 /* jmps $seg,$caddr */
02524   {
02525     XC16X_INSN_JMPS, "jmps", "jmps", 32,
02526     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02527   },
02528 /* jb $genreg$dot$qlobit,$relhi */
02529   {
02530     XC16X_INSN_JB, "jb", "jb", 32,
02531     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02532   },
02533 /* jbc $genreg$dot$qlobit,$relhi */
02534   {
02535     XC16X_INSN_JBC, "jbc", "jbc", 32,
02536     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02537   },
02538 /* jnb $genreg$dot$qlobit,$relhi */
02539   {
02540     XC16X_INSN_JNB, "jnb", "jnb", 32,
02541     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02542   },
02543 /* jnbs $genreg$dot$qlobit,$relhi */
02544   {
02545     XC16X_INSN_JNBS, "jnbs", "jnbs", 32,
02546     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02547   },
02548 /* calla+ $extcond,$caddr */
02549   {
02550     XC16X_INSN_CALLA0, "calla0", "calla+", 32,
02551     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02552   },
02553 /* calla $extcond,$caddr */
02554   {
02555     XC16X_INSN_CALLA1, "calla1", "calla", 32,
02556     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02557   },
02558 /* calla- $extcond,$caddr */
02559   {
02560     XC16X_INSN_CALLA_, "calla-", "calla-", 32,
02561     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02562   },
02563 /* calli $icond,[$sr] */
02564   {
02565     XC16X_INSN_CALLI, "calli", "calli", 16,
02566     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02567   },
02568 /* callr $rel */
02569   {
02570     XC16X_INSN_CALLR, "callr", "callr", 16,
02571     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02572   },
02573 /* calls $hash$segm$useg8,$hash$sof$usof16 */
02574   {
02575     XC16X_INSN_CALLSEG, "callseg", "calls", 32,
02576     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02577   },
02578 /* calls $seg,$caddr */
02579   {
02580     XC16X_INSN_CALLS, "calls", "calls", 32,
02581     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02582   },
02583 /* pcall $reg8,$caddr */
02584   {
02585     XC16X_INSN_PCALL, "pcall", "pcall", 32,
02586     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02587   },
02588 /* trap $hash$uimm7 */
02589   {
02590     XC16X_INSN_TRAP, "trap", "trap", 16,
02591     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02592   },
02593 /* ret */
02594   {
02595     XC16X_INSN_RET, "ret", "ret", 16,
02596     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02597   },
02598 /* rets */
02599   {
02600     XC16X_INSN_RETS, "rets", "rets", 16,
02601     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02602   },
02603 /* retp $reg8 */
02604   {
02605     XC16X_INSN_RETP, "retp", "retp", 16,
02606     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02607   },
02608 /* reti */
02609   {
02610     XC16X_INSN_RETI, "reti", "reti", 16,
02611     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02612   },
02613 /* pop $reg8 */
02614   {
02615     XC16X_INSN_POP, "pop", "pop", 16,
02616     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02617   },
02618 /* push $reg8 */
02619   {
02620     XC16X_INSN_PUSH, "push", "push", 16,
02621     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02622   },
02623 /* scxt $reg8,$hash$uimm16 */
02624   {
02625     XC16X_INSN_SCXTI, "scxti", "scxt", 32,
02626     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02627   },
02628 /* scxt $reg8,$pof$upof16 */
02629   {
02630     XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32,
02631     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02632   },
02633 /* scxt $regmem8,$memgr8 */
02634   {
02635     XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32,
02636     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02637   },
02638 /* scxt $reg8,$memory */
02639   {
02640     XC16X_INSN_SCXTM, "scxtm", "scxt", 32,
02641     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02642   },
02643 /* nop */
02644   {
02645     XC16X_INSN_NOP, "nop", "nop", 16,
02646     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02647   },
02648 /* srst */
02649   {
02650     XC16X_INSN_SRSTM, "srstm", "srst", 32,
02651     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02652   },
02653 /* idle */
02654   {
02655     XC16X_INSN_IDLEM, "idlem", "idle", 32,
02656     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02657   },
02658 /* pwrdn */
02659   {
02660     XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32,
02661     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02662   },
02663 /* diswdt */
02664   {
02665     XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32,
02666     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02667   },
02668 /* enwdt */
02669   {
02670     XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32,
02671     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02672   },
02673 /* einit */
02674   {
02675     XC16X_INSN_EINITM, "einitm", "einit", 32,
02676     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02677   },
02678 /* srvwdt */
02679   {
02680     XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32,
02681     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02682   },
02683 /* sbrk */
02684   {
02685     XC16X_INSN_SBRK, "sbrk", "sbrk", 16,
02686     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02687   },
02688 /* atomic $hash$uimm2 */
02689   {
02690     XC16X_INSN_ATOMIC, "atomic", "atomic", 16,
02691     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02692   },
02693 /* extr $hash$uimm2 */
02694   {
02695     XC16X_INSN_EXTR, "extr", "extr", 16,
02696     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02697   },
02698 /* extp $sr,$hash$uimm2 */
02699   {
02700     XC16X_INSN_EXTP, "extp", "extp", 16,
02701     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02702   },
02703 /* extp $hash$pagenum,$hash$uimm2 */
02704   {
02705     XC16X_INSN_EXTP1, "extp1", "extp", 32,
02706     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02707   },
02708 /* extp $hash$pag$upag16,$hash$uimm2 */
02709   {
02710     XC16X_INSN_EXTPG1, "extpg1", "extp", 32,
02711     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02712   },
02713 /* extpr $sr,$hash$uimm2 */
02714   {
02715     XC16X_INSN_EXTPR, "extpr", "extpr", 16,
02716     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02717   },
02718 /* extpr $hash$pagenum,$hash$uimm2 */
02719   {
02720     XC16X_INSN_EXTPR1, "extpr1", "extpr", 32,
02721     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02722   },
02723 /* exts $sr,$hash$uimm2 */
02724   {
02725     XC16X_INSN_EXTS, "exts", "exts", 16,
02726     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02727   },
02728 /* exts $hash$seghi8,$hash$uimm2 */
02729   {
02730     XC16X_INSN_EXTS1, "exts1", "exts", 32,
02731     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02732   },
02733 /* extsr $sr,$hash$uimm2 */
02734   {
02735     XC16X_INSN_EXTSR, "extsr", "extsr", 16,
02736     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02737   },
02738 /* extsr $hash$seghi8,$hash$uimm2 */
02739   {
02740     XC16X_INSN_EXTSR1, "extsr1", "extsr", 32,
02741     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02742   },
02743 /* prior $dr,$sr */
02744   {
02745     XC16X_INSN_PRIOR, "prior", "prior", 16,
02746     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02747   },
02748 /* bclr $RegNam */
02749   {
02750     XC16X_INSN_BCLR18, "bclr18", "bclr", 16,
02751     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02752   },
02753 /* bclr $reg8$dot$qbit */
02754   {
02755     XC16X_INSN_BCLR0, "bclr0", "bclr", 16,
02756     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02757   },
02758 /* bclr $reg8$dot$qbit */
02759   {
02760     XC16X_INSN_BCLR1, "bclr1", "bclr", 16,
02761     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02762   },
02763 /* bclr $reg8$dot$qbit */
02764   {
02765     XC16X_INSN_BCLR2, "bclr2", "bclr", 16,
02766     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02767   },
02768 /* bclr $reg8$dot$qbit */
02769   {
02770     XC16X_INSN_BCLR3, "bclr3", "bclr", 16,
02771     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02772   },
02773 /* bclr $reg8$dot$qbit */
02774   {
02775     XC16X_INSN_BCLR4, "bclr4", "bclr", 16,
02776     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02777   },
02778 /* bclr $reg8$dot$qbit */
02779   {
02780     XC16X_INSN_BCLR5, "bclr5", "bclr", 16,
02781     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02782   },
02783 /* bclr $reg8$dot$qbit */
02784   {
02785     XC16X_INSN_BCLR6, "bclr6", "bclr", 16,
02786     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02787   },
02788 /* bclr $reg8$dot$qbit */
02789   {
02790     XC16X_INSN_BCLR7, "bclr7", "bclr", 16,
02791     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02792   },
02793 /* bclr $reg8$dot$qbit */
02794   {
02795     XC16X_INSN_BCLR8, "bclr8", "bclr", 16,
02796     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02797   },
02798 /* bclr $reg8$dot$qbit */
02799   {
02800     XC16X_INSN_BCLR9, "bclr9", "bclr", 16,
02801     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02802   },
02803 /* bclr $reg8$dot$qbit */
02804   {
02805     XC16X_INSN_BCLR10, "bclr10", "bclr", 16,
02806     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02807   },
02808 /* bclr $reg8$dot$qbit */
02809   {
02810     XC16X_INSN_BCLR11, "bclr11", "bclr", 16,
02811     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02812   },
02813 /* bclr $reg8$dot$qbit */
02814   {
02815     XC16X_INSN_BCLR12, "bclr12", "bclr", 16,
02816     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02817   },
02818 /* bclr $reg8$dot$qbit */
02819   {
02820     XC16X_INSN_BCLR13, "bclr13", "bclr", 16,
02821     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02822   },
02823 /* bclr $reg8$dot$qbit */
02824   {
02825     XC16X_INSN_BCLR14, "bclr14", "bclr", 16,
02826     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02827   },
02828 /* bclr $reg8$dot$qbit */
02829   {
02830     XC16X_INSN_BCLR15, "bclr15", "bclr", 16,
02831     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02832   },
02833 /* bset $RegNam */
02834   {
02835     XC16X_INSN_BSET19, "bset19", "bset", 16,
02836     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02837   },
02838 /* bset $reg8$dot$qbit */
02839   {
02840     XC16X_INSN_BSET0, "bset0", "bset", 16,
02841     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02842   },
02843 /* bset $reg8$dot$qbit */
02844   {
02845     XC16X_INSN_BSET1, "bset1", "bset", 16,
02846     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02847   },
02848 /* bset $reg8$dot$qbit */
02849   {
02850     XC16X_INSN_BSET2, "bset2", "bset", 16,
02851     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02852   },
02853 /* bset $reg8$dot$qbit */
02854   {
02855     XC16X_INSN_BSET3, "bset3", "bset", 16,
02856     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02857   },
02858 /* bset $reg8$dot$qbit */
02859   {
02860     XC16X_INSN_BSET4, "bset4", "bset", 16,
02861     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02862   },
02863 /* bset $reg8$dot$qbit */
02864   {
02865     XC16X_INSN_BSET5, "bset5", "bset", 16,
02866     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02867   },
02868 /* bset $reg8$dot$qbit */
02869   {
02870     XC16X_INSN_BSET6, "bset6", "bset", 16,
02871     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02872   },
02873 /* bset $reg8$dot$qbit */
02874   {
02875     XC16X_INSN_BSET7, "bset7", "bset", 16,
02876     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02877   },
02878 /* bset $reg8$dot$qbit */
02879   {
02880     XC16X_INSN_BSET8, "bset8", "bset", 16,
02881     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02882   },
02883 /* bset $reg8$dot$qbit */
02884   {
02885     XC16X_INSN_BSET9, "bset9", "bset", 16,
02886     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02887   },
02888 /* bset $reg8$dot$qbit */
02889   {
02890     XC16X_INSN_BSET10, "bset10", "bset", 16,
02891     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02892   },
02893 /* bset $reg8$dot$qbit */
02894   {
02895     XC16X_INSN_BSET11, "bset11", "bset", 16,
02896     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02897   },
02898 /* bset $reg8$dot$qbit */
02899   {
02900     XC16X_INSN_BSET12, "bset12", "bset", 16,
02901     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02902   },
02903 /* bset $reg8$dot$qbit */
02904   {
02905     XC16X_INSN_BSET13, "bset13", "bset", 16,
02906     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02907   },
02908 /* bset $reg8$dot$qbit */
02909   {
02910     XC16X_INSN_BSET14, "bset14", "bset", 16,
02911     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02912   },
02913 /* bset $reg8$dot$qbit */
02914   {
02915     XC16X_INSN_BSET15, "bset15", "bset", 16,
02916     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02917   },
02918 /* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
02919   {
02920     XC16X_INSN_BMOV, "bmov", "bmov", 32,
02921     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02922   },
02923 /* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
02924   {
02925     XC16X_INSN_BMOVN, "bmovn", "bmovn", 32,
02926     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02927   },
02928 /* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
02929   {
02930     XC16X_INSN_BAND, "band", "band", 32,
02931     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02932   },
02933 /* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
02934   {
02935     XC16X_INSN_BOR, "bor", "bor", 32,
02936     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02937   },
02938 /* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
02939   {
02940     XC16X_INSN_BXOR, "bxor", "bxor", 32,
02941     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02942   },
02943 /* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
02944   {
02945     XC16X_INSN_BCMP, "bcmp", "bcmp", 32,
02946     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02947   },
02948 /* bfldl $reg8,$hash$mask8,$hash$datahi8 */
02949   {
02950     XC16X_INSN_BFLDL, "bfldl", "bfldl", 32,
02951     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02952   },
02953 /* bfldh $reg8,$hash$masklo8,$hash$data8 */
02954   {
02955     XC16X_INSN_BFLDH, "bfldh", "bfldh", 32,
02956     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02957   },
02958 /* cmp $src1,$src2 */
02959   {
02960     XC16X_INSN_CMPR, "cmpr", "cmp", 16,
02961     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02962   },
02963 /* cmpb $drb,$srb */
02964   {
02965     XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16,
02966     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02967   },
02968 /* cmp $src1,$hash$uimm3 */
02969   {
02970     XC16X_INSN_CMPRI, "cmpri", "cmp", 16,
02971     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02972   },
02973 /* cmpb $drb,$hash$uimm3 */
02974   {
02975     XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16,
02976     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02977   },
02978 /* cmp $reg8,$hash$uimm16 */
02979   {
02980     XC16X_INSN_CMPI, "cmpi", "cmp", 32,
02981     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02982   },
02983 /* cmpb $regb8,$hash$uimm8 */
02984   {
02985     XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32,
02986     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02987   },
02988 /* cmp $dr,[$sr2] */
02989   {
02990     XC16X_INSN_CMPR2, "cmpr2", "cmp", 16,
02991     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02992   },
02993 /* cmpb $drb,[$sr2] */
02994   {
02995     XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16,
02996     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
02997   },
02998 /* cmp $dr,[$sr2+] */
02999   {
03000     XC16X_INSN_CMP2I, "cmp2i", "cmp", 16,
03001     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03002   },
03003 /* cmpb $drb,[$sr2+] */
03004   {
03005     XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16,
03006     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03007   },
03008 /* cmp $reg8,$pof$upof16 */
03009   {
03010     XC16X_INSN_CMP04, "cmp04", "cmp", 32,
03011     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03012   },
03013 /* cmpb $regb8,$pof$upof16 */
03014   {
03015     XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32,
03016     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03017   },
03018 /* cmp $regmem8,$memgr8 */
03019   {
03020     XC16X_INSN_CMP004, "cmp004", "cmp", 32,
03021     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03022   },
03023 /* cmp $reg8,$memory */
03024   {
03025     XC16X_INSN_CMP0004, "cmp0004", "cmp", 32,
03026     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03027   },
03028 /* cmpb $regbmem8,$memgr8 */
03029   {
03030     XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32,
03031     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03032   },
03033 /* cmpb $regb8,$memory */
03034   {
03035     XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32,
03036     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03037   },
03038 /* cmpd1 $sr,$hash$uimm4 */
03039   {
03040     XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16,
03041     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03042   },
03043 /* cmpd2 $sr,$hash$uimm4 */
03044   {
03045     XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16,
03046     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03047   },
03048 /* cmpi1 $sr,$hash$uimm4 */
03049   {
03050     XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16,
03051     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03052   },
03053 /* cmpi2 $sr,$hash$uimm4 */
03054   {
03055     XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16,
03056     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03057   },
03058 /* cmpd1 $reg8,$hash$uimm16 */
03059   {
03060     XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32,
03061     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03062   },
03063 /* cmpd2 $reg8,$hash$uimm16 */
03064   {
03065     XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32,
03066     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03067   },
03068 /* cmpi1 $reg8,$hash$uimm16 */
03069   {
03070     XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32,
03071     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03072   },
03073 /* cmpi2 $reg8,$hash$uimm16 */
03074   {
03075     XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32,
03076     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03077   },
03078 /* cmpd1 $reg8,$pof$upof16 */
03079   {
03080     XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32,
03081     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03082   },
03083 /* cmpd2 $reg8,$pof$upof16 */
03084   {
03085     XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32,
03086     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03087   },
03088 /* cmpi1 $reg8,$pof$upof16 */
03089   {
03090     XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32,
03091     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03092   },
03093 /* cmpi2 $reg8,$pof$upof16 */
03094   {
03095     XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32,
03096     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03097   },
03098 /* cmpd1 $regmem8,$memgr8 */
03099   {
03100     XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32,
03101     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03102   },
03103 /* cmpd2 $regmem8,$memgr8 */
03104   {
03105     XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32,
03106     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03107   },
03108 /* cmpi1 $regmem8,$memgr8 */
03109   {
03110     XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32,
03111     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03112   },
03113 /* cmpi2 $regmem8,$memgr8 */
03114   {
03115     XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32,
03116     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03117   },
03118 /* cmpd1 $reg8,$memory */
03119   {
03120     XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32,
03121     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03122   },
03123 /* cmpd2 $reg8,$memory */
03124   {
03125     XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32,
03126     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03127   },
03128 /* cmpi1 $reg8,$memory */
03129   {
03130     XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32,
03131     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03132   },
03133 /* cmpi2 $reg8,$memory */
03134   {
03135     XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32,
03136     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03137   },
03138 /* shl $dr,$sr */
03139   {
03140     XC16X_INSN_SHLR, "shlr", "shl", 16,
03141     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03142   },
03143 /* shr $dr,$sr */
03144   {
03145     XC16X_INSN_SHRR, "shrr", "shr", 16,
03146     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03147   },
03148 /* rol $dr,$sr */
03149   {
03150     XC16X_INSN_ROLR, "rolr", "rol", 16,
03151     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03152   },
03153 /* ror $dr,$sr */
03154   {
03155     XC16X_INSN_RORR, "rorr", "ror", 16,
03156     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03157   },
03158 /* ashr $dr,$sr */
03159   {
03160     XC16X_INSN_ASHRR, "ashrr", "ashr", 16,
03161     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03162   },
03163 /* shl $sr,$hash$uimm4 */
03164   {
03165     XC16X_INSN_SHLRI, "shlri", "shl", 16,
03166     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03167   },
03168 /* shr $sr,$hash$uimm4 */
03169   {
03170     XC16X_INSN_SHRRI, "shrri", "shr", 16,
03171     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03172   },
03173 /* rol $sr,$hash$uimm4 */
03174   {
03175     XC16X_INSN_ROLRI, "rolri", "rol", 16,
03176     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03177   },
03178 /* ror $sr,$hash$uimm4 */
03179   {
03180     XC16X_INSN_RORRI, "rorri", "ror", 16,
03181     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03182   },
03183 /* ashr $sr,$hash$uimm4 */
03184   {
03185     XC16X_INSN_ASHRRI, "ashrri", "ashr", 16,
03186     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
03187   },
03188 };
03189 
03190 #undef OP
03191 #undef A
03192 
03193 /* Initialize anything needed to be done once, before any cpu_open call.  */
03194 
03195 static void
03196 init_tables (void)
03197 {
03198 }
03199 
03200 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
03201 static void build_hw_table      (CGEN_CPU_TABLE *);
03202 static void build_ifield_table  (CGEN_CPU_TABLE *);
03203 static void build_operand_table (CGEN_CPU_TABLE *);
03204 static void build_insn_table    (CGEN_CPU_TABLE *);
03205 static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *);
03206 
03207 /* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name.  */
03208 
03209 static const CGEN_MACH *
03210 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
03211 {
03212   while (table->name)
03213     {
03214       if (strcmp (name, table->bfd_name) == 0)
03215        return table;
03216       ++table;
03217     }
03218   abort ();
03219 }
03220 
03221 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
03222 
03223 static void
03224 build_hw_table (CGEN_CPU_TABLE *cd)
03225 {
03226   int i;
03227   int machs = cd->machs;
03228   const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
03229   /* MAX_HW is only an upper bound on the number of selected entries.
03230      However each entry is indexed by it's enum so there can be holes in
03231      the table.  */
03232   const CGEN_HW_ENTRY **selected =
03233     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
03234 
03235   cd->hw_table.init_entries = init;
03236   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
03237   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
03238   /* ??? For now we just use machs to determine which ones we want.  */
03239   for (i = 0; init[i].name != NULL; ++i)
03240     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
03241        & machs)
03242       selected[init[i].type] = &init[i];
03243   cd->hw_table.entries = selected;
03244   cd->hw_table.num_entries = MAX_HW;
03245 }
03246 
03247 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
03248 
03249 static void
03250 build_ifield_table (CGEN_CPU_TABLE *cd)
03251 {
03252   cd->ifld_table = & xc16x_cgen_ifld_table[0];
03253 }
03254 
03255 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
03256 
03257 static void
03258 build_operand_table (CGEN_CPU_TABLE *cd)
03259 {
03260   int i;
03261   int machs = cd->machs;
03262   const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
03263   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
03264      However each entry is indexed by it's enum so there can be holes in
03265      the table.  */
03266   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
03267 
03268   cd->operand_table.init_entries = init;
03269   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
03270   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
03271   /* ??? For now we just use mach to determine which ones we want.  */
03272   for (i = 0; init[i].name != NULL; ++i)
03273     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
03274        & machs)
03275       selected[init[i].type] = &init[i];
03276   cd->operand_table.entries = selected;
03277   cd->operand_table.num_entries = MAX_OPERANDS;
03278 }
03279 
03280 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.
03281    ??? This could leave out insns not supported by the specified mach/isa,
03282    but that would cause errors like "foo only supported by bar" to become
03283    "unknown insn", so for now we include all insns and require the app to
03284    do the checking later.
03285    ??? On the other hand, parsing of such insns may require their hardware or
03286    operand elements to be in the table [which they mightn't be].  */
03287 
03288 static void
03289 build_insn_table (CGEN_CPU_TABLE *cd)
03290 {
03291   int i;
03292   const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
03293   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
03294 
03295   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
03296   for (i = 0; i < MAX_INSNS; ++i)
03297     insns[i].base = &ib[i];
03298   cd->insn_table.init_entries = insns;
03299   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
03300   cd->insn_table.num_init_entries = MAX_INSNS;
03301 }
03302 
03303 /* Subroutine of xc16x_cgen_cpu_open to rebuild the tables.  */
03304 
03305 static void
03306 xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
03307 {
03308   int i;
03309   CGEN_BITSET *isas = cd->isas;
03310   unsigned int machs = cd->machs;
03311 
03312   cd->int_insn_p = CGEN_INT_INSN_P;
03313 
03314   /* Data derived from the isa spec.  */
03315 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
03316   cd->default_insn_bitsize = UNSET;
03317   cd->base_insn_bitsize = UNSET;
03318   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
03319   cd->max_insn_bitsize = 0;
03320   for (i = 0; i < MAX_ISAS; ++i)
03321     if (cgen_bitset_contains (isas, i))
03322       {
03323        const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];
03324 
03325        /* Default insn sizes of all selected isas must be
03326           equal or we set the result to 0, meaning "unknown".  */
03327        if (cd->default_insn_bitsize == UNSET)
03328          cd->default_insn_bitsize = isa->default_insn_bitsize;
03329        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
03330          ; /* This is ok.  */
03331        else
03332          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
03333 
03334        /* Base insn sizes of all selected isas must be equal
03335           or we set the result to 0, meaning "unknown".  */
03336        if (cd->base_insn_bitsize == UNSET)
03337          cd->base_insn_bitsize = isa->base_insn_bitsize;
03338        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
03339          ; /* This is ok.  */
03340        else
03341          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
03342 
03343        /* Set min,max insn sizes.  */
03344        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
03345          cd->min_insn_bitsize = isa->min_insn_bitsize;
03346        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
03347          cd->max_insn_bitsize = isa->max_insn_bitsize;
03348       }
03349 
03350   /* Data derived from the mach spec.  */
03351   for (i = 0; i < MAX_MACHS; ++i)
03352     if (((1 << i) & machs) != 0)
03353       {
03354        const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];
03355 
03356        if (mach->insn_chunk_bitsize != 0)
03357        {
03358          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
03359            {
03360              fprintf (stderr, "xc16x_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
03361                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
03362              abort ();
03363            }
03364 
03365          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
03366        }
03367       }
03368 
03369   /* Determine which hw elements are used by MACH.  */
03370   build_hw_table (cd);
03371 
03372   /* Build the ifield table.  */
03373   build_ifield_table (cd);
03374 
03375   /* Determine which operands are used by MACH/ISA.  */
03376   build_operand_table (cd);
03377 
03378   /* Build the instruction table.  */
03379   build_insn_table (cd);
03380 }
03381 
03382 /* Initialize a cpu table and return a descriptor.
03383    It's much like opening a file, and must be the first function called.
03384    The arguments are a set of (type/value) pairs, terminated with
03385    CGEN_CPU_OPEN_END.
03386 
03387    Currently supported values:
03388    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
03389    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
03390    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
03391    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
03392    CGEN_CPU_OPEN_END:     terminates arguments
03393 
03394    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
03395    precluded.
03396 
03397    ??? We only support ISO C stdargs here, not K&R.
03398    Laziness, plus experiment to see if anything requires K&R - eventually
03399    K&R will no longer be supported - e.g. GDB is currently trying this.  */
03400 
03401 CGEN_CPU_DESC
03402 xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
03403 {
03404   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
03405   static int init_p;
03406   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
03407   unsigned int machs = 0; /* 0 = "unspecified" */
03408   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
03409   va_list ap;
03410 
03411   if (! init_p)
03412     {
03413       init_tables ();
03414       init_p = 1;
03415     }
03416 
03417   memset (cd, 0, sizeof (*cd));
03418 
03419   va_start (ap, arg_type);
03420   while (arg_type != CGEN_CPU_OPEN_END)
03421     {
03422       switch (arg_type)
03423        {
03424        case CGEN_CPU_OPEN_ISAS :
03425          isas = va_arg (ap, CGEN_BITSET *);
03426          break;
03427        case CGEN_CPU_OPEN_MACHS :
03428          machs = va_arg (ap, unsigned int);
03429          break;
03430        case CGEN_CPU_OPEN_BFDMACH :
03431          {
03432            const char *name = va_arg (ap, const char *);
03433            const CGEN_MACH *mach =
03434              lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);
03435 
03436            machs |= 1 << mach->num;
03437            break;
03438          }
03439        case CGEN_CPU_OPEN_ENDIAN :
03440          endian = va_arg (ap, enum cgen_endian);
03441          break;
03442        default :
03443          fprintf (stderr, "xc16x_cgen_cpu_open: unsupported argument `%d'\n",
03444                  arg_type);
03445          abort (); /* ??? return NULL? */
03446        }
03447       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
03448     }
03449   va_end (ap);
03450 
03451   /* Mach unspecified means "all".  */
03452   if (machs == 0)
03453     machs = (1 << MAX_MACHS) - 1;
03454   /* Base mach is always selected.  */
03455   machs |= 1;
03456   if (endian == CGEN_ENDIAN_UNKNOWN)
03457     {
03458       /* ??? If target has only one, could have a default.  */
03459       fprintf (stderr, "xc16x_cgen_cpu_open: no endianness specified\n");
03460       abort ();
03461     }
03462 
03463   cd->isas = cgen_bitset_copy (isas);
03464   cd->machs = machs;
03465   cd->endian = endian;
03466   /* FIXME: for the sparc case we can determine insn-endianness statically.
03467      The worry here is where both data and insn endian can be independently
03468      chosen, in which case this function will need another argument.
03469      Actually, will want to allow for more arguments in the future anyway.  */
03470   cd->insn_endian = endian;
03471 
03472   /* Table (re)builder.  */
03473   cd->rebuild_tables = xc16x_cgen_rebuild_tables;
03474   xc16x_cgen_rebuild_tables (cd);
03475 
03476   /* Default to not allowing signed overflow.  */
03477   cd->signed_overflow_ok_p = 0;
03478   
03479   return (CGEN_CPU_DESC) cd;
03480 }
03481 
03482 /* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
03483    MACH_NAME is the bfd name of the mach.  */
03484 
03485 CGEN_CPU_DESC
03486 xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
03487 {
03488   return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
03489                             CGEN_CPU_OPEN_ENDIAN, endian,
03490                             CGEN_CPU_OPEN_END);
03491 }
03492 
03493 /* Close a cpu table.
03494    ??? This can live in a machine independent file, but there's currently
03495    no place to put this file (there's no libcgen).  libopcodes is the wrong
03496    place as some simulator ports use this but they don't use libopcodes.  */
03497 
03498 void
03499 xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
03500 {
03501   unsigned int i;
03502   const CGEN_INSN *insns;
03503 
03504   if (cd->macro_insn_table.init_entries)
03505     {
03506       insns = cd->macro_insn_table.init_entries;
03507       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
03508        if (CGEN_INSN_RX ((insns)))
03509          regfree (CGEN_INSN_RX (insns));
03510     }
03511 
03512   if (cd->insn_table.init_entries)
03513     {
03514       insns = cd->insn_table.init_entries;
03515       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
03516        if (CGEN_INSN_RX (insns))
03517          regfree (CGEN_INSN_RX (insns));
03518     }  
03519 
03520   if (cd->macro_insn_table.init_entries)
03521     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
03522 
03523   if (cd->insn_table.init_entries)
03524     free ((CGEN_INSN *) cd->insn_table.init_entries);
03525 
03526   if (cd->hw_table.entries)
03527     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
03528 
03529   if (cd->operand_table.entries)
03530     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
03531 
03532   free (cd);
03533 }
03534