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cell-binutils  2.17cvs20070401
Defines | Functions | Variables
xc16x-desc.c File Reference
#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "xc16x-desc.h"
#include "xc16x-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"

Go to the source code of this file.

Defines

#define A(a)   (1 << CGEN_HW_a)
#define A(a)   (1 << CGEN_IFLD_a)
#define A(a)   (1 << CGEN_OPERAND_a)
#define OPERAND(op)   XC16X_OPERAND_op
#define OP(field)   CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#define A(a)   (1 << CGEN_INSN_a)
#define UNSET   (CGEN_SIZE_UNKNOWN + 1)

Functions

static void init_tables (void)
static const CGEN_MACHlookup_mach_via_bfd_name (const CGEN_MACH *, const char *)
static void build_hw_table (CGEN_CPU_TABLE *)
static void build_ifield_table (CGEN_CPU_TABLE *)
static void build_operand_table (CGEN_CPU_TABLE *)
static void build_insn_table (CGEN_CPU_TABLE *)
static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *)
CGEN_CPU_DESC xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type,...)
CGEN_CPU_DESC xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
void xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)

Variables

static const CGEN_ATTR_ENTRY bool_attr []
static const CGEN_ATTR_ENTRY
MACH_attr[] 
ATTRIBUTE_UNUSED
const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table []
const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table []
const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table []
const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table []
static const CGEN_ISA xc16x_cgen_isa_table []
static const CGEN_MACH xc16x_cgen_mach_table []
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_gr_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_ext_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_psw_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_grb_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_grb8_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_r8_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_regmem8_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries []
CGEN_KEYWORD xc16x_cgen_opval_reg0_name
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries []
CGEN_KEYWORD xc16x_cgen_opval_reg0_name1
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names
static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries []
CGEN_KEYWORD xc16x_cgen_opval_memgr8_names
const CGEN_HW_ENTRY xc16x_cgen_hw_table []
const CGEN_IFLD xc16x_cgen_ifld_table []
const CGEN_OPERAND xc16x_cgen_operand_table []
static const CGEN_IBASE xc16x_cgen_insn_table [MAX_INSNS]

Define Documentation

#define A (   a)    (1 << CGEN_HW_a)

Definition at line 1029 of file xc16x-desc.c.

#define A (   a)    (1 << CGEN_IFLD_a)

Definition at line 1029 of file xc16x-desc.c.

#define A (   a)    (1 << CGEN_OPERAND_a)

Definition at line 1029 of file xc16x-desc.c.

#define A (   a)    (1 << CGEN_INSN_a)

Definition at line 1029 of file xc16x-desc.c.

#define OP (   field)    CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))

Definition at line 1025 of file xc16x-desc.c.

#define OPERAND (   op)    XC16X_OPERAND_op

Definition at line 749 of file xc16x-desc.c.

#define UNSET   (CGEN_SIZE_UNKNOWN + 1)

Function Documentation

static void build_hw_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 3224 of file xc16x-desc.c.

{
  int i;
  int machs = cd->machs;
  const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
  /* MAX_HW is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_HW_ENTRY **selected =
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));

  cd->hw_table.init_entries = init;
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
  /* ??? For now we just use machs to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
       & machs)
      selected[init[i].type] = &init[i];
  cd->hw_table.entries = selected;
  cd->hw_table.num_entries = MAX_HW;
}

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static void build_ifield_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 3250 of file xc16x-desc.c.

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static void build_insn_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 3289 of file xc16x-desc.c.

{
  int i;
  const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));

  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
  for (i = 0; i < MAX_INSNS; ++i)
    insns[i].base = &ib[i];
  cd->insn_table.init_entries = insns;
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
  cd->insn_table.num_init_entries = MAX_INSNS;
}

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static void build_operand_table ( CGEN_CPU_TABLE cd) [static]

Definition at line 3258 of file xc16x-desc.c.

{
  int i;
  int machs = cd->machs;
  const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
     However each entry is indexed by it's enum so there can be holes in
     the table.  */
  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));

  cd->operand_table.init_entries = init;
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
  /* ??? For now we just use mach to determine which ones we want.  */
  for (i = 0; init[i].name != NULL; ++i)
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
       & machs)
      selected[init[i].type] = &init[i];
  cd->operand_table.entries = selected;
  cd->operand_table.num_entries = MAX_OPERANDS;
}

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static void init_tables ( void  ) [static]

Definition at line 3196 of file xc16x-desc.c.

{
}

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static const CGEN_MACH * lookup_mach_via_bfd_name ( const CGEN_MACH table,
const char *  name 
) [static]

Definition at line 3210 of file xc16x-desc.c.

{
  while (table->name)
    {
      if (strcmp (name, table->bfd_name) == 0)
       return table;
      ++table;
    }
  abort ();
}

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Definition at line 3499 of file xc16x-desc.c.

{
  unsigned int i;
  const CGEN_INSN *insns;

  if (cd->macro_insn_table.init_entries)
    {
      insns = cd->macro_insn_table.init_entries;
      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
       if (CGEN_INSN_RX ((insns)))
         regfree (CGEN_INSN_RX (insns));
    }

  if (cd->insn_table.init_entries)
    {
      insns = cd->insn_table.init_entries;
      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
       if (CGEN_INSN_RX (insns))
         regfree (CGEN_INSN_RX (insns));
    }  

  if (cd->macro_insn_table.init_entries)
    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);

  if (cd->insn_table.init_entries)
    free ((CGEN_INSN *) cd->insn_table.init_entries);

  if (cd->hw_table.entries)
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);

  if (cd->operand_table.entries)
    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);

  free (cd);
}

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CGEN_CPU_DESC xc16x_cgen_cpu_open ( enum cgen_cpu_open_arg  arg_type,
  ... 
)

Definition at line 3402 of file xc16x-desc.c.

{
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
  static int init_p;
  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
  unsigned int machs = 0; /* 0 = "unspecified" */
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
  va_list ap;

  if (! init_p)
    {
      init_tables ();
      init_p = 1;
    }

  memset (cd, 0, sizeof (*cd));

  va_start (ap, arg_type);
  while (arg_type != CGEN_CPU_OPEN_END)
    {
      switch (arg_type)
       {
       case CGEN_CPU_OPEN_ISAS :
         isas = va_arg (ap, CGEN_BITSET *);
         break;
       case CGEN_CPU_OPEN_MACHS :
         machs = va_arg (ap, unsigned int);
         break;
       case CGEN_CPU_OPEN_BFDMACH :
         {
           const char *name = va_arg (ap, const char *);
           const CGEN_MACH *mach =
             lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);

           machs |= 1 << mach->num;
           break;
         }
       case CGEN_CPU_OPEN_ENDIAN :
         endian = va_arg (ap, enum cgen_endian);
         break;
       default :
         fprintf (stderr, "xc16x_cgen_cpu_open: unsupported argument `%d'\n",
                 arg_type);
         abort (); /* ??? return NULL? */
       }
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
    }
  va_end (ap);

  /* Mach unspecified means "all".  */
  if (machs == 0)
    machs = (1 << MAX_MACHS) - 1;
  /* Base mach is always selected.  */
  machs |= 1;
  if (endian == CGEN_ENDIAN_UNKNOWN)
    {
      /* ??? If target has only one, could have a default.  */
      fprintf (stderr, "xc16x_cgen_cpu_open: no endianness specified\n");
      abort ();
    }

  cd->isas = cgen_bitset_copy (isas);
  cd->machs = machs;
  cd->endian = endian;
  /* FIXME: for the sparc case we can determine insn-endianness statically.
     The worry here is where both data and insn endian can be independently
     chosen, in which case this function will need another argument.
     Actually, will want to allow for more arguments in the future anyway.  */
  cd->insn_endian = endian;

  /* Table (re)builder.  */
  cd->rebuild_tables = xc16x_cgen_rebuild_tables;
  xc16x_cgen_rebuild_tables (cd);

  /* Default to not allowing signed overflow.  */
  cd->signed_overflow_ok_p = 0;
  
  return (CGEN_CPU_DESC) cd;
}

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CGEN_CPU_DESC xc16x_cgen_cpu_open_1 ( const char *  mach_name,
enum cgen_endian  endian 
)

Definition at line 3486 of file xc16x-desc.c.

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static void xc16x_cgen_rebuild_tables ( CGEN_CPU_TABLE cd) [static]

Definition at line 3306 of file xc16x-desc.c.

{
  int i;
  CGEN_BITSET *isas = cd->isas;
  unsigned int machs = cd->machs;

  cd->int_insn_p = CGEN_INT_INSN_P;

  /* Data derived from the isa spec.  */
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
  cd->default_insn_bitsize = UNSET;
  cd->base_insn_bitsize = UNSET;
  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
  cd->max_insn_bitsize = 0;
  for (i = 0; i < MAX_ISAS; ++i)
    if (cgen_bitset_contains (isas, i))
      {
       const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];

       /* Default insn sizes of all selected isas must be
          equal or we set the result to 0, meaning "unknown".  */
       if (cd->default_insn_bitsize == UNSET)
         cd->default_insn_bitsize = isa->default_insn_bitsize;
       else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
         ; /* This is ok.  */
       else
         cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;

       /* Base insn sizes of all selected isas must be equal
          or we set the result to 0, meaning "unknown".  */
       if (cd->base_insn_bitsize == UNSET)
         cd->base_insn_bitsize = isa->base_insn_bitsize;
       else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
         ; /* This is ok.  */
       else
         cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;

       /* Set min,max insn sizes.  */
       if (isa->min_insn_bitsize < cd->min_insn_bitsize)
         cd->min_insn_bitsize = isa->min_insn_bitsize;
       if (isa->max_insn_bitsize > cd->max_insn_bitsize)
         cd->max_insn_bitsize = isa->max_insn_bitsize;
      }

  /* Data derived from the mach spec.  */
  for (i = 0; i < MAX_MACHS; ++i)
    if (((1 << i) & machs) != 0)
      {
       const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];

       if (mach->insn_chunk_bitsize != 0)
       {
         if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
           {
             fprintf (stderr, "xc16x_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
                     cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
             abort ();
           }

         cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
       }
      }

  /* Determine which hw elements are used by MACH.  */
  build_hw_table (cd);

  /* Build the ifield table.  */
  build_ifield_table (cd);

  /* Determine which operands are used by MACH/ISA.  */
  build_operand_table (cd);

  /* Build the instruction table.  */
  build_insn_table (cd);
}

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Variable Documentation

const CGEN_ATTR_ENTRY PIPE_attr [] ATTRIBUTE_UNUSED [static]
Initial value:
{
  { "base", MACH_BASE },
  { "xc16x", MACH_XC16X },
  { "max", MACH_MAX },
  { 0, 0 }
}

Definition at line 46 of file xc16x-desc.c.

Initial value:
{
  { "#f", 0 },
  { "#t", 1 },
  { 0, 0 }
}

Definition at line 39 of file xc16x-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  { "PC", &bool_attr[0], &bool_attr[0] },
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 81 of file xc16x-desc.c.

Initial value:
{
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
  { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
}

Definition at line 631 of file xc16x-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "RELOC", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 68 of file xc16x-desc.c.

Definition at line 670 of file xc16x-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
  { "RELAXED", &bool_attr[0], &bool_attr[0] },
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
  { "PBB", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 112 of file xc16x-desc.c.

Definition at line 1032 of file xc16x-desc.c.

Initial value:
 {
  { "xc16x", 16, 32, 16, 32 },
  { 0, 0, 0, 0, 0 }
}

Definition at line 131 of file xc16x-desc.c.

Initial value:
 {
  { "xc16x", "xc16x", MACH_XC16X, 32 },
  { 0, 0, 0, 0 }
}

Definition at line 138 of file xc16x-desc.c.

Initial value:
{
  { "MACH", & MACH_attr[0], & MACH_attr[0] },
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  { "RELAX", &bool_attr[0], &bool_attr[0] },
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  { "RELOC", &bool_attr[0], &bool_attr[0] },
  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
  { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
  { 0, 0, 0 }
}

Definition at line 91 of file xc16x-desc.c.

Definition at line 752 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_conditioncode_names_entries[0],
  20,
  0, 0, 0, 0, ""
}

Definition at line 268 of file xc16x-desc.c.

Initial value:
{
  { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 244 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_ext_names_entries[0],
  8,
  0, 0, 0, 0, ""
}

Definition at line 182 of file xc16x-desc.c.

Initial value:
{
  { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 170 of file xc16x-desc.c.

Initial value:

Definition at line 303 of file xc16x-desc.c.

Initial value:
{
  { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 275 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_gr_names_entries[0],
  16,
  0, 0, 0, 0, ""
}

Definition at line 163 of file xc16x-desc.c.

Initial value:
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 143 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_grb8_names_entries[0],
  36,
  0, 0, 0, 0, ""
}

Definition at line 350 of file xc16x-desc.c.

Definition at line 310 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_grb_names_entries[0],
  16,
  0, 0, 0, 0, ""
}

Definition at line 237 of file xc16x-desc.c.

Initial value:
{
  { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
  { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
  { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
  { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
  { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
  { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
  { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
  { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 217 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_memgr8_names_entries[0],
  20,
  0, 0, 0, 0, ""
}

Definition at line 615 of file xc16x-desc.c.

Initial value:
{
  { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
  { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
  { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
  { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
  { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
  { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
  { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
  { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
  { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
  { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
  { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
  { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
  { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
  { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
  { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
  { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
  { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 591 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_psw_names_entries[0],
  17,
  0, 0, 0, 0, ""
}

Definition at line 210 of file xc16x-desc.c.

Initial value:
{
  { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
  { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
  { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
  { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
  { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
  { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
  { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
  { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
  { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
  { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
  { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
  { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
  { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
  { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
  { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
  { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 189 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_r8_names_entries[0],
  36,
  0, 0, 0, 0, ""
}

Definition at line 397 of file xc16x-desc.c.

Definition at line 357 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_reg0_name_entries[0],
  30,
  0, 0, 0, 0, ""
}

Definition at line 512 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_reg0_name1_entries[0],
  14,
  0, 0, 0, 0, ""
}

Definition at line 537 of file xc16x-desc.c.

Initial value:
{
  { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
  { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
  { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
  { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
  { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
  { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
  { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
  { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 519 of file xc16x-desc.c.

Definition at line 478 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_regbmem8_names_entries[0],
  36,
  0, 0, 0, 0, ""
}

Definition at line 584 of file xc16x-desc.c.

Definition at line 544 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_regdiv8_names_entries[0],
  16,
  0, 0, 0, 0, ""
}

Definition at line 471 of file xc16x-desc.c.

Initial value:
{
  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
  { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
  { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
  { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
  { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
  { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
  { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
  { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
  { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
  { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
  { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
  { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
  { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
  { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
  { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
}

Definition at line 451 of file xc16x-desc.c.

Initial value:
{
  & xc16x_cgen_opval_regmem8_names_entries[0],
  36,
  0, 0, 0, 0, ""
}

Definition at line 444 of file xc16x-desc.c.

Definition at line 404 of file xc16x-desc.c.