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cell-binutils  2.17cvs20070401
tic80-opc.c
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00001 /* Opcode table for TI TMS320C80 (MVP).
00002    Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
00003 
00004 This file is part of GDB, GAS, and the GNU binutils.
00005 
00006 GDB, GAS, and the GNU binutils are free software; you can redistribute
00007 them and/or modify them under the terms of the GNU General Public
00008 License as published by the Free Software Foundation; either version
00009 1, or (at your option) any later version.
00010 
00011 GDB, GAS, and the GNU binutils are distributed in the hope that they
00012 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00013 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00014 the GNU General Public License for more details.
00015 
00016 You should have received a copy of the GNU General Public License
00017 along with this file; see the file COPYING.  If not, write to the Free
00018 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00019 02110-1301, USA.  */
00020 
00021 #include <stdio.h>
00022 #include "sysdep.h"
00023 #include "opcode/tic80.h"
00024 
00025 /* This file holds various tables for the TMS320C80 (MVP).
00026 
00027    The opcode table is strictly constant data, so the compiler should
00028    be able to put it in the .text section.
00029 
00030    This file also holds the operand table.  All knowledge about
00031    inserting operands into instructions and vice-versa is kept in this
00032    file.
00033 
00034    The predefined register table maps from register names to register
00035    values.  */
00036 
00037 
00038 /* Table of predefined symbol names, such as general purpose registers,
00039    floating point registers, condition codes, control registers, and bit
00040    numbers.
00041 
00042    The table is sorted case independently by name so that it is suitable for
00043    searching via a binary search using a case independent comparison
00044    function.
00045 
00046    Note that the type of the symbol is stored in the upper bits of the value
00047    field, which allows the value and type to be passed around as a unit in a
00048    single int.  The types have to be masked off before using the numeric
00049    value as a number.
00050 */
00051 
00052 const struct predefined_symbol tic80_predefined_symbols[] =
00053 {
00054   { "a0",     TIC80_OPERAND_FPA | 0 },
00055   { "a1",     TIC80_OPERAND_FPA | 1 },
00056   { "alw.b",  TIC80_OPERAND_CC | 7 },
00057   { "alw.h",  TIC80_OPERAND_CC | 15 },
00058   { "alw.w",  TIC80_OPERAND_CC | 23 },
00059   { "ANASTAT",       TIC80_OPERAND_CR | 0x34 },
00060   { "BRK1",   TIC80_OPERAND_CR | 0x39 },
00061   { "BRK2",   TIC80_OPERAND_CR | 0x3A },
00062   { "CONFIG", TIC80_OPERAND_CR | 2 },
00063   { "DLRU",   TIC80_OPERAND_CR | 0x500 },
00064   { "DTAG0",  TIC80_OPERAND_CR | 0x400 },
00065   { "DTAG1",  TIC80_OPERAND_CR | 0x401 },
00066   { "DTAG10", TIC80_OPERAND_CR | 0x40A },
00067   { "DTAG11", TIC80_OPERAND_CR | 0x40B },
00068   { "DTAG12", TIC80_OPERAND_CR | 0x40C },
00069   { "DTAG13", TIC80_OPERAND_CR | 0x40D },
00070   { "DTAG14", TIC80_OPERAND_CR | 0x40E },
00071   { "DTAG15", TIC80_OPERAND_CR | 0x40F },
00072   { "DTAG2",  TIC80_OPERAND_CR | 0x402 },
00073   { "DTAG3",  TIC80_OPERAND_CR | 0x403 },
00074   { "DTAG4",  TIC80_OPERAND_CR | 0x404 },
00075   { "DTAG5",  TIC80_OPERAND_CR | 0x405 },
00076   { "DTAG6",  TIC80_OPERAND_CR | 0x406 },
00077   { "DTAG7",  TIC80_OPERAND_CR | 0x407 },
00078   { "DTAG8",  TIC80_OPERAND_CR | 0x408 },
00079   { "DTAG9",  TIC80_OPERAND_CR | 0x409 },
00080   { "ECOMCNTL",      TIC80_OPERAND_CR | 0x33 },
00081   { "EIP",    TIC80_OPERAND_CR | 1 },
00082   { "EPC",    TIC80_OPERAND_CR | 0 },
00083   { "eq.b",   TIC80_OPERAND_BITNUM  | 0 },
00084   { "eq.f",   TIC80_OPERAND_BITNUM  | 20 },
00085   { "eq.h",   TIC80_OPERAND_BITNUM  | 10 },
00086   { "eq.w",   TIC80_OPERAND_BITNUM  | 20 },
00087   { "eq0.b",  TIC80_OPERAND_CC | 2 },
00088   { "eq0.h",  TIC80_OPERAND_CC | 10 },
00089   { "eq0.w",  TIC80_OPERAND_CC | 18 },
00090   { "FLTADR", TIC80_OPERAND_CR | 0x11 },
00091   { "FLTDTH", TIC80_OPERAND_CR | 0x14 },
00092   { "FLTDTL", TIC80_OPERAND_CR | 0x13 },
00093   { "FLTOP",  TIC80_OPERAND_CR | 0x10 },
00094   { "FLTTAG", TIC80_OPERAND_CR | 0x12 },
00095   { "FPST",   TIC80_OPERAND_CR | 8 },
00096   { "ge.b",   TIC80_OPERAND_BITNUM  | 5 },
00097   { "ge.f",   TIC80_OPERAND_BITNUM  | 25 },
00098   { "ge.h",   TIC80_OPERAND_BITNUM  | 15 },
00099   { "ge.w",   TIC80_OPERAND_BITNUM  | 25 },
00100   { "ge0.b",  TIC80_OPERAND_CC | 3 },
00101   { "ge0.h",  TIC80_OPERAND_CC | 11 },
00102   { "ge0.w",  TIC80_OPERAND_CC | 19 },
00103   { "gt.b",   TIC80_OPERAND_BITNUM  | 2 },
00104   { "gt.f",   TIC80_OPERAND_BITNUM  | 22 },
00105   { "gt.h",   TIC80_OPERAND_BITNUM  | 12 },
00106   { "gt.w",   TIC80_OPERAND_BITNUM  | 22 },
00107   { "gt0.b",  TIC80_OPERAND_CC | 1 },
00108   { "gt0.h",  TIC80_OPERAND_CC | 9 },
00109   { "gt0.w",  TIC80_OPERAND_CC | 17 },
00110   { "hi.b",   TIC80_OPERAND_BITNUM  | 6 },
00111   { "hi.h",   TIC80_OPERAND_BITNUM  | 16 },
00112   { "hi.w",   TIC80_OPERAND_BITNUM  | 26 },
00113   { "hs.b",   TIC80_OPERAND_BITNUM  | 9 },
00114   { "hs.h",   TIC80_OPERAND_BITNUM  | 19 },
00115   { "hs.w",   TIC80_OPERAND_BITNUM  | 29 },
00116   { "ib.f",   TIC80_OPERAND_BITNUM  | 28 },
00117   { "IE",     TIC80_OPERAND_CR | 6 },
00118   { "ILRU",   TIC80_OPERAND_CR | 0x300 },
00119   { "in.f",   TIC80_OPERAND_BITNUM  | 27 },
00120   { "IN0P",   TIC80_OPERAND_CR | 0x4000 },
00121   { "IN1P",   TIC80_OPERAND_CR | 0x4001 },
00122   { "INTPEN", TIC80_OPERAND_CR | 4 },
00123   { "ITAG0",  TIC80_OPERAND_CR | 0x200 },
00124   { "ITAG1",  TIC80_OPERAND_CR | 0x201 },
00125   { "ITAG10", TIC80_OPERAND_CR | 0x20A },
00126   { "ITAG11", TIC80_OPERAND_CR | 0x20B },
00127   { "ITAG12", TIC80_OPERAND_CR | 0x20C },
00128   { "ITAG13", TIC80_OPERAND_CR | 0x20D },
00129   { "ITAG14", TIC80_OPERAND_CR | 0x20E },
00130   { "ITAG15", TIC80_OPERAND_CR | 0x20F },
00131   { "ITAG2",  TIC80_OPERAND_CR | 0x202 },
00132   { "ITAG3",  TIC80_OPERAND_CR | 0x203 },
00133   { "ITAG4",  TIC80_OPERAND_CR | 0x204 },
00134   { "ITAG5",  TIC80_OPERAND_CR | 0x205 },
00135   { "ITAG6",  TIC80_OPERAND_CR | 0x206 },
00136   { "ITAG7",  TIC80_OPERAND_CR | 0x207 },
00137   { "ITAG8",  TIC80_OPERAND_CR | 0x208 },
00138   { "ITAG9",  TIC80_OPERAND_CR | 0x209 },
00139   { "le.b",   TIC80_OPERAND_BITNUM  | 3 },
00140   { "le.f",   TIC80_OPERAND_BITNUM  | 23 },
00141   { "le.h",   TIC80_OPERAND_BITNUM  | 13 },
00142   { "le.w",   TIC80_OPERAND_BITNUM  | 23 },
00143   { "le0.b",  TIC80_OPERAND_CC | 6 },
00144   { "le0.h",  TIC80_OPERAND_CC | 14 },
00145   { "le0.w",  TIC80_OPERAND_CC | 22 },
00146   { "lo.b",   TIC80_OPERAND_BITNUM  | 8 },
00147   { "lo.h",   TIC80_OPERAND_BITNUM  | 18 },
00148   { "lo.w",   TIC80_OPERAND_BITNUM  | 28 },
00149   { "ls.b",   TIC80_OPERAND_BITNUM  | 7 },
00150   { "ls.h",   TIC80_OPERAND_BITNUM  | 17 },
00151   { "ls.w",   TIC80_OPERAND_BITNUM  | 27 },
00152   { "lt.b",   TIC80_OPERAND_BITNUM  | 4 },
00153   { "lt.f",   TIC80_OPERAND_BITNUM  | 24 },
00154   { "lt.h",   TIC80_OPERAND_BITNUM  | 14 },
00155   { "lt.w",   TIC80_OPERAND_BITNUM  | 24 },
00156   { "lt0.b",  TIC80_OPERAND_CC | 4 },
00157   { "lt0.h",  TIC80_OPERAND_CC | 12 },
00158   { "lt0.w",  TIC80_OPERAND_CC | 20 },
00159   { "MIP",    TIC80_OPERAND_CR | 0x31 },
00160   { "MPC",    TIC80_OPERAND_CR | 0x30 },
00161   { "ne.b",   TIC80_OPERAND_BITNUM  | 1 },
00162   { "ne.f",   TIC80_OPERAND_BITNUM  | 21 },
00163   { "ne.h",   TIC80_OPERAND_BITNUM  | 11 },
00164   { "ne.w",   TIC80_OPERAND_BITNUM  | 21 },
00165   { "ne0.b",  TIC80_OPERAND_CC | 5 },
00166   { "ne0.h",  TIC80_OPERAND_CC | 13 },
00167   { "ne0.w",  TIC80_OPERAND_CC | 21 },
00168   { "nev.b",  TIC80_OPERAND_CC | 0 },
00169   { "nev.h",  TIC80_OPERAND_CC | 8 },
00170   { "nev.w",  TIC80_OPERAND_CC | 16 },
00171   { "ob.f",   TIC80_OPERAND_BITNUM  | 29 },
00172   { "or.f",   TIC80_OPERAND_BITNUM  | 31 },
00173   { "ou.f",   TIC80_OPERAND_BITNUM  | 26 },
00174   { "OUTP",   TIC80_OPERAND_CR | 0x4002 },
00175   { "PKTREQ", TIC80_OPERAND_CR | 0xD },
00176   { "PPERROR",       TIC80_OPERAND_CR | 0xA },
00177   { "r0",     TIC80_OPERAND_GPR | 0 },
00178   { "r1",     TIC80_OPERAND_GPR | 1 },
00179   { "r10",    TIC80_OPERAND_GPR | 10 },
00180   { "r11",    TIC80_OPERAND_GPR | 11 },
00181   { "r12",    TIC80_OPERAND_GPR | 12 },
00182   { "r13",    TIC80_OPERAND_GPR | 13 },
00183   { "r14",    TIC80_OPERAND_GPR | 14 },
00184   { "r15",    TIC80_OPERAND_GPR | 15 },
00185   { "r16",    TIC80_OPERAND_GPR | 16 },
00186   { "r17",    TIC80_OPERAND_GPR | 17 },
00187   { "r18",    TIC80_OPERAND_GPR | 18 },
00188   { "r19",    TIC80_OPERAND_GPR | 19 },
00189   { "r2",     TIC80_OPERAND_GPR | 2 },
00190   { "r20",    TIC80_OPERAND_GPR | 20 },
00191   { "r21",    TIC80_OPERAND_GPR | 21 },
00192   { "r22",    TIC80_OPERAND_GPR | 22 },
00193   { "r23",    TIC80_OPERAND_GPR | 23 },
00194   { "r24",    TIC80_OPERAND_GPR | 24 },
00195   { "r25",    TIC80_OPERAND_GPR | 25 },
00196   { "r26",    TIC80_OPERAND_GPR | 26 },
00197   { "r27",    TIC80_OPERAND_GPR | 27 },
00198   { "r28",    TIC80_OPERAND_GPR | 28 },
00199   { "r29",    TIC80_OPERAND_GPR | 29 },
00200   { "r3",     TIC80_OPERAND_GPR | 3 },
00201   { "r30",    TIC80_OPERAND_GPR | 30 },
00202   { "r31",    TIC80_OPERAND_GPR | 31 },
00203   { "r4",     TIC80_OPERAND_GPR | 4 },
00204   { "r5",     TIC80_OPERAND_GPR | 5 },
00205   { "r6",     TIC80_OPERAND_GPR | 6 },
00206   { "r7",     TIC80_OPERAND_GPR | 7 },
00207   { "r8",     TIC80_OPERAND_GPR | 8 },
00208   { "r9",     TIC80_OPERAND_GPR | 9 },
00209   { "SYSSTK", TIC80_OPERAND_CR | 0x20 },
00210   { "SYSTMP", TIC80_OPERAND_CR | 0x21 },
00211   { "TCOUNT", TIC80_OPERAND_CR | 0xE },
00212   { "TSCALE", TIC80_OPERAND_CR | 0xF },
00213   { "uo.f",   TIC80_OPERAND_BITNUM  | 30 },
00214 };
00215 
00216 const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol);
00217 
00218 /* This function takes a predefined symbol name in NAME, symbol class
00219    in CLASS, and translates it to a numeric value, which it returns.
00220 
00221    If CLASS is zero, any symbol that matches NAME is translated.  If
00222    CLASS is non-zero, then only a symbol that has class CLASS is
00223    matched.
00224 
00225    If no translation is possible, it returns -1, a value not used by
00226    any predefined symbol. Note that the predefined symbol array is
00227    presorted case independently by name.
00228 
00229    This function is implemented with the assumption that there are no
00230    duplicate names in the predefined symbol array, which happens to be
00231    true at the moment.
00232 
00233  */
00234 
00235 int
00236 tic80_symbol_to_value (name, class)
00237      char *name;
00238      int class;
00239 {
00240   const struct predefined_symbol *pdsp;
00241   int low = 0;
00242   int middle;
00243   int high = tic80_num_predefined_symbols - 1;
00244   int cmp;
00245   int rtnval = -1;
00246 
00247   while (low <= high)
00248     {
00249       middle = (low + high) / 2;
00250       cmp = strcasecmp (name, tic80_predefined_symbols[middle].name);
00251       if (cmp < 0)
00252        {
00253          high = middle - 1;
00254        }
00255       else if (cmp > 0)
00256        {
00257          low = middle + 1;
00258        }
00259       else 
00260        {
00261          pdsp = &tic80_predefined_symbols[middle];
00262          if ((class == 0) || (class & PDS_VALUE (pdsp)))
00263            {
00264              rtnval = PDS_VALUE (pdsp);
00265            }
00266          /* For now we assume that there are no duplicate names */
00267          break;
00268        }
00269     }
00270   return (rtnval);
00271 }
00272 
00273 /* This function takes a value VAL and finds a matching predefined
00274    symbol that is in the operand class specified by CLASS.  If CLASS
00275    is zero, the first matching symbol is returned. */
00276 
00277 const char *
00278 tic80_value_to_symbol (val, class)
00279      int val;
00280      int class;
00281 {
00282   const struct predefined_symbol *pdsp;
00283   int ival;
00284   char *name;
00285 
00286   name = NULL;
00287   for (pdsp = tic80_predefined_symbols;
00288        pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols;
00289        pdsp++)
00290     {
00291       ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
00292       if (ival == val)
00293        {
00294          if ((class == 0) || (class & PDS_VALUE (pdsp)))
00295            {
00296              /* Found the desired match */
00297              name = PDS_NAME (pdsp);
00298              break;
00299            }
00300        }
00301     }
00302   return (name);
00303 }
00304 
00305 /* This function returns a pointer to the next symbol in the predefined
00306    symbol table after PDSP, or NULL if PDSP points to the last symbol.  If
00307    PDSP is NULL, it returns the first symbol in the table.  Thus it can be
00308    used to walk through the table by first calling it with NULL and then
00309    calling it with each value it returned on the previous call, until it
00310    returns NULL. */
00311 
00312 const struct predefined_symbol *
00313 tic80_next_predefined_symbol (pdsp)
00314      const struct predefined_symbol *pdsp;
00315 {
00316   if (pdsp == NULL)
00317     {
00318       pdsp = tic80_predefined_symbols;
00319     }
00320   else if (pdsp >= tic80_predefined_symbols &&
00321           pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1)
00322     {
00323       pdsp++;
00324     }
00325   else
00326     {
00327       pdsp = NULL;
00328     }
00329   return (pdsp);
00330 }
00331 
00332 
00333 
00334 /* The operands table.  The fields are:
00335 
00336        bits, shift, insertion function, extraction function, flags
00337  */
00338 
00339 const struct tic80_operand tic80_operands[] =
00340 {
00341 
00342   /* The zero index is used to indicate the end of the list of operands.  */
00343 
00344 #define UNUSED (0)
00345   { 0, 0, 0, 0, 0 },
00346 
00347   /* Short signed immediate value in bits 14-0. */
00348 
00349 #define SSI (UNUSED + 1)
00350   { 15, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
00351 
00352   /* Short unsigned immediate value in bits 14-0 */
00353 
00354 #define SUI (SSI + 1)
00355   { 15, 0, NULL, NULL, 0 },
00356 
00357   /* Short unsigned bitfield in bits 14-0.  We distinguish this
00358      from a regular unsigned immediate value only for the convenience
00359      of the disassembler and the user. */
00360 
00361 #define SUBF (SUI + 1)
00362   { 15, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
00363 
00364   /* Long signed immediate in following 32 bit word */
00365 
00366 #define LSI (SUBF + 1)
00367   { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED },
00368 
00369   /* Long unsigned immediate in following 32 bit word */
00370 
00371 #define LUI (LSI + 1)
00372   { 32, 0, NULL, NULL, 0 },
00373 
00374   /* Long unsigned bitfield in following 32 bit word.  We distinguish
00375      this from a regular unsigned immediate value only for the
00376      convenience of the disassembler and the user. */
00377 
00378 #define LUBF (LUI + 1)
00379   { 32, 0, NULL, NULL, TIC80_OPERAND_BITFIELD },
00380 
00381   /* Single precision floating point immediate in following 32 bit
00382      word. */
00383 
00384 #define SPFI (LUBF + 1)
00385   { 32, 0, NULL, NULL, TIC80_OPERAND_FLOAT },
00386 
00387   /* Register in bits 4-0 */
00388 
00389 #define REG_0 (SPFI + 1)
00390   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR },
00391 
00392   /* Even register in bits 4-0 */
00393 
00394 #define REG_0_E (REG_0 + 1)
00395   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
00396 
00397   /* Register in bits 26-22 */
00398 
00399 #define REG_22 (REG_0_E + 1)
00400   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR },
00401 
00402   /* Even register in bits 26-22 */
00403 
00404 #define REG_22_E (REG_22 + 1)
00405   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
00406 
00407   /* Register in bits 31-27 */
00408 
00409 #define REG_DEST (REG_22_E + 1)
00410   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
00411 
00412   /* Even register in bits 31-27 */
00413 
00414 #define REG_DEST_E (REG_DEST + 1)
00415   { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN },
00416 
00417   /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB)
00418      and bit 11 (LSB) */
00419   /* FIXME!  Needs to use functions to insert and extract the register
00420      number in bits 16 and 11. */
00421 
00422 #define REG_FPA (REG_DEST_E + 1)
00423   { 0, 0, NULL, NULL, TIC80_OPERAND_FPA },
00424 
00425   /* Short signed PC word offset in bits 14-0 */
00426 
00427 #define OFF_SS_PC (REG_FPA + 1)
00428   { 15, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
00429 
00430   /* Long signed PC word offset in following 32 bit word */
00431 
00432 #define OFF_SL_PC (OFF_SS_PC + 1)
00433   { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED },
00434 
00435   /* Short signed base relative byte offset in bits 14-0 */
00436 
00437 #define OFF_SS_BR (OFF_SL_PC + 1)
00438   { 15, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
00439 
00440   /* Long signed base relative byte offset in following 32 bit word */
00441 
00442 #define OFF_SL_BR (OFF_SS_BR + 1)
00443   { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED },
00444 
00445   /* Long signed base relative byte offset in following 32 bit word
00446      with optional ":s" modifier flag in bit 11 */
00447 
00448 #define OFF_SL_BR_SCALED (OFF_SL_BR + 1)
00449   { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED },
00450 
00451   /* BITNUM in bits 31-27 */
00452 
00453 #define BITNUM (OFF_SL_BR_SCALED + 1)
00454   { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
00455 
00456   /* Condition code in bits 31-27 */
00457 
00458 #define CC (BITNUM + 1)
00459   { 5, 27, NULL, NULL, TIC80_OPERAND_CC },
00460 
00461   /* Control register number in bits 14-0 */
00462 
00463 #define CR_SI (CC + 1)
00464   { 15, 0, NULL, NULL, TIC80_OPERAND_CR },
00465 
00466   /* Control register number in next 32 bit word */
00467 
00468 #define CR_LI (CR_SI + 1)
00469   { 32, 0, NULL, NULL, TIC80_OPERAND_CR },
00470 
00471   /* A base register in bits 26-22, enclosed in parens */
00472 
00473 #define REG_BASE (CR_LI + 1)
00474   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS },
00475 
00476   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
00477      flag in bit 17 (short immediate instructions only) */
00478 
00479 #define REG_BASE_M_SI (REG_BASE + 1)
00480   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_SI },
00481 
00482   /* A base register in bits 26-22, enclosed in parens, with optional ":m"
00483    flag in bit 15 (long immediate and register instructions only) */
00484 
00485 #define REG_BASE_M_LI (REG_BASE_M_SI + 1)
00486   { 5, 22, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_PARENS | TIC80_OPERAND_M_LI },
00487 
00488   /* Scaled register in bits 4-0, with optional ":s" modifier flag in bit 11 */
00489 
00490 #define REG_SCALED (REG_BASE_M_LI + 1)
00491   { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED },
00492 
00493   /* Unsigned immediate in bits 4-0, used only for shift instructions */
00494 
00495 #define ROTATE (REG_SCALED + 1)
00496   { 5, 0, NULL, NULL, 0 },
00497 
00498   /* Unsigned immediate in bits 9-5, used only for shift instructions */
00499 #define ENDMASK (ROTATE + 1)
00500   { 5, 5, NULL, NULL, TIC80_OPERAND_ENDMASK },
00501 
00502 };
00503 
00504 const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
00505 
00506 
00507 /* Macros used to generate entries for the opcodes table. */
00508 
00509 #define FIXME 0
00510 
00511 /* Short-Immediate Format Instructions - basic opcode */
00512 #define OP_SI(x)     (((x) & 0x7F) << 15)
00513 #define MASK_SI             OP_SI(0x7F)
00514 
00515 /* Long-Immediate Format Instructions - basic opcode */
00516 #define OP_LI(x)     (((x) & 0x3FF) << 12)
00517 #define MASK_LI             OP_LI(0x3FF)
00518 
00519 /* Register Format Instructions - basic opcode */
00520 #define OP_REG(x)    OP_LI(x)      /* For readability */
00521 #define MASK_REG     MASK_LI              /* For readability */
00522 
00523 /* The 'n' bit at bit 10 */
00524 #define n(x)         ((x) << 10)
00525 
00526 /* The 'i' bit at bit 11 */
00527 #define i(x)         ((x) << 11)
00528 
00529 /* The 'F' bit at bit 27 */
00530 #define F(x)         ((x) << 27)
00531 
00532 /* The 'E' bit at bit 27 */
00533 #define E(x)         ((x) << 27)
00534 
00535 /* The 'M' bit at bit 15 in register and long immediate opcodes */
00536 #define M_REG(x)     ((x) << 15)
00537 #define M_LI(x)             ((x) << 15)
00538 
00539 /* The 'M' bit at bit 17 in short immediate opcodes */
00540 #define M_SI(x)             ((x) << 17)
00541 
00542 /* The 'SZ' field at bits 14-13 in register and long immediate opcodes */
00543 #define SZ_REG(x)    ((x) << 13)
00544 #define SZ_LI(x)     ((x) << 13)
00545 
00546 /* The 'SZ' field at bits 16-15 in short immediate opcodes */
00547 #define SZ_SI(x)     ((x) << 15)
00548 
00549 /* The 'D' (direct external memory access) bit at bit 10 in long immediate
00550    and register opcodes. */
00551 #define D(x)         ((x) << 10)
00552 
00553 /* The 'S' (scale offset by data size) bit at bit 11 in long immediate
00554    and register opcodes. */
00555 #define S(x)         ((x) << 11)
00556 
00557 /* The 'PD' field at bits 10-9 in floating point instructions */
00558 #define PD(x)        ((x) << 9)
00559 
00560 /* The 'P2' field at bits 8-7 in floating point instructions */
00561 #define P2(x)        ((x) << 7)
00562 
00563 /* The 'P1' field at bits 6-5 in floating point instructions */
00564 #define P1(x)        ((x) << 5)
00565 
00566 /* The 'a' field at bit 16 in vector instructions */
00567 #define V_a1(x)             ((x) << 16)
00568 
00569 /* The 'a' field at bit 11 in vector instructions */
00570 #define V_a0(x)             ((x) << 11)
00571 
00572 /* The 'm' field at bit 10 in vector instructions */
00573 #define V_m(x)              ((x) << 10)
00574 
00575 /* The 'S' field at bit 9 in vector instructions */
00576 #define V_S(x)              ((x) << 9)
00577 
00578 /* The 'Z' field at bit 8 in vector instructions */
00579 #define V_Z(x)              ((x) << 8)
00580 
00581 /* The 'p' field at bit 6 in vector instructions */
00582 #define V_p(x)              ((x) << 6)
00583 
00584 /* The opcode field at bits 21-17 for vector instructions */
00585 #define OP_V(x)             ((x) << 17)
00586 #define MASK_V              OP_V(0x1F)
00587 
00588 
00589 /* The opcode table.  Formatted for better readability on a wide screen.  Also, all
00590  entries with the same mnemonic are sorted so that they are adjacent in the table,
00591  allowing the use of a hash table to locate the first of a sequence of opcodes that have
00592  a particular name.  The short immediate forms also come before the long immediate forms
00593  so that the assembler will pick the "best fit" for the size of the operand, except for
00594  the case of the PC relative forms, where the long forms come first and are the default
00595  forms. */
00596 
00597 const struct tic80_opcode tic80_opcodes[] = {
00598 
00599   /* The "nop" instruction is really "rdcr 0,r0".  We put it first so that this
00600      specific bit pattern will get disassembled as a nop rather than an rdcr. The
00601      mask of all ones ensures that this will happen. */
00602 
00603   {"nop",     OP_SI(0x4),   ~0,           0,            {0}                  },
00604 
00605   /* The "br" instruction is really "bbz target,r0,31".  We put it first so that
00606      this specific bit pattern will get disassembled as a br rather than bbz. */
00607 
00608   {"br",      OP_SI(0x48),  0xFFFF8000,   0,     {OFF_SS_PC}   },
00609   {"br",      OP_LI(0x391), 0xFFFFF000,   0,     {OFF_SL_PC}   },
00610   {"br",      OP_REG(0x390),       0xFFFFF000,   0,     {REG_0}              },
00611   {"br.a",    OP_SI(0x49),  0xFFFF8000,   0,     {OFF_SS_PC}   },
00612   {"br.a",    OP_LI(0x393), 0xFFFFF000,   0,     {OFF_SL_PC}   },
00613   {"br.a",    OP_REG(0x392),       0xFFFFF000,   0,     {REG_0}              },
00614 
00615   /* Signed integer ADD */
00616 
00617   {"add",     OP_SI(0x58),  MASK_SI,      0,     {SSI, REG_22, REG_DEST}            },
00618   {"add",     OP_LI(0x3B1), MASK_LI,      0,     {LSI, REG_22, REG_DEST}            },
00619   {"add",     OP_REG(0x3B0),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00620 
00621   /* Unsigned integer ADD */
00622 
00623   {"addu",    OP_SI(0x59),  MASK_SI,      0,     {SSI, REG_22, REG_DEST}            },
00624   {"addu",    OP_LI(0x3B3), MASK_LI,      0,     {LSI, REG_22, REG_DEST}            },
00625   {"addu",    OP_REG(0x3B2),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00626 
00627   /* Bitwise AND */
00628 
00629   {"and",     OP_SI(0x11),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST}    },
00630   {"and",     OP_LI(0x323), MASK_LI,      0,     {LUBF, REG_22, REG_DEST}    },
00631   {"and",     OP_REG(0x322),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00632   {"and.tt",  OP_SI(0x11),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST}    },
00633   {"and.tt",  OP_LI(0x323), MASK_LI,      0,     {LUBF, REG_22, REG_DEST}    },
00634   {"and.tt",  OP_REG(0x322),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00635 
00636   /* Bitwise AND with ones complement of both sources */
00637 
00638   {"and.ff",  OP_SI(0x18),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST}    },
00639   {"and.ff",  OP_LI(0x331), MASK_LI,      0,     {LUBF, REG_22, REG_DEST}    },
00640   {"and.ff",  OP_REG(0x330),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00641 
00642   /* Bitwise AND with ones complement of source 1 */
00643 
00644   {"and.ft",  OP_SI(0x14),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST}    },
00645   {"and.ft",  OP_LI(0x329), MASK_LI,      0,     {LUBF, REG_22, REG_DEST}    },
00646   {"and.ft",  OP_REG(0x328),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00647 
00648   /* Bitwise AND with ones complement of source 2 */
00649 
00650   {"and.tf",  OP_SI(0x12),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST}    },
00651   {"and.tf",  OP_LI(0x325), MASK_LI,      0,     {LUBF, REG_22, REG_DEST}    },
00652   {"and.tf",  OP_REG(0x324),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00653 
00654   /* Branch Bit One - nonannulled */
00655 
00656   {"bbo",     OP_SI(0x4A),  MASK_SI,      0,     {OFF_SS_PC, REG_22, BITNUM} },
00657   {"bbo",     OP_LI(0x395), MASK_LI,      0,     {OFF_SL_PC, REG_22, BITNUM} },
00658   {"bbo",     OP_REG(0x394),       MASK_REG,     0,     {REG_0, REG_22, BITNUM}            },
00659 
00660   /* Branch Bit One - annulled */
00661 
00662   {"bbo.a",   OP_SI(0x4B),  MASK_SI,      0,     {OFF_SS_PC, REG_22, BITNUM} },
00663   {"bbo.a",   OP_LI(0x397), MASK_LI,      0,     {OFF_SL_PC, REG_22, BITNUM} },
00664   {"bbo.a",   OP_REG(0x396),       MASK_REG,     0,     {REG_0, REG_22, BITNUM}            },
00665 
00666   /* Branch Bit Zero - nonannulled */
00667 
00668   {"bbz",     OP_SI(0x48),  MASK_SI,      0,     {OFF_SS_PC, REG_22, BITNUM} },
00669   {"bbz",     OP_LI(0x391), MASK_LI,      0,     {OFF_SL_PC, REG_22, BITNUM} },
00670   {"bbz",     OP_REG(0x390),       MASK_REG,     0,     {REG_0, REG_22, BITNUM}            },
00671 
00672   /* Branch Bit Zero - annulled */
00673 
00674   {"bbz.a",   OP_SI(0x49),  MASK_SI,      0,     {OFF_SS_PC, REG_22, BITNUM} },
00675   {"bbz.a",   OP_LI(0x393), MASK_LI,      0,     {OFF_SL_PC, REG_22, BITNUM} },
00676   {"bbz.a",   OP_REG(0x392),       MASK_REG,     0,     {REG_0, REG_22, BITNUM}            },
00677 
00678   /* Branch Conditional - nonannulled */
00679 
00680   {"bcnd",    OP_SI(0x4C),  MASK_SI,      0,     {OFF_SS_PC, REG_22, CC}     },
00681   {"bcnd",    OP_LI(0x399), MASK_LI,      0,     {OFF_SL_PC, REG_22, CC}     },
00682   {"bcnd",    OP_REG(0x398),       MASK_REG,     0,     {REG_0, REG_22, CC}  },
00683 
00684   /* Branch Conditional - annulled */
00685 
00686   {"bcnd.a",  OP_SI(0x4D),  MASK_SI,      0,     {OFF_SS_PC, REG_22, CC}     },
00687   {"bcnd.a",  OP_LI(0x39B), MASK_LI,      0,     {OFF_SL_PC, REG_22, CC}     },
00688   {"bcnd.a",  OP_REG(0x39A),       MASK_REG,     0,     {REG_0, REG_22, CC}  },
00689 
00690   /* Branch Control Register */
00691 
00692   {"brcr",    OP_SI(0x6),   MASK_SI,      0,     {CR_SI}       },
00693   {"brcr",    OP_LI(0x30D), MASK_LI,      0,     {CR_LI}       },
00694   {"brcr",    OP_REG(0x30C),       MASK_REG,     0,     {REG_0}       },
00695 
00696   /* Branch and save return - nonannulled */
00697 
00698   {"bsr",     OP_SI(0x40),  MASK_SI,      0,     {OFF_SS_PC, REG_DEST}       },
00699   {"bsr",     OP_LI(0x381), MASK_LI,      0,     {OFF_SL_PC, REG_DEST}       },
00700   {"bsr",     OP_REG(0x380),       MASK_REG,     0,     {REG_0, REG_DEST}    },
00701 
00702   /* Branch and save return - annulled */
00703 
00704   {"bsr.a",   OP_SI(0x41),  MASK_SI,      0,     {OFF_SS_PC, REG_DEST}       },
00705   {"bsr.a",   OP_LI(0x383), MASK_LI,      0,     {OFF_SL_PC, REG_DEST}       },
00706   {"bsr.a",   OP_REG(0x382),       MASK_REG,     0,     {REG_0, REG_DEST}    },
00707 
00708   /* Send command */
00709 
00710   {"cmnd",    OP_SI(0x2),   MASK_SI,      0,     {SUI}  },
00711   {"cmnd",    OP_LI(0x305), MASK_LI,      0,     {LUI}  },
00712   {"cmnd",    OP_REG(0x304),       MASK_REG,     0,     {REG_0}       },
00713 
00714   /* Integer compare */
00715 
00716   {"cmp",     OP_SI(0x50),  MASK_SI,      0,     {SSI, REG_22, REG_DEST}            },
00717   {"cmp",     OP_LI(0x3A1), MASK_LI,      0,     {LSI, REG_22, REG_DEST}            },
00718   {"cmp",     OP_REG(0x3A0),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00719 
00720   /* Flush data cache subblock - don't clear subblock preset flag */
00721 
00722   {"dcachec", OP_SI(0x38),  F(1) | (MASK_SI  & ~M_SI(1)),                    0, {SSI, REG_BASE_M_SI}            },
00723   {"dcachec", OP_LI(0x371), F(1) | (MASK_LI  & ~M_LI(1))  | S(1) | D(1),     0, {LSI, REG_BASE_M_LI}            },
00724   {"dcachec", OP_REG(0x370),       F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),     0, {REG_0, REG_BASE_M_LI}   },
00725 
00726   /* Flush data cache subblock - clear subblock preset flag */
00727 
00728   {"dcachef", OP_SI(0x38)   | F(1),       F(1) | (MASK_SI  & ~M_SI(1)),                    0, {SSI, REG_BASE_M_SI}            },
00729   {"dcachef", OP_LI(0x371)  | F(1),       F(1) | (MASK_LI  & ~M_LI(1))   | S(1) | D(1),    0, {LSI, REG_BASE_M_LI}            },
00730   {"dcachef", OP_REG(0x370) | F(1),       F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1),     0, {REG_0, REG_BASE_M_LI}   },
00731 
00732   /* Direct load signed data into register */
00733 
00734   {"dld",     OP_LI(0x345)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00735   {"dld",     OP_REG(0x344) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00736   {"dld.b",   OP_LI(0x341)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00737   {"dld.b",   OP_REG(0x340) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00738   {"dld.d",   OP_LI(0x347)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}    },
00739   {"dld.d",   OP_REG(0x346) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}          },
00740   {"dld.h",   OP_LI(0x343)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00741   {"dld.h",   OP_REG(0x342) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00742 
00743   /* Direct load unsigned data into register */
00744 
00745   {"dld.ub",  OP_LI(0x351)  | D(1),       (MASK_LI  &  ~M_REG(1)) | D(1),    0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00746   {"dld.ub",  OP_REG(0x350) | D(1),       (MASK_REG & ~M_REG(1))  | D(1),    0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00747   {"dld.uh",  OP_LI(0x353)  | D(1),       (MASK_LI  &  ~M_REG(1)) | D(1),    0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00748   {"dld.uh",  OP_REG(0x352) | D(1),       (MASK_REG & ~M_REG(1))  | D(1),    0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00749 
00750   /* Direct store data into memory */
00751 
00752   {"dst",     OP_LI(0x365)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00753   {"dst",     OP_REG(0x364) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00754   {"dst.b",   OP_LI(0x361)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00755   {"dst.b",   OP_REG(0x360) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00756   {"dst.d",   OP_LI(0x367)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}    },
00757   {"dst.d",   OP_REG(0x366) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}          },
00758   {"dst.h",   OP_LI(0x363)  | D(1),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00759   {"dst.h",   OP_REG(0x362) | D(1),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00760 
00761   /* Emulation stop */
00762 
00763   {"estop",   OP_LI(0x3FC), MASK_LI,      0,            {0}    },
00764 
00765   /* Emulation trap */
00766 
00767   {"etrap",   OP_SI(0x1)    | E(1),       MASK_SI  | E(1),     0,     {SUI}  },
00768   {"etrap",   OP_LI(0x303)  | E(1),       MASK_LI  | E(1),     0,     {LUI}  },
00769   {"etrap",   OP_REG(0x302) | E(1),       MASK_REG | E(1),     0,     {REG_0}       },
00770 
00771   /* Floating-point addition */
00772 
00773   {"fadd.ddd",       OP_REG(0x3E0) | PD(1) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22_E, REG_DEST_E}   },
00774   {"fadd.dsd",       OP_REG(0x3E0) | PD(1) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22, REG_DEST_E}     },
00775   {"fadd.sdd",       OP_LI(0x3E1)  | PD(1) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22_E, REG_DEST_E}      },
00776   {"fadd.sdd",       OP_REG(0x3E0) | PD(1) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22_E, REG_DEST_E}     },
00777   {"fadd.ssd",       OP_LI(0x3E1)  | PD(1) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST_E} },
00778   {"fadd.ssd",       OP_REG(0x3E0) | PD(1) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST_E}       },
00779   {"fadd.sss",       OP_LI(0x3E1)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST}   },
00780   {"fadd.sss",       OP_REG(0x3E0) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST}  },
00781 
00782   /* Floating point compare */
00783 
00784   {"fcmp.dd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3),  0,      {REG_0_E, REG_22_E, REG_DEST}     },
00785   {"fcmp.ds", OP_REG(0x3EA) | PD(0) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3),  0,      {REG_0_E, REG_22, REG_DEST}       },
00786   {"fcmp.sd", OP_LI(0x3EB)  | PD(0) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3),  0,      {SPFI, REG_22_E, REG_DEST} },
00787   {"fcmp.sd", OP_REG(0x3EA) | PD(0) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3),  0,      {REG_0, REG_22_E, REG_DEST}       },
00788   {"fcmp.ss", OP_LI(0x3EB)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3),  0,      {SPFI, REG_22, REG_DEST}   },
00789   {"fcmp.ss", OP_REG(0x3EA) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3),  0,      {REG_0, REG_22, REG_DEST}  },
00790 
00791   /* Floating point divide */
00792 
00793   {"fdiv.ddd",       OP_REG(0x3E6) | PD(1) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22_E, REG_DEST_E}   },
00794   {"fdiv.dsd",       OP_REG(0x3E6) | PD(1) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22, REG_DEST_E}     },
00795   {"fdiv.sdd",       OP_LI(0x3E7)  | PD(1) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22_E, REG_DEST_E}      },
00796   {"fdiv.sdd",       OP_REG(0x3E6) | PD(1) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22_E, REG_DEST_E}     },
00797   {"fdiv.ssd",       OP_LI(0x3E7)  | PD(1) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST_E} },
00798   {"fdiv.ssd",       OP_REG(0x3E6) | PD(1) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST_E}       },
00799   {"fdiv.sss",       OP_LI(0x3E7)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST}   },
00800   {"fdiv.sss",       OP_REG(0x3E6) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST}  },
00801 
00802   /* Floating point multiply */
00803 
00804   {"fmpy.ddd",       OP_REG(0x3E4) | PD(1) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22_E, REG_DEST_E}   },
00805   {"fmpy.dsd",       OP_REG(0x3E4) | PD(1) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22, REG_DEST_E}     },
00806   {"fmpy.iii",       OP_LI(0x3E5)  | PD(2) | P2(2) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_22, REG_DEST}    },
00807   {"fmpy.iii",       OP_REG(0x3E4) | PD(2) | P2(2) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST}  },
00808   {"fmpy.sdd",       OP_LI(0x3E5)  | PD(1) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22_E, REG_DEST_E}      },
00809   {"fmpy.sdd",       OP_REG(0x3E4) | PD(1) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22_E, REG_DEST_E}     },
00810   {"fmpy.ssd",       OP_LI(0x3E5)  | PD(1) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST_E} },
00811   {"fmpy.ssd",       OP_REG(0x3E4) | PD(1) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST_E}       },
00812   {"fmpy.sss",       OP_LI(0x3E5)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST}   },
00813   {"fmpy.sss",       OP_REG(0x3E4) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST}  },
00814   {"fmpy.uuu",       OP_LI(0x3E5)  | PD(3) | P2(3) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LUI, REG_22, REG_DEST}    },
00815   {"fmpy.uuu",       OP_REG(0x3E4) | PD(3) | P2(3) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST}  },
00816 
00817   /* Convert/Round to Minus Infinity */
00818 
00819   {"frndm.dd",       OP_REG(0x3E8) | PD(1) | P2(3) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST_E}      },
00820   {"frndm.di",       OP_REG(0x3E8) | PD(2) | P2(3) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00821   {"frndm.ds",       OP_REG(0x3E8) | PD(0) | P2(3) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00822   {"frndm.du",       OP_REG(0x3E8) | PD(3) | P2(3) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00823   {"frndm.id",       OP_LI(0x3E9)  | PD(1) | P2(3) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00824   {"frndm.id",       OP_REG(0x3E8) | PD(1) | P2(3) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00825   {"frndm.is",       OP_LI(0x3E9)  | PD(0) | P2(3) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00826   {"frndm.is",       OP_REG(0x3E8) | PD(0) | P2(3) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00827   {"frndm.sd",       OP_LI(0x3E9)  | PD(1) | P2(3) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST_E}  },
00828   {"frndm.sd",       OP_REG(0x3E8) | PD(1) | P2(3) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00829   {"frndm.si",       OP_LI(0x3E9)  | PD(2) | P2(3) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00830   {"frndm.si",       OP_REG(0x3E8) | PD(2) | P2(3) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00831   {"frndm.ss",       OP_LI(0x3E9)  | PD(0) | P2(3) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00832   {"frndm.ss",       OP_REG(0x3E8) | PD(0) | P2(3) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00833   {"frndm.su",       OP_LI(0x3E9)  | PD(3) | P2(3) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00834   {"frndm.su",       OP_REG(0x3E8) | PD(3) | P2(3) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00835   {"frndm.ud",       OP_LI(0x3E9)  | PD(1) | P2(3) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00836   {"frndm.ud",       OP_REG(0x3E8) | PD(1) | P2(3) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00837   {"frndm.us",       OP_LI(0x3E9)  | PD(0) | P2(3) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00838   {"frndm.us",       OP_REG(0x3E8) | PD(0) | P2(3) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00839 
00840   /* Convert/Round to Nearest */
00841 
00842   {"frndn.dd",       OP_REG(0x3E8) | PD(1) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST_E}      },
00843   {"frndn.di",       OP_REG(0x3E8) | PD(2) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00844   {"frndn.ds",       OP_REG(0x3E8) | PD(0) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00845   {"frndn.du",       OP_REG(0x3E8) | PD(3) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00846   {"frndn.id",       OP_LI(0x3E9)  | PD(1) | P2(0) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00847   {"frndn.id",       OP_REG(0x3E8) | PD(1) | P2(0) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00848   {"frndn.is",       OP_LI(0x3E9)  | PD(0) | P2(0) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00849   {"frndn.is",       OP_REG(0x3E8) | PD(0) | P2(0) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00850   {"frndn.sd",       OP_LI(0x3E9)  | PD(1) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST_E}  },
00851   {"frndn.sd",       OP_REG(0x3E8) | PD(1) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00852   {"frndn.si",       OP_LI(0x3E9)  | PD(2) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00853   {"frndn.si",       OP_REG(0x3E8) | PD(2) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00854   {"frndn.ss",       OP_LI(0x3E9)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00855   {"frndn.ss",       OP_REG(0x3E8) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00856   {"frndn.su",       OP_LI(0x3E9)  | PD(3) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00857   {"frndn.su",       OP_REG(0x3E8) | PD(3) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00858   {"frndn.ud",       OP_LI(0x3E9)  | PD(1) | P2(0) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00859   {"frndn.ud",       OP_REG(0x3E8) | PD(1) | P2(0) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00860   {"frndn.us",       OP_LI(0x3E9)  | PD(0) | P2(0) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00861   {"frndn.us",       OP_REG(0x3E8) | PD(0) | P2(0) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00862 
00863   /* Convert/Round to Positive Infinity */
00864 
00865   {"frndp.dd",       OP_REG(0x3E8) | PD(1) | P2(2) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST_E}      },
00866   {"frndp.di",       OP_REG(0x3E8) | PD(2) | P2(2) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00867   {"frndp.ds",       OP_REG(0x3E8) | PD(0) | P2(2) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00868   {"frndp.du",       OP_REG(0x3E8) | PD(3) | P2(2) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00869   {"frndp.id",       OP_LI(0x3E9)  | PD(1) | P2(2) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00870   {"frndp.id",       OP_REG(0x3E8) | PD(1) | P2(2) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00871   {"frndp.is",       OP_LI(0x3E9)  | PD(0) | P2(2) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00872   {"frndp.is",       OP_REG(0x3E8) | PD(0) | P2(2) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00873   {"frndp.sd",       OP_LI(0x3E9)  | PD(1) | P2(2) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST_E}  },
00874   {"frndp.sd",       OP_REG(0x3E8) | PD(1) | P2(2) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00875   {"frndp.si",       OP_LI(0x3E9)  | PD(2) | P2(2) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00876   {"frndp.si",       OP_REG(0x3E8) | PD(2) | P2(2) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00877   {"frndp.ss",       OP_LI(0x3E9)  | PD(0) | P2(2) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00878   {"frndp.ss",       OP_REG(0x3E8) | PD(0) | P2(2) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00879   {"frndp.su",       OP_LI(0x3E9)  | PD(3) | P2(2) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00880   {"frndp.su",       OP_REG(0x3E8) | PD(3) | P2(2) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00881   {"frndp.ud",       OP_LI(0x3E9)  | PD(1) | P2(2) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00882   {"frndp.ud",       OP_REG(0x3E8) | PD(1) | P2(2) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00883   {"frndp.us",       OP_LI(0x3E9)  | PD(0) | P2(2) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00884   {"frndp.us",       OP_REG(0x3E8) | PD(0) | P2(2) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00885 
00886   /* Convert/Round to Zero */
00887 
00888   {"frndz.dd",       OP_REG(0x3E8) | PD(1) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST_E}      },
00889   {"frndz.di",       OP_REG(0x3E8) | PD(2) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00890   {"frndz.ds",       OP_REG(0x3E8) | PD(0) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00891   {"frndz.du",       OP_REG(0x3E8) | PD(3) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST} },
00892   {"frndz.id",       OP_LI(0x3E9)  | PD(1) | P2(1) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00893   {"frndz.id",       OP_REG(0x3E8) | PD(1) | P2(1) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00894   {"frndz.is",       OP_LI(0x3E9)  | PD(0) | P2(1) | P1(2),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00895   {"frndz.is",       OP_REG(0x3E8) | PD(0) | P2(1) | P1(2),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00896   {"frndz.sd",       OP_LI(0x3E9)  | PD(1) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST_E}  },
00897   {"frndz.sd",       OP_REG(0x3E8) | PD(1) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00898   {"frndz.si",       OP_LI(0x3E9)  | PD(2) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00899   {"frndz.si",       OP_REG(0x3E8) | PD(2) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00900   {"frndz.ss",       OP_LI(0x3E9)  | PD(0) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00901   {"frndz.ss",       OP_REG(0x3E8) | PD(0) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00902   {"frndz.su",       OP_LI(0x3E9)  | PD(3) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00903   {"frndz.su",       OP_REG(0x3E8) | PD(3) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00904   {"frndz.ud",       OP_LI(0x3E9)  | PD(1) | P2(1) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST_E}   },
00905   {"frndz.ud",       OP_REG(0x3E8) | PD(1) | P2(1) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00906   {"frndz.us",       OP_LI(0x3E9)  | PD(0) | P2(1) | P1(3),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {LSI, REG_DEST}     },
00907   {"frndz.us",       OP_REG(0x3E8) | PD(0) | P2(1) | P1(3),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00908 
00909   /* Floating point square root */
00910 
00911   {"fsqrt.dd",       OP_REG(0x3EE) | PD(1) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_DEST_E}      },
00912   {"fsqrt.sd",       OP_LI(0x3EF)  | PD(1) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST_E}  },
00913   {"fsqrt.sd",       OP_REG(0x3EE) | PD(1) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST_E} },
00914   {"fsqrt.ss",       OP_LI(0x3EF)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_DEST}    },
00915   {"fsqrt.ss",       OP_REG(0x3EE) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_DEST}   },
00916 
00917   /* Floating point subtraction */
00918 
00919   { "fsub.ddd",      OP_REG(0x3E2) | PD(1) | P2(1) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22_E, REG_DEST_E}   },
00920   { "fsub.dsd",      OP_REG(0x3E2) | PD(1) | P2(0) | P1(1),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0_E, REG_22, REG_DEST_E}     },
00921   { "fsub.sdd",      OP_LI(0x3E3)  | PD(1) | P2(1) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22_E, REG_DEST_E}      },
00922   { "fsub.sdd",      OP_REG(0x3E2) | PD(1) | P2(1) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22_E, REG_DEST_E}     },
00923   { "fsub.ssd",      OP_LI(0x3E3)  | PD(1) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST_E} },
00924   { "fsub.ssd",      OP_REG(0x3E2) | PD(1) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST_E}       },
00925   { "fsub.sss",      OP_LI(0x3E3)  | PD(0) | P2(0) | P1(0),    MASK_LI  | PD(3) | P2(3) | P1(3), 0,       {SPFI, REG_22, REG_DEST}   },
00926   { "fsub.sss",      OP_REG(0x3E2) | PD(0) | P2(0) | P1(0),    MASK_REG | PD(3) | P2(3) | P1(3), 0,       {REG_0, REG_22, REG_DEST}  },
00927 
00928   /* Illegal instructions */
00929 
00930   {"illop0",  OP_SI(0x0),   MASK_SI,      0,     {0}    },
00931   {"illopF",  0x1FF << 13,  0x1FF << 13,  0,     {0}    },
00932 
00933   /* Jump and save return */
00934 
00935   {"jsr",     OP_SI(0x44),  MASK_SI,      0,     {OFF_SS_BR, REG_BASE, REG_DEST}    },
00936   {"jsr",     OP_LI(0x389), MASK_LI,      0,     {OFF_SL_BR, REG_BASE, REG_DEST}    },
00937   {"jsr",     OP_REG(0x388),       MASK_REG,     0,     {REG_0, REG_BASE, REG_DEST} },
00938   {"jsr.a",   OP_SI(0x45),  MASK_SI,      0,     {OFF_SS_BR, REG_BASE, REG_DEST}    },
00939   {"jsr.a",   OP_LI(0x38B), MASK_LI,      0,     {OFF_SL_BR, REG_BASE, REG_DEST}    },
00940   {"jsr.a",   OP_REG(0x38A),       MASK_REG,     0,     {REG_0, REG_BASE, REG_DEST} },
00941 
00942   /* Load Signed Data Into Register */
00943 
00944   {"ld",      OP_SI(0x22),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
00945   {"ld",      OP_LI(0x345)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00946   {"ld",      OP_REG(0x344) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00947   {"ld.b",    OP_SI(0x20),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
00948   {"ld.b",    OP_LI(0x341)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00949   {"ld.b",    OP_REG(0x340) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00950   {"ld.d",    OP_SI(0x23),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E}           },
00951   {"ld.d",    OP_LI(0x347)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}    },
00952   {"ld.d",    OP_REG(0x346) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}          },
00953   {"ld.h",    OP_SI(0x21),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
00954   {"ld.h",    OP_LI(0x343)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00955   {"ld.h",    OP_REG(0x342) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00956 
00957   /* Load Unsigned Data Into Register */
00958 
00959   {"ld.ub",   OP_SI(0x28),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
00960   {"ld.ub",   OP_LI(0x351)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00961   {"ld.ub",   OP_REG(0x350) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00962   {"ld.uh",   OP_SI(0x29),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
00963   {"ld.uh",   OP_LI(0x353)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
00964   {"ld.uh",   OP_REG(0x352) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
00965 
00966   /* Leftmost one */
00967 
00968   {"lmo",     OP_LI(0x3F0), MASK_LI,      0,     {REG_22, REG_DEST}   },
00969 
00970   /* Bitwise logical OR.  Note that "or.tt" and "or" are the same instructions. */
00971 
00972   {"or.ff",   OP_SI(0x1E),  MASK_SI,      0,     {SUI, REG_22, REG_DEST}            },
00973   {"or.ff",   OP_LI(0x33D), MASK_LI,      0,     {LUI, REG_22, REG_DEST}            },
00974   {"or.ff",   OP_REG(0x33C),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00975   {"or.ft",   OP_SI(0x1D),  MASK_SI,      0,     {SUI, REG_22, REG_DEST}            },
00976   {"or.ft",   OP_LI(0x33B), MASK_LI,      0,     {LUI, REG_22, REG_DEST}            },
00977   {"or.ft",   OP_REG(0x33A),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00978   {"or.tf",   OP_SI(0x1B),  MASK_SI,      0,     {SUI, REG_22, REG_DEST}            },
00979   {"or.tf",   OP_LI(0x337), MASK_LI,      0,     {LUI, REG_22, REG_DEST}            },
00980   {"or.tf",   OP_REG(0x336),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00981   {"or.tt",   OP_SI(0x17),  MASK_SI,      0,     {SUI, REG_22, REG_DEST}            },
00982   {"or.tt",   OP_LI(0x32F), MASK_LI,      0,     {LUI, REG_22, REG_DEST}            },
00983   {"or.tt",   OP_REG(0x32E),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00984   {"or",      OP_SI(0x17),  MASK_SI,      0,     {SUI, REG_22, REG_DEST}            },
00985   {"or",      OP_LI(0x32F), MASK_LI,      0,     {LUI, REG_22, REG_DEST}            },
00986   {"or",      OP_REG(0x32E),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
00987 
00988   /* Read Control Register */
00989 
00990   {"rdcr",    OP_SI(0x4),   MASK_SI  | (0x1F << 22),    0,     {CR_SI, REG_DEST}    },
00991   {"rdcr",    OP_LI(0x309), MASK_LI  | (0x1F << 22),    0,     {CR_LI, REG_DEST}    },
00992   {"rdcr",    OP_REG(0x308),       MASK_REG | (0x1F << 22),    0,     {REG_0, REG_DEST}    },
00993 
00994   /* Rightmost one */
00995 
00996   {"rmo",     OP_LI(0x3F2), MASK_LI,      0,            {REG_22, REG_DEST}   },
00997 
00998   /* Shift Register Left - note that rotl, shl, and ins are all alternate names for one of the shift instructions.
00999      They appear prior to their sl equivalent so that they will be diassembled as the alternate name. */
01000 
01001 
01002   {"ins",     OP_REG(0x31E) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01003   {"ins",     OP_SI(0xF)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01004   {"rotl",    OP_REG(0x310) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01005   {"rotl",    OP_SI(0x8)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01006   {"shl",     OP_REG(0x31C) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01007   {"shl",     OP_SI(0xE)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01008   {"sl.dm",   OP_REG(0x312) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01009   {"sl.dm",   OP_SI(0x9)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01010   {"sl.ds",   OP_REG(0x314) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01011   {"sl.ds",   OP_SI(0xA)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01012   {"sl.dz",   OP_REG(0x310) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01013   {"sl.dz",   OP_SI(0x8)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01014   {"sl.em",   OP_REG(0x318) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01015   {"sl.em",   OP_SI(0xC)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01016   {"sl.es",   OP_REG(0x31A) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01017   {"sl.es",   OP_SI(0xD)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01018   {"sl.ez",   OP_REG(0x316) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01019   {"sl.ez",   OP_SI(0xB)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01020   {"sl.im",   OP_REG(0x31E) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01021   {"sl.im",   OP_SI(0xF)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01022   {"sl.iz",   OP_REG(0x31C) | i(0) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01023   {"sl.iz",   OP_SI(0xE)    | i(0) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01024 
01025   /* Shift Register Left With Inverted Endmask */
01026 
01027   {"sli.dm",  OP_REG(0x312) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01028   {"sli.dm",  OP_SI(0x9)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01029   {"sli.ds",  OP_REG(0x314) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01030   {"sli.ds",  OP_SI(0xA)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01031   {"sli.dz",  OP_REG(0x310) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01032   {"sli.dz",  OP_SI(0x8)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01033   {"sli.em",  OP_REG(0x318) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01034   {"sli.em",  OP_SI(0xC)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01035   {"sli.es",  OP_REG(0x31A) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01036   {"sli.es",  OP_SI(0xD)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01037   {"sli.ez",  OP_REG(0x316) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01038   {"sli.ez",  OP_SI(0xB)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01039   {"sli.im",  OP_REG(0x31E) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01040   {"sli.im",  OP_SI(0xF)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01041   {"sli.iz",  OP_REG(0x31C) | i(1) | n(0),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01042   {"sli.iz",  OP_SI(0xE)    | i(1) | n(0),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01043 
01044   /* Shift Register Right - note that exts, extu, rotr, sra, and srl are all alternate names for one of the shift instructions.
01045      They appear prior to their sr equivalent so that they will be diassembled as the alternate name. */
01046 
01047   {"exts",    OP_REG(0x314) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01048   {"exts",    OP_SI(0xA)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01049   {"extu",    OP_REG(0x310) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01050   {"extu",    OP_SI(0x8)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01051   {"rotr",    OP_REG(0x310) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01052   {"rotr",    OP_SI(0x8)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01053   {"sra",     OP_REG(0x31A) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01054   {"sra",     OP_SI(0xD)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01055   {"srl",     OP_REG(0x316) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01056   {"srl",     OP_SI(0xB)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01057   {"sr.dm",   OP_REG(0x312) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01058   {"sr.dm",   OP_SI(0x9)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01059   {"sr.ds",   OP_REG(0x314) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01060   {"sr.ds",   OP_SI(0xA)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01061   {"sr.dz",   OP_REG(0x310) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01062   {"sr.dz",   OP_SI(0x8)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01063   {"sr.em",   OP_REG(0x318) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01064   {"sr.em",   OP_SI(0xC)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01065   {"sr.es",   OP_REG(0x31A) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01066   {"sr.es",   OP_SI(0xD)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01067   {"sr.ez",   OP_REG(0x316) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01068   {"sr.ez",   OP_SI(0xB)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01069   {"sr.im",   OP_REG(0x31E) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01070   {"sr.im",   OP_SI(0xF)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01071   {"sr.iz",   OP_REG(0x31C) | i(0) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01072   {"sr.iz",   OP_SI(0xE)    | i(0) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01073 
01074   /* Shift Register Right With Inverted Endmask */
01075 
01076   {"sri.dm",  OP_REG(0x312) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01077   {"sri.dm",  OP_SI(0x9)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01078   {"sri.ds",  OP_REG(0x314) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01079   {"sri.ds",  OP_SI(0xA)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01080   {"sri.dz",  OP_REG(0x310) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01081   {"sri.dz",  OP_SI(0x8)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01082   {"sri.em",  OP_REG(0x318) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01083   {"sri.em",  OP_SI(0xC)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01084   {"sri.es",  OP_REG(0x31A) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01085   {"sri.es",  OP_SI(0xD)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01086   {"sri.ez",  OP_REG(0x316) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01087   {"sri.ez",  OP_SI(0xB)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01088   {"sri.im",  OP_REG(0x31E) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01089   {"sri.im",  OP_SI(0xF)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01090   {"sri.iz",  OP_REG(0x31C) | i(1) | n(1),       MASK_REG | i(1) | n(1),     0,     {REG_0, ENDMASK, REG_22, REG_DEST} },
01091   {"sri.iz",  OP_SI(0xE)    | i(1) | n(1),       MASK_SI  | i(1) | n(1),     0,     {ROTATE, ENDMASK, REG_22, REG_DEST}       },
01092 
01093   /* Store Data into Memory */
01094 
01095   {"st",      OP_SI(0x32),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
01096   {"st",      OP_LI(0x365)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
01097   {"st",      OP_REG(0x364) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
01098   {"st.b",    OP_SI(0x30),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
01099   {"st.b",    OP_LI(0x361)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
01100   {"st.b",    OP_REG(0x360) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
01101   {"st.d",    OP_SI(0x33),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E}           },
01102   {"st.d",    OP_LI(0x367)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E}    },
01103   {"st.d",    OP_REG(0x366) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST_E}          },
01104   {"st.h",    OP_SI(0x31),         (MASK_SI  & ~M_SI(1)),             0,     {OFF_SS_BR, REG_BASE_M_SI, REG_DEST}             },
01105   {"st.h",    OP_LI(0x363)  | D(0),       (MASK_LI  & ~M_REG(1)) | D(1),     0,     {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST}      },
01106   {"st.h",    OP_REG(0x362) | D(0),       (MASK_REG & ~M_REG(1)) | D(1),     0,     {REG_SCALED, REG_BASE_M_LI, REG_DEST}            },
01107 
01108   /* Signed Integer Subtract */
01109 
01110   {"sub",     OP_SI(0x5A),  MASK_SI,      0,     {SSI, REG_22, REG_DEST}            },
01111   {"sub",     OP_LI(0x3B5), MASK_LI,      0,     {LSI, REG_22, REG_DEST}            },
01112   {"sub",     OP_REG(0x3B4),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
01113 
01114   /* Unsigned Integer Subtract */
01115 
01116   {"subu",    OP_SI(0x5B),  MASK_SI,      0,     {SSI, REG_22, REG_DEST}            },
01117   {"subu",    OP_LI(0x3B7), MASK_LI,      0,     {LSI, REG_22, REG_DEST}            },
01118   {"subu",    OP_REG(0x3B6),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
01119 
01120   /* Write Control Register
01121      Is a special form of the "swcr" instruction so comes before it in the table. */
01122 
01123   {"wrcr",    OP_SI(0x5),   MASK_SI | (0x1F << 27),            0,     {CR_SI, REG_22}      },
01124   {"wrcr",    OP_LI(0x30B), MASK_LI | (0x1F << 27),            0,     {CR_LI, REG_22}      },
01125   {"wrcr",    OP_REG(0x30A),       MASK_REG | (0x1F << 27),    0,     {REG_0, REG_22}      },
01126 
01127   /* Swap Control Register */
01128 
01129   {"swcr",    OP_SI(0x5),   MASK_SI,      0,     {CR_SI, REG_22, REG_DEST}   },
01130   {"swcr",    OP_LI(0x30B), MASK_LI,      0,     {CR_LI, REG_22, REG_DEST}   },
01131   {"swcr",    OP_REG(0x30A),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST}   },
01132 
01133   /* Trap */
01134 
01135   {"trap",    OP_SI(0x1)    | E(0),       MASK_SI  | E(1),     0,     {SUI}  },
01136   {"trap",    OP_LI(0x303)  | E(0),       MASK_LI  | E(1),     0,     {LUI}  },
01137   {"trap",    OP_REG(0x302) | E(0),       MASK_REG | E(1),     0,     {REG_0}       },
01138 
01139   /* Vector Floating-Point Add */
01140 
01141   {"vadd.dd", OP_REG(0x3C0) | P2(1) | P1(1),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E}      },
01142   {"vadd.sd", OP_LI(0x3C1)  | P2(1) | P1(0),     MASK_LI  | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E}  },
01143   {"vadd.sd", OP_REG(0x3C0) | P2(1) | P1(0),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
01144   {"vadd.ss", OP_LI(0x3C1)  | P2(0) | P1(0),     MASK_LI  | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {SPFI, REG_22, REG_22}      },
01145   {"vadd.ss", OP_REG(0x3C0) | P2(0) | P1(0),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {REG_0, REG_22, REG_22}     },
01146 
01147   /* Vector Floating-Point Multiply and Add to Accumulator FIXME! This is not yet fully implemented.
01148    From the documentation there appears to be no way to tell the difference between the opcodes for
01149    instructions that have register destinations and instructions that have accumulator destinations.
01150    Further investigation is necessary.  Since this isn't critical to getting a TIC80 toolchain up
01151    and running, it is defered until later. */
01152 
01153   /* Vector Floating-Point Multiply
01154    Note: If r0 is in the destination reg, then this is a "vector nop" instruction. */
01155 
01156   {"vmpy.dd", OP_REG(0x3C4) | P2(1) | P1(1),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0_E, REG_22_E, REG_22_E} },
01157   {"vmpy.sd", OP_LI(0x3C5)  | P2(1) | P1(0),     MASK_LI  | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22_E, REG_22_E}    },
01158   {"vmpy.sd", OP_REG(0x3C4) | P2(1) | P1(0),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22_E, REG_22_E} },
01159   {"vmpy.ss", OP_LI(0x3C5)  | P2(0) | P1(0),     MASK_LI  | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR | TIC80_NO_R0_DEST, {SPFI, REG_22, REG_22} },
01160   {"vmpy.ss", OP_REG(0x3C4) | P2(0) | P1(0),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR | TIC80_NO_R0_DEST, {REG_0, REG_22, REG_22} },
01161 
01162   /* Vector Floating-Point Multiply and Subtract from Accumulator
01163      FIXME: See note above for vmac instruction */
01164 
01165   /* Vector Floating-Point Subtract Accumulator From Source
01166      FIXME: See note above for vmac instruction */
01167 
01168   /* Vector Round With Floating-Point Input
01169      FIXME: See note above for vmac instruction */
01170 
01171   /* Vector Round with Integer Input */
01172 
01173   {"vrnd.id", OP_LI (0x3CB)  | P2(1) | P1(0),    MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LSI, REG_22_E}},
01174   {"vrnd.id", OP_REG (0x3CA) | P2(1) | P1(0),    MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {REG_0, REG_22_E}},
01175   {"vrnd.is", OP_LI (0x3CB)  | P2(0) | P1(0),    MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LSI, REG_22}},
01176   {"vrnd.is", OP_REG (0x3CA) | P2(0) | P1(0),    MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {REG_0, REG_22}},
01177   {"vrnd.ud", OP_LI (0x3CB)  | P2(1) | P1(1),    MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LUI, REG_22_E}},
01178   {"vrnd.ud", OP_REG (0x3CA) | P2(1) | P1(1),    MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {REG_0, REG_22_E}},
01179   {"vrnd.us", OP_LI (0x3CB)  | P2(0) | P1(1),    MASK_LI  | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {LUI, REG_22}},
01180   {"vrnd.us", OP_REG (0x3CA) | P2(0) | P1(1),    MASK_REG | V_a0(1) | V_Z(1) | P2(1) | P1(1),     TIC80_VECTOR, {REG_0, REG_22}},
01181 
01182   /* Vector Floating-Point Subtract */
01183 
01184   {"vsub.dd", OP_REG(0x3C2) | P2(1) | P1(1),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {REG_0_E, REG_22_E, REG_22_E}      },
01185   {"vsub.sd", OP_LI(0x3C3)  | P2(1) | P1(0),     MASK_LI  | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {SPFI, REG_22_E, REG_22_E}  },
01186   {"vsub.sd", OP_REG(0x3C2) | P2(1) | P1(0),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {REG_0, REG_22_E, REG_22_E} },
01187   {"vsub.ss", OP_LI(0x3C3)  | P2(0) | P1(0),     MASK_LI  | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {SPFI, REG_22, REG_22}      },
01188   {"vsub.ss", OP_REG(0x3C2) | P2(0) | P1(0),     MASK_REG | V_a1(1) | P2(1) | P1(1),       TIC80_VECTOR, {REG_0, REG_22, REG_22}     },
01189 
01190   /* Vector Load Data Into Register - Note that the vector load/store instructions come after the other
01191    vector instructions so that the disassembler will always print the load/store instruction second for
01192    vector instructions that have two instructions in the same opcode. */
01193 
01194   {"vld0.d",  OP_V(0x1E) | V_m(1) | V_S(1) | V_p(0),    MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
01195   {"vld0.s",  OP_V(0x1E) | V_m(1) | V_S(0) | V_p(0),    MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
01196   {"vld1.d",  OP_V(0x1E) | V_m(1) | V_S(1) | V_p(1),    MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
01197   {"vld1.s",  OP_V(0x1E) | V_m(1) | V_S(0) | V_p(1),    MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
01198 
01199   /* Vector Store Data Into Memory - Note that the vector load/store instructions come after the other
01200    vector instructions so that the disassembler will always print the load/store instruction second for
01201    vector instructions that have two instructions in the same opcode. */
01202 
01203   {"vst.d",   OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1),    MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} },
01204   {"vst.s",   OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1),    MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} },
01205 
01206   {"xnor",    OP_SI(0x19),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST} },
01207   {"xnor",    OP_LI(0x333), MASK_LI,      0,     {LUBF, REG_22, REG_DEST} },
01208   {"xnor",    OP_REG(0x332),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST} },
01209 
01210   {"xor",     OP_SI(0x16),  MASK_SI,      0,     {SUBF, REG_22, REG_DEST} },
01211   {"xor",     OP_LI(0x32D), MASK_LI,      0,     {LUBF, REG_22, REG_DEST} },
01212   {"xor",     OP_REG(0x32C),       MASK_REG,     0,     {REG_0, REG_22, REG_DEST} },
01213 
01214 };
01215 
01216 const int tic80_num_opcodes = sizeof (tic80_opcodes) / sizeof (tic80_opcodes[0]);