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cell-binutils  2.17cvs20070401
tic54x-opc.c
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00001 /* Table of opcodes for the Texas Instruments TMS320C54X
00002    Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
00003    Contributed by Timothy Wall (twall@cygnus.com)
00004 
00005    This program is free software; you can redistribute it and/or modify
00006    it under the terms of the GNU General Public License as published by
00007    the Free Software Foundation; either version 2 of the License, or
00008    (at your option) any later version.
00009 
00010    This program is distributed in the hope that it will be useful,
00011    but WITHOUT ANY WARRANTY; without even the implied warranty of
00012    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013    GNU General Public License for more details.
00014 
00015    You should have received a copy of the GNU General Public License
00016    along with this program; if not, write to the Free Software
00017    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
00018    02110-1301, USA.  */
00019 
00020 #include "sysdep.h"
00021 #include "dis-asm.h"
00022 #include "opcode/tic54x.h"
00023 
00024 /* these are the only register names not found in mmregs */
00025 const symbol regs[] = {
00026   { "AR0", 16 },                  { "ar0", 16 },
00027   { "AR1", 17 },                  { "ar1", 17 },
00028   { "AR2", 18 },                  { "ar2", 18 },
00029   { "AR3", 19 },                  { "ar3", 19 },
00030   { "AR4", 20 },                  { "ar4", 20 },
00031   { "AR5", 21 },                  { "ar5", 21 },
00032   { "AR6", 22 },                  { "ar6", 22 },
00033   { "AR7", 23 },                  { "ar7", 23 },
00034   { NULL, 0}
00035 };
00036 
00037 /* status bits, MM registers, condition codes, etc */
00038 /* some symbols are only valid for certain chips... */
00039 const symbol mmregs[] = {
00040   { "IMR", 0 },                   { "imr", 0 },
00041   { "IFR", 1 },                   { "ifr", 1 },
00042   { "ST0", 6 },                   { "st0", 6 },
00043   { "ST1", 7 },                   { "st1", 7 },
00044   { "AL",  8 },                   { "al",  8 },
00045   { "AH",  9 },                   { "ah",  9 },
00046   { "AG",  10 },                  { "ag",  10 },
00047   { "BL",  11 },                  { "bl",  11 },
00048   { "BH",  12 },                  { "bh",  12 },
00049   { "BG",  13 },                  { "bg",  13 },
00050   { "T",   14 },                  { "t",   14 },
00051   { "TRN", 15 },                  { "trn", 15 },
00052   { "AR0", 16 },                  { "ar0", 16 },
00053   { "AR1", 17 },                  { "ar1", 17 },
00054   { "AR2", 18 },                  { "ar2", 18 },
00055   { "AR3", 19 },                  { "ar3", 19 },
00056   { "AR4", 20 },                  { "ar4", 20 },
00057   { "AR5", 21 },                  { "ar5", 21 },
00058   { "AR6", 22 },                  { "ar6", 22 },
00059   { "AR7", 23 },                  { "ar7", 23 },
00060   { "SP",  24 },                  { "sp",  24 },
00061   { "BK",  25 },                  { "bk",  25 },
00062   { "BRC", 26 },                  { "brc", 26 },
00063   { "RSA", 27 },                  { "rsa", 27 },
00064   { "REA", 28 },                  { "rea", 28 },
00065   { "PMST",29 },                  { "pmst",29 },
00066   { "XPC", 30 },                  { "xpc", 30 }, /* 'c548 only */
00067   /* optional peripherals */      /* optional peripherals */
00068   { "M1F", 31 },                  { "m1f", 31 },
00069   { "DRR0",0x20 },                { "drr0",0x20 },
00070   { "BDRR0",0x20 },               { "bdrr0",0x20 }, /* 'c543, 545 */
00071   { "DXR0",0x21 },                { "dxr0",0x21 },
00072   { "BDXR0",0x21 },               { "bdxr0",0x21 }, /* 'c543, 545 */
00073   { "SPC0",0x22 },                { "spc0",0x22 },
00074   { "BSPC0",0x22 },               { "bspc0",0x22 }, /* 'c543, 545 */
00075   { "SPCE0",0x23 },               { "spce0",0x23 },
00076   { "BSPCE0",0x23 },              { "bspce0",0x23 }, /* 'c543, 545 */
00077   { "TIM", 0x24 },                { "tim", 0x24 },
00078   { "PRD", 0x25 },                { "prd", 0x25 },
00079   { "TCR", 0x26 },                { "tcr", 0x26 },
00080   { "SWWSR",0x28 },               { "swwsr",0x28 },
00081   { "BSCR",0x29 },                { "bscr",0x29 },
00082   { "HPIC",0x2C },                { "hpic",0x2c },
00083   /* 'c541, 'c545 */              /* 'c541, 'c545 */
00084   { "DRR1",0x30 },                { "drr1",0x30 },
00085   { "DXR1",0x31 },                { "dxr1",0x31 },
00086   { "SPC1",0x32 },                { "spc1",0x32 },
00087   /* 'c542, 'c543 */              /* 'c542, 'c543 */
00088   { "TRCV",0x30 },                { "trcv",0x30 },
00089   { "TDXR",0x31 },                { "tdxr",0x31 },
00090   { "TSPC",0x32 },                { "tspc",0x32 },
00091   { "TCSR",0x33 },                { "tcsr",0x33 },
00092   { "TRTA",0x34 },                { "trta",0x34 },
00093   { "TRAD",0x35 },                { "trad",0x35 },
00094   { "AXR0",0x38 },                { "axr0",0x38 },
00095   { "BKX0",0x39 },                { "bkx0",0x39 },
00096   { "ARR0",0x3A },                { "arr0",0x3a },
00097   { "BKR0",0x3B },                { "bkr0",0x3b },
00098   /* 'c545, 'c546, 'c548 */       /* 'c545, 'c546, 'c548 */
00099   { "CLKMD",0x58 },               { "clkmd",0x58 },
00100   /* 'c548 */                     /* 'c548 */
00101   { "AXR1",0x3C },                { "axr1",0x3c },
00102   { "BKX1",0x3D },                { "bkx1",0x3d },
00103   { "ARR1",0x3E },                { "arr1",0x3e },
00104   { "BKR1",0x3F },                { "bkr1",0x3f },
00105   { "BDRR1",0x40 },               { "bdrr1",0x40 },
00106   { "BDXR1",0x41 },               { "bdxr1",0x41 },
00107   { "BSPC1",0x42 },               { "bspc1",0x42 },
00108   { "BSPCE1",0x43 },              { "bspce1",0x43 },
00109   { NULL, 0},
00110 };
00111 
00112 const symbol condition_codes[] = {
00113   /* condition codes */
00114   { "UNC",  0 },                { "unc",  0 },
00115 #define CC1   0x40
00116 #define CCB   0x08
00117 #define CCEQ  0x05
00118 #define CCNEQ 0x04
00119 #define CCLT  0x03
00120 #define CCLEQ 0x07
00121 #define CCGT  0x06
00122 #define CCGEQ 0x02
00123 #define CCOV  0x70
00124 #define CCNOV 0x60
00125 #define CCBIO 0x03
00126 #define CCNBIO 0x02
00127 #define CCTC  0x30
00128 #define CCNTC 0x20
00129 #define CCC   0x0C
00130 #define CCNC  0x08
00131   { "aeq",  CC1|CCEQ },         { "AEQ",  CC1|CCEQ },
00132   { "aneq", CC1|CCNEQ },        { "ANEQ", CC1|CCNEQ },
00133   { "alt",  CC1|CCLT },         { "ALT",  CC1|CCLT },
00134   { "aleq", CC1|CCLEQ },        { "ALEQ", CC1|CCLEQ },
00135   { "agt",  CC1|CCGT },         { "AGT",  CC1|CCGT },
00136   { "ageq", CC1|CCGEQ },        { "AGEQ", CC1|CCGEQ },
00137   { "aov",  CC1|CCOV },         { "AOV",  CC1|CCOV },
00138   { "anov", CC1|CCNOV },        { "ANOV", CC1|CCNOV },
00139   { "beq",  CC1|CCB|CCEQ },     { "BEQ",  CC1|CCB|CCEQ },
00140   { "bneq", CC1|CCB|CCNEQ },    { "BNEQ", CC1|CCB|CCNEQ },
00141   { "blt",  CC1|CCB|CCLT },     { "BLT",  CC1|CCB|CCLT },
00142   { "bleq", CC1|CCB|CCLEQ },    { "BLEQ", CC1|CCB|CCLEQ },
00143   { "bgt",  CC1|CCB|CCGT },     { "BGT",  CC1|CCB|CCGT },
00144   { "bgeq", CC1|CCB|CCGEQ },    { "BGEQ", CC1|CCB|CCGEQ },
00145   { "bov",  CC1|CCB|CCOV },     { "BOV",  CC1|CCB|CCOV },
00146   { "bnov", CC1|CCB|CCNOV },    { "BNOV", CC1|CCB|CCNOV },
00147   { "tc",   CCTC },             { "TC",   CCTC },
00148   { "ntc",  CCNTC },            { "NTC",  CCNTC },
00149   { "c",    CCC },              { "C",    CCC },
00150   { "nc",   CCNC },             { "NC",   CCNC },
00151   { "bio",  CCBIO },            { "BIO",  CCBIO },
00152   { "nbio", CCNBIO },           { "NBIO", CCNBIO },
00153   { NULL, 0 }
00154 };
00155 
00156 const symbol cc2_codes[] = {
00157   { "UNC", 0 },  { "unc", 0 },
00158   { "AEQ", 5 },  { "aeq", 5 },
00159   { "ANEQ", 4 }, { "aneq", 4 },
00160   { "AGT", 6 },  { "agt", 6 },
00161   { "ALT", 3 },  { "alt", 3 },
00162   { "ALEQ", 7 }, { "aleq", 7 },
00163   { "AGEQ", 2 }, { "ageq", 2 },
00164   { "BEQ", 13 }, { "beq", 13 },
00165   { "BNEQ", 12 },{ "bneq", 12 },
00166   { "BGT", 14 }, { "bgt", 14 },
00167   { "BLT", 11 }, { "blt", 11 },
00168   { "BLEQ", 15 },{ "bleq", 15 },
00169   { "BGEQ", 10 },{ "bgeq", 10 },
00170   { NULL, 0 },
00171 };
00172 
00173 const symbol cc3_codes[] = {
00174   { "EQ", 0x0000 },  { "eq", 0x0000 },
00175   { "LT", 0x0100 },  { "lt", 0x0100 },
00176   { "GT", 0x0200 },  { "gt", 0x0200 },
00177   { "NEQ", 0x0300 }, { "neq", 0x0300 },
00178   { "0", 0x0000 },
00179   { "1", 0x0100 },
00180   { "2", 0x0200 },
00181   { "3", 0x0300 },
00182   { "00", 0x0000 },
00183   { "01", 0x0100 },
00184   { "10", 0x0200 },
00185   { "11", 0x0300 },
00186   { NULL, 0 },
00187 };
00188 
00189 /* FIXME -- also allow decimal digits */
00190 const symbol status_bits[] = {
00191   /* status register 0 */
00192   { "TC",  12 },                { "tc",  12 },
00193   { "C",   11 },                { "c",   11 },
00194   { "OVA", 10 },                { "ova", 10 },
00195   { "OVB",  9 },                { "ovb",  9 },
00196   /* status register 1 */
00197   { "BRAF",15 },                { "braf",15 },
00198   { "CPL", 14 },                { "cpl", 14 },
00199   { "XF",  13 },                { "xf",  13 },
00200   { "HM",  12 },                { "hm",  12 },
00201   { "INTM",11 },                { "intm",11 },
00202   { "OVM",  9 },                { "ovm",  9 },
00203   { "SXM",  8 },                { "sxm",  8 },
00204   { "C16",  7 },                { "c16",  7 },
00205   { "FRCT", 6 },                { "frct", 6 },
00206   { "CMPT", 5 },                { "cmpt", 5 },
00207   { NULL, 0 },
00208 };
00209 
00210 const char *misc_symbols[] = {
00211   "ARP", "arp",
00212   "DP",  "dp",
00213   "ASM", "asm",
00214   "TS",  "ts",
00215   NULL
00216 };
00217 
00218 /* Due to the way instructions are hashed and scanned in
00219    gas/config/tc-tic54x.c, all identically-named opcodes must be consecutively
00220    placed
00221 
00222    Items marked with "PREFER" have been moved prior to a more costly
00223    instruction with a similar operand format.
00224 
00225    Mnemonics which can take either a predefined symbol or a memory reference
00226    as an argument are arranged so that the more restrictive (predefined
00227    symbol) version is checked first (marked "SRC").
00228 */
00229 #define ZPAR 0,{OP_None}
00230 #define REST 0,0,ZPAR
00231 #define XREST ZPAR
00232 const template tic54x_unknown_opcode =
00233   { "???",   1,0,0,0x0000, 0x0000, {0}, 0, REST};
00234 const template tic54x_optab[] = {
00235   /* these must precede bc/bcd, cc/ccd to avoid misinterpretation */
00236   { "fb",    2,1,1,0xF880, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
00237   { "fbd",   2,1,1,0xFA80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
00238   { "fcall", 2,1,1,0xF980, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_NR, REST},
00239   { "fcalld",2,1,1,0xFB80, 0xFF80, {OP_xpmad}, B_BRANCH|FL_FAR|FL_DELAY|FL_NR, REST},
00240 
00241   { "abdst", 1,2,2,0xE300, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
00242   { "abs",   1,1,2,0xF485, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
00243   { "add",   1,1,3,0xF400, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
00244   { "add",   1,2,3,0xF480, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
00245   { "add",   1,2,2,0x0000, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00246   { "add",   1,3,3,0x0400, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
00247   { "add",   1,3,4,0x3C00, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
00248   { "add",   1,3,3,0x9000, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST},/*PREFER*/
00249   { "add",   2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
00250     FL_EXT|FL_SMR, 0x0C00, 0xFCE0, XREST},
00251   { "add",   1,3,3,0xA000, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
00252   { "add",   2,2,4,0xF000, 0xFCF0, {OP_lk,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST}, 0, REST},
00253   { "add",   2,3,4,0xF060, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
00254   { "addc",  1,2,2,0x0600, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00255   { "addm",  2,2,2,0x6B00, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
00256   { "adds",  1,2,2,0x0200, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00257   { "and",   1,1,3,0xF080, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},
00258   { "and",   1,2,2,0x1800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST },
00259   { "and",   2,2,4,0xF030, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
00260   { "and",   2,3,4,0xF063, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
00261   { "andm",  2,2,2,0x6800, 0xFF00, {OP_lk,OP_Smem}, FL_NR, REST},
00262   { "b",     2,1,1,0xF073, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
00263   { "bd",    2,1,1,0xF273, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
00264   { "bacc",  1,1,1,0xF4E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
00265   { "baccd", 1,1,1,0xF6E2, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
00266   { "banz",  2,2,2,0x6C00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_NR, REST},
00267   { "banzd", 2,2,2,0x6E00, 0xFF00, {OP_pmad,OP_Sind}, B_BRANCH|FL_DELAY|FL_NR, REST},
00268   { "bc",    2,2,4,0xF800, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
00269     B_BRANCH|FL_NR, REST},
00270   { "bcd",   2,2,4,0xFA00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
00271     B_BRANCH|FL_DELAY|FL_NR, REST},
00272   { "bit",   1,2,2,0x9600, 0xFF00, {OP_Xmem,OP_BITC}, 0, REST},
00273   { "bitf",  2,2,2,0x6100, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
00274   { "bitt",  1,1,1,0x3400, 0xFF00, {OP_Smem}, FL_SMR, REST},
00275   { "cala",  1,1,1,0xF4E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_NR, REST},
00276   { "calad", 1,1,1,0xF6E3, 0xFEFF, {OP_SRC1}, B_BACC|FL_DELAY|FL_NR, REST},
00277   { "call",  2,1,1,0xF074, 0xFFFF, {OP_pmad}, B_BRANCH|FL_NR, REST},
00278   { "calld", 2,1,1,0xF274, 0xFFFF, {OP_pmad}, B_BRANCH|FL_DELAY|FL_NR, REST},
00279   { "cc",    2,2,4,0xF900, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
00280     B_BRANCH|FL_NR, REST},
00281   { "ccd",   2,2,4,0xFB00, 0xFF00, {OP_pmad,OP_CC,OPT|OP_CC,OPT|OP_CC},
00282     B_BRANCH|FL_DELAY|FL_NR, REST},
00283   { "cmpl",  1,1,2,0xF493, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
00284   { "cmpm",  2,2,2,0x6000, 0xFF00, {OP_Smem,OP_lk}, FL_SMR, REST},
00285   { "cmpr",  1,2,2,0xF4A8, 0xFCF8, {OP_CC3,OP_ARX}, FL_NR, REST},
00286   { "cmps",  1,2,2,0x8E00, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
00287   { "dadd",  1,2,3,0x5000, 0xFC00, {OP_Lmem,OP_SRC,OPT|OP_DST}, 0, REST},
00288   { "dadst", 1,2,2,0x5A00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
00289   { "delay", 1,1,1,0x4D00, 0xFF00, {OP_Smem}, FL_SMR, REST},
00290   { "dld",   1,2,2,0x5600, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
00291   { "drsub", 1,2,2,0x5800, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
00292   { "dsadt", 1,2,2,0x5E00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
00293   { "dst",   1,2,2,0x4E00, 0xFE00, {OP_SRC1,OP_Lmem}, FL_NR, REST},
00294   { "dsub",  1,2,2,0x5400, 0xFE00, {OP_Lmem,OP_SRC1}, 0, REST},
00295   { "dsubt", 1,2,2,0x5C00, 0xFE00, {OP_Lmem,OP_DST}, 0, REST},
00296   { "estop", 1,0,0,0xF4F0, 0xFFFF, {OP_None}, 0, REST}, /* undocumented */
00297   { "exp",   1,1,1,0xF48E, 0xFEFF, {OP_SRC1}, 0, REST},
00298   { "fbacc", 1,1,1,0xF4E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
00299   { "fbaccd",1,1,1,0xF6E6, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
00300   { "fcala", 1,1,1,0xF4E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_NR, REST},
00301   { "fcalad",1,1,1,0xF6E7, 0xFEFF, {OP_SRC1}, B_BACC|FL_FAR|FL_DELAY|FL_NR, REST},
00302   { "firs",  2,3,3,0xE000, 0xFF00, {OP_Xmem,OP_Ymem,OP_pmad}, 0, REST},
00303   { "frame", 1,1,1,0xEE00, 0xFF00, {OP_k8}, 0, REST},
00304   { "fret",  1,0,0,0xF4E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
00305   { "fretd", 1,0,0,0xF6E4, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
00306   { "frete", 1,0,0,0xF4E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_NR, REST},
00307   { "freted",1,0,0,0xF6E5, 0xFFFF, {OP_None}, B_RET|FL_FAR|FL_DELAY|FL_NR, REST},
00308   { "idle",  1,1,1,0xF4E1, 0xFCFF, {OP_123}, FL_NR, REST},
00309   { "intr",  1,1,1,0xF7C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
00310   { "ld",    1,2,3,0xF482, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
00311   { "ld",    1,2,3,0xF440, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OP_DST}, 0, REST},/*SRC*/
00312   /* alternate syntax */
00313   { "ld",    1,2,3,0xF440, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
00314   { "ld",    1,2,2,0xE800, 0xFE00, {OP_k8u,OP_DST}, 0, REST},/*SRC*/
00315   { "ld",    1,2,2,0xED00, 0xFFE0, {OP_k5,OP_ASM}, 0, REST},/*SRC*/
00316   { "ld",    1,2,2,0xF4A0, 0xFFF8, {OP_k3,OP_ARP}, FL_NR, REST},/*SRC*/
00317   { "ld",    1,2,2,0xEA00, 0xFE00, {OP_k9,OP_DP}, FL_NR, REST},/*PREFER */
00318   { "ld",    1,2,2,0x3000, 0xFF00, {OP_Smem,OP_T}, FL_SMR, REST},/*SRC*/
00319   { "ld",    1,2,2,0x4600, 0xFF00, {OP_Smem,OP_DP}, FL_SMR, REST},/*SRC*/
00320   { "ld",    1,2,2,0x3200, 0xFF00, {OP_Smem,OP_ASM}, FL_SMR, REST},/*SRC*/
00321   { "ld",    1,2,2,0x1000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00322   { "ld",    1,3,3,0x1400, 0xFE00, {OP_Smem,OP_TS,OP_DST}, FL_SMR, REST},
00323   { "ld",    1,3,3,0x4400, 0xFE00, {OP_Smem,OP_16,OP_DST}, FL_SMR, REST},
00324   { "ld",    1,3,3,0x9400, 0xFE00, {OP_Xmem,OP_SHFT,OP_DST}, 0, REST},/*PREFER*/
00325   { "ld",    2,2,3,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_DST},
00326     FL_EXT|FL_SMR, 0x0C40, 0xFEE0, XREST},
00327   { "ld",    2,2,3,0xF020, 0xFEF0, {OP_lk,OPT|OP_SHFT,OP_DST}, 0, REST},
00328   { "ld",    2,3,3,0xF062, 0xFEFF, {OP_lk,OP_16,OP_DST}, 0, REST},
00329   { "ldm",   1,2,2,0x4800, 0xFE00, {OP_MMR,OP_DST}, 0, REST},
00330   { "ldr",   1,2,2,0x1600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00331   { "ldu",   1,2,2,0x1200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00332   { "ldx",   2,3,3,0xF062, 0xFEFF, {OP_xpmad_ms7,OP_16,OP_DST}, FL_FAR, REST},/*pseudo-op*/
00333   { "lms",   1,2,2,0xE100, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
00334   { "ltd",   1,1,1,0x4C00, 0xFF00, {OP_Smem}, FL_SMR, REST},
00335   { "mac",   1,2,2,0x2800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00336   { "mac",   1,3,4,0xB000, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
00337   { "mac",   2,2,3,0xF067, 0xFCFF, {OP_lk,OP_SRC,OPT|OP_DST}, 0, REST},
00338   { "mac",   2,3,4,0x6400, 0xFC00, {OP_Smem,OP_lk,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
00339   { "macr",  1,2,2,0x2A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00340   { "macr",  1,3,4,0xB400, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST},FL_SMR, REST},
00341   { "maca",  1,2,3,0xF488, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
00342   { "maca",  1,1,2,0x3500, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
00343   { "macar", 1,2,3,0xF489, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, FL_SMR, REST},/*SRC*/
00344   { "macar", 1,1,2,0x3700, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
00345   { "macd",  2,3,3,0x7A00, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
00346   { "macp",  2,3,3,0x7800, 0xFE00, {OP_Smem,OP_pmad,OP_SRC1}, FL_SMR, REST},
00347   { "macsu", 1,3,3,0xA600, 0xFE00, {OP_Xmem,OP_Ymem,OP_SRC1}, 0, REST},
00348   { "mar",   1,1,1,0x6D00, 0xFF00, {OP_Smem}, 0, REST},
00349   { "mas",   1,2,2,0x2C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00350   { "mas",   1,3,4,0xB800, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
00351   { "masr",  1,2,2,0x2E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00352   { "masr",  1,3,4,0xBC00, 0xFC00, {OP_Xmem,OP_Ymem,OP_SRC,OPT|OP_DST}, 0, REST},
00353   { "masa",  1,2,3,0xF48A, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},/*SRC*/
00354   { "masa",  1,1,2,0x3300, 0xFF00, {OP_Smem,OPT|OP_B}, FL_SMR, REST},
00355   { "masar", 1,2,3,0xF48B, 0xFCFF, {OP_T,OP_SRC,OPT|OP_DST}, 0, REST},
00356   { "max",   1,1,1,0xF486, 0xFEFF, {OP_DST}, 0, REST},
00357   { "min",   1,1,1,0xF487, 0xFEFF, {OP_DST}, 0, REST},
00358   { "mpy",   1,2,2,0x2000, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00359   { "mpy",   1,3,3,0xA400, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
00360   { "mpy",   2,3,3,0x6200, 0xFE00, {OP_Smem,OP_lk,OP_DST}, FL_SMR, REST},
00361   { "mpy",   2,2,2,0xF066, 0xFEFF, {OP_lk,OP_DST}, 0, REST},
00362   { "mpyr",  1,2,2,0x2200, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00363   { "mpya",  1,1,1,0xF48C, 0xFEFF, {OP_DST}, 0, REST}, /*SRC*/
00364   { "mpya",  1,1,1,0x3100, 0xFF00, {OP_Smem}, FL_SMR, REST},
00365   { "mpyu",  1,2,2,0x2400, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00366   { "mvdd",  1,2,2,0xE500, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
00367   { "mvdk",  2,2,2,0x7100, 0xFF00, {OP_Smem,OP_dmad}, FL_SMR, REST},
00368   { "mvdm",  2,2,2,0x7200, 0xFF00, {OP_dmad,OP_MMR}, 0, REST},
00369   { "mvdp",  2,2,2,0x7D00, 0xFF00, {OP_Smem,OP_pmad}, FL_SMR, REST},
00370   { "mvkd",  2,2,2,0x7000, 0xFF00, {OP_dmad,OP_Smem}, 0, REST},
00371   { "mvmd",  2,2,2,0x7300, 0xFF00, {OP_MMR,OP_dmad}, 0, REST},
00372   { "mvmm",  1,2,2,0xE700, 0xFF00, {OP_MMRX,OP_MMRY}, FL_NR, REST},
00373   { "mvpd",  2,2,2,0x7C00, 0xFF00, {OP_pmad,OP_Smem}, 0, REST},
00374   { "neg",   1,1,2,0xF484, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
00375   { "nop",   1,0,0,0xF495, 0xFFFF, {OP_None}, 0, REST},
00376   { "norm",  1,1,2,0xF48F, 0xFCFF, {OP_SRC,OPT|OP_DST}, 0, REST},
00377   { "or",    1,1,3,0xF0A0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
00378   { "or",    1,2,2,0x1A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00379   { "or",    2,2,4,0xF040, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
00380   { "or",    2,3,4,0xF064, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
00381   { "orm",   2,2,2,0x6900, 0xFF00, {OP_lk,OP_Smem}, FL_NR|FL_SMR, REST},
00382   { "poly",  1,1,1,0x3600, 0xFF00, {OP_Smem}, FL_SMR, REST},
00383   { "popd",  1,1,1,0x8B00, 0xFF00, {OP_Smem}, 0, REST},
00384   { "popm",  1,1,1,0x8A00, 0xFF00, {OP_MMR}, 0, REST},
00385   { "portr", 2,2,2,0x7400, 0xFF00, {OP_PA,OP_Smem}, 0, REST},
00386   { "portw", 2,2,2,0x7500, 0xFF00, {OP_Smem,OP_PA}, FL_SMR, REST},
00387   { "pshd",  1,1,1,0x4B00, 0xFF00, {OP_Smem}, FL_SMR, REST},
00388   { "pshm",  1,1,1,0x4A00, 0xFF00, {OP_MMR}, 0, REST},
00389   { "ret",   1,0,0,0xFC00, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
00390   { "retd",  1,0,0,0xFE00, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
00391   { "rc",    1,1,3,0xFC00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
00392     B_RET|FL_NR, REST},
00393   { "rcd",   1,1,3,0xFE00, 0xFF00, {OP_CC,OPT|OP_CC,OPT|OP_CC},
00394     B_RET|FL_DELAY|FL_NR, REST},
00395   { "reada", 1,1,1,0x7E00, 0xFF00, {OP_Smem}, 0, REST},
00396   { "reset", 1,0,0,0xF7E0, 0xFFFF, {OP_None}, FL_NR, REST},
00397   { "rete",  1,0,0,0xF4EB, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
00398   { "reted", 1,0,0,0xF6EB, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
00399   { "retf",  1,0,0,0xF49B, 0xFFFF, {OP_None}, B_RET|FL_NR, REST},
00400   { "retfd", 1,0,0,0xF69B, 0xFFFF, {OP_None}, B_RET|FL_DELAY|FL_NR, REST},
00401   { "rnd",   1,1,2,0xF49F, 0xFCFF, {OP_SRC,OPT|OP_DST}, FL_LP|FL_NR, REST},
00402   { "rol",   1,1,1,0xF491, 0xFEFF, {OP_SRC1}, 0, REST},
00403   { "roltc", 1,1,1,0xF492, 0xFEFF, {OP_SRC1}, 0, REST},
00404   { "ror",   1,1,1,0xF490, 0xFEFF, {OP_SRC1}, 0, REST},
00405   { "rpt",   1,1,1,0x4700, 0xFF00, {OP_Smem}, B_REPEAT|FL_NR|FL_SMR, REST},
00406   { "rpt",   1,1,1,0xEC00, 0xFF00, {OP_k8u}, B_REPEAT|FL_NR, REST},
00407   { "rpt",   2,1,1,0xF070, 0xFFFF, {OP_lku}, B_REPEAT|FL_NR, REST},
00408   { "rptb",  2,1,1,0xF072, 0xFFFF, {OP_pmad}, FL_NR, REST},
00409   { "rptbd", 2,1,1,0xF272, 0xFFFF, {OP_pmad}, FL_DELAY|FL_NR, REST},
00410   { "rptz",  2,2,2,0xF071, 0xFEFF, {OP_DST,OP_lku}, B_REPEAT|FL_NR, REST},
00411   { "rsbx",  1,1,2,0xF4B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
00412   { "saccd", 1,3,3,0x9E00, 0xFE00, {OP_SRC1,OP_Xmem,OP_CC2}, 0, REST},
00413   { "sat",   1,1,1,0xF483, 0xFEFF, {OP_SRC1}, 0, REST},
00414   { "sfta",  1,2,3,0xF460, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
00415   { "sftc",  1,1,1,0xF494, 0xFEFF, {OP_SRC1}, 0, REST},
00416   { "sftl",  1,2,3,0xF0E0, 0xFCE0, {OP_SRC,OP_SHIFT,OPT|OP_DST}, 0, REST},
00417   { "sqdst", 1,2,2,0xE200, 0xFF00, {OP_Xmem,OP_Ymem}, 0, REST},
00418   { "squr",  1,2,2,0xF48D, 0xFEFF, {OP_A,OP_DST}, 0, REST},/*SRC*/
00419   { "squr",  1,2,2,0x2600, 0xFE00, {OP_Smem,OP_DST}, FL_SMR, REST},
00420   { "squra", 1,2,2,0x3800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00421   { "squrs", 1,2,2,0x3A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00422   { "srccd", 1,2,2,0x9D00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
00423   { "ssbx",  1,1,2,0xF5B0, 0xFDF0, {OPT|OP_N,OP_SBIT}, FL_NR, REST},
00424   { "st",    1,2,2,0x8C00, 0xFF00, {OP_T,OP_Smem}, 0, REST},
00425   { "st",    1,2,2,0x8D00, 0xFF00, {OP_TRN,OP_Smem}, 0, REST},
00426   { "st",    2,2,2,0x7600, 0xFF00, {OP_lk,OP_Smem}, 0, REST},
00427   { "sth",   1,2,2,0x8200, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
00428   { "sth",   1,3,3,0x8600, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
00429   { "sth",   1,3,3,0x9A00, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
00430   { "sth",   2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
00431     FL_EXT, 0x0C60, 0xFEE0, XREST},
00432   { "stl",   1,2,2,0x8000, 0xFE00, {OP_SRC1,OP_Smem}, 0, REST},
00433   { "stl",   1,3,3,0x8400, 0xFE00, {OP_SRC1,OP_ASM,OP_Smem}, 0, REST},
00434   { "stl",   1,3,3,0x9800, 0xFE00, {OP_SRC1,OP_SHFT,OP_Xmem}, 0, REST},
00435   { "stl",   2,2,3,0x6F00, 0xFF00, {OP_SRC1,OPT|OP_SHIFT,OP_Smem},
00436     FL_EXT, 0x0C80, 0xFEE0, XREST },
00437   { "stlm",  1,2,2,0x8800, 0xFE00, {OP_SRC1,OP_MMR}, 0, REST},
00438   { "stm",   2,2,2,0x7700, 0xFF00, {OP_lk,OP_MMR}, 0, REST},
00439   { "strcd", 1,2,2,0x9C00, 0xFF00, {OP_Xmem,OP_CC2}, 0, REST},
00440   { "sub",   1,1,3,0xF420, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
00441   { "sub",   1,2,3,0xF481, 0xFCFF, {OP_SRC,OP_ASM,OPT|OP_DST}, 0, REST},/*SRC*/
00442   { "sub",   1,2,2,0x0800, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00443   { "sub",   1,3,3,0x0C00, 0xFE00, {OP_Smem,OP_TS,OP_SRC1}, FL_SMR, REST},
00444   { "sub",   1,3,4,0x4000, 0xFC00, {OP_Smem,OP_16,OP_SRC,OPT|OP_DST}, FL_SMR, REST},
00445   { "sub",   1,3,3,0x9200, 0xFE00, {OP_Xmem,OP_SHFT,OP_SRC1}, 0, REST}, /*PREFER*/
00446   { "sub",   2,2,4,0x6F00, 0xFF00, {OP_Smem,OPT|OP_SHIFT,OP_SRC,OPT|OP_DST},
00447     FL_EXT|FL_SMR, 0x0C20, 0xFCE0, XREST},
00448   { "sub",   1,3,3,0xA200, 0xFE00, {OP_Xmem,OP_Ymem,OP_DST}, 0, REST},
00449   { "sub",   2,2,4,0xF010, 0xFCF0, {OP_lk,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
00450   { "sub",   2,3,4,0xF061, 0xFCFF, {OP_lk,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
00451   { "subb",  1,2,2,0x0E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00452   { "subc",  1,2,2,0x1E00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00453   { "subs",  1,2,2,0x0A00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00454   { "trap",  1,1,1,0xF4C0, 0xFFE0, {OP_031}, B_BRANCH|FL_NR, REST},
00455   { "writa", 1,1,1,0x7F00, 0xFF00, {OP_Smem}, FL_SMR, REST},
00456   { "xc",    1,2,4,0xFD00, 0xFD00, {OP_12,OP_CC,OPT|OP_CC,OPT|OP_CC}, FL_NR, REST},
00457   { "xor",   1,1,3,0xF0C0, 0xFCE0, {OP_SRC,OPT|OP_SHIFT,OPT|OP_DST}, 0, REST},/*SRC*/
00458   { "xor",   1,2,2,0x1C00, 0xFE00, {OP_Smem,OP_SRC1}, FL_SMR, REST},
00459   { "xor",   2,2,4,0xF050, 0xFCF0, {OP_lku,OPT|OP_SHFT,OP_SRC,OPT|OP_DST}, 0, REST},
00460   { "xor",   2,3,4,0xF065, 0xFCFF, {OP_lku,OP_16,OP_SRC,OPT|OP_DST}, 0, REST},
00461   { "xorm",  2,2,2,0x6A00, 0xFF00, {OP_lku,OP_Smem}, FL_NR|FL_SMR, REST},
00462   { NULL, 0,0,0,0,0, {}, 0, REST},
00463 };
00464 
00465 /* assume all parallel instructions have at least three operands */
00466 const template tic54x_paroptab[] = {
00467   { "ld",1,1,2,0xA800, 0xFE00, {OP_Xmem,OP_DST},      FL_PAR,0,0,
00468     "mac",                     {OP_Ymem,OPT|OP_RND},},
00469   { "ld",1,1,2,0xAA00, 0xFE00, {OP_Xmem,OP_DST},      FL_PAR,0,0,
00470     "macr",                    {OP_Ymem,OPT|OP_RND},},
00471   { "ld",1,1,2,0xAC00, 0xFE00, {OP_Xmem,OP_DST},      FL_PAR,0,0,
00472     "mas",                     {OP_Ymem,OPT|OP_RND},},
00473   { "ld",1,1,2,0xAE00, 0xFE00, {OP_Xmem,OP_DST},      FL_PAR,0,0,
00474     "masr",                    {OP_Ymem,OPT|OP_RND},},
00475   { "st",1,2,2,0xC000, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00476     "add",                     {OP_Xmem,OP_DST}, },
00477   { "st",1,2,2,0xC800, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00478     "ld",                      {OP_Xmem,OP_DST}, },
00479   { "st",1,2,2,0xE400, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00480     "ld",                      {OP_Xmem,OP_T}, },
00481   { "st",1,2,2,0xD000, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00482     "mac",                     {OP_Xmem,OP_DST}, },
00483   { "st",1,2,2,0xD400, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00484     "macr",                    {OP_Xmem,OP_DST}, },
00485   { "st",1,2,2,0xD800, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00486     "mas",                     {OP_Xmem,OP_DST}, },
00487   { "st",1,2,2,0xDC00, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00488     "masr",                    {OP_Xmem,OP_DST}, },
00489   { "st",1,2,2,0xCC00, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00490     "mpy",                     {OP_Xmem,OP_DST}, },
00491   { "st",1,2,2,0xC400, 0xFC00, {OP_SRC,OP_Ymem},      FL_PAR,0,0,
00492     "sub",                     {OP_Xmem,OP_DST}, },
00493   { NULL, 0, 0, 0, 0, 0, {0,0,0,0}, 0, REST },
00494 };