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cell-binutils  2.17cvs20070401
tc-sparc.c
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00001 /* tc-sparc.c -- Assemble for the SPARC
00002    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
00003    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
00004    Free Software Foundation, Inc.
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public
00018    License along with GAS; see the file COPYING.  If not, write
00019    to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
00020    Boston, MA 02110-1301, USA.  */
00021 
00022 #include "as.h"
00023 #include "safe-ctype.h"
00024 #include "subsegs.h"
00025 
00026 #include "opcode/sparc.h"
00027 #include "dw2gencfi.h"
00028 
00029 #ifdef OBJ_ELF
00030 #include "elf/sparc.h"
00031 #include "dwarf2dbg.h"
00032 #endif
00033 
00034 /* Some ancient Sun C compilers would not take such hex constants as
00035    unsigned, and would end up sign-extending them to form an offsetT,
00036    so use these constants instead.  */
00037 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
00038 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
00039 
00040 static struct sparc_arch *lookup_arch PARAMS ((char *));
00041 static void init_default_arch PARAMS ((void));
00042 static int sparc_ip PARAMS ((char *, const struct sparc_opcode **));
00043 static int in_signed_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
00044 static int in_unsigned_range PARAMS ((bfd_vma, bfd_vma));
00045 static int in_bitfield_range PARAMS ((bfd_signed_vma, bfd_signed_vma));
00046 static int sparc_ffs PARAMS ((unsigned int));
00047 static void synthetize_setuw PARAMS ((const struct sparc_opcode *));
00048 static void synthetize_setsw PARAMS ((const struct sparc_opcode *));
00049 static void synthetize_setx PARAMS ((const struct sparc_opcode *));
00050 static bfd_vma BSR PARAMS ((bfd_vma, int));
00051 static int cmp_reg_entry PARAMS ((const PTR, const PTR));
00052 static int parse_keyword_arg PARAMS ((int (*) (const char *), char **, int *));
00053 static int parse_const_expr_arg PARAMS ((char **, int *));
00054 static int get_expression PARAMS ((char *str));
00055 
00056 /* Default architecture.  */
00057 /* ??? The default value should be V8, but sparclite support was added
00058    by making it the default.  GCC now passes -Asparclite, so maybe sometime in
00059    the future we can set this to V8.  */
00060 #ifndef DEFAULT_ARCH
00061 #define DEFAULT_ARCH "sparclite"
00062 #endif
00063 static char *default_arch = DEFAULT_ARCH;
00064 
00065 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
00066    have been set.  */
00067 static int default_init_p;
00068 
00069 /* Current architecture.  We don't bump up unless necessary.  */
00070 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
00071 
00072 /* The maximum architecture level we can bump up to.
00073    In a 32 bit environment, don't allow bumping up to v9 by default.
00074    The native assembler works this way.  The user is required to pass
00075    an explicit argument before we'll create v9 object files.  However, if
00076    we don't see any v9 insns, a v8plus object file is not created.  */
00077 static enum sparc_opcode_arch_val max_architecture;
00078 
00079 /* Either 32 or 64, selects file format.  */
00080 static int sparc_arch_size;
00081 /* Initial (default) value, recorded separately in case a user option
00082    changes the value before md_show_usage is called.  */
00083 static int default_arch_size;
00084 
00085 #ifdef OBJ_ELF
00086 /* The currently selected v9 memory model.  Currently only used for
00087    ELF.  */
00088 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
00089 #endif
00090 
00091 static int architecture_requested;
00092 static int warn_on_bump;
00093 
00094 /* If warn_on_bump and the needed architecture is higher than this
00095    architecture, issue a warning.  */
00096 static enum sparc_opcode_arch_val warn_after_architecture;
00097 
00098 /* Non-zero if as should generate error if an undeclared g[23] register
00099    has been used in -64.  */
00100 static int no_undeclared_regs;
00101 
00102 /* Non-zero if we should try to relax jumps and calls.  */
00103 static int sparc_relax;
00104 
00105 /* Non-zero if we are generating PIC code.  */
00106 int sparc_pic_code;
00107 
00108 /* Non-zero if we should give an error when misaligned data is seen.  */
00109 static int enforce_aligned_data;
00110 
00111 extern int target_big_endian;
00112 
00113 static int target_little_endian_data;
00114 
00115 /* Symbols for global registers on v9.  */
00116 static symbolS *globals[8];
00117 
00118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
00119 int sparc_cie_data_alignment;
00120 
00121 /* V9 and 86x have big and little endian data, but instructions are always big
00122    endian.  The sparclet has bi-endian support but both data and insns have
00123    the same endianness.  Global `target_big_endian' is used for data.
00124    The following macro is used for instructions.  */
00125 #ifndef INSN_BIG_ENDIAN
00126 #define INSN_BIG_ENDIAN (target_big_endian \
00127                       || default_arch_type == sparc86x \
00128                       || SPARC_OPCODE_ARCH_V9_P (max_architecture))
00129 #endif
00130 
00131 /* Handle of the OPCODE hash table.  */
00132 static struct hash_control *op_hash;
00133 
00134 static int mylog2 PARAMS ((int));
00135 static void s_data1 PARAMS ((void));
00136 static void s_seg PARAMS ((int));
00137 static void s_proc PARAMS ((int));
00138 static void s_reserve PARAMS ((int));
00139 static void s_common PARAMS ((int));
00140 static void s_empty PARAMS ((int));
00141 static void s_uacons PARAMS ((int));
00142 static void s_ncons PARAMS ((int));
00143 #ifdef OBJ_ELF
00144 static void s_register PARAMS ((int));
00145 #endif
00146 
00147 const pseudo_typeS md_pseudo_table[] =
00148 {
00149   {"align", s_align_bytes, 0},     /* Defaulting is invalid (0).  */
00150   {"common", s_common, 0},
00151   {"empty", s_empty, 0},
00152   {"global", s_globl, 0},
00153   {"half", cons, 2},
00154   {"nword", s_ncons, 0},
00155   {"optim", s_ignore, 0},
00156   {"proc", s_proc, 0},
00157   {"reserve", s_reserve, 0},
00158   {"seg", s_seg, 0},
00159   {"skip", s_space, 0},
00160   {"word", cons, 4},
00161   {"xword", cons, 8},
00162   {"uahalf", s_uacons, 2},
00163   {"uaword", s_uacons, 4},
00164   {"uaxword", s_uacons, 8},
00165 #ifdef OBJ_ELF
00166   /* These are specific to sparc/svr4.  */
00167   {"2byte", s_uacons, 2},
00168   {"4byte", s_uacons, 4},
00169   {"8byte", s_uacons, 8},
00170   {"register", s_register, 0},
00171 #endif
00172   {NULL, 0, 0},
00173 };
00174 
00175 /* This array holds the chars that always start a comment.  If the
00176    pre-processor is disabled, these aren't very useful.  */
00177 const char comment_chars[] = "!";  /* JF removed '|' from
00178                                            comment_chars.  */
00179 
00180 /* This array holds the chars that only start a comment at the beginning of
00181    a line.  If the line seems to have the form '# 123 filename'
00182    .line and .file directives will appear in the pre-processed output.  */
00183 /* Note that input_file.c hand checks for '#' at the beginning of the
00184    first line of the input file.  This is because the compiler outputs
00185    #NO_APP at the beginning of its output.  */
00186 /* Also note that comments started like this one will always
00187    work if '/' isn't otherwise defined.  */
00188 const char line_comment_chars[] = "#";
00189 
00190 const char line_separator_chars[] = ";";
00191 
00192 /* Chars that can be used to separate mant from exp in floating point
00193    nums.  */
00194 const char EXP_CHARS[] = "eE";
00195 
00196 /* Chars that mean this number is a floating point constant.
00197    As in 0f12.456
00198    or    0d1.2345e12  */
00199 const char FLT_CHARS[] = "rRsSfFdDxXpP";
00200 
00201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
00202    changed in read.c.  Ideally it shouldn't have to know about it at all,
00203    but nothing is ideal around here.  */
00204 
00205 #define isoctal(c)  ((unsigned) ((c) - '0') < 8)
00206 
00207 struct sparc_it
00208   {
00209     char *error;
00210     unsigned long opcode;
00211     struct nlist *nlistp;
00212     expressionS exp;
00213     expressionS exp2;
00214     int pcrel;
00215     bfd_reloc_code_real_type reloc;
00216   };
00217 
00218 struct sparc_it the_insn, set_insn;
00219 
00220 static void output_insn
00221   PARAMS ((const struct sparc_opcode *, struct sparc_it *));
00222 
00223 /* Table of arguments to -A.
00224    The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
00225    for this use.  That table is for opcodes only.  This table is for opcodes
00226    and file formats.  */
00227 
00228 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
00229                      v8plusa, v9, v9a, v9b, v9_64};
00230 
00231 static struct sparc_arch {
00232   char *name;
00233   char *opcode_arch;
00234   enum sparc_arch_types arch_type;
00235   /* Default word size, as specified during configuration.
00236      A value of zero means can't be used to specify default architecture.  */
00237   int default_arch_size;
00238   /* Allowable arg to -A?  */
00239   int user_option_p;
00240 } sparc_arch_table[] = {
00241   { "v6", "v6", v6, 0, 1 },
00242   { "v7", "v7", v7, 0, 1 },
00243   { "v8", "v8", v8, 32, 1 },
00244   { "sparclet", "sparclet", sparclet, 32, 1 },
00245   { "sparclite", "sparclite", sparclite, 32, 1 },
00246   { "sparc86x", "sparclite", sparc86x, 32, 1 },
00247   { "v8plus", "v9", v9, 0, 1 },
00248   { "v8plusa", "v9a", v9, 0, 1 },
00249   { "v8plusb", "v9b", v9, 0, 1 },
00250   { "v9", "v9", v9, 0, 1 },
00251   { "v9a", "v9a", v9, 0, 1 },
00252   { "v9b", "v9b", v9, 0, 1 },
00253   /* This exists to allow configure.in/Makefile.in to pass one
00254      value to specify both the default machine and default word size.  */
00255   { "v9-64", "v9", v9, 64, 0 },
00256   { NULL, NULL, v8, 0, 0 }
00257 };
00258 
00259 /* Variant of default_arch */
00260 static enum sparc_arch_types default_arch_type;
00261 
00262 static struct sparc_arch *
00263 lookup_arch (name)
00264      char *name;
00265 {
00266   struct sparc_arch *sa;
00267 
00268   for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
00269     if (strcmp (sa->name, name) == 0)
00270       break;
00271   if (sa->name == NULL)
00272     return NULL;
00273   return sa;
00274 }
00275 
00276 /* Initialize the default opcode arch and word size from the default
00277    architecture name.  */
00278 
00279 static void
00280 init_default_arch ()
00281 {
00282   struct sparc_arch *sa = lookup_arch (default_arch);
00283 
00284   if (sa == NULL
00285       || sa->default_arch_size == 0)
00286     as_fatal (_("Invalid default architecture, broken assembler."));
00287 
00288   max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
00289   if (max_architecture == SPARC_OPCODE_ARCH_BAD)
00290     as_fatal (_("Bad opcode table, broken assembler."));
00291   default_arch_size = sparc_arch_size = sa->default_arch_size;
00292   default_init_p = 1;
00293   default_arch_type = sa->arch_type;
00294 }
00295 
00296 /* Called by TARGET_FORMAT.  */
00297 
00298 const char *
00299 sparc_target_format ()
00300 {
00301   /* We don't get a chance to initialize anything before we're called,
00302      so handle that now.  */
00303   if (! default_init_p)
00304     init_default_arch ();
00305 
00306 #ifdef OBJ_AOUT
00307 #ifdef TE_NetBSD
00308   return "a.out-sparc-netbsd";
00309 #else
00310 #ifdef TE_SPARCAOUT
00311   if (target_big_endian)
00312     return "a.out-sunos-big";
00313   else if (default_arch_type == sparc86x && target_little_endian_data)
00314     return "a.out-sunos-big";
00315   else
00316     return "a.out-sparc-little";
00317 #else
00318   return "a.out-sunos-big";
00319 #endif
00320 #endif
00321 #endif
00322 
00323 #ifdef OBJ_BOUT
00324   return "b.out.big";
00325 #endif
00326 
00327 #ifdef OBJ_COFF
00328 #ifdef TE_LYNX
00329   return "coff-sparc-lynx";
00330 #else
00331   return "coff-sparc";
00332 #endif
00333 #endif
00334 
00335 #ifdef TE_VXWORKS
00336   return "elf32-sparc-vxworks";
00337 #endif
00338 
00339 #ifdef OBJ_ELF
00340   return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
00341 #endif
00342 
00343   abort ();
00344 }
00345 
00346 /* md_parse_option
00347  *     Invocation line includes a switch not recognized by the base assembler.
00348  *     See if it's a processor-specific option.  These are:
00349  *
00350  *     -bump
00351  *            Warn on architecture bumps.  See also -A.
00352  *
00353  *     -Av6, -Av7, -Av8, -Asparclite, -Asparclet
00354  *            Standard 32 bit architectures.
00355  *     -Av9, -Av9a, -Av9b
00356  *            Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
00357  *            This used to only mean 64 bits, but properly specifying it
00358  *            complicated gcc's ASM_SPECs, so now opcode selection is
00359  *            specified orthogonally to word size (except when specifying
00360  *            the default, but that is an internal implementation detail).
00361  *     -Av8plus, -Av8plusa, -Av8plusb
00362  *            Same as -Av9{,a,b}.
00363  *     -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
00364  *            Same as -Av8plus{,a,b} -32, for compatibility with Sun's
00365  *            assembler.
00366  *     -xarch=v9, -xarch=v9a, -xarch=v9b
00367  *            Same as -Av9{,a,b} -64, for compatibility with Sun's
00368  *            assembler.
00369  *
00370  *            Select the architecture and possibly the file format.
00371  *            Instructions or features not supported by the selected
00372  *            architecture cause fatal errors.
00373  *
00374  *            The default is to start at v6, and bump the architecture up
00375  *            whenever an instruction is seen at a higher level.  In 32 bit
00376  *            environments, v9 is not bumped up to, the user must pass
00377  *            -Av8plus{,a,b}.
00378  *
00379  *            If -bump is specified, a warning is printing when bumping to
00380  *            higher levels.
00381  *
00382  *            If an architecture is specified, all instructions must match
00383  *            that architecture.  Any higher level instructions are flagged
00384  *            as errors.  Note that in the 32 bit environment specifying
00385  *            -Av8plus does not automatically create a v8plus object file, a
00386  *            v9 insn must be seen.
00387  *
00388  *            If both an architecture and -bump are specified, the
00389  *            architecture starts at the specified level, but bumps are
00390  *            warnings.  Note that we can't set `current_architecture' to
00391  *            the requested level in this case: in the 32 bit environment,
00392  *            we still must avoid creating v8plus object files unless v9
00393  *            insns are seen.
00394  *
00395  * Note:
00396  *            Bumping between incompatible architectures is always an
00397  *            error.  For example, from sparclite to v9.
00398  */
00399 
00400 #ifdef OBJ_ELF
00401 const char *md_shortopts = "A:K:VQ:sq";
00402 #else
00403 #ifdef OBJ_AOUT
00404 const char *md_shortopts = "A:k";
00405 #else
00406 const char *md_shortopts = "A:";
00407 #endif
00408 #endif
00409 struct option md_longopts[] = {
00410 #define OPTION_BUMP (OPTION_MD_BASE)
00411   {"bump", no_argument, NULL, OPTION_BUMP},
00412 #define OPTION_SPARC (OPTION_MD_BASE + 1)
00413   {"sparc", no_argument, NULL, OPTION_SPARC},
00414 #define OPTION_XARCH (OPTION_MD_BASE + 2)
00415   {"xarch", required_argument, NULL, OPTION_XARCH},
00416 #ifdef OBJ_ELF
00417 #define OPTION_32 (OPTION_MD_BASE + 3)
00418   {"32", no_argument, NULL, OPTION_32},
00419 #define OPTION_64 (OPTION_MD_BASE + 4)
00420   {"64", no_argument, NULL, OPTION_64},
00421 #define OPTION_TSO (OPTION_MD_BASE + 5)
00422   {"TSO", no_argument, NULL, OPTION_TSO},
00423 #define OPTION_PSO (OPTION_MD_BASE + 6)
00424   {"PSO", no_argument, NULL, OPTION_PSO},
00425 #define OPTION_RMO (OPTION_MD_BASE + 7)
00426   {"RMO", no_argument, NULL, OPTION_RMO},
00427 #endif
00428 #ifdef SPARC_BIENDIAN
00429 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
00430   {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
00431 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
00432   {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
00433 #endif
00434 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
00435   {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
00436 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
00437   {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
00438 #ifdef OBJ_ELF
00439 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
00440   {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
00441 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
00442   {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
00443 #endif
00444 #define OPTION_RELAX (OPTION_MD_BASE + 14)
00445   {"relax", no_argument, NULL, OPTION_RELAX},
00446 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
00447   {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
00448   {NULL, no_argument, NULL, 0}
00449 };
00450 
00451 size_t md_longopts_size = sizeof (md_longopts);
00452 
00453 int
00454 md_parse_option (c, arg)
00455      int c;
00456      char *arg;
00457 {
00458   /* We don't get a chance to initialize anything before we're called,
00459      so handle that now.  */
00460   if (! default_init_p)
00461     init_default_arch ();
00462 
00463   switch (c)
00464     {
00465     case OPTION_BUMP:
00466       warn_on_bump = 1;
00467       warn_after_architecture = SPARC_OPCODE_ARCH_V6;
00468       break;
00469 
00470     case OPTION_XARCH:
00471 #ifdef OBJ_ELF
00472       if (strncmp (arg, "v9", 2) != 0)
00473        md_parse_option (OPTION_32, NULL);
00474       else
00475        md_parse_option (OPTION_64, NULL);
00476 #endif
00477       /* Fall through.  */
00478 
00479     case 'A':
00480       {
00481        struct sparc_arch *sa;
00482        enum sparc_opcode_arch_val opcode_arch;
00483 
00484        sa = lookup_arch (arg);
00485        if (sa == NULL
00486            || ! sa->user_option_p)
00487          {
00488            if (c == OPTION_XARCH)
00489              as_bad (_("invalid architecture -xarch=%s"), arg);
00490            else
00491              as_bad (_("invalid architecture -A%s"), arg);
00492            return 0;
00493          }
00494 
00495        opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
00496        if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
00497          as_fatal (_("Bad opcode table, broken assembler."));
00498 
00499        max_architecture = opcode_arch;
00500        architecture_requested = 1;
00501       }
00502       break;
00503 
00504     case OPTION_SPARC:
00505       /* Ignore -sparc, used by SunOS make default .s.o rule.  */
00506       break;
00507 
00508     case OPTION_ENFORCE_ALIGNED_DATA:
00509       enforce_aligned_data = 1;
00510       break;
00511 
00512 #ifdef SPARC_BIENDIAN
00513     case OPTION_LITTLE_ENDIAN:
00514       target_big_endian = 0;
00515       if (default_arch_type != sparclet)
00516        as_fatal ("This target does not support -EL");
00517       break;
00518     case OPTION_LITTLE_ENDIAN_DATA:
00519       target_little_endian_data = 1;
00520       target_big_endian = 0;
00521       if (default_arch_type != sparc86x
00522          && default_arch_type != v9)
00523        as_fatal ("This target does not support --little-endian-data");
00524       break;
00525     case OPTION_BIG_ENDIAN:
00526       target_big_endian = 1;
00527       break;
00528 #endif
00529 
00530 #ifdef OBJ_AOUT
00531     case 'k':
00532       sparc_pic_code = 1;
00533       break;
00534 #endif
00535 
00536 #ifdef OBJ_ELF
00537     case OPTION_32:
00538     case OPTION_64:
00539       {
00540        const char **list, **l;
00541 
00542        sparc_arch_size = c == OPTION_32 ? 32 : 64;
00543        list = bfd_target_list ();
00544        for (l = list; *l != NULL; l++)
00545          {
00546            if (sparc_arch_size == 32)
00547              {
00548               if (CONST_STRNEQ (*l, "elf32-sparc"))
00549                 break;
00550              }
00551            else
00552              {
00553               if (CONST_STRNEQ (*l, "elf64-sparc"))
00554                 break;
00555              }
00556          }
00557        if (*l == NULL)
00558          as_fatal (_("No compiled in support for %d bit object file format"),
00559                   sparc_arch_size);
00560        free (list);
00561       }
00562       break;
00563 
00564     case OPTION_TSO:
00565       sparc_memory_model = MM_TSO;
00566       break;
00567 
00568     case OPTION_PSO:
00569       sparc_memory_model = MM_PSO;
00570       break;
00571 
00572     case OPTION_RMO:
00573       sparc_memory_model = MM_RMO;
00574       break;
00575 
00576     case 'V':
00577       print_version_id ();
00578       break;
00579 
00580     case 'Q':
00581       /* Qy - do emit .comment
00582         Qn - do not emit .comment.  */
00583       break;
00584 
00585     case 's':
00586       /* Use .stab instead of .stab.excl.  */
00587       break;
00588 
00589     case 'q':
00590       /* quick -- Native assembler does fewer checks.  */
00591       break;
00592 
00593     case 'K':
00594       if (strcmp (arg, "PIC") != 0)
00595        as_warn (_("Unrecognized option following -K"));
00596       else
00597        sparc_pic_code = 1;
00598       break;
00599 
00600     case OPTION_NO_UNDECLARED_REGS:
00601       no_undeclared_regs = 1;
00602       break;
00603 
00604     case OPTION_UNDECLARED_REGS:
00605       no_undeclared_regs = 0;
00606       break;
00607 #endif
00608 
00609     case OPTION_RELAX:
00610       sparc_relax = 1;
00611       break;
00612 
00613     case OPTION_NO_RELAX:
00614       sparc_relax = 0;
00615       break;
00616 
00617     default:
00618       return 0;
00619     }
00620 
00621   return 1;
00622 }
00623 
00624 void
00625 md_show_usage (stream)
00626      FILE *stream;
00627 {
00628   const struct sparc_arch *arch;
00629   int column;
00630 
00631   /* We don't get a chance to initialize anything before we're called,
00632      so handle that now.  */
00633   if (! default_init_p)
00634     init_default_arch ();
00635 
00636   fprintf (stream, _("SPARC options:\n"));
00637   column = 0;
00638   for (arch = &sparc_arch_table[0]; arch->name; arch++)
00639     {
00640       if (!arch->user_option_p)
00641        continue;
00642       if (arch != &sparc_arch_table[0])
00643        fprintf (stream, " | ");
00644       if (column + strlen (arch->name) > 70)
00645        {
00646          column = 0;
00647          fputc ('\n', stream);
00648        }
00649       column += 5 + 2 + strlen (arch->name);
00650       fprintf (stream, "-A%s", arch->name);
00651     }
00652   for (arch = &sparc_arch_table[0]; arch->name; arch++)
00653     {
00654       if (!arch->user_option_p)
00655        continue;
00656       fprintf (stream, " | ");
00657       if (column + strlen (arch->name) > 65)
00658        {
00659          column = 0;
00660          fputc ('\n', stream);
00661        }
00662       column += 5 + 7 + strlen (arch->name);
00663       fprintf (stream, "-xarch=%s", arch->name);
00664     }
00665   fprintf (stream, _("\n\
00666                      specify variant of SPARC architecture\n\
00667 -bump                warn when assembler switches architectures\n\
00668 -sparc               ignored\n\
00669 --enforce-aligned-data      force .long, etc., to be aligned correctly\n\
00670 -relax               relax jumps and branches (default)\n\
00671 -no-relax            avoid changing any jumps and branches\n"));
00672 #ifdef OBJ_AOUT
00673   fprintf (stream, _("\
00674 -k                   generate PIC\n"));
00675 #endif
00676 #ifdef OBJ_ELF
00677   fprintf (stream, _("\
00678 -32                  create 32 bit object file\n\
00679 -64                  create 64 bit object file\n"));
00680   fprintf (stream, _("\
00681                      [default is %d]\n"), default_arch_size);
00682   fprintf (stream, _("\
00683 -TSO                 use Total Store Ordering\n\
00684 -PSO                 use Partial Store Ordering\n\
00685 -RMO                 use Relaxed Memory Ordering\n"));
00686   fprintf (stream, _("\
00687                      [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
00688   fprintf (stream, _("\
00689 -KPIC                generate PIC\n\
00690 -V                   print assembler version number\n\
00691 -undeclared-regs     ignore application global register usage without\n\
00692                      appropriate .register directive (default)\n\
00693 -no-undeclared-regs  force error on application global register usage\n\
00694                      without appropriate .register directive\n\
00695 -q                   ignored\n\
00696 -Qy, -Qn             ignored\n\
00697 -s                   ignored\n"));
00698 #endif
00699 #ifdef SPARC_BIENDIAN
00700   fprintf (stream, _("\
00701 -EL                  generate code for a little endian machine\n\
00702 -EB                  generate code for a big endian machine\n\
00703 --little-endian-data generate code for a machine having big endian\n\
00704                         instructions and little endian data.\n"));
00705 #endif
00706 }
00707 
00708 /* Native operand size opcode translation.  */
00709 struct
00710   {
00711     char *name;
00712     char *name32;
00713     char *name64;
00714   } native_op_table[] =
00715 {
00716   {"ldn", "ld", "ldx"},
00717   {"ldna", "lda", "ldxa"},
00718   {"stn", "st", "stx"},
00719   {"stna", "sta", "stxa"},
00720   {"slln", "sll", "sllx"},
00721   {"srln", "srl", "srlx"},
00722   {"sran", "sra", "srax"},
00723   {"casn", "cas", "casx"},
00724   {"casna", "casa", "casxa"},
00725   {"clrn", "clr", "clrx"},
00726   {NULL, NULL, NULL},
00727 };
00728 
00729 /* sparc64 privileged and hyperprivileged registers.  */
00730 
00731 struct priv_reg_entry
00732 {
00733   char *name;
00734   int regnum;
00735 };
00736 
00737 struct priv_reg_entry priv_reg_table[] =
00738 {
00739   {"tpc", 0},
00740   {"tnpc", 1},
00741   {"tstate", 2},
00742   {"tt", 3},
00743   {"tick", 4},
00744   {"tba", 5},
00745   {"pstate", 6},
00746   {"tl", 7},
00747   {"pil", 8},
00748   {"cwp", 9},
00749   {"cansave", 10},
00750   {"canrestore", 11},
00751   {"cleanwin", 12},
00752   {"otherwin", 13},
00753   {"wstate", 14},
00754   {"fq", 15},
00755   {"gl", 16},
00756   {"ver", 31},
00757   {"", -1},                 /* End marker.  */
00758 };
00759 
00760 struct priv_reg_entry hpriv_reg_table[] =
00761 {
00762   {"hpstate", 0},
00763   {"htstate", 1},
00764   {"hintp", 3},
00765   {"htba", 5},
00766   {"hver", 6},
00767   {"hstick_cmpr", 31},
00768   {"", -1},                 /* End marker.  */
00769 };
00770 
00771 /* v9a specific asrs.  */
00772 
00773 struct priv_reg_entry v9a_asr_table[] =
00774 {
00775   {"tick_cmpr", 23},
00776   {"sys_tick_cmpr", 25},
00777   {"sys_tick", 24},
00778   {"softint", 22},
00779   {"set_softint", 20},
00780   {"pic", 17},
00781   {"pcr", 16},
00782   {"gsr", 19},
00783   {"dcr", 18},
00784   {"clear_softint", 21},
00785   {"", -1},                 /* End marker.  */
00786 };
00787 
00788 static int
00789 cmp_reg_entry (parg, qarg)
00790      const PTR parg;
00791      const PTR qarg;
00792 {
00793   const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
00794   const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
00795 
00796   return strcmp (q->name, p->name);
00797 }
00798 
00799 /* This function is called once, at assembler startup time.  It should
00800    set up all the tables, etc. that the MD part of the assembler will
00801    need.  */
00802 
00803 void
00804 md_begin ()
00805 {
00806   register const char *retval = NULL;
00807   int lose = 0;
00808   register unsigned int i = 0;
00809 
00810   /* We don't get a chance to initialize anything before md_parse_option
00811      is called, and it may not be called, so handle default initialization
00812      now if not already done.  */
00813   if (! default_init_p)
00814     init_default_arch ();
00815 
00816   sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
00817   op_hash = hash_new ();
00818 
00819   while (i < (unsigned int) sparc_num_opcodes)
00820     {
00821       const char *name = sparc_opcodes[i].name;
00822       retval = hash_insert (op_hash, name, (PTR) &sparc_opcodes[i]);
00823       if (retval != NULL)
00824        {
00825          as_bad (_("Internal error: can't hash `%s': %s\n"),
00826                 sparc_opcodes[i].name, retval);
00827          lose = 1;
00828        }
00829       do
00830        {
00831          if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
00832            {
00833              as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
00834                     sparc_opcodes[i].name, sparc_opcodes[i].args);
00835              lose = 1;
00836            }
00837          ++i;
00838        }
00839       while (i < (unsigned int) sparc_num_opcodes
00840             && !strcmp (sparc_opcodes[i].name, name));
00841     }
00842 
00843   for (i = 0; native_op_table[i].name; i++)
00844     {
00845       const struct sparc_opcode *insn;
00846       char *name = ((sparc_arch_size == 32)
00847                   ? native_op_table[i].name32
00848                   : native_op_table[i].name64);
00849       insn = (struct sparc_opcode *) hash_find (op_hash, name);
00850       if (insn == NULL)
00851        {
00852          as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
00853                 name, native_op_table[i].name);
00854          lose = 1;
00855        }
00856       else
00857        {
00858          retval = hash_insert (op_hash, native_op_table[i].name, (PTR) insn);
00859          if (retval != NULL)
00860            {
00861              as_bad (_("Internal error: can't hash `%s': %s\n"),
00862                     sparc_opcodes[i].name, retval);
00863              lose = 1;
00864            }
00865        }
00866     }
00867 
00868   if (lose)
00869     as_fatal (_("Broken assembler.  No assembly attempted."));
00870 
00871   qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
00872         sizeof (priv_reg_table[0]), cmp_reg_entry);
00873 
00874   /* If -bump, record the architecture level at which we start issuing
00875      warnings.  The behaviour is different depending upon whether an
00876      architecture was explicitly specified.  If it wasn't, we issue warnings
00877      for all upwards bumps.  If it was, we don't start issuing warnings until
00878      we need to bump beyond the requested architecture or when we bump between
00879      conflicting architectures.  */
00880 
00881   if (warn_on_bump
00882       && architecture_requested)
00883     {
00884       /* `max_architecture' records the requested architecture.
00885         Issue warnings if we go above it.  */
00886       warn_after_architecture = max_architecture;
00887 
00888       /* Find the highest architecture level that doesn't conflict with
00889         the requested one.  */
00890       for (max_architecture = SPARC_OPCODE_ARCH_MAX;
00891           max_architecture > warn_after_architecture;
00892           --max_architecture)
00893        if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
00894                                    warn_after_architecture))
00895          break;
00896     }
00897 }
00898 
00899 /* Called after all assembly has been done.  */
00900 
00901 void
00902 sparc_md_end ()
00903 {
00904   unsigned long mach = bfd_mach_sparc;
00905 
00906   if (sparc_arch_size == 64)
00907     switch (current_architecture)
00908       {
00909       case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
00910       case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
00911       default: mach = bfd_mach_sparc_v9; break;
00912       }
00913   else
00914     switch (current_architecture)
00915       {
00916       case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
00917       case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
00918       case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
00919       case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
00920       /* The sparclite is treated like a normal sparc.  Perhaps it shouldn't
00921         be but for now it is (since that's the way it's always been
00922         treated).  */
00923       default: break;
00924       }
00925   bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
00926 }
00927 
00928 /* Return non-zero if VAL is in the range -(MAX+1) to MAX.  */
00929 
00930 static INLINE int
00931 in_signed_range (val, max)
00932      bfd_signed_vma val, max;
00933 {
00934   if (max <= 0)
00935     abort ();
00936   /* Sign-extend the value from the architecture word size, so that
00937      0xffffffff is always considered -1 on sparc32.  */
00938   if (sparc_arch_size == 32)
00939     {
00940       bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
00941       val = ((val & U0xffffffff) ^ sign) - sign;
00942     }
00943   if (val > max)
00944     return 0;
00945   if (val < ~max)
00946     return 0;
00947   return 1;
00948 }
00949 
00950 /* Return non-zero if VAL is in the range 0 to MAX.  */
00951 
00952 static INLINE int
00953 in_unsigned_range (val, max)
00954      bfd_vma val, max;
00955 {
00956   if (val > max)
00957     return 0;
00958   return 1;
00959 }
00960 
00961 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
00962    (e.g. -15 to +31).  */
00963 
00964 static INLINE int
00965 in_bitfield_range (val, max)
00966      bfd_signed_vma val, max;
00967 {
00968   if (max <= 0)
00969     abort ();
00970   if (val > max)
00971     return 0;
00972   if (val < ~(max >> 1))
00973     return 0;
00974   return 1;
00975 }
00976 
00977 static int
00978 sparc_ffs (mask)
00979      unsigned int mask;
00980 {
00981   int i;
00982 
00983   if (mask == 0)
00984     return -1;
00985 
00986   for (i = 0; (mask & 1) == 0; ++i)
00987     mask >>= 1;
00988   return i;
00989 }
00990 
00991 /* Implement big shift right.  */
00992 static bfd_vma
00993 BSR (val, amount)
00994      bfd_vma val;
00995      int amount;
00996 {
00997   if (sizeof (bfd_vma) <= 4 && amount >= 32)
00998     as_fatal (_("Support for 64-bit arithmetic not compiled in."));
00999   return val >> amount;
01000 }
01001 
01002 /* For communication between sparc_ip and get_expression.  */
01003 static char *expr_end;
01004 
01005 /* Values for `special_case'.
01006    Instructions that require wierd handling because they're longer than
01007    4 bytes.  */
01008 #define SPECIAL_CASE_NONE   0
01009 #define       SPECIAL_CASE_SET     1
01010 #define SPECIAL_CASE_SETSW  2
01011 #define SPECIAL_CASE_SETX   3
01012 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this.  */
01013 #define       SPECIAL_CASE_FDIV    4
01014 
01015 /* Bit masks of various insns.  */
01016 #define NOP_INSN 0x01000000
01017 #define OR_INSN 0x80100000
01018 #define XOR_INSN 0x80180000
01019 #define FMOVS_INSN 0x81A00020
01020 #define SETHI_INSN 0x01000000
01021 #define SLLX_INSN 0x81281000
01022 #define SRA_INSN 0x81380000
01023 
01024 /* The last instruction to be assembled.  */
01025 static const struct sparc_opcode *last_insn;
01026 /* The assembled opcode of `last_insn'.  */
01027 static unsigned long last_opcode;
01028 
01029 /* Handle the set and setuw synthetic instructions.  */
01030 
01031 static void
01032 synthetize_setuw (insn)
01033      const struct sparc_opcode *insn;
01034 {
01035   int need_hi22_p = 0;
01036   int rd = (the_insn.opcode & RD (~0)) >> 25;
01037 
01038   if (the_insn.exp.X_op == O_constant)
01039     {
01040       if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
01041        {
01042          if (sizeof (offsetT) > 4
01043              && (the_insn.exp.X_add_number < 0
01044                 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
01045            as_warn (_("set: number not in 0..4294967295 range"));
01046        }
01047       else
01048        {
01049          if (sizeof (offsetT) > 4
01050              && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
01051                 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
01052            as_warn (_("set: number not in -2147483648..4294967295 range"));
01053          the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
01054        }
01055     }
01056 
01057   /* See if operand is absolute and small; skip sethi if so.  */
01058   if (the_insn.exp.X_op != O_constant
01059       || the_insn.exp.X_add_number >= (1 << 12)
01060       || the_insn.exp.X_add_number < -(1 << 12))
01061     {
01062       the_insn.opcode = (SETHI_INSN | RD (rd)
01063                       | ((the_insn.exp.X_add_number >> 10)
01064                          & (the_insn.exp.X_op == O_constant
01065                             ? 0x3fffff : 0)));
01066       the_insn.reloc = (the_insn.exp.X_op != O_constant
01067                      ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
01068       output_insn (insn, &the_insn);
01069       need_hi22_p = 1;
01070     }
01071 
01072   /* See if operand has no low-order bits; skip OR if so.  */
01073   if (the_insn.exp.X_op != O_constant
01074       || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
01075       || ! need_hi22_p)
01076     {
01077       the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
01078                       | RD (rd) | IMMED
01079                       | (the_insn.exp.X_add_number
01080                          & (the_insn.exp.X_op != O_constant
01081                             ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
01082       the_insn.reloc = (the_insn.exp.X_op != O_constant
01083                      ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
01084       output_insn (insn, &the_insn);
01085     }
01086 }
01087 
01088 /* Handle the setsw synthetic instruction.  */
01089 
01090 static void
01091 synthetize_setsw (insn)
01092      const struct sparc_opcode *insn;
01093 {
01094   int low32, rd, opc;
01095 
01096   rd = (the_insn.opcode & RD (~0)) >> 25;
01097 
01098   if (the_insn.exp.X_op != O_constant)
01099     {
01100       synthetize_setuw (insn);
01101 
01102       /* Need to sign extend it.  */
01103       the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
01104       the_insn.reloc = BFD_RELOC_NONE;
01105       output_insn (insn, &the_insn);
01106       return;
01107     }
01108 
01109   if (sizeof (offsetT) > 4
01110       && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
01111          || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
01112     as_warn (_("setsw: number not in -2147483648..4294967295 range"));
01113 
01114   low32 = the_insn.exp.X_add_number;
01115 
01116   if (low32 >= 0)
01117     {
01118       synthetize_setuw (insn);
01119       return;
01120     }
01121 
01122   opc = OR_INSN;
01123 
01124   the_insn.reloc = BFD_RELOC_NONE;
01125   /* See if operand is absolute and small; skip sethi if so.  */
01126   if (low32 < -(1 << 12))
01127     {
01128       the_insn.opcode = (SETHI_INSN | RD (rd)
01129                       | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
01130       output_insn (insn, &the_insn);
01131       low32 = 0x1c00 | (low32 & 0x3ff);
01132       opc = RS1 (rd) | XOR_INSN;
01133     }
01134 
01135   the_insn.opcode = (opc | RD (rd) | IMMED
01136                    | (low32 & 0x1fff));
01137   output_insn (insn, &the_insn);
01138 }
01139 
01140 /* Handle the setsw synthetic instruction.  */
01141 
01142 static void
01143 synthetize_setx (insn)
01144      const struct sparc_opcode *insn;
01145 {
01146   int upper32, lower32;
01147   int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
01148   int dstreg = (the_insn.opcode & RD (~0)) >> 25;
01149   int upper_dstreg;
01150   int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
01151   int need_xor10_p = 0;
01152 
01153 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
01154   lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
01155   upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
01156 #undef SIGNEXT32
01157 
01158   upper_dstreg = tmpreg;
01159   /* The tmp reg should not be the dst reg.  */
01160   if (tmpreg == dstreg)
01161     as_warn (_("setx: temporary register same as destination register"));
01162 
01163   /* ??? Obviously there are other optimizations we can do
01164      (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
01165      doing some of these.  Later.  If you do change things, try to
01166      change all of this to be table driven as well.  */
01167   /* What to output depends on the number if it's constant.
01168      Compute that first, then output what we've decided upon.  */
01169   if (the_insn.exp.X_op != O_constant)
01170     {
01171       if (sparc_arch_size == 32)
01172        {
01173          /* When arch size is 32, we want setx to be equivalent
01174             to setuw for anything but constants.  */
01175          the_insn.exp.X_add_number &= 0xffffffff;
01176          synthetize_setuw (insn);
01177          return;
01178        }
01179       need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
01180       lower32 = 0;
01181       upper32 = 0;
01182     }
01183   else
01184     {
01185       /* Reset X_add_number, we've extracted it as upper32/lower32.
01186         Otherwise fixup_segment will complain about not being able to
01187         write an 8 byte number in a 4 byte field.  */
01188       the_insn.exp.X_add_number = 0;
01189 
01190       /* Only need hh22 if `or' insn can't handle constant.  */
01191       if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
01192        need_hh22_p = 1;
01193 
01194       /* Does bottom part (after sethi) have bits?  */
01195       if ((need_hh22_p && (upper32 & 0x3ff) != 0)
01196          /* No hh22, but does upper32 still have bits we can't set
01197             from lower32?  */
01198          || (! need_hh22_p && upper32 != 0 && upper32 != -1))
01199        need_hm10_p = 1;
01200 
01201       /* If the lower half is all zero, we build the upper half directly
01202         into the dst reg.  */
01203       if (lower32 != 0
01204          /* Need lower half if number is zero or 0xffffffff00000000.  */
01205          || (! need_hh22_p && ! need_hm10_p))
01206        {
01207          /* No need for sethi if `or' insn can handle constant.  */
01208          if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
01209              /* Note that we can't use a negative constant in the `or'
01210                insn unless the upper 32 bits are all ones.  */
01211              || (lower32 < 0 && upper32 != -1)
01212              || (lower32 >= 0 && upper32 == -1))
01213            need_hi22_p = 1;
01214 
01215          if (need_hi22_p && upper32 == -1)
01216            need_xor10_p = 1;
01217 
01218          /* Does bottom part (after sethi) have bits?  */
01219          else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
01220                  /* No sethi.  */
01221                  || (! need_hi22_p && (lower32 & 0x1fff) != 0)
01222                  /* Need `or' if we didn't set anything else.  */
01223                  || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
01224            need_lo10_p = 1;
01225        }
01226       else
01227        /* Output directly to dst reg if lower 32 bits are all zero.  */
01228        upper_dstreg = dstreg;
01229     }
01230 
01231   if (!upper_dstreg && dstreg)
01232     as_warn (_("setx: illegal temporary register g0"));
01233 
01234   if (need_hh22_p)
01235     {
01236       the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
01237                       | ((upper32 >> 10) & 0x3fffff));
01238       the_insn.reloc = (the_insn.exp.X_op != O_constant
01239                      ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
01240       output_insn (insn, &the_insn);
01241     }
01242 
01243   if (need_hi22_p)
01244     {
01245       the_insn.opcode = (SETHI_INSN | RD (dstreg)
01246                       | (((need_xor10_p ? ~lower32 : lower32)
01247                           >> 10) & 0x3fffff));
01248       the_insn.reloc = (the_insn.exp.X_op != O_constant
01249                      ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
01250       output_insn (insn, &the_insn);
01251     }
01252 
01253   if (need_hm10_p)
01254     {
01255       the_insn.opcode = (OR_INSN
01256                       | (need_hh22_p ? RS1 (upper_dstreg) : 0)
01257                       | RD (upper_dstreg)
01258                       | IMMED
01259                       | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
01260       the_insn.reloc = (the_insn.exp.X_op != O_constant
01261                      ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
01262       output_insn (insn, &the_insn);
01263     }
01264 
01265   if (need_lo10_p)
01266     {
01267       /* FIXME: One nice optimization to do here is to OR the low part
01268         with the highpart if hi22 isn't needed and the low part is
01269         positive.  */
01270       the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
01271                       | RD (dstreg)
01272                       | IMMED
01273                       | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
01274       the_insn.reloc = (the_insn.exp.X_op != O_constant
01275                      ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
01276       output_insn (insn, &the_insn);
01277     }
01278 
01279   /* If we needed to build the upper part, shift it into place.  */
01280   if (need_hh22_p || need_hm10_p)
01281     {
01282       the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
01283                       | IMMED | 32);
01284       the_insn.reloc = BFD_RELOC_NONE;
01285       output_insn (insn, &the_insn);
01286     }
01287 
01288   /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r.  */
01289   if (need_xor10_p)
01290     {
01291       the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
01292                       | 0x1c00 | (lower32 & 0x3ff));
01293       the_insn.reloc = BFD_RELOC_NONE;
01294       output_insn (insn, &the_insn);
01295     }
01296 
01297   /* If we needed to build both upper and lower parts, OR them together.  */
01298   else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
01299     {
01300       the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
01301                       | RD (dstreg));
01302       the_insn.reloc = BFD_RELOC_NONE;
01303       output_insn (insn, &the_insn);
01304     }
01305 }
01306 
01307 /* Main entry point to assemble one instruction.  */
01308 
01309 void
01310 md_assemble (str)
01311      char *str;
01312 {
01313   const struct sparc_opcode *insn;
01314   int special_case;
01315 
01316   know (str);
01317   special_case = sparc_ip (str, &insn);
01318   if (insn == NULL)
01319     return;
01320 
01321   /* We warn about attempts to put a floating point branch in a delay slot,
01322      unless the delay slot has been annulled.  */
01323   if (last_insn != NULL
01324       && (insn->flags & F_FBR) != 0
01325       && (last_insn->flags & F_DELAYED) != 0
01326       /* ??? This test isn't completely accurate.  We assume anything with
01327         F_{UNBR,CONDBR,FBR} set is annullable.  */
01328       && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
01329          || (last_opcode & ANNUL) == 0))
01330     as_warn (_("FP branch in delay slot"));
01331 
01332   /* SPARC before v9 requires a nop instruction between a floating
01333      point instruction and a floating point branch.  We insert one
01334      automatically, with a warning.  */
01335   if (max_architecture < SPARC_OPCODE_ARCH_V9
01336       && last_insn != NULL
01337       && (insn->flags & F_FBR) != 0
01338       && (last_insn->flags & F_FLOAT) != 0)
01339     {
01340       struct sparc_it nop_insn;
01341 
01342       nop_insn.opcode = NOP_INSN;
01343       nop_insn.reloc = BFD_RELOC_NONE;
01344       output_insn (insn, &nop_insn);
01345       as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
01346     }
01347 
01348   switch (special_case)
01349     {
01350     case SPECIAL_CASE_NONE:
01351       /* Normal insn.  */
01352       output_insn (insn, &the_insn);
01353       break;
01354 
01355     case SPECIAL_CASE_SETSW:
01356       synthetize_setsw (insn);
01357       break;
01358 
01359     case SPECIAL_CASE_SET:
01360       synthetize_setuw (insn);
01361       break;
01362 
01363     case SPECIAL_CASE_SETX:
01364       synthetize_setx (insn);
01365       break;
01366 
01367     case SPECIAL_CASE_FDIV:
01368       {
01369        int rd = (the_insn.opcode >> 25) & 0x1f;
01370 
01371        output_insn (insn, &the_insn);
01372 
01373        /* According to information leaked from Sun, the "fdiv" instructions
01374           on early SPARC machines would produce incorrect results sometimes.
01375           The workaround is to add an fmovs of the destination register to
01376           itself just after the instruction.  This was true on machines
01377           with Weitek 1165 float chips, such as the Sun-4/260 and /280.  */
01378        assert (the_insn.reloc == BFD_RELOC_NONE);
01379        the_insn.opcode = FMOVS_INSN | rd | RD (rd);
01380        output_insn (insn, &the_insn);
01381        return;
01382       }
01383 
01384     default:
01385       as_fatal (_("failed special case insn sanity check"));
01386     }
01387 }
01388 
01389 /* Subroutine of md_assemble to do the actual parsing.  */
01390 
01391 static int
01392 sparc_ip (str, pinsn)
01393      char *str;
01394      const struct sparc_opcode **pinsn;
01395 {
01396   char *error_message = "";
01397   char *s;
01398   const char *args;
01399   char c;
01400   const struct sparc_opcode *insn;
01401   char *argsStart;
01402   unsigned long opcode;
01403   unsigned int mask = 0;
01404   int match = 0;
01405   int comma = 0;
01406   int v9_arg_p;
01407   int special_case = SPECIAL_CASE_NONE;
01408 
01409   s = str;
01410   if (ISLOWER (*s))
01411     {
01412       do
01413        ++s;
01414       while (ISLOWER (*s) || ISDIGIT (*s));
01415     }
01416 
01417   switch (*s)
01418     {
01419     case '\0':
01420       break;
01421 
01422     case ',':
01423       comma = 1;
01424       /* Fall through.  */
01425 
01426     case ' ':
01427       *s++ = '\0';
01428       break;
01429 
01430     default:
01431       as_bad (_("Unknown opcode: `%s'"), str);
01432       *pinsn = NULL;
01433       return special_case;
01434     }
01435   insn = (struct sparc_opcode *) hash_find (op_hash, str);
01436   *pinsn = insn;
01437   if (insn == NULL)
01438     {
01439       as_bad (_("Unknown opcode: `%s'"), str);
01440       return special_case;
01441     }
01442   if (comma)
01443     {
01444       *--s = ',';
01445     }
01446 
01447   argsStart = s;
01448   for (;;)
01449     {
01450       opcode = insn->match;
01451       memset (&the_insn, '\0', sizeof (the_insn));
01452       the_insn.reloc = BFD_RELOC_NONE;
01453       v9_arg_p = 0;
01454 
01455       /* Build the opcode, checking as we go to make sure that the
01456          operands match.  */
01457       for (args = insn->args;; ++args)
01458        {
01459          switch (*args)
01460            {
01461            case 'K':
01462              {
01463               int kmask = 0;
01464 
01465               /* Parse a series of masks.  */
01466               if (*s == '#')
01467                 {
01468                   while (*s == '#')
01469                     {
01470                      int mask;
01471 
01472                      if (! parse_keyword_arg (sparc_encode_membar, &s,
01473                                            &mask))
01474                        {
01475                          error_message = _(": invalid membar mask name");
01476                          goto error;
01477                        }
01478                      kmask |= mask;
01479                      while (*s == ' ')
01480                        ++s;
01481                      if (*s == '|' || *s == '+')
01482                        ++s;
01483                      while (*s == ' ')
01484                        ++s;
01485                     }
01486                 }
01487               else
01488                 {
01489                   if (! parse_const_expr_arg (&s, &kmask))
01490                     {
01491                      error_message = _(": invalid membar mask expression");
01492                      goto error;
01493                     }
01494                   if (kmask < 0 || kmask > 127)
01495                     {
01496                      error_message = _(": invalid membar mask number");
01497                      goto error;
01498                     }
01499                 }
01500 
01501               opcode |= MEMBAR (kmask);
01502               continue;
01503              }
01504 
01505            case '3':
01506              {
01507               int smask = 0;
01508 
01509               if (! parse_const_expr_arg (&s, &smask))
01510                 {
01511                   error_message = _(": invalid siam mode expression");
01512                   goto error;
01513                 }
01514               if (smask < 0 || smask > 7)
01515                 {
01516                   error_message = _(": invalid siam mode number");
01517                   goto error;
01518                 }
01519               opcode |= smask;
01520               continue;
01521              }
01522 
01523            case '*':
01524              {
01525               int fcn = 0;
01526 
01527               /* Parse a prefetch function.  */
01528               if (*s == '#')
01529                 {
01530                   if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
01531                     {
01532                      error_message = _(": invalid prefetch function name");
01533                      goto error;
01534                     }
01535                 }
01536               else
01537                 {
01538                   if (! parse_const_expr_arg (&s, &fcn))
01539                     {
01540                      error_message = _(": invalid prefetch function expression");
01541                      goto error;
01542                     }
01543                   if (fcn < 0 || fcn > 31)
01544                     {
01545                      error_message = _(": invalid prefetch function number");
01546                      goto error;
01547                     }
01548                 }
01549               opcode |= RD (fcn);
01550               continue;
01551              }
01552 
01553            case '!':
01554            case '?':
01555              /* Parse a sparc64 privileged register.  */
01556              if (*s == '%')
01557               {
01558                 struct priv_reg_entry *p = priv_reg_table;
01559                 unsigned int len = 9999999; /* Init to make gcc happy.  */
01560 
01561                 s += 1;
01562                 while (p->name[0] > s[0])
01563                   p++;
01564                 while (p->name[0] == s[0])
01565                   {
01566                     len = strlen (p->name);
01567                     if (strncmp (p->name, s, len) == 0)
01568                      break;
01569                     p++;
01570                   }
01571                 if (p->name[0] != s[0])
01572                   {
01573                     error_message = _(": unrecognizable privileged register");
01574                     goto error;
01575                   }
01576                 if (*args == '?')
01577                   opcode |= (p->regnum << 14);
01578                 else
01579                   opcode |= (p->regnum << 25);
01580                 s += len;
01581                 continue;
01582               }
01583              else
01584               {
01585                 error_message = _(": unrecognizable privileged register");
01586                 goto error;
01587               }
01588 
01589            case '$':
01590            case '%':
01591              /* Parse a sparc64 hyperprivileged register.  */
01592              if (*s == '%')
01593               {
01594                 struct priv_reg_entry *p = hpriv_reg_table;
01595                 unsigned int len = 9999999; /* Init to make gcc happy.  */
01596 
01597                 s += 1;
01598                 while (p->name[0] > s[0])
01599                   p++;
01600                 while (p->name[0] == s[0])
01601                   {
01602                     len = strlen (p->name);
01603                     if (strncmp (p->name, s, len) == 0)
01604                      break;
01605                     p++;
01606                   }
01607                 if (p->name[0] != s[0])
01608                   {
01609                     error_message = _(": unrecognizable hyperprivileged register");
01610                     goto error;
01611                   }
01612                 if (*args == '$')
01613                   opcode |= (p->regnum << 14);
01614                 else
01615                   opcode |= (p->regnum << 25);
01616                 s += len;
01617                 continue;
01618               }
01619              else
01620               {
01621                 error_message = _(": unrecognizable hyperprivileged register");
01622                 goto error;
01623               }
01624 
01625            case '_':
01626            case '/':
01627              /* Parse a v9a/v9b ancillary state register.  */
01628              if (*s == '%')
01629               {
01630                 struct priv_reg_entry *p = v9a_asr_table;
01631                 unsigned int len = 9999999; /* Init to make gcc happy.  */
01632 
01633                 s += 1;
01634                 while (p->name[0] > s[0])
01635                   p++;
01636                 while (p->name[0] == s[0])
01637                   {
01638                     len = strlen (p->name);
01639                     if (strncmp (p->name, s, len) == 0)
01640                      break;
01641                     p++;
01642                   }
01643                 if (p->name[0] != s[0])
01644                   {
01645                     error_message = _(": unrecognizable v9a or v9b ancillary state register");
01646                     goto error;
01647                   }
01648                 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
01649                   {
01650                     error_message = _(": rd on write only ancillary state register");
01651                     goto error;
01652                   }
01653                 if (p->regnum >= 24
01654                     && (insn->architecture
01655                        & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
01656                   {
01657                     /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
01658                     error_message = _(": unrecognizable v9a ancillary state register");
01659                     goto error;
01660                   }
01661                 if (*args == '/')
01662                   opcode |= (p->regnum << 14);
01663                 else
01664                   opcode |= (p->regnum << 25);
01665                 s += len;
01666                 continue;
01667               }
01668              else
01669               {
01670                 error_message = _(": unrecognizable v9a or v9b ancillary state register");
01671                 goto error;
01672               }
01673 
01674            case 'M':
01675            case 'm':
01676              if (strncmp (s, "%asr", 4) == 0)
01677               {
01678                 s += 4;
01679 
01680                 if (ISDIGIT (*s))
01681                   {
01682                     long num = 0;
01683 
01684                     while (ISDIGIT (*s))
01685                      {
01686                        num = num * 10 + *s - '0';
01687                        ++s;
01688                      }
01689 
01690                     if (current_architecture >= SPARC_OPCODE_ARCH_V9)
01691                      {
01692                        if (num < 16 || 31 < num)
01693                          {
01694                            error_message = _(": asr number must be between 16 and 31");
01695                            goto error;
01696                          }
01697                      }
01698                     else
01699                      {
01700                        if (num < 0 || 31 < num)
01701                          {
01702                            error_message = _(": asr number must be between 0 and 31");
01703                            goto error;
01704                          }
01705                      }
01706 
01707                     opcode |= (*args == 'M' ? RS1 (num) : RD (num));
01708                     continue;
01709                   }
01710                 else
01711                   {
01712                     error_message = _(": expecting %asrN");
01713                     goto error;
01714                   }
01715               } /* if %asr  */
01716              break;
01717 
01718            case 'I':
01719              the_insn.reloc = BFD_RELOC_SPARC_11;
01720              goto immediate;
01721 
01722            case 'j':
01723              the_insn.reloc = BFD_RELOC_SPARC_10;
01724              goto immediate;
01725 
01726            case 'X':
01727              /* V8 systems don't understand BFD_RELOC_SPARC_5.  */
01728              if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
01729               the_insn.reloc = BFD_RELOC_SPARC_5;
01730              else
01731               the_insn.reloc = BFD_RELOC_SPARC13;
01732              /* These fields are unsigned, but for upward compatibility,
01733                allow negative values as well.  */
01734              goto immediate;
01735 
01736            case 'Y':
01737              /* V8 systems don't understand BFD_RELOC_SPARC_6.  */
01738              if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
01739               the_insn.reloc = BFD_RELOC_SPARC_6;
01740              else
01741               the_insn.reloc = BFD_RELOC_SPARC13;
01742              /* These fields are unsigned, but for upward compatibility,
01743                allow negative values as well.  */
01744              goto immediate;
01745 
01746            case 'k':
01747              the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
01748              the_insn.pcrel = 1;
01749              goto immediate;
01750 
01751            case 'G':
01752              the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
01753              the_insn.pcrel = 1;
01754              goto immediate;
01755 
01756            case 'N':
01757              if (*s == 'p' && s[1] == 'n')
01758               {
01759                 s += 2;
01760                 continue;
01761               }
01762              break;
01763 
01764            case 'T':
01765              if (*s == 'p' && s[1] == 't')
01766               {
01767                 s += 2;
01768                 continue;
01769               }
01770              break;
01771 
01772            case 'z':
01773              if (*s == ' ')
01774               {
01775                 ++s;
01776               }
01777              if (strncmp (s, "%icc", 4) == 0)
01778               {
01779                 s += 4;
01780                 continue;
01781               }
01782              break;
01783 
01784            case 'Z':
01785              if (*s == ' ')
01786               {
01787                 ++s;
01788               }
01789              if (strncmp (s, "%xcc", 4) == 0)
01790               {
01791                 s += 4;
01792                 continue;
01793               }
01794              break;
01795 
01796            case '6':
01797              if (*s == ' ')
01798               {
01799                 ++s;
01800               }
01801              if (strncmp (s, "%fcc0", 5) == 0)
01802               {
01803                 s += 5;
01804                 continue;
01805               }
01806              break;
01807 
01808            case '7':
01809              if (*s == ' ')
01810               {
01811                 ++s;
01812               }
01813              if (strncmp (s, "%fcc1", 5) == 0)
01814               {
01815                 s += 5;
01816                 continue;
01817               }
01818              break;
01819 
01820            case '8':
01821              if (*s == ' ')
01822               {
01823                 ++s;
01824               }
01825              if (strncmp (s, "%fcc2", 5) == 0)
01826               {
01827                 s += 5;
01828                 continue;
01829               }
01830              break;
01831 
01832            case '9':
01833              if (*s == ' ')
01834               {
01835                 ++s;
01836               }
01837              if (strncmp (s, "%fcc3", 5) == 0)
01838               {
01839                 s += 5;
01840                 continue;
01841               }
01842              break;
01843 
01844            case 'P':
01845              if (strncmp (s, "%pc", 3) == 0)
01846               {
01847                 s += 3;
01848                 continue;
01849               }
01850              break;
01851 
01852            case 'W':
01853              if (strncmp (s, "%tick", 5) == 0)
01854               {
01855                 s += 5;
01856                 continue;
01857               }
01858              break;
01859 
01860            case '\0':              /* End of args.  */
01861              if (s[0] == ',' && s[1] == '%')
01862               {
01863                 static const struct tls_ops {
01864                   /* The name as it appears in assembler.  */
01865                   char *name;
01866                   /* strlen (name), precomputed for speed */
01867                   int len;
01868                   /* The reloc this pseudo-op translates to.  */
01869                   int reloc;
01870                   /* 1 if call.  */
01871                   int call;
01872                 } tls_ops[] = {
01873                   { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
01874                   { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
01875                   { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
01876                   { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
01877                   { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
01878                   { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
01879                   { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
01880                   { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }
01881                 };
01882                 const struct tls_ops *o;
01883                 char *s1;
01884                 int npar = 0;
01885 
01886                 for (o = tls_ops; o->name; o++)
01887                   if (strncmp (s + 2, o->name, o->len) == 0)
01888                     break;
01889                 if (o->name == NULL)
01890                   break;
01891 
01892                 if (s[o->len + 2] != '(')
01893                   {
01894                     as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
01895                     return special_case;
01896                   }
01897 
01898                 if (! o->call && the_insn.reloc != BFD_RELOC_NONE)
01899                   {
01900                     as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
01901                            o->name);
01902                     return special_case;
01903                   }
01904 
01905                 if (o->call
01906                     && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
01907                        || the_insn.exp.X_add_number != 0
01908                        || the_insn.exp.X_add_symbol
01909                           != symbol_find_or_make ("__tls_get_addr")))
01910                   {
01911                     as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
01912                            o->name);
01913                     return special_case;
01914                   }
01915 
01916                 the_insn.reloc = o->reloc;
01917                 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
01918                 s += o->len + 3;
01919 
01920                 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
01921                   if (*s1 == '(')
01922                     npar++;
01923                   else if (*s1 == ')')
01924                     {
01925                      if (!npar)
01926                        break;
01927                      npar--;
01928                     }
01929 
01930                 if (*s1 != ')')
01931                   {
01932                     as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
01933                     return special_case;
01934                   }
01935 
01936                 *s1 = '\0';
01937                 (void) get_expression (s);
01938                 *s1 = ')';
01939                 s = s1 + 1;
01940               }
01941              if (*s == '\0')
01942               match = 1;
01943              break;
01944 
01945            case '+':
01946              if (*s == '+')
01947               {
01948                 ++s;
01949                 continue;
01950               }
01951              if (*s == '-')
01952               {
01953                 continue;
01954               }
01955              break;
01956 
01957            case '[':        /* These must match exactly.  */
01958            case ']':
01959            case ',':
01960            case ' ':
01961              if (*s++ == *args)
01962               continue;
01963              break;
01964 
01965            case '#':        /* Must be at least one digit.  */
01966              if (ISDIGIT (*s++))
01967               {
01968                 while (ISDIGIT (*s))
01969                   {
01970                     ++s;
01971                   }
01972                 continue;
01973               }
01974              break;
01975 
01976            case 'C':        /* Coprocessor state register.  */
01977              if (strncmp (s, "%csr", 4) == 0)
01978               {
01979                 s += 4;
01980                 continue;
01981               }
01982              break;
01983 
01984            case 'b':        /* Next operand is a coprocessor register.  */
01985            case 'c':
01986            case 'D':
01987              if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
01988               {
01989                 mask = *s++;
01990                 if (ISDIGIT (*s))
01991                   {
01992                     mask = 10 * (mask - '0') + (*s++ - '0');
01993                     if (mask >= 32)
01994                      {
01995                        break;
01996                      }
01997                   }
01998                 else
01999                   {
02000                     mask -= '0';
02001                   }
02002                 switch (*args)
02003                   {
02004 
02005                   case 'b':
02006                     opcode |= mask << 14;
02007                     continue;
02008 
02009                   case 'c':
02010                     opcode |= mask;
02011                     continue;
02012 
02013                   case 'D':
02014                     opcode |= mask << 25;
02015                     continue;
02016                   }
02017               }
02018              break;
02019 
02020            case 'r':        /* next operand must be a register */
02021            case 'O':
02022            case '1':
02023            case '2':
02024            case 'd':
02025              if (*s++ == '%')
02026               {
02027                 switch (c = *s++)
02028                   {
02029 
02030                   case 'f': /* frame pointer */
02031                     if (*s++ == 'p')
02032                      {
02033                        mask = 0x1e;
02034                        break;
02035                      }
02036                     goto error;
02037 
02038                   case 'g': /* global register */
02039                     c = *s++;
02040                     if (isoctal (c))
02041                      {
02042                        mask = c - '0';
02043                        break;
02044                      }
02045                     goto error;
02046 
02047                   case 'i': /* in register */
02048                     c = *s++;
02049                     if (isoctal (c))
02050                      {
02051                        mask = c - '0' + 24;
02052                        break;
02053                      }
02054                     goto error;
02055 
02056                   case 'l': /* local register */
02057                     c = *s++;
02058                     if (isoctal (c))
02059                      {
02060                        mask = (c - '0' + 16);
02061                        break;
02062                      }
02063                     goto error;
02064 
02065                   case 'o': /* out register */
02066                     c = *s++;
02067                     if (isoctal (c))
02068                      {
02069                        mask = (c - '0' + 8);
02070                        break;
02071                      }
02072                     goto error;
02073 
02074                   case 's': /* stack pointer */
02075                     if (*s++ == 'p')
02076                      {
02077                        mask = 0xe;
02078                        break;
02079                      }
02080                     goto error;
02081 
02082                   case 'r': /* any register */
02083                     if (!ISDIGIT ((c = *s++)))
02084                      {
02085                        goto error;
02086                      }
02087                     /* FALLTHROUGH */
02088                   case '0':
02089                   case '1':
02090                   case '2':
02091                   case '3':
02092                   case '4':
02093                   case '5':
02094                   case '6':
02095                   case '7':
02096                   case '8':
02097                   case '9':
02098                     if (ISDIGIT (*s))
02099                      {
02100                        if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
02101                          {
02102                            goto error;
02103                          }
02104                      }
02105                     else
02106                      {
02107                        c -= '0';
02108                      }
02109                     mask = c;
02110                     break;
02111 
02112                   default:
02113                     goto error;
02114                   }
02115 
02116                 if ((mask & ~1) == 2 && sparc_arch_size == 64
02117                     && no_undeclared_regs && ! globals[mask])
02118                   as_bad (_("detected global register use not covered by .register pseudo-op"));
02119 
02120                 /* Got the register, now figure out where
02121                    it goes in the opcode.  */
02122                 switch (*args)
02123                   {
02124                   case '1':
02125                     opcode |= mask << 14;
02126                     continue;
02127 
02128                   case '2':
02129                     opcode |= mask;
02130                     continue;
02131 
02132                   case 'd':
02133                     opcode |= mask << 25;
02134                     continue;
02135 
02136                   case 'r':
02137                     opcode |= (mask << 25) | (mask << 14);
02138                     continue;
02139 
02140                   case 'O':
02141                     opcode |= (mask << 25) | (mask << 0);
02142                     continue;
02143                   }
02144               }
02145              break;
02146 
02147            case 'e':        /* next operand is a floating point register */
02148            case 'v':
02149            case 'V':
02150 
02151            case 'f':
02152            case 'B':
02153            case 'R':
02154 
02155            case 'g':
02156            case 'H':
02157            case 'J':
02158              {
02159               char format;
02160 
02161               if (*s++ == '%'
02162                   && ((format = *s) == 'f')
02163                   && ISDIGIT (*++s))
02164                 {
02165                   for (mask = 0; ISDIGIT (*s); ++s)
02166                     {
02167                      mask = 10 * mask + (*s - '0');
02168                     }              /* read the number */
02169 
02170                   if ((*args == 'v'
02171                       || *args == 'B'
02172                       || *args == 'H')
02173                      && (mask & 1))
02174                     {
02175                      break;
02176                     }              /* register must be even numbered */
02177 
02178                   if ((*args == 'V'
02179                       || *args == 'R'
02180                       || *args == 'J')
02181                      && (mask & 3))
02182                     {
02183                      break;
02184                     }              /* register must be multiple of 4 */
02185 
02186                   if (mask >= 64)
02187                     {
02188                      if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
02189                        error_message = _(": There are only 64 f registers; [0-63]");
02190                      else
02191                        error_message = _(": There are only 32 f registers; [0-31]");
02192                      goto error;
02193                     }       /* on error */
02194                   else if (mask >= 32)
02195                     {
02196                      if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
02197                        {
02198                          if (*args == 'e' || *args == 'f' || *args == 'g')
02199                            {
02200                             error_message
02201                               = _(": There are only 32 single precision f registers; [0-31]");
02202                             goto error;
02203                            }
02204                          v9_arg_p = 1;
02205                          mask -= 31;      /* wrap high bit */
02206                        }
02207                      else
02208                        {
02209                          error_message = _(": There are only 32 f registers; [0-31]");
02210                          goto error;
02211                        }
02212                     }
02213                 }
02214               else
02215                 {
02216                   break;
02217                 }    /* if not an 'f' register.  */
02218 
02219               switch (*args)
02220                 {
02221                 case 'v':
02222                 case 'V':
02223                 case 'e':
02224                   opcode |= RS1 (mask);
02225                   continue;
02226 
02227                 case 'f':
02228                 case 'B':
02229                 case 'R':
02230                   opcode |= RS2 (mask);
02231                   continue;
02232 
02233                 case 'g':
02234                 case 'H':
02235                 case 'J':
02236                   opcode |= RD (mask);
02237                   continue;
02238                 }           /* Pack it in.  */
02239 
02240               know (0);
02241               break;
02242              }                     /* float arg  */
02243 
02244            case 'F':
02245              if (strncmp (s, "%fsr", 4) == 0)
02246               {
02247                 s += 4;
02248                 continue;
02249               }
02250              break;
02251 
02252            case '0':        /* 64 bit immediate (set, setsw, setx insn)  */
02253              the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere  */
02254              goto immediate;
02255 
02256            case 'l':        /* 22 bit PC relative immediate  */
02257              the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
02258              the_insn.pcrel = 1;
02259              goto immediate;
02260 
02261            case 'L':        /* 30 bit immediate  */
02262              the_insn.reloc = BFD_RELOC_32_PCREL_S2;
02263              the_insn.pcrel = 1;
02264              goto immediate;
02265 
02266            case 'h':
02267            case 'n':        /* 22 bit immediate  */
02268              the_insn.reloc = BFD_RELOC_SPARC22;
02269              goto immediate;
02270 
02271            case 'i':        /* 13 bit immediate  */
02272              the_insn.reloc = BFD_RELOC_SPARC13;
02273 
02274              /* fallthrough */
02275 
02276            immediate:
02277              if (*s == ' ')
02278               s++;
02279 
02280              {
02281               char *s1;
02282               char *op_arg = NULL;
02283               static expressionS op_exp;
02284               bfd_reloc_code_real_type old_reloc = the_insn.reloc;
02285 
02286               /* Check for %hi, etc.  */
02287               if (*s == '%')
02288                 {
02289                   static const struct ops {
02290                     /* The name as it appears in assembler.  */
02291                     char *name;
02292                     /* strlen (name), precomputed for speed */
02293                     int len;
02294                     /* The reloc this pseudo-op translates to.  */
02295                     int reloc;
02296                     /* Non-zero if for v9 only.  */
02297                     int v9_p;
02298                     /* Non-zero if can be used in pc-relative contexts.  */
02299                     int pcrel_p;/*FIXME:wip*/
02300                   } ops[] = {
02301                     /* hix/lox must appear before hi/lo so %hix won't be
02302                       mistaken for %hi.  */
02303                     { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
02304                     { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
02305                     { "hi", 2, BFD_RELOC_HI22, 0, 1 },
02306                     { "lo", 2, BFD_RELOC_LO10, 0, 1 },
02307                     { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
02308                     { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
02309                     { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
02310                     { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
02311                     { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
02312                     { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
02313                     { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
02314                     { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
02315                     { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
02316                     { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
02317                     { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
02318                     { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
02319                     { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
02320                                                                 0 },
02321                     { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
02322                                                                 0 },
02323                     { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
02324                     { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
02325                     { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
02326                     { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
02327                     { NULL, 0, 0, 0, 0 }
02328                   };
02329                   const struct ops *o;
02330 
02331                   for (o = ops; o->name; o++)
02332                     if (strncmp (s + 1, o->name, o->len) == 0)
02333                      break;
02334                   if (o->name == NULL)
02335                     break;
02336 
02337                   if (s[o->len + 1] != '(')
02338                     {
02339                      as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
02340                      return special_case;
02341                     }
02342 
02343                   op_arg = o->name;
02344                   the_insn.reloc = o->reloc;
02345                   s += o->len + 2;
02346                   v9_arg_p = o->v9_p;
02347                 }
02348 
02349               /* Note that if the get_expression() fails, we will still
02350                  have created U entries in the symbol table for the
02351                  'symbols' in the input string.  Try not to create U
02352                  symbols for registers, etc.  */
02353 
02354               /* This stuff checks to see if the expression ends in
02355                  +%reg.  If it does, it removes the register from
02356                  the expression, and re-sets 's' to point to the
02357                  right place.  */
02358 
02359               if (op_arg)
02360                 {
02361                   int npar = 0;
02362 
02363                   for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
02364                     if (*s1 == '(')
02365                      npar++;
02366                     else if (*s1 == ')')
02367                      {
02368                        if (!npar)
02369                          break;
02370                        npar--;
02371                      }
02372 
02373                   if (*s1 != ')')
02374                     {
02375                      as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
02376                      return special_case;
02377                     }
02378 
02379                   *s1 = '\0';
02380                   (void) get_expression (s);
02381                   *s1 = ')';
02382                   s = s1 + 1;
02383                   if (*s == ',' || *s == ']' || !*s)
02384                     continue;
02385                   if (*s != '+' && *s != '-')
02386                     {
02387                      as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
02388                      return special_case;
02389                     }
02390                   *s1 = '0';
02391                   s = s1;
02392                   op_exp = the_insn.exp;
02393                   memset (&the_insn.exp, 0, sizeof (the_insn.exp));
02394                 }
02395 
02396               for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
02397                 ;
02398 
02399               if (s1 != s && ISDIGIT (s1[-1]))
02400                 {
02401                   if (s1[-2] == '%' && s1[-3] == '+')
02402                     s1 -= 3;
02403                   else if (strchr ("goli0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
02404                     s1 -= 4;
02405                   else
02406                     s1 = NULL;
02407                   if (s1)
02408                     {
02409                      *s1 = '\0';
02410                      if (op_arg && s1 == s + 1)
02411                        the_insn.exp.X_op = O_absent;
02412                      else
02413                        (void) get_expression (s);
02414                      *s1 = '+';
02415                      if (op_arg)
02416                        *s = ')';
02417                      s = s1;
02418                     }
02419                 }
02420               else
02421                 s1 = NULL;
02422 
02423               if (!s1)
02424                 {
02425                   (void) get_expression (s);
02426                   if (op_arg)
02427                     *s = ')';
02428                   s = expr_end;
02429                 }
02430 
02431               if (op_arg)
02432                 {
02433                   the_insn.exp2 = the_insn.exp;
02434                   the_insn.exp = op_exp;
02435                   if (the_insn.exp2.X_op == O_absent)
02436                     the_insn.exp2.X_op = O_illegal;
02437                   else if (the_insn.exp.X_op == O_absent)
02438                     {
02439                      the_insn.exp = the_insn.exp2;
02440                      the_insn.exp2.X_op = O_illegal;
02441                     }
02442                   else if (the_insn.exp.X_op == O_constant)
02443                     {
02444                      valueT val = the_insn.exp.X_add_number;
02445                      switch (the_insn.reloc)
02446                        {
02447                        default:
02448                          break;
02449 
02450                        case BFD_RELOC_SPARC_HH22:
02451                          val = BSR (val, 32);
02452                          /* Fall through.  */
02453 
02454                        case BFD_RELOC_SPARC_LM22:
02455                        case BFD_RELOC_HI22:
02456                          val = (val >> 10) & 0x3fffff;
02457                          break;
02458 
02459                        case BFD_RELOC_SPARC_HM10:
02460                          val = BSR (val, 32);
02461                          /* Fall through.  */
02462 
02463                        case BFD_RELOC_LO10:
02464                          val &= 0x3ff;
02465                          break;
02466 
02467                        case BFD_RELOC_SPARC_H44:
02468                          val >>= 22;
02469                          val &= 0x3fffff;
02470                          break;
02471 
02472                        case BFD_RELOC_SPARC_M44:
02473                          val >>= 12;
02474                          val &= 0x3ff;
02475                          break;
02476 
02477                        case BFD_RELOC_SPARC_L44:
02478                          val &= 0xfff;
02479                          break;
02480 
02481                        case BFD_RELOC_SPARC_HIX22:
02482                          val = ~val;
02483                          val = (val >> 10) & 0x3fffff;
02484                          break;
02485 
02486                        case BFD_RELOC_SPARC_LOX10:
02487                          val = (val & 0x3ff) | 0x1c00;
02488                          break;
02489                        }
02490                      the_insn.exp = the_insn.exp2;
02491                      the_insn.exp.X_add_number += val;
02492                      the_insn.exp2.X_op = O_illegal;
02493                      the_insn.reloc = old_reloc;
02494                     }
02495                   else if (the_insn.exp2.X_op != O_constant)
02496                     {
02497                      as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
02498                      return special_case;
02499                     }
02500                   else
02501                     {
02502                      if (old_reloc != BFD_RELOC_SPARC13
02503                          || the_insn.reloc != BFD_RELOC_LO10
02504                          || sparc_arch_size != 64
02505                          || sparc_pic_code)
02506                        {
02507                          as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
02508                          return special_case;
02509                        }
02510                      the_insn.reloc = BFD_RELOC_SPARC_OLO10;
02511                     }
02512                 }
02513              }
02514              /* Check for constants that don't require emitting a reloc.  */
02515              if (the_insn.exp.X_op == O_constant
02516                 && the_insn.exp.X_add_symbol == 0
02517                 && the_insn.exp.X_op_symbol == 0)
02518               {
02519                 /* For pc-relative call instructions, we reject
02520                    constants to get better code.  */
02521                 if (the_insn.pcrel
02522                     && the_insn.reloc == BFD_RELOC_32_PCREL_S2
02523                     && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
02524                   {
02525                     error_message = _(": PC-relative operand can't be a constant");
02526                     goto error;
02527                   }
02528 
02529                 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
02530                     && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
02531                   {
02532                     error_message = _(": TLS operand can't be a constant");
02533                     goto error;
02534                   }
02535 
02536                 /* Constants that won't fit are checked in md_apply_fix
02537                    and bfd_install_relocation.
02538                    ??? It would be preferable to install the constants
02539                    into the insn here and save having to create a fixS
02540                    for each one.  There already exists code to handle
02541                    all the various cases (e.g. in md_apply_fix and
02542                    bfd_install_relocation) so duplicating all that code
02543                    here isn't right.  */
02544               }
02545 
02546              continue;
02547 
02548            case 'a':
02549              if (*s++ == 'a')
02550               {
02551                 opcode |= ANNUL;
02552                 continue;
02553               }
02554              break;
02555 
02556            case 'A':
02557              {
02558               int asi = 0;
02559 
02560               /* Parse an asi.  */
02561               if (*s == '#')
02562                 {
02563                   if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
02564                     {
02565                      error_message = _(": invalid ASI name");
02566                      goto error;
02567                     }
02568                 }
02569               else
02570                 {
02571                   if (! parse_const_expr_arg (&s, &asi))
02572                     {
02573                      error_message = _(": invalid ASI expression");
02574                      goto error;
02575                     }
02576                   if (asi < 0 || asi > 255)
02577                     {
02578                      error_message = _(": invalid ASI number");
02579                      goto error;
02580                     }
02581                 }
02582               opcode |= ASI (asi);
02583               continue;
02584              }                     /* Alternate space.  */
02585 
02586            case 'p':
02587              if (strncmp (s, "%psr", 4) == 0)
02588               {
02589                 s += 4;
02590                 continue;
02591               }
02592              break;
02593 
02594            case 'q':        /* Floating point queue.  */
02595              if (strncmp (s, "%fq", 3) == 0)
02596               {
02597                 s += 3;
02598                 continue;
02599               }
02600              break;
02601 
02602            case 'Q':        /* Coprocessor queue.  */
02603              if (strncmp (s, "%cq", 3) == 0)
02604               {
02605                 s += 3;
02606                 continue;
02607               }
02608              break;
02609 
02610            case 'S':
02611              if (strcmp (str, "set") == 0
02612                 || strcmp (str, "setuw") == 0)
02613               {
02614                 special_case = SPECIAL_CASE_SET;
02615                 continue;
02616               }
02617              else if (strcmp (str, "setsw") == 0)
02618               {
02619                 special_case = SPECIAL_CASE_SETSW;
02620                 continue;
02621               }
02622              else if (strcmp (str, "setx") == 0)
02623               {
02624                 special_case = SPECIAL_CASE_SETX;
02625                 continue;
02626               }
02627              else if (strncmp (str, "fdiv", 4) == 0)
02628               {
02629                 special_case = SPECIAL_CASE_FDIV;
02630                 continue;
02631               }
02632              break;
02633 
02634            case 'o':
02635              if (strncmp (s, "%asi", 4) != 0)
02636               break;
02637              s += 4;
02638              continue;
02639 
02640            case 's':
02641              if (strncmp (s, "%fprs", 5) != 0)
02642               break;
02643              s += 5;
02644              continue;
02645 
02646            case 'E':
02647              if (strncmp (s, "%ccr", 4) != 0)
02648               break;
02649              s += 4;
02650              continue;
02651 
02652            case 't':
02653              if (strncmp (s, "%tbr", 4) != 0)
02654               break;
02655              s += 4;
02656              continue;
02657 
02658            case 'w':
02659              if (strncmp (s, "%wim", 4) != 0)
02660               break;
02661              s += 4;
02662              continue;
02663 
02664            case 'x':
02665              {
02666               char *push = input_line_pointer;
02667               expressionS e;
02668 
02669               input_line_pointer = s;
02670               expression (&e);
02671               if (e.X_op == O_constant)
02672                 {
02673                   int n = e.X_add_number;
02674                   if (n != e.X_add_number || (n & ~0x1ff) != 0)
02675                     as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
02676                   else
02677                     opcode |= e.X_add_number << 5;
02678                 }
02679               else
02680                 as_bad (_("non-immediate OPF operand, ignored"));
02681               s = input_line_pointer;
02682               input_line_pointer = push;
02683               continue;
02684              }
02685 
02686            case 'y':
02687              if (strncmp (s, "%y", 2) != 0)
02688               break;
02689              s += 2;
02690              continue;
02691 
02692            case 'u':
02693            case 'U':
02694              {
02695               /* Parse a sparclet cpreg.  */
02696               int cpreg;
02697               if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
02698                 {
02699                   error_message = _(": invalid cpreg name");
02700                   goto error;
02701                 }
02702               opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
02703               continue;
02704              }
02705 
02706            default:
02707              as_fatal (_("failed sanity check."));
02708            }                /* switch on arg code.  */
02709 
02710          /* Break out of for() loop.  */
02711          break;
02712        }                    /* For each arg that we expect.  */
02713 
02714     error:
02715       if (match == 0)
02716        {
02717          /* Args don't match.  */
02718          if (&insn[1] - sparc_opcodes < sparc_num_opcodes
02719              && (insn->name == insn[1].name
02720                 || !strcmp (insn->name, insn[1].name)))
02721            {
02722              ++insn;
02723              s = argsStart;
02724              continue;
02725            }
02726          else
02727            {
02728              as_bad (_("Illegal operands%s"), error_message);
02729              return special_case;
02730            }
02731        }
02732       else
02733        {
02734          /* We have a match.  Now see if the architecture is OK.  */
02735          int needed_arch_mask = insn->architecture;
02736 
02737          if (v9_arg_p)
02738            {
02739              needed_arch_mask &=
02740               ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
02741              if (! needed_arch_mask)
02742               needed_arch_mask =
02743                 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
02744            }
02745 
02746          if (needed_arch_mask
02747              & SPARC_OPCODE_SUPPORTED (current_architecture))
02748            /* OK.  */
02749            ;
02750          /* Can we bump up the architecture?  */
02751          else if (needed_arch_mask
02752                  & SPARC_OPCODE_SUPPORTED (max_architecture))
02753            {
02754              enum sparc_opcode_arch_val needed_architecture =
02755               sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
02756                         & needed_arch_mask);
02757 
02758              assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
02759              if (warn_on_bump
02760                 && needed_architecture > warn_after_architecture)
02761               {
02762                 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
02763                         sparc_opcode_archs[current_architecture].name,
02764                         sparc_opcode_archs[needed_architecture].name,
02765                         str);
02766                 warn_after_architecture = needed_architecture;
02767               }
02768              current_architecture = needed_architecture;
02769            }
02770          /* Conflict.  */
02771          /* ??? This seems to be a bit fragile.  What if the next entry in
02772             the opcode table is the one we want and it is supported?
02773             It is possible to arrange the table today so that this can't
02774             happen but what about tomorrow?  */
02775          else
02776            {
02777              int arch, printed_one_p = 0;
02778              char *p;
02779              char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
02780 
02781              /* Create a list of the architectures that support the insn.  */
02782              needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
02783              p = required_archs;
02784              arch = sparc_ffs (needed_arch_mask);
02785              while ((1 << arch) <= needed_arch_mask)
02786               {
02787                 if ((1 << arch) & needed_arch_mask)
02788                   {
02789                     if (printed_one_p)
02790                      *p++ = '|';
02791                     strcpy (p, sparc_opcode_archs[arch].name);
02792                     p += strlen (p);
02793                     printed_one_p = 1;
02794                   }
02795                 ++arch;
02796               }
02797 
02798              as_bad (_("Architecture mismatch on \"%s\"."), str);
02799              as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
02800                       required_archs,
02801                       sparc_opcode_archs[max_architecture].name);
02802              return special_case;
02803            }
02804        } /* If no match.  */
02805 
02806       break;
02807     } /* Forever looking for a match.  */
02808 
02809   the_insn.opcode = opcode;
02810   return special_case;
02811 }
02812 
02813 /* Parse an argument that can be expressed as a keyword.
02814    (eg: #StoreStore or %ccfr).
02815    The result is a boolean indicating success.
02816    If successful, INPUT_POINTER is updated.  */
02817 
02818 static int
02819 parse_keyword_arg (lookup_fn, input_pointerP, valueP)
02820      int (*lookup_fn) PARAMS ((const char *));
02821      char **input_pointerP;
02822      int *valueP;
02823 {
02824   int value;
02825   char c, *p, *q;
02826 
02827   p = *input_pointerP;
02828   for (q = p + (*p == '#' || *p == '%');
02829        ISALNUM (*q) || *q == '_';
02830        ++q)
02831     continue;
02832   c = *q;
02833   *q = 0;
02834   value = (*lookup_fn) (p);
02835   *q = c;
02836   if (value == -1)
02837     return 0;
02838   *valueP = value;
02839   *input_pointerP = q;
02840   return 1;
02841 }
02842 
02843 /* Parse an argument that is a constant expression.
02844    The result is a boolean indicating success.  */
02845 
02846 static int
02847 parse_const_expr_arg (input_pointerP, valueP)
02848      char **input_pointerP;
02849      int *valueP;
02850 {
02851   char *save = input_line_pointer;
02852   expressionS exp;
02853 
02854   input_line_pointer = *input_pointerP;
02855   /* The next expression may be something other than a constant
02856      (say if we're not processing the right variant of the insn).
02857      Don't call expression unless we're sure it will succeed as it will
02858      signal an error (which we want to defer until later).  */
02859   /* FIXME: It might be better to define md_operand and have it recognize
02860      things like %asi, etc. but continuing that route through to the end
02861      is a lot of work.  */
02862   if (*input_line_pointer == '%')
02863     {
02864       input_line_pointer = save;
02865       return 0;
02866     }
02867   expression (&exp);
02868   *input_pointerP = input_line_pointer;
02869   input_line_pointer = save;
02870   if (exp.X_op != O_constant)
02871     return 0;
02872   *valueP = exp.X_add_number;
02873   return 1;
02874 }
02875 
02876 /* Subroutine of sparc_ip to parse an expression.  */
02877 
02878 static int
02879 get_expression (str)
02880      char *str;
02881 {
02882   char *save_in;
02883   segT seg;
02884 
02885   save_in = input_line_pointer;
02886   input_line_pointer = str;
02887   seg = expression (&the_insn.exp);
02888   if (seg != absolute_section
02889       && seg != text_section
02890       && seg != data_section
02891       && seg != bss_section
02892       && seg != undefined_section)
02893     {
02894       the_insn.error = _("bad segment");
02895       expr_end = input_line_pointer;
02896       input_line_pointer = save_in;
02897       return 1;
02898     }
02899   expr_end = input_line_pointer;
02900   input_line_pointer = save_in;
02901   return 0;
02902 }
02903 
02904 /* Subroutine of md_assemble to output one insn.  */
02905 
02906 static void
02907 output_insn (insn, the_insn)
02908      const struct sparc_opcode *insn;
02909      struct sparc_it *the_insn;
02910 {
02911   char *toP = frag_more (4);
02912 
02913   /* Put out the opcode.  */
02914   if (INSN_BIG_ENDIAN)
02915     number_to_chars_bigendian (toP, (valueT) the_insn->opcode, 4);
02916   else
02917     number_to_chars_littleendian (toP, (valueT) the_insn->opcode, 4);
02918 
02919   /* Put out the symbol-dependent stuff.  */
02920   if (the_insn->reloc != BFD_RELOC_NONE)
02921     {
02922       fixS *fixP =  fix_new_exp (frag_now,       /* Which frag.  */
02923                              (toP - frag_now->fr_literal),     /* Where.  */
02924                              4,           /* Size.  */
02925                              &the_insn->exp,
02926                              the_insn->pcrel,
02927                              the_insn->reloc);
02928       /* Turn off overflow checking in fixup_segment.  We'll do our
02929         own overflow checking in md_apply_fix.  This is necessary because
02930         the insn size is 4 and fixup_segment will signal an overflow for
02931         large 8 byte quantities.  */
02932       fixP->fx_no_overflow = 1;
02933       if (the_insn->reloc == BFD_RELOC_SPARC_OLO10)
02934        fixP->tc_fix_data = the_insn->exp2.X_add_number;
02935     }
02936 
02937   last_insn = insn;
02938   last_opcode = the_insn->opcode;
02939 
02940 #ifdef OBJ_ELF
02941   dwarf2_emit_insn (4);
02942 #endif
02943 }
02944 
02945 /* This is identical to the md_atof in m68k.c.  I think this is right,
02946    but I'm not sure.
02947 
02948    Turn a string in input_line_pointer into a floating point constant
02949    of type TYPE, and store the appropriate bytes in *LITP.  The number
02950    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
02951    returned, or NULL on OK.  */
02952 
02953 /* Equal to MAX_PRECISION in atof-ieee.c.  */
02954 #define MAX_LITTLENUMS 6
02955 
02956 char *
02957 md_atof (type, litP, sizeP)
02958      char type;
02959      char *litP;
02960      int *sizeP;
02961 {
02962   int i, prec;
02963   LITTLENUM_TYPE words[MAX_LITTLENUMS];
02964   char *t;
02965 
02966   switch (type)
02967     {
02968     case 'f':
02969     case 'F':
02970     case 's':
02971     case 'S':
02972       prec = 2;
02973       break;
02974 
02975     case 'd':
02976     case 'D':
02977     case 'r':
02978     case 'R':
02979       prec = 4;
02980       break;
02981 
02982     case 'x':
02983     case 'X':
02984       prec = 6;
02985       break;
02986 
02987     case 'p':
02988     case 'P':
02989       prec = 6;
02990       break;
02991 
02992     default:
02993       *sizeP = 0;
02994       return _("Bad call to MD_ATOF()");
02995     }
02996 
02997   t = atof_ieee (input_line_pointer, type, words);
02998   if (t)
02999     input_line_pointer = t;
03000   *sizeP = prec * sizeof (LITTLENUM_TYPE);
03001 
03002   if (target_big_endian)
03003     {
03004       for (i = 0; i < prec; i++)
03005        {
03006          md_number_to_chars (litP, (valueT) words[i],
03007                            sizeof (LITTLENUM_TYPE));
03008          litP += sizeof (LITTLENUM_TYPE);
03009        }
03010     }
03011   else
03012     {
03013       for (i = prec - 1; i >= 0; i--)
03014        {
03015          md_number_to_chars (litP, (valueT) words[i],
03016                            sizeof (LITTLENUM_TYPE));
03017          litP += sizeof (LITTLENUM_TYPE);
03018        }
03019     }
03020 
03021   return 0;
03022 }
03023 
03024 /* Write a value out to the object file, using the appropriate
03025    endianness.  */
03026 
03027 void
03028 md_number_to_chars (buf, val, n)
03029      char *buf;
03030      valueT val;
03031      int n;
03032 {
03033   if (target_big_endian)
03034     number_to_chars_bigendian (buf, val, n);
03035   else if (target_little_endian_data
03036           && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
03037     /* Output debug words, which are not in allocated sections, as big
03038        endian.  */
03039     number_to_chars_bigendian (buf, val, n);
03040   else if (target_little_endian_data || ! target_big_endian)
03041     number_to_chars_littleendian (buf, val, n);
03042 }
03043 
03044 /* Apply a fixS to the frags, now that we know the value it ought to
03045    hold.  */
03046 
03047 void
03048 md_apply_fix (fixP, valP, segment)
03049      fixS *fixP;
03050      valueT *valP;
03051      segT segment ATTRIBUTE_UNUSED;
03052 {
03053   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
03054   offsetT val = * (offsetT *) valP;
03055   long insn;
03056 
03057   assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
03058 
03059   fixP->fx_addnumber = val; /* Remember value for emit_reloc.  */
03060 
03061 #ifdef OBJ_ELF
03062   /* SPARC ELF relocations don't use an addend in the data field.  */
03063   if (fixP->fx_addsy != NULL)
03064     {
03065       switch (fixP->fx_r_type)
03066        {
03067        case BFD_RELOC_SPARC_TLS_GD_HI22:
03068        case BFD_RELOC_SPARC_TLS_GD_LO10:
03069        case BFD_RELOC_SPARC_TLS_GD_ADD:
03070        case BFD_RELOC_SPARC_TLS_GD_CALL:
03071        case BFD_RELOC_SPARC_TLS_LDM_HI22:
03072        case BFD_RELOC_SPARC_TLS_LDM_LO10:
03073        case BFD_RELOC_SPARC_TLS_LDM_ADD:
03074        case BFD_RELOC_SPARC_TLS_LDM_CALL:
03075        case BFD_RELOC_SPARC_TLS_LDO_HIX22:
03076        case BFD_RELOC_SPARC_TLS_LDO_LOX10:
03077        case BFD_RELOC_SPARC_TLS_LDO_ADD:
03078        case BFD_RELOC_SPARC_TLS_IE_HI22:
03079        case BFD_RELOC_SPARC_TLS_IE_LO10:
03080        case BFD_RELOC_SPARC_TLS_IE_LD:
03081        case BFD_RELOC_SPARC_TLS_IE_LDX:
03082        case BFD_RELOC_SPARC_TLS_IE_ADD:
03083        case BFD_RELOC_SPARC_TLS_LE_HIX22:
03084        case BFD_RELOC_SPARC_TLS_LE_LOX10:
03085        case BFD_RELOC_SPARC_TLS_DTPMOD32:
03086        case BFD_RELOC_SPARC_TLS_DTPMOD64:
03087        case BFD_RELOC_SPARC_TLS_DTPOFF32:
03088        case BFD_RELOC_SPARC_TLS_DTPOFF64:
03089        case BFD_RELOC_SPARC_TLS_TPOFF32:
03090        case BFD_RELOC_SPARC_TLS_TPOFF64:
03091          S_SET_THREAD_LOCAL (fixP->fx_addsy);
03092 
03093        default:
03094          break;
03095        }
03096 
03097       return;
03098     }
03099 #endif
03100 
03101   /* This is a hack.  There should be a better way to
03102      handle this.  Probably in terms of howto fields, once
03103      we can look at these fixups in terms of howtos.  */
03104   if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
03105     val += fixP->fx_where + fixP->fx_frag->fr_address;
03106 
03107 #ifdef OBJ_AOUT
03108   /* FIXME: More ridiculous gas reloc hacking.  If we are going to
03109      generate a reloc, then we just want to let the reloc addend set
03110      the value.  We do not want to also stuff the addend into the
03111      object file.  Including the addend in the object file works when
03112      doing a static link, because the linker will ignore the object
03113      file contents.  However, the dynamic linker does not ignore the
03114      object file contents.  */
03115   if (fixP->fx_addsy != NULL
03116       && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
03117     val = 0;
03118 
03119   /* When generating PIC code, we do not want an addend for a reloc
03120      against a local symbol.  We adjust fx_addnumber to cancel out the
03121      value already included in val, and to also cancel out the
03122      adjustment which bfd_install_relocation will create.  */
03123   if (sparc_pic_code
03124       && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
03125       && fixP->fx_addsy != NULL
03126       && ! S_IS_COMMON (fixP->fx_addsy)
03127       && symbol_section_p (fixP->fx_addsy))
03128     fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
03129 
03130   /* When generating PIC code, we need to fiddle to get
03131      bfd_install_relocation to do the right thing for a PC relative
03132      reloc against a local symbol which we are going to keep.  */
03133   if (sparc_pic_code
03134       && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
03135       && fixP->fx_addsy != NULL
03136       && (S_IS_EXTERNAL (fixP->fx_addsy)
03137          || S_IS_WEAK (fixP->fx_addsy))
03138       && S_IS_DEFINED (fixP->fx_addsy)
03139       && ! S_IS_COMMON (fixP->fx_addsy))
03140     {
03141       val = 0;
03142       fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
03143     }
03144 #endif
03145 
03146   /* If this is a data relocation, just output VAL.  */
03147 
03148   if (fixP->fx_r_type == BFD_RELOC_16
03149       || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
03150     {
03151       md_number_to_chars (buf, val, 2);
03152     }
03153   else if (fixP->fx_r_type == BFD_RELOC_32
03154           || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
03155           || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
03156     {
03157       md_number_to_chars (buf, val, 4);
03158     }
03159   else if (fixP->fx_r_type == BFD_RELOC_64
03160           || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
03161     {
03162       md_number_to_chars (buf, val, 8);
03163     }
03164   else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
03165            || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
03166     {
03167       fixP->fx_done = 0;
03168       return;
03169     }
03170   else
03171     {
03172       /* It's a relocation against an instruction.  */
03173 
03174       if (INSN_BIG_ENDIAN)
03175        insn = bfd_getb32 ((unsigned char *) buf);
03176       else
03177        insn = bfd_getl32 ((unsigned char *) buf);
03178 
03179       switch (fixP->fx_r_type)
03180        {
03181        case BFD_RELOC_32_PCREL_S2:
03182          val = val >> 2;
03183          /* FIXME: This increment-by-one deserves a comment of why it's
03184             being done!  */
03185          if (! sparc_pic_code
03186              || fixP->fx_addsy == NULL
03187              || symbol_section_p (fixP->fx_addsy))
03188            ++val;
03189 
03190          insn |= val & 0x3fffffff;
03191 
03192          /* See if we have a delay slot.  */
03193          if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
03194            {
03195 #define G0           0
03196 #define O7           15
03197 #define XCC          (2 << 20)
03198 #define COND(x)             (((x)&0xf)<<25)
03199 #define CONDA        COND(0x8)
03200 #define INSN_BPA     (F2(0,1) | CONDA | BPRED | XCC)
03201 #define INSN_BA             (F2(0,2) | CONDA)
03202 #define INSN_OR             F3(2, 0x2, 0)
03203 #define INSN_NOP     F2(0,4)
03204 
03205              long delay;
03206 
03207              /* If the instruction is a call with either:
03208                restore
03209                arithmetic instruction with rd == %o7
03210                where rs1 != %o7 and rs2 if it is register != %o7
03211                then we can optimize if the call destination is near
03212                by changing the call into a branch always.  */
03213              if (INSN_BIG_ENDIAN)
03214               delay = bfd_getb32 ((unsigned char *) buf + 4);
03215              else
03216               delay = bfd_getl32 ((unsigned char *) buf + 4);
03217              if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
03218               break;
03219              if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore.  */
03220                 && ((delay & OP3 (0x28)) != 0 /* Arithmetic.  */
03221                     || ((delay & RD (~0)) != RD (O7))))
03222               break;
03223              if ((delay & RS1 (~0)) == RS1 (O7)
03224                 || ((delay & F3I (~0)) == 0
03225                     && (delay & RS2 (~0)) == RS2 (O7)))
03226               break;
03227              /* Ensure the branch will fit into simm22.  */
03228              if ((val & 0x3fe00000)
03229                 && (val & 0x3fe00000) != 0x3fe00000)
03230               break;
03231              /* Check if the arch is v9 and branch will fit
03232                into simm19.  */
03233              if (((val & 0x3c0000) == 0
03234                  || (val & 0x3c0000) == 0x3c0000)
03235                 && (sparc_arch_size == 64
03236                     || current_architecture >= SPARC_OPCODE_ARCH_V9))
03237               /* ba,pt %xcc  */
03238               insn = INSN_BPA | (val & 0x7ffff);
03239              else
03240               /* ba  */
03241               insn = INSN_BA | (val & 0x3fffff);
03242              if (fixP->fx_where >= 4
03243                 && ((delay & (0xffffffff ^ RS1 (~0)))
03244                     == (INSN_OR | RD (O7) | RS2 (G0))))
03245               {
03246                 long setter;
03247                 int reg;
03248 
03249                 if (INSN_BIG_ENDIAN)
03250                   setter = bfd_getb32 ((unsigned char *) buf - 4);
03251                 else
03252                   setter = bfd_getl32 ((unsigned char *) buf - 4);
03253                 if ((setter & (0xffffffff ^ RD (~0)))
03254                     != (INSN_OR | RS1 (O7) | RS2 (G0)))
03255                   break;
03256                 /* The sequence was
03257                    or %o7, %g0, %rN
03258                    call foo
03259                    or %rN, %g0, %o7
03260 
03261                    If call foo was replaced with ba, replace
03262                    or %rN, %g0, %o7 with nop.  */
03263                 reg = (delay & RS1 (~0)) >> 14;
03264                 if (reg != ((setter & RD (~0)) >> 25)
03265                     || reg == G0 || reg == O7)
03266                   break;
03267 
03268                 if (INSN_BIG_ENDIAN)
03269                   bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
03270                 else
03271                   bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
03272               }
03273            }
03274          break;
03275 
03276        case BFD_RELOC_SPARC_11:
03277          if (! in_signed_range (val, 0x7ff))
03278            as_bad_where (fixP->fx_file, fixP->fx_line,
03279                        _("relocation overflow"));
03280          insn |= val & 0x7ff;
03281          break;
03282 
03283        case BFD_RELOC_SPARC_10:
03284          if (! in_signed_range (val, 0x3ff))
03285            as_bad_where (fixP->fx_file, fixP->fx_line,
03286                        _("relocation overflow"));
03287          insn |= val & 0x3ff;
03288          break;
03289 
03290        case BFD_RELOC_SPARC_7:
03291          if (! in_bitfield_range (val, 0x7f))
03292            as_bad_where (fixP->fx_file, fixP->fx_line,
03293                        _("relocation overflow"));
03294          insn |= val & 0x7f;
03295          break;
03296 
03297        case BFD_RELOC_SPARC_6:
03298          if (! in_bitfield_range (val, 0x3f))
03299            as_bad_where (fixP->fx_file, fixP->fx_line,
03300                        _("relocation overflow"));
03301          insn |= val & 0x3f;
03302          break;
03303 
03304        case BFD_RELOC_SPARC_5:
03305          if (! in_bitfield_range (val, 0x1f))
03306            as_bad_where (fixP->fx_file, fixP->fx_line,
03307                        _("relocation overflow"));
03308          insn |= val & 0x1f;
03309          break;
03310 
03311        case BFD_RELOC_SPARC_WDISP16:
03312          /* FIXME: simplify.  */
03313          if (((val > 0) && (val & ~0x3fffc))
03314              || ((val < 0) && (~(val - 1) & ~0x3fffc)))
03315            as_bad_where (fixP->fx_file, fixP->fx_line,
03316                        _("relocation overflow"));
03317          /* FIXME: The +1 deserves a comment.  */
03318          val = (val >> 2) + 1;
03319          insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
03320          break;
03321 
03322        case BFD_RELOC_SPARC_WDISP19:
03323          /* FIXME: simplify.  */
03324          if (((val > 0) && (val & ~0x1ffffc))
03325              || ((val < 0) && (~(val - 1) & ~0x1ffffc)))
03326            as_bad_where (fixP->fx_file, fixP->fx_line,
03327                        _("relocation overflow"));
03328          /* FIXME: The +1 deserves a comment.  */
03329          val = (val >> 2) + 1;
03330          insn |= val & 0x7ffff;
03331          break;
03332 
03333        case BFD_RELOC_SPARC_HH22:
03334          val = BSR (val, 32);
03335          /* Fall through.  */
03336 
03337        case BFD_RELOC_SPARC_LM22:
03338        case BFD_RELOC_HI22:
03339          if (!fixP->fx_addsy)
03340            insn |= (val >> 10) & 0x3fffff;
03341          else
03342            /* FIXME: Need comment explaining why we do this.  */
03343            insn &= ~0xffff;
03344          break;
03345 
03346        case BFD_RELOC_SPARC22:
03347          if (val & ~0x003fffff)
03348            as_bad_where (fixP->fx_file, fixP->fx_line,
03349                        _("relocation overflow"));
03350          insn |= (val & 0x3fffff);
03351          break;
03352 
03353        case BFD_RELOC_SPARC_HM10:
03354          val = BSR (val, 32);
03355          /* Fall through.  */
03356 
03357        case BFD_RELOC_LO10:
03358          if (!fixP->fx_addsy)
03359            insn |= val & 0x3ff;
03360          else
03361            /* FIXME: Need comment explaining why we do this.  */
03362            insn &= ~0xff;
03363          break;
03364 
03365        case BFD_RELOC_SPARC_OLO10:
03366          val &= 0x3ff;
03367          val += fixP->tc_fix_data;
03368          /* Fall through.  */
03369 
03370        case BFD_RELOC_SPARC13:
03371          if (! in_signed_range (val, 0x1fff))
03372            as_bad_where (fixP->fx_file, fixP->fx_line,
03373                        _("relocation overflow"));
03374          insn |= val & 0x1fff;
03375          break;
03376 
03377        case BFD_RELOC_SPARC_WDISP22:
03378          val = (val >> 2) + 1;
03379          /* Fall through.  */
03380        case BFD_RELOC_SPARC_BASE22:
03381          insn |= val & 0x3fffff;
03382          break;
03383 
03384        case BFD_RELOC_SPARC_H44:
03385          if (!fixP->fx_addsy)
03386            {
03387              bfd_vma tval = val;
03388              tval >>= 22;
03389              insn |= tval & 0x3fffff;
03390            }
03391          break;
03392 
03393        case BFD_RELOC_SPARC_M44:
03394          if (!fixP->fx_addsy)
03395            insn |= (val >> 12) & 0x3ff;
03396          break;
03397 
03398        case BFD_RELOC_SPARC_L44:
03399          if (!fixP->fx_addsy)
03400            insn |= val & 0xfff;
03401          break;
03402 
03403        case BFD_RELOC_SPARC_HIX22:
03404          if (!fixP->fx_addsy)
03405            {
03406              val ^= ~(offsetT) 0;
03407              insn |= (val >> 10) & 0x3fffff;
03408            }
03409          break;
03410 
03411        case BFD_RELOC_SPARC_LOX10:
03412          if (!fixP->fx_addsy)
03413            insn |= 0x1c00 | (val & 0x3ff);
03414          break;
03415 
03416        case BFD_RELOC_NONE:
03417        default:
03418          as_bad_where (fixP->fx_file, fixP->fx_line,
03419                      _("bad or unhandled relocation type: 0x%02x"),
03420                      fixP->fx_r_type);
03421          break;
03422        }
03423 
03424       if (INSN_BIG_ENDIAN)
03425        bfd_putb32 (insn, (unsigned char *) buf);
03426       else
03427        bfd_putl32 (insn, (unsigned char *) buf);
03428     }
03429 
03430   /* Are we finished with this relocation now?  */
03431   if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
03432     fixP->fx_done = 1;
03433 }
03434 
03435 /* Translate internal representation of relocation info to BFD target
03436    format.  */
03437 
03438 arelent **
03439 tc_gen_reloc (section, fixp)
03440      asection *section;
03441      fixS *fixp;
03442 {
03443   static arelent *relocs[3];
03444   arelent *reloc;
03445   bfd_reloc_code_real_type code;
03446 
03447   relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
03448   relocs[1] = NULL;
03449 
03450   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
03451   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
03452   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
03453 
03454   switch (fixp->fx_r_type)
03455     {
03456     case BFD_RELOC_16:
03457     case BFD_RELOC_32:
03458     case BFD_RELOC_HI22:
03459     case BFD_RELOC_LO10:
03460     case BFD_RELOC_32_PCREL_S2:
03461     case BFD_RELOC_SPARC13:
03462     case BFD_RELOC_SPARC22:
03463     case BFD_RELOC_SPARC_BASE13:
03464     case BFD_RELOC_SPARC_WDISP16:
03465     case BFD_RELOC_SPARC_WDISP19:
03466     case BFD_RELOC_SPARC_WDISP22:
03467     case BFD_RELOC_64:
03468     case BFD_RELOC_SPARC_5:
03469     case BFD_RELOC_SPARC_6:
03470     case BFD_RELOC_SPARC_7:
03471     case BFD_RELOC_SPARC_10:
03472     case BFD_RELOC_SPARC_11:
03473     case BFD_RELOC_SPARC_HH22:
03474     case BFD_RELOC_SPARC_HM10:
03475     case BFD_RELOC_SPARC_LM22:
03476     case BFD_RELOC_SPARC_PC_HH22:
03477     case BFD_RELOC_SPARC_PC_HM10:
03478     case BFD_RELOC_SPARC_PC_LM22:
03479     case BFD_RELOC_SPARC_H44:
03480     case BFD_RELOC_SPARC_M44:
03481     case BFD_RELOC_SPARC_L44:
03482     case BFD_RELOC_SPARC_HIX22:
03483     case BFD_RELOC_SPARC_LOX10:
03484     case BFD_RELOC_SPARC_REV32:
03485     case BFD_RELOC_SPARC_OLO10:
03486     case BFD_RELOC_SPARC_UA16:
03487     case BFD_RELOC_SPARC_UA32:
03488     case BFD_RELOC_SPARC_UA64:
03489     case BFD_RELOC_8_PCREL:
03490     case BFD_RELOC_16_PCREL:
03491     case BFD_RELOC_32_PCREL:
03492     case BFD_RELOC_64_PCREL:
03493     case BFD_RELOC_SPARC_PLT32:
03494     case BFD_RELOC_SPARC_PLT64:
03495     case BFD_RELOC_VTABLE_ENTRY:
03496     case BFD_RELOC_VTABLE_INHERIT:
03497     case BFD_RELOC_SPARC_TLS_GD_HI22:
03498     case BFD_RELOC_SPARC_TLS_GD_LO10:
03499     case BFD_RELOC_SPARC_TLS_GD_ADD:
03500     case BFD_RELOC_SPARC_TLS_GD_CALL:
03501     case BFD_RELOC_SPARC_TLS_LDM_HI22:
03502     case BFD_RELOC_SPARC_TLS_LDM_LO10:
03503     case BFD_RELOC_SPARC_TLS_LDM_ADD:
03504     case BFD_RELOC_SPARC_TLS_LDM_CALL:
03505     case BFD_RELOC_SPARC_TLS_LDO_HIX22:
03506     case BFD_RELOC_SPARC_TLS_LDO_LOX10:
03507     case BFD_RELOC_SPARC_TLS_LDO_ADD:
03508     case BFD_RELOC_SPARC_TLS_IE_HI22:
03509     case BFD_RELOC_SPARC_TLS_IE_LO10:
03510     case BFD_RELOC_SPARC_TLS_IE_LD:
03511     case BFD_RELOC_SPARC_TLS_IE_LDX:
03512     case BFD_RELOC_SPARC_TLS_IE_ADD:
03513     case BFD_RELOC_SPARC_TLS_LE_HIX22:
03514     case BFD_RELOC_SPARC_TLS_LE_LOX10:
03515     case BFD_RELOC_SPARC_TLS_DTPOFF32:
03516     case BFD_RELOC_SPARC_TLS_DTPOFF64:
03517       code = fixp->fx_r_type;
03518       break;
03519     default:
03520       abort ();
03521       return NULL;
03522     }
03523 
03524 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
03525   /* If we are generating PIC code, we need to generate a different
03526      set of relocs.  */
03527 
03528 #ifdef OBJ_ELF
03529 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
03530 #else
03531 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
03532 #endif
03533 #ifdef TE_VXWORKS
03534 #define GOTT_BASE "__GOTT_BASE__"
03535 #define GOTT_INDEX "__GOTT_INDEX__"
03536 #endif
03537 
03538   /* This code must be parallel to the OBJ_ELF tc_fix_adjustable.  */
03539 
03540   if (sparc_pic_code)
03541     {
03542       switch (code)
03543        {
03544        case BFD_RELOC_32_PCREL_S2:
03545          if (generic_force_reloc (fixp))
03546            code = BFD_RELOC_SPARC_WPLT30;
03547          break;
03548        case BFD_RELOC_HI22:
03549          code = BFD_RELOC_SPARC_GOT22;
03550          if (fixp->fx_addsy != NULL)
03551            {
03552              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
03553               code = BFD_RELOC_SPARC_PC22;
03554 #ifdef TE_VXWORKS
03555              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
03556                 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
03557               code = BFD_RELOC_HI22; /* Unchanged.  */
03558 #endif
03559            }
03560          break;
03561        case BFD_RELOC_LO10:
03562          code = BFD_RELOC_SPARC_GOT10;
03563          if (fixp->fx_addsy != NULL)
03564            {
03565              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
03566               code = BFD_RELOC_SPARC_PC10;
03567 #ifdef TE_VXWORKS
03568              if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
03569                 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
03570               code = BFD_RELOC_LO10; /* Unchanged.  */
03571 #endif
03572            }
03573          break;
03574        case BFD_RELOC_SPARC13:
03575          code = BFD_RELOC_SPARC_GOT13;
03576          break;
03577        default:
03578          break;
03579        }
03580     }
03581 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT)  */
03582 
03583   /* Nothing is aligned in DWARF debugging sections.  */
03584   if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
03585     switch (code)
03586       {
03587       case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
03588       case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
03589       case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
03590       default: break;
03591       }
03592 
03593   if (code == BFD_RELOC_SPARC_OLO10)
03594     reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
03595   else
03596     reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
03597   if (reloc->howto == 0)
03598     {
03599       as_bad_where (fixp->fx_file, fixp->fx_line,
03600                   _("internal error: can't export reloc type %d (`%s')"),
03601                   fixp->fx_r_type, bfd_get_reloc_code_name (code));
03602       xfree (reloc);
03603       relocs[0] = NULL;
03604       return relocs;
03605     }
03606 
03607   /* @@ Why fx_addnumber sometimes and fx_offset other times?  */
03608 #ifdef OBJ_AOUT
03609 
03610   if (reloc->howto->pc_relative == 0
03611       || code == BFD_RELOC_SPARC_PC10
03612       || code == BFD_RELOC_SPARC_PC22)
03613     reloc->addend = fixp->fx_addnumber;
03614   else if (sparc_pic_code
03615           && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
03616           && fixp->fx_addsy != NULL
03617           && (S_IS_EXTERNAL (fixp->fx_addsy)
03618               || S_IS_WEAK (fixp->fx_addsy))
03619           && S_IS_DEFINED (fixp->fx_addsy)
03620           && ! S_IS_COMMON (fixp->fx_addsy))
03621     reloc->addend = fixp->fx_addnumber;
03622   else
03623     reloc->addend = fixp->fx_offset - reloc->address;
03624 
03625 #else /* elf or coff  */
03626 
03627   if (code != BFD_RELOC_32_PCREL_S2
03628       && code != BFD_RELOC_SPARC_WDISP22
03629       && code != BFD_RELOC_SPARC_WDISP16
03630       && code != BFD_RELOC_SPARC_WDISP19
03631       && code != BFD_RELOC_SPARC_WPLT30
03632       && code != BFD_RELOC_SPARC_TLS_GD_CALL
03633       && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
03634     reloc->addend = fixp->fx_addnumber;
03635   else if (symbol_section_p (fixp->fx_addsy))
03636     reloc->addend = (section->vma
03637                    + fixp->fx_addnumber
03638                    + md_pcrel_from (fixp));
03639   else
03640     reloc->addend = fixp->fx_offset;
03641 #endif
03642 
03643   /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
03644      on the same location.  */
03645   if (code == BFD_RELOC_SPARC_OLO10)
03646     {
03647       relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
03648       relocs[2] = NULL;
03649 
03650       reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
03651       *reloc->sym_ptr_ptr
03652        = symbol_get_bfdsym (section_symbol (absolute_section));
03653       reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
03654       reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
03655       reloc->addend = fixp->tc_fix_data;
03656     }
03657 
03658   return relocs;
03659 }
03660 
03661 /* We have no need to default values of symbols.  */
03662 
03663 symbolS *
03664 md_undefined_symbol (name)
03665      char *name ATTRIBUTE_UNUSED;
03666 {
03667   return 0;
03668 }
03669 
03670 /* Round up a section size to the appropriate boundary.  */
03671 
03672 valueT
03673 md_section_align (segment, size)
03674      segT segment ATTRIBUTE_UNUSED;
03675      valueT size;
03676 {
03677 #ifndef OBJ_ELF
03678   /* This is not right for ELF; a.out wants it, and COFF will force
03679      the alignment anyways.  */
03680   valueT align = ((valueT) 1
03681                 << (valueT) bfd_get_section_alignment (stdoutput, segment));
03682   valueT newsize;
03683 
03684   /* Turn alignment value into a mask.  */
03685   align--;
03686   newsize = (size + align) & ~align;
03687   return newsize;
03688 #else
03689   return size;
03690 #endif
03691 }
03692 
03693 /* Exactly what point is a PC-relative offset relative TO?
03694    On the sparc, they're relative to the address of the offset, plus
03695    its size.  This gets us to the following instruction.
03696    (??? Is this right?  FIXME-SOON)  */
03697 long
03698 md_pcrel_from (fixP)
03699      fixS *fixP;
03700 {
03701   long ret;
03702 
03703   ret = fixP->fx_where + fixP->fx_frag->fr_address;
03704   if (! sparc_pic_code
03705       || fixP->fx_addsy == NULL
03706       || symbol_section_p (fixP->fx_addsy))
03707     ret += fixP->fx_size;
03708   return ret;
03709 }
03710 
03711 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
03712    of two.  */
03713 
03714 static int
03715 mylog2 (value)
03716      int value;
03717 {
03718   int shift;
03719 
03720   if (value <= 0)
03721     return -1;
03722 
03723   for (shift = 0; (value & 1) == 0; value >>= 1)
03724     ++shift;
03725 
03726   return (value == 1) ? shift : -1;
03727 }
03728 
03729 /* Sort of like s_lcomm.  */
03730 
03731 #ifndef OBJ_ELF
03732 static int max_alignment = 15;
03733 #endif
03734 
03735 static void
03736 s_reserve (ignore)
03737      int ignore ATTRIBUTE_UNUSED;
03738 {
03739   char *name;
03740   char *p;
03741   char c;
03742   int align;
03743   int size;
03744   int temp;
03745   symbolS *symbolP;
03746 
03747   name = input_line_pointer;
03748   c = get_symbol_end ();
03749   p = input_line_pointer;
03750   *p = c;
03751   SKIP_WHITESPACE ();
03752 
03753   if (*input_line_pointer != ',')
03754     {
03755       as_bad (_("Expected comma after name"));
03756       ignore_rest_of_line ();
03757       return;
03758     }
03759 
03760   ++input_line_pointer;
03761 
03762   if ((size = get_absolute_expression ()) < 0)
03763     {
03764       as_bad (_("BSS length (%d.) <0! Ignored."), size);
03765       ignore_rest_of_line ();
03766       return;
03767     }                       /* Bad length.  */
03768 
03769   *p = 0;
03770   symbolP = symbol_find_or_make (name);
03771   *p = c;
03772 
03773   if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
03774       && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
03775     {
03776       as_bad (_("bad .reserve segment -- expected BSS segment"));
03777       return;
03778     }
03779 
03780   if (input_line_pointer[2] == '.')
03781     input_line_pointer += 7;
03782   else
03783     input_line_pointer += 6;
03784   SKIP_WHITESPACE ();
03785 
03786   if (*input_line_pointer == ',')
03787     {
03788       ++input_line_pointer;
03789 
03790       SKIP_WHITESPACE ();
03791       if (*input_line_pointer == '\n')
03792        {
03793          as_bad (_("missing alignment"));
03794          ignore_rest_of_line ();
03795          return;
03796        }
03797 
03798       align = (int) get_absolute_expression ();
03799 
03800 #ifndef OBJ_ELF
03801       if (align > max_alignment)
03802        {
03803          align = max_alignment;
03804          as_warn (_("alignment too large; assuming %d"), align);
03805        }
03806 #endif
03807 
03808       if (align < 0)
03809        {
03810          as_bad (_("negative alignment"));
03811          ignore_rest_of_line ();
03812          return;
03813        }
03814 
03815       if (align != 0)
03816        {
03817          temp = mylog2 (align);
03818          if (temp < 0)
03819            {
03820              as_bad (_("alignment not a power of 2"));
03821              ignore_rest_of_line ();
03822              return;
03823            }
03824 
03825          align = temp;
03826        }
03827 
03828       record_alignment (bss_section, align);
03829     }
03830   else
03831     align = 0;
03832 
03833   if (!S_IS_DEFINED (symbolP)
03834 #ifdef OBJ_AOUT
03835       && S_GET_OTHER (symbolP) == 0
03836       && S_GET_DESC (symbolP) == 0
03837 #endif
03838       )
03839     {
03840       if (! need_pass_2)
03841        {
03842          char *pfrag;
03843          segT current_seg = now_seg;
03844          subsegT current_subseg = now_subseg;
03845 
03846          /* Switch to bss.  */
03847          subseg_set (bss_section, 1);
03848 
03849          if (align)
03850            /* Do alignment.  */
03851            frag_align (align, 0, 0);
03852 
03853          /* Detach from old frag.  */
03854          if (S_GET_SEGMENT (symbolP) == bss_section)
03855            symbol_get_frag (symbolP)->fr_symbol = NULL;
03856 
03857          symbol_set_frag (symbolP, frag_now);
03858          pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
03859                          (offsetT) size, (char *) 0);
03860          *pfrag = 0;
03861 
03862          S_SET_SEGMENT (symbolP, bss_section);
03863 
03864          subseg_set (current_seg, current_subseg);
03865 
03866 #ifdef OBJ_ELF
03867          S_SET_SIZE (symbolP, size);
03868 #endif
03869        }
03870     }
03871   else
03872     {
03873       as_warn ("Ignoring attempt to re-define symbol %s",
03874               S_GET_NAME (symbolP));
03875     }                       /* if not redefining.  */
03876 
03877   demand_empty_rest_of_line ();
03878 }
03879 
03880 static void
03881 s_common (ignore)
03882      int ignore ATTRIBUTE_UNUSED;
03883 {
03884   char *name;
03885   char c;
03886   char *p;
03887   offsetT temp, size;
03888   symbolS *symbolP;
03889 
03890   name = input_line_pointer;
03891   c = get_symbol_end ();
03892   /* Just after name is now '\0'.  */
03893   p = input_line_pointer;
03894   *p = c;
03895   SKIP_WHITESPACE ();
03896   if (*input_line_pointer != ',')
03897     {
03898       as_bad (_("Expected comma after symbol-name"));
03899       ignore_rest_of_line ();
03900       return;
03901     }
03902 
03903   /* Skip ','.  */
03904   input_line_pointer++;
03905 
03906   if ((temp = get_absolute_expression ()) < 0)
03907     {
03908       as_bad (_(".COMMon length (%lu) out of range ignored"),
03909              (unsigned long) temp);
03910       ignore_rest_of_line ();
03911       return;
03912     }
03913   size = temp;
03914   *p = 0;
03915   symbolP = symbol_find_or_make (name);
03916   *p = c;
03917   if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
03918     {
03919       as_bad (_("Ignoring attempt to re-define symbol"));
03920       ignore_rest_of_line ();
03921       return;
03922     }
03923   if (S_GET_VALUE (symbolP) != 0)
03924     {
03925       if (S_GET_VALUE (symbolP) != (valueT) size)
03926        {
03927          as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
03928                  S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
03929        }
03930     }
03931   else
03932     {
03933 #ifndef OBJ_ELF
03934       S_SET_VALUE (symbolP, (valueT) size);
03935       S_SET_EXTERNAL (symbolP);
03936 #endif
03937     }
03938   know (symbol_get_frag (symbolP) == &zero_address_frag);
03939   if (*input_line_pointer != ',')
03940     {
03941       as_bad (_("Expected comma after common length"));
03942       ignore_rest_of_line ();
03943       return;
03944     }
03945   input_line_pointer++;
03946   SKIP_WHITESPACE ();
03947   if (*input_line_pointer != '"')
03948     {
03949       temp = get_absolute_expression ();
03950 
03951 #ifndef OBJ_ELF
03952       if (temp > max_alignment)
03953        {
03954          temp = max_alignment;
03955          as_warn (_("alignment too large; assuming %ld"), (long) temp);
03956        }
03957 #endif
03958 
03959       if (temp < 0)
03960        {
03961          as_bad (_("negative alignment"));
03962          ignore_rest_of_line ();
03963          return;
03964        }
03965 
03966 #ifdef OBJ_ELF
03967       if (symbol_get_obj (symbolP)->local)
03968        {
03969          segT old_sec;
03970          int old_subsec;
03971          char *p;
03972          int align;
03973 
03974          old_sec = now_seg;
03975          old_subsec = now_subseg;
03976 
03977          if (temp == 0)
03978            align = 0;
03979          else
03980            align = mylog2 (temp);
03981 
03982          if (align < 0)
03983            {
03984              as_bad (_("alignment not a power of 2"));
03985              ignore_rest_of_line ();
03986              return;
03987            }
03988 
03989          record_alignment (bss_section, align);
03990          subseg_set (bss_section, 0);
03991          if (align)
03992            frag_align (align, 0, 0);
03993          if (S_GET_SEGMENT (symbolP) == bss_section)
03994            symbol_get_frag (symbolP)->fr_symbol = 0;
03995          symbol_set_frag (symbolP, frag_now);
03996          p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
03997                      (offsetT) size, (char *) 0);
03998          *p = 0;
03999          S_SET_SEGMENT (symbolP, bss_section);
04000          S_CLEAR_EXTERNAL (symbolP);
04001          S_SET_SIZE (symbolP, size);
04002          subseg_set (old_sec, old_subsec);
04003        }
04004       else
04005 #endif /* OBJ_ELF  */
04006        {
04007        allocate_common:
04008          S_SET_VALUE (symbolP, (valueT) size);
04009 #ifdef OBJ_ELF
04010          S_SET_ALIGN (symbolP, temp);
04011          S_SET_SIZE (symbolP, size);
04012 #endif
04013          S_SET_EXTERNAL (symbolP);
04014          S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
04015        }
04016     }
04017   else
04018     {
04019       input_line_pointer++;
04020       /* @@ Some use the dot, some don't.  Can we get some consistency??  */
04021       if (*input_line_pointer == '.')
04022        input_line_pointer++;
04023       /* @@ Some say data, some say bss.  */
04024       if (strncmp (input_line_pointer, "bss\"", 4)
04025          && strncmp (input_line_pointer, "data\"", 5))
04026        {
04027          while (*--input_line_pointer != '"')
04028            ;
04029          input_line_pointer--;
04030          goto bad_common_segment;
04031        }
04032       while (*input_line_pointer++ != '"')
04033        ;
04034       goto allocate_common;
04035     }
04036 
04037   symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
04038 
04039   demand_empty_rest_of_line ();
04040   return;
04041 
04042   {
04043   bad_common_segment:
04044     p = input_line_pointer;
04045     while (*p && *p != '\n')
04046       p++;
04047     c = *p;
04048     *p = '\0';
04049     as_bad (_("bad .common segment %s"), input_line_pointer + 1);
04050     *p = c;
04051     input_line_pointer = p;
04052     ignore_rest_of_line ();
04053     return;
04054   }
04055 }
04056 
04057 /* Handle the .empty pseudo-op.  This suppresses the warnings about
04058    invalid delay slot usage.  */
04059 
04060 static void
04061 s_empty (ignore)
04062      int ignore ATTRIBUTE_UNUSED;
04063 {
04064   /* The easy way to implement is to just forget about the last
04065      instruction.  */
04066   last_insn = NULL;
04067 }
04068 
04069 static void
04070 s_seg (ignore)
04071      int ignore ATTRIBUTE_UNUSED;
04072 {
04073 
04074   if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
04075     {
04076       input_line_pointer += 6;
04077       s_text (0);
04078       return;
04079     }
04080   if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
04081     {
04082       input_line_pointer += 6;
04083       s_data (0);
04084       return;
04085     }
04086   if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
04087     {
04088       input_line_pointer += 7;
04089       s_data1 ();
04090       return;
04091     }
04092   if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
04093     {
04094       input_line_pointer += 5;
04095       /* We only support 2 segments -- text and data -- for now, so
04096         things in the "bss segment" will have to go into data for now.
04097         You can still allocate SEG_BSS stuff with .lcomm or .reserve.  */
04098       subseg_set (data_section, 255);     /* FIXME-SOMEDAY.  */
04099       return;
04100     }
04101   as_bad (_("Unknown segment type"));
04102   demand_empty_rest_of_line ();
04103 }
04104 
04105 static void
04106 s_data1 ()
04107 {
04108   subseg_set (data_section, 1);
04109   demand_empty_rest_of_line ();
04110 }
04111 
04112 static void
04113 s_proc (ignore)
04114      int ignore ATTRIBUTE_UNUSED;
04115 {
04116   while (!is_end_of_line[(unsigned char) *input_line_pointer])
04117     {
04118       ++input_line_pointer;
04119     }
04120   ++input_line_pointer;
04121 }
04122 
04123 /* This static variable is set by s_uacons to tell sparc_cons_align
04124    that the expression does not need to be aligned.  */
04125 
04126 static int sparc_no_align_cons = 0;
04127 
04128 /* This static variable is set by sparc_cons to emit requested types
04129    of relocations in cons_fix_new_sparc.  */
04130 
04131 static const char *sparc_cons_special_reloc;
04132 
04133 /* This handles the unaligned space allocation pseudo-ops, such as
04134    .uaword.  .uaword is just like .word, but the value does not need
04135    to be aligned.  */
04136 
04137 static void
04138 s_uacons (bytes)
04139      int bytes;
04140 {
04141   /* Tell sparc_cons_align not to align this value.  */
04142   sparc_no_align_cons = 1;
04143   cons (bytes);
04144   sparc_no_align_cons = 0;
04145 }
04146 
04147 /* This handles the native word allocation pseudo-op .nword.
04148    For sparc_arch_size 32 it is equivalent to .word,  for
04149    sparc_arch_size 64 it is equivalent to .xword.  */
04150 
04151 static void
04152 s_ncons (bytes)
04153      int bytes ATTRIBUTE_UNUSED;
04154 {
04155   cons (sparc_arch_size == 32 ? 4 : 8);
04156 }
04157 
04158 #ifdef OBJ_ELF
04159 /* Handle the SPARC ELF .register pseudo-op.  This sets the binding of a
04160    global register.
04161    The syntax is:
04162 
04163    .register %g[2367],{#scratch|symbolname|#ignore}
04164 */
04165 
04166 static void
04167 s_register (ignore)
04168      int ignore ATTRIBUTE_UNUSED;
04169 {
04170   char c;
04171   int reg;
04172   int flags;
04173   const char *regname;
04174 
04175   if (input_line_pointer[0] != '%'
04176       || input_line_pointer[1] != 'g'
04177       || ((input_line_pointer[2] & ~1) != '2'
04178          && (input_line_pointer[2] & ~1) != '6')
04179       || input_line_pointer[3] != ',')
04180     as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
04181   reg = input_line_pointer[2] - '0';
04182   input_line_pointer += 4;
04183 
04184   if (*input_line_pointer == '#')
04185     {
04186       ++input_line_pointer;
04187       regname = input_line_pointer;
04188       c = get_symbol_end ();
04189       if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
04190        as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
04191       if (regname[0] == 'i')
04192        regname = NULL;
04193       else
04194        regname = "";
04195     }
04196   else
04197     {
04198       regname = input_line_pointer;
04199       c = get_symbol_end ();
04200     }
04201   if (sparc_arch_size == 64)
04202     {
04203       if (globals[reg])
04204        {
04205          if ((regname && globals[reg] != (symbolS *) 1
04206               && strcmp (S_GET_NAME (globals[reg]), regname))
04207              || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
04208            as_bad (_("redefinition of global register"));
04209        }
04210       else
04211        {
04212          if (regname == NULL)
04213            globals[reg] = (symbolS *) 1;
04214          else
04215            {
04216              if (*regname)
04217               {
04218                 if (symbol_find (regname))
04219                   as_bad (_("Register symbol %s already defined."),
04220                          regname);
04221               }
04222              globals[reg] = symbol_make (regname);
04223              flags = symbol_get_bfdsym (globals[reg])->flags;
04224              if (! *regname)
04225               flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
04226              if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
04227               flags |= BSF_GLOBAL;
04228              symbol_get_bfdsym (globals[reg])->flags = flags;
04229              S_SET_VALUE (globals[reg], (valueT) reg);
04230              S_SET_ALIGN (globals[reg], reg);
04231              S_SET_SIZE (globals[reg], 0);
04232              /* Although we actually want undefined_section here,
04233                we have to use absolute_section, because otherwise
04234                generic as code will make it a COM section.
04235                We fix this up in sparc_adjust_symtab.  */
04236              S_SET_SEGMENT (globals[reg], absolute_section);
04237              S_SET_OTHER (globals[reg], 0);
04238              elf_symbol (symbol_get_bfdsym (globals[reg]))
04239               ->internal_elf_sym.st_info =
04240                 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
04241              elf_symbol (symbol_get_bfdsym (globals[reg]))
04242               ->internal_elf_sym.st_shndx = SHN_UNDEF;
04243            }
04244        }
04245     }
04246 
04247   *input_line_pointer = c;
04248 
04249   demand_empty_rest_of_line ();
04250 }
04251 
04252 /* Adjust the symbol table.  We set undefined sections for STT_REGISTER
04253    symbols which need it.  */
04254 
04255 void
04256 sparc_adjust_symtab ()
04257 {
04258   symbolS *sym;
04259 
04260   for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
04261     {
04262       if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
04263                      ->internal_elf_sym.st_info) != STT_REGISTER)
04264        continue;
04265 
04266       if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
04267                      ->internal_elf_sym.st_shndx != SHN_UNDEF))
04268        continue;
04269 
04270       S_SET_SEGMENT (sym, undefined_section);
04271     }
04272 }
04273 #endif
04274 
04275 /* If the --enforce-aligned-data option is used, we require .word,
04276    et. al., to be aligned correctly.  We do it by setting up an
04277    rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
04278    no unexpected alignment was introduced.
04279 
04280    The SunOS and Solaris native assemblers enforce aligned data by
04281    default.  We don't want to do that, because gcc can deliberately
04282    generate misaligned data if the packed attribute is used.  Instead,
04283    we permit misaligned data by default, and permit the user to set an
04284    option to check for it.  */
04285 
04286 void
04287 sparc_cons_align (nbytes)
04288      int nbytes;
04289 {
04290   int nalign;
04291   char *p;
04292 
04293   /* Only do this if we are enforcing aligned data.  */
04294   if (! enforce_aligned_data)
04295     return;
04296 
04297   /* Don't align if this is an unaligned pseudo-op.  */
04298   if (sparc_no_align_cons)
04299     return;
04300 
04301   nalign = mylog2 (nbytes);
04302   if (nalign == 0)
04303     return;
04304 
04305   assert (nalign > 0);
04306 
04307   if (now_seg == absolute_section)
04308     {
04309       if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
04310        as_bad (_("misaligned data"));
04311       return;
04312     }
04313 
04314   p = frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
04315               (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
04316 
04317   record_alignment (now_seg, nalign);
04318 }
04319 
04320 /* This is called from HANDLE_ALIGN in tc-sparc.h.  */
04321 
04322 void
04323 sparc_handle_align (fragp)
04324      fragS *fragp;
04325 {
04326   int count, fix;
04327   char *p;
04328 
04329   count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
04330 
04331   switch (fragp->fr_type)
04332     {
04333     case rs_align_test:
04334       if (count != 0)
04335        as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
04336       break;
04337 
04338     case rs_align_code:
04339       p = fragp->fr_literal + fragp->fr_fix;
04340       fix = 0;
04341 
04342       if (count & 3)
04343        {
04344          fix = count & 3;
04345          memset (p, 0, fix);
04346          p += fix;
04347          count -= fix;
04348        }
04349 
04350       if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
04351        {
04352          unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f  */
04353          if (INSN_BIG_ENDIAN)
04354            number_to_chars_bigendian (p, wval, 4);
04355          else
04356            number_to_chars_littleendian (p, wval, 4);
04357          p += 4;
04358          count -= 4;
04359          fix += 4;
04360        }
04361 
04362       if (INSN_BIG_ENDIAN)
04363        number_to_chars_bigendian (p, 0x01000000, 4);
04364       else
04365        number_to_chars_littleendian (p, 0x01000000, 4);
04366 
04367       fragp->fr_fix += fix;
04368       fragp->fr_var = 4;
04369       break;
04370 
04371     default:
04372       break;
04373     }
04374 }
04375 
04376 #ifdef OBJ_ELF
04377 /* Some special processing for a Sparc ELF file.  */
04378 
04379 void
04380 sparc_elf_final_processing ()
04381 {
04382   /* Set the Sparc ELF flag bits.  FIXME: There should probably be some
04383      sort of BFD interface for this.  */
04384   if (sparc_arch_size == 64)
04385     {
04386       switch (sparc_memory_model)
04387        {
04388        case MM_RMO:
04389          elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
04390          break;
04391        case MM_PSO:
04392          elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
04393          break;
04394        default:
04395          break;
04396        }
04397     }
04398   else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
04399     elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
04400   if (current_architecture == SPARC_OPCODE_ARCH_V9A)
04401     elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
04402   else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
04403     elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
04404 }
04405 
04406 void
04407 sparc_cons (exp, size)
04408      expressionS *exp;
04409      int size;
04410 {
04411   char *save;
04412 
04413   SKIP_WHITESPACE ();
04414   sparc_cons_special_reloc = NULL;
04415   save = input_line_pointer;
04416   if (input_line_pointer[0] == '%'
04417       && input_line_pointer[1] == 'r'
04418       && input_line_pointer[2] == '_')
04419     {
04420       if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
04421        {
04422          input_line_pointer += 7;
04423          sparc_cons_special_reloc = "disp";
04424        }
04425       else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
04426        {
04427          if (size != 4 && size != 8)
04428            as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
04429          else
04430            {
04431              input_line_pointer += 6;
04432              sparc_cons_special_reloc = "plt";
04433            }
04434        }
04435       else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
04436        {
04437          if (size != 4 && size != 8)
04438            as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
04439          else
04440            {
04441              input_line_pointer += 13;
04442              sparc_cons_special_reloc = "tls_dtpoff";
04443            }
04444        }
04445       if (sparc_cons_special_reloc)
04446        {
04447          int bad = 0;
04448 
04449          switch (size)
04450            {
04451            case 1:
04452              if (*input_line_pointer != '8')
04453               bad = 1;
04454              input_line_pointer--;
04455              break;
04456            case 2:
04457              if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
04458               bad = 1;
04459              break;
04460            case 4:
04461              if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
04462               bad = 1;
04463              break;
04464            case 8:
04465              if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
04466               bad = 1;
04467              break;
04468            default:
04469              bad = 1;
04470              break;
04471            }
04472 
04473          if (bad)
04474            {
04475              as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
04476                     sparc_cons_special_reloc, size * 8, size);
04477            }
04478          else
04479            {
04480              input_line_pointer += 2;
04481              if (*input_line_pointer != '(')
04482               {
04483                 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
04484                        sparc_cons_special_reloc, size * 8);
04485                 bad = 1;
04486               }
04487            }
04488 
04489          if (bad)
04490            {
04491              input_line_pointer = save;
04492              sparc_cons_special_reloc = NULL;
04493            }
04494          else
04495            {
04496              int c;
04497              char *end = ++input_line_pointer;
04498              int npar = 0;
04499 
04500              while (! is_end_of_line[(c = *end)])
04501               {
04502                 if (c == '(')
04503                   npar++;
04504                 else if (c == ')')
04505                   {
04506                     if (!npar)
04507                      break;
04508                     npar--;
04509                   }
04510                 end++;
04511               }
04512 
04513              if (c != ')')
04514               as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
04515                      sparc_cons_special_reloc, size * 8);
04516              else
04517               {
04518                 *end = '\0';
04519                 expression (exp);
04520                 *end = c;
04521                 if (input_line_pointer != end)
04522                   {
04523                     as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
04524                            sparc_cons_special_reloc, size * 8);
04525                   }
04526                 else
04527                   {
04528                     input_line_pointer++;
04529                     SKIP_WHITESPACE ();
04530                     c = *input_line_pointer;
04531                     if (! is_end_of_line[c] && c != ',')
04532                      as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
04533                              sparc_cons_special_reloc, size * 8);
04534                   }
04535               }
04536            }
04537        }
04538     }
04539   if (sparc_cons_special_reloc == NULL)
04540     expression (exp);
04541 }
04542 
04543 #endif
04544 
04545 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
04546    reloc for a cons.  We could use the definition there, except that
04547    we want to handle little endian relocs specially.  */
04548 
04549 void
04550 cons_fix_new_sparc (frag, where, nbytes, exp)
04551      fragS *frag;
04552      int where;
04553      unsigned int nbytes;
04554      expressionS *exp;
04555 {
04556   bfd_reloc_code_real_type r;
04557 
04558   r = (nbytes == 1 ? BFD_RELOC_8 :
04559        (nbytes == 2 ? BFD_RELOC_16 :
04560        (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
04561 
04562   if (target_little_endian_data
04563       && nbytes == 4
04564       && now_seg->flags & SEC_ALLOC)
04565     r = BFD_RELOC_SPARC_REV32;
04566 
04567   if (sparc_cons_special_reloc)
04568     {
04569       if (*sparc_cons_special_reloc == 'd')
04570        switch (nbytes)
04571          {
04572          case 1: r = BFD_RELOC_8_PCREL; break;
04573          case 2: r = BFD_RELOC_16_PCREL; break;
04574          case 4: r = BFD_RELOC_32_PCREL; break;
04575          case 8: r = BFD_RELOC_64_PCREL; break;
04576          default: abort ();
04577          }
04578       else if (*sparc_cons_special_reloc == 'p')
04579        switch (nbytes)
04580          {
04581          case 4: r = BFD_RELOC_SPARC_PLT32; break;
04582          case 8: r = BFD_RELOC_SPARC_PLT64; break;
04583          }
04584       else
04585        switch (nbytes)
04586          {
04587          case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
04588          case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
04589          }
04590     }
04591   else if (sparc_no_align_cons)
04592     {
04593       switch (nbytes)
04594        {
04595        case 2: r = BFD_RELOC_SPARC_UA16; break;
04596        case 4: r = BFD_RELOC_SPARC_UA32; break;
04597        case 8: r = BFD_RELOC_SPARC_UA64; break;
04598        default: abort ();
04599        }
04600    }
04601 
04602   fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
04603   sparc_cons_special_reloc = NULL;
04604 }
04605 
04606 void
04607 sparc_cfi_frame_initial_instructions ()
04608 {
04609   cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
04610 }
04611 
04612 int
04613 sparc_regname_to_dw2regnum (char *regname)
04614 {
04615   char *p, *q;
04616 
04617   if (!regname[0])
04618     return -1;
04619 
04620   q = "goli";
04621   p = strchr (q, regname[0]);
04622   if (p)
04623     {
04624       if (regname[1] < '0' || regname[1] > '8' || regname[2])
04625        return -1;
04626       return (p - q) * 8 + regname[1] - '0';
04627     }
04628   if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
04629     return 14;
04630   if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
04631     return 30;
04632   if (regname[0] == 'f' || regname[0] == 'r')
04633     {
04634       unsigned int regnum;
04635 
04636       regnum = strtoul (regname + 1, &q, 10);
04637       if (p == q || *q)
04638         return -1;
04639       if (regnum >= ((regname[0] == 'f'
04640                     && SPARC_OPCODE_ARCH_V9_P (max_architecture))
04641                    ? 64 : 32))
04642        return -1;
04643       if (regname[0] == 'f')
04644        {
04645           regnum += 32;
04646           if (regnum >= 64 && (regnum & 1))
04647            return -1;
04648         }
04649       return regnum;
04650     }
04651   return -1;
04652 }
04653 
04654 void
04655 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
04656 {
04657   sparc_cons_special_reloc = "disp";
04658   sparc_no_align_cons = 1;
04659   emit_expr (exp, nbytes);
04660   sparc_no_align_cons = 0;
04661   sparc_cons_special_reloc = NULL;
04662 }