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cell-binutils  2.17cvs20070401
Defines | Enumerations | Functions | Variables
tc-mips.h File Reference

Go to the source code of this file.

Defines

#define TARGET_BYTES_BIG_ENDIAN   1
#define TARGET_ARCH   bfd_arch_mips
#define WORKING_DOT_WORD   1
#define OLD_FLOAT_READS
#define REPEAT_CONS_EXPRESSIONS
#define RELOC_EXPANSION_POSSIBLE
#define MAX_RELOC_EXPANSION   3
#define LOCAL_LABELS_FB   1
#define MAX_GPREL_OFFSET   (0x7FF0)
#define md_relax_frag(segment, fragp, stretch)   mips_relax_frag(segment, fragp, stretch)
#define md_undefined_symbol(name)   (0)
#define md_operand(x)
#define HANDLE_ALIGN(fragp)   mips_handle_align (fragp)
#define MAX_MEM_FOR_RS_ALIGN_CODE   (1 + 2)
#define TC_SEGMENT_INFO_TYPE   struct insn_label_list *
#define HAVE_ITBL_CPU
#define TARGET_FORMAT   mips_target_format()
#define md_after_parse_args()   mips_after_parse_args()
#define tc_init_after_args()   mips_init_after_args()
#define md_parse_long_option(arg)   mips_parse_long_option (arg)
#define tc_frob_label(sym)   mips_define_label (sym)
#define tc_frob_file_before_adjust()   mips_frob_file_before_adjust ()
#define tc_frob_file_before_fix()   mips_frob_file ()
#define tc_fix_adjustable(fixp)   mips_fix_adjustable (fixp)
#define MD_APPLY_SYM_VALUE(FIX)   0
#define EXTERN_FORCE_RELOC   (OUTPUT_FLAVOR == bfd_target_elf_flavour)
#define TC_FORCE_RELOCATION(FIX)   mips_force_relocation (FIX)
#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG)   (! SEG_NORMAL (SEG) || mips_force_relocation (FIX))
#define md_end()   md_mips_end()
#define md_pop_insert()   mips_pop_insert()
#define md_flush_pending_output   mips_emit_delays
#define md_elf_section_change_hook()   mips_enable_auto_align()
#define DWARF2_FORMAT()   mips_dwarf2_format ()
#define DWARF2_ADDR_SIZE(bfd)   mips_dwarf2_addr_size ()
#define TARGET_USE_CFIPOP   1
#define tc_cfi_frame_initial_instructions   mips_cfi_frame_initial_instructions
#define tc_regname_to_dw2regnum   tc_mips_regname_to_dw2regnum
#define DWARF2_DEFAULT_RETURN_COLUMN   31
#define DWARF2_CIE_DATA_ALIGNMENT   (-4)

Enumerations

enum  mips_pic_level { NO_PIC, SVR4_PIC, VXWORKS_PIC }

Functions

int mips_relax_frag (asection *, struct frag *, long)
void mips_handle_align (struct frag *)
const char * mips_target_format (void)
enum mips_pic_level int tc_get_register (int frame)
void mips_after_parse_args (void)
void mips_init_after_args (void)
int mips_parse_long_option (const char *)
void mips_define_label (symbolS *)
void mips_frob_file_before_adjust (void)
void mips_frob_file (void)
int mips_fix_adjustable (struct fix *)
int mips_force_relocation (struct fix *)
void md_mips_end (void)
void mips_pop_insert (void)
void mips_emit_delays (void)
void mips_enable_auto_align (void)
enum dwarf2_format mips_dwarf2_format (void)
int mips_dwarf2_addr_size (void)
void mips_cfi_frame_initial_instructions (void)
int tc_mips_regname_to_dw2regnum (char *regname)

Variables

unsigned long mips_gprmask
unsigned long mips_cprmask [4]

Define Documentation

#define DWARF2_ADDR_SIZE (   bfd)    mips_dwarf2_addr_size ()

Definition at line 160 of file tc-mips.h.

#define DWARF2_CIE_DATA_ALIGNMENT   (-4)

Definition at line 171 of file tc-mips.h.

Definition at line 170 of file tc-mips.h.

#define DWARF2_FORMAT ( )    mips_dwarf2_format ()

Definition at line 157 of file tc-mips.h.

Definition at line 120 of file tc-mips.h.

#define HANDLE_ALIGN (   fragp)    mips_handle_align (fragp)

Definition at line 57 of file tc-mips.h.

#define HAVE_ITBL_CPU

Definition at line 65 of file tc-mips.h.

#define LOCAL_LABELS_FB   1

Definition at line 43 of file tc-mips.h.

#define MAX_GPREL_OFFSET   (0x7FF0)

Definition at line 47 of file tc-mips.h.

#define MAX_MEM_FOR_RS_ALIGN_CODE   (1 + 2)

Definition at line 59 of file tc-mips.h.

#define MAX_RELOC_EXPANSION   3

Definition at line 42 of file tc-mips.h.

Definition at line 90 of file tc-mips.h.

#define MD_APPLY_SYM_VALUE (   FIX)    0

Definition at line 117 of file tc-mips.h.

Definition at line 153 of file tc-mips.h.

#define md_end ( )    md_mips_end()

Definition at line 144 of file tc-mips.h.

Definition at line 150 of file tc-mips.h.

#define md_operand (   x)

Definition at line 54 of file tc-mips.h.

Definition at line 96 of file tc-mips.h.

#define md_pop_insert ( )    mips_pop_insert()

Definition at line 147 of file tc-mips.h.

#define md_relax_frag (   segment,
  fragp,
  stretch 
)    mips_relax_frag(segment, fragp, stretch)

Definition at line 49 of file tc-mips.h.

#define md_undefined_symbol (   name)    (0)

Definition at line 53 of file tc-mips.h.

#define OLD_FLOAT_READS

Definition at line 39 of file tc-mips.h.

Definition at line 41 of file tc-mips.h.

Definition at line 40 of file tc-mips.h.

#define TARGET_ARCH   bfd_arch_mips

Definition at line 36 of file tc-mips.h.

#define TARGET_BYTES_BIG_ENDIAN   1

Definition at line 33 of file tc-mips.h.

Definition at line 69 of file tc-mips.h.

#define TARGET_USE_CFIPOP   1

Definition at line 162 of file tc-mips.h.

Definition at line 164 of file tc-mips.h.

#define tc_fix_adjustable (   fixp)    mips_fix_adjustable (fixp)

Definition at line 113 of file tc-mips.h.

Definition at line 125 of file tc-mips.h.

#define TC_FORCE_RELOCATION_SUB_SAME (   FIX,
  SEG 
)    (! SEG_NORMAL (SEG) || mips_force_relocation (FIX))

Definition at line 128 of file tc-mips.h.

Definition at line 102 of file tc-mips.h.

Definition at line 105 of file tc-mips.h.

#define tc_frob_label (   sym)    mips_define_label (sym)

Definition at line 99 of file tc-mips.h.

Definition at line 93 of file tc-mips.h.

Definition at line 167 of file tc-mips.h.

Definition at line 62 of file tc-mips.h.

#define WORKING_DOT_WORD   1

Definition at line 38 of file tc-mips.h.


Enumeration Type Documentation

Enumerator:
NO_PIC 
SVR4_PIC 
VXWORKS_PIC 

Definition at line 74 of file tc-mips.h.

{
  /* Do not generate PIC code.  */
  NO_PIC,

  /* Generate PIC code as in the SVR4 MIPS ABI.  */
  SVR4_PIC,

  /* VxWorks's PIC model.  */
  VXWORKS_PIC
};

Function Documentation

void md_mips_end ( void  )

Definition at line 1944 of file tc-mips.c.

{
  if (! ECOFF_DEBUGGING)
    md_obj_end ();
}

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void mips_after_parse_args ( void  )

Definition at line 11409 of file tc-mips.c.

{
  const struct mips_cpu_info *arch_info = 0;
  const struct mips_cpu_info *tune_info = 0;

  /* GP relative stuff not working for PE */
  if (strncmp (TARGET_OS, "pe", 2) == 0)
    {
      if (g_switch_seen && g_switch_value != 0)
       as_bad (_("-G not supported in this configuration."));
      g_switch_value = 0;
    }

  if (mips_abi == NO_ABI)
    mips_abi = MIPS_DEFAULT_ABI;

  /* The following code determines the architecture and register size.
     Similar code was added to GCC 3.3 (see override_options() in
     config/mips/mips.c).  The GAS and GCC code should be kept in sync
     as much as possible.  */

  if (mips_arch_string != 0)
    arch_info = mips_parse_cpu ("-march", mips_arch_string);

  if (file_mips_isa != ISA_UNKNOWN)
    {
      /* Handle -mipsN.  At this point, file_mips_isa contains the
        ISA level specified by -mipsN, while arch_info->isa contains
        the -march selection (if any).  */
      if (arch_info != 0)
       {
         /* -march takes precedence over -mipsN, since it is more descriptive.
            There's no harm in specifying both as long as the ISA levels
            are the same.  */
         if (file_mips_isa != arch_info->isa)
           as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
                  mips_cpu_info_from_isa (file_mips_isa)->name,
                  mips_cpu_info_from_isa (arch_info->isa)->name);
       }
      else
       arch_info = mips_cpu_info_from_isa (file_mips_isa);
    }

  if (arch_info == 0)
    arch_info = mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT);

  if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
    as_bad ("-march=%s is not compatible with the selected ABI",
           arch_info->name);

  mips_set_architecture (arch_info);

  /* Optimize for file_mips_arch, unless -mtune selects a different processor.  */
  if (mips_tune_string != 0)
    tune_info = mips_parse_cpu ("-mtune", mips_tune_string);

  if (tune_info == 0)
    mips_set_tune (arch_info);
  else
    mips_set_tune (tune_info);

  if (file_mips_gp32 >= 0)
    {
      /* The user specified the size of the integer registers.  Make sure
        it agrees with the ABI and ISA.  */
      if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa))
       as_bad (_("-mgp64 used with a 32-bit processor"));
      else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi))
       as_bad (_("-mgp32 used with a 64-bit ABI"));
      else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi))
       as_bad (_("-mgp64 used with a 32-bit ABI"));
    }
  else
    {
      /* Infer the integer register size from the ABI and processor.
        Restrict ourselves to 32-bit registers if that's all the
        processor has, or if the ABI cannot handle 64-bit registers.  */
      file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
                     || !ISA_HAS_64BIT_REGS (mips_opts.isa));
    }

  switch (file_mips_fp32)
    {
    default:
    case -1:
      /* No user specified float register size.
        ??? GAS treats single-float processors as though they had 64-bit
        float registers (although it complains when double-precision
        instructions are used).  As things stand, saying they have 32-bit
        registers would lead to spurious "register must be even" messages.
        So here we assume float registers are never smaller than the
        integer ones.  */
      if (file_mips_gp32 == 0)
       /* 64-bit integer registers implies 64-bit float registers.  */
       file_mips_fp32 = 0;
      else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
              && ISA_HAS_64BIT_FPRS (mips_opts.isa))
       /* -mips3d and -mdmx imply 64-bit float registers, if possible.  */
       file_mips_fp32 = 0;
      else
       /* 32-bit float registers.  */
       file_mips_fp32 = 1;
      break;

    /* The user specified the size of the float registers.  Check if it
       agrees with the ABI and ISA.  */
    case 0:
      if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
       as_bad (_("-mfp64 used with a 32-bit fpu"));
      else if (ABI_NEEDS_32BIT_REGS (mips_abi)
              && !ISA_HAS_MXHC1 (mips_opts.isa))
       as_warn (_("-mfp64 used with a 32-bit ABI"));
      break;
    case 1:
      if (ABI_NEEDS_64BIT_REGS (mips_abi))
       as_warn (_("-mfp32 used with a 64-bit ABI"));
      break;
    }

  /* End of GCC-shared inference code.  */

  /* This flag is set when we have a 64-bit capable CPU but use only
     32-bit wide registers.  Note that EABI does not use it.  */
  if (ISA_HAS_64BIT_REGS (mips_opts.isa)
      && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
         || mips_abi == O32_ABI))
    mips_32bitmode = 1;

  if (mips_opts.isa == ISA_MIPS1 && mips_trap)
    as_bad (_("trap exception not supported at ISA 1"));

  /* If the selected architecture includes support for ASEs, enable
     generation of code for them.  */
  if (mips_opts.mips16 == -1)
    mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
  if (mips_opts.ase_mips3d == -1)
    mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
                         && file_mips_fp32 == 0) ? 1 : 0;
  if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
    as_bad (_("-mfp32 used with -mips3d"));

  if (mips_opts.ase_mdmx == -1)
    mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
                       && file_mips_fp32 == 0) ? 1 : 0;
  if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
    as_bad (_("-mfp32 used with -mdmx"));

  if (mips_opts.ase_smartmips == -1)
    mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
  if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
      as_warn ("%s ISA does not support SmartMIPS", 
              mips_cpu_info_from_isa (mips_opts.isa)->name);

  if (mips_opts.ase_dsp == -1)
    mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
  if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
      as_warn ("%s ISA does not support DSP ASE", 
              mips_cpu_info_from_isa (mips_opts.isa)->name);

  if (mips_opts.ase_dspr2 == -1)
    {
      mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
      mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
    }
  if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
      as_warn ("%s ISA does not support DSP R2 ASE",
              mips_cpu_info_from_isa (mips_opts.isa)->name);

  if (mips_opts.ase_mt == -1)
    mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
  if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
      as_warn ("%s ISA does not support MT ASE",
              mips_cpu_info_from_isa (mips_opts.isa)->name);

  file_mips_isa = mips_opts.isa;
  file_ase_mips16 = mips_opts.mips16;
  file_ase_mips3d = mips_opts.ase_mips3d;
  file_ase_mdmx = mips_opts.ase_mdmx;
  file_ase_smartmips = mips_opts.ase_smartmips;
  file_ase_dsp = mips_opts.ase_dsp;
  file_ase_dspr2 = mips_opts.ase_dspr2;
  file_ase_mt = mips_opts.ase_mt;
  mips_opts.gp32 = file_mips_gp32;
  mips_opts.fp32 = file_mips_fp32;

  if (mips_flag_mdebug < 0)
    {
#ifdef OBJ_MAYBE_ECOFF
      if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
       mips_flag_mdebug = 1;
      else
#endif /* OBJ_MAYBE_ECOFF */
       mips_flag_mdebug = 0;
    }
}

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Definition at line 15000 of file tc-mips.c.

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void mips_define_label ( symbolS *  )

Definition at line 14106 of file tc-mips.c.

{
  segment_info_type *si = seg_info (now_seg);
  struct insn_label_list *l;

  if (free_insn_labels == NULL)
    l = (struct insn_label_list *) xmalloc (sizeof *l);
  else
    {
      l = free_insn_labels;
      free_insn_labels = l->next;
    }

  l->label = sym;
  l->next = si->label_list;
  si->label_list = l;

#ifdef OBJ_ELF
  dwarf2_emit_label (sym);
#endif
}

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Definition at line 14990 of file tc-mips.c.

{
  if (mips_abi == N64_ABI)
    return 8;
  else
    return 4;
}

Definition at line 14975 of file tc-mips.c.

{
  if (mips_abi == N64_ABI)
    {
#ifdef TE_IRIX
      return dwarf2_format_64bit_irix;
#else
      return dwarf2_format_64bit;
#endif
    }
  else
    return dwarf2_format_32bit;
}
void mips_emit_delays ( void  )

Definition at line 3146 of file tc-mips.c.

{
  if (! mips_opts.noreorder)
    {
      int nops = nops_for_insn (history, NULL);
      if (nops > 0)
       {
         while (nops-- > 0)
           add_fixed_insn (NOP_INSN);
         mips_move_labels ();
       }
    }
  mips_no_prev_insn ();
}

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void mips_enable_auto_align ( void  )

Definition at line 12215 of file tc-mips.c.

{
  auto_align = 1;
}
void mips_frob_file ( void  )

Definition at line 11699 of file tc-mips.c.

{
  struct mips_hi_fixup *l;

  for (l = mips_hi_fixup_list; l != NULL; l = l->next)
    {
      segment_info_type *seginfo;
      bfd_boolean matched_lo_p;
      fixS **hi_pos, **lo_pos, **pos;

      assert (reloc_needs_lo_p (l->fixp->fx_r_type));

      /* If a GOT16 relocation turns out to be against a global symbol,
        there isn't supposed to be a matching LO.  */
      if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
         && !pic_need_relax (l->fixp->fx_addsy, l->seg))
       continue;

      /* Check quickly whether the next fixup happens to be a matching %lo.  */
      if (fixup_has_matching_lo_p (l->fixp))
       continue;

      seginfo = seg_info (l->seg);

      /* Set HI_POS to the position of this relocation in the chain.
        Set LO_POS to the position of the chosen low-part relocation.
        MATCHED_LO_P is true on entry to the loop if *POS is a low-part
        relocation that matches an immediately-preceding high-part
        relocation.  */
      hi_pos = NULL;
      lo_pos = NULL;
      matched_lo_p = FALSE;
      for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
       {
         if (*pos == l->fixp)
           hi_pos = pos;

         if (((*pos)->fx_r_type == BFD_RELOC_LO16
              || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16)
             && (*pos)->fx_addsy == l->fixp->fx_addsy
             && (*pos)->fx_offset >= l->fixp->fx_offset
             && (lo_pos == NULL
                || (*pos)->fx_offset < (*lo_pos)->fx_offset
                || (!matched_lo_p
                    && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
           lo_pos = pos;

         matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
                       && fixup_has_matching_lo_p (*pos));
       }

      /* If we found a match, remove the high-part relocation from its
        current position and insert it before the low-part relocation.
        Make the offsets match so that fixup_has_matching_lo_p()
        will return true.

        We don't warn about unmatched high-part relocations since some
        versions of gcc have been known to emit dead "lui ...%hi(...)"
        instructions.  */
      if (lo_pos != NULL)
       {
         l->fixp->fx_offset = (*lo_pos)->fx_offset;
         if (l->fixp->fx_next != *lo_pos)
           {
             *hi_pos = l->fixp->fx_next;
             l->fixp->fx_next = *lo_pos;
             *lo_pos = l->fixp;
           }
       }
    }
}

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Definition at line 11640 of file tc-mips.c.

{
#ifndef NO_ECOFF_DEBUGGING
  if (ECOFF_DEBUGGING
      && mips_debug != 0
      && ! ecoff_debugging_seen)
    flag_keep_locals = 1;
#endif
}
void mips_init_after_args ( void  )

Definition at line 11606 of file tc-mips.c.

{
  /* initialize opcodes */
  bfd_mips_num_opcodes = bfd_mips_num_builtin_opcodes;
  mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes;
}
void mips_pop_insert ( void  )

Definition at line 1164 of file tc-mips.c.

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int mips_relax_frag ( asection ,
struct frag ,
long   
)
const char* mips_target_format ( void  )

Definition at line 1232 of file tc-mips.c.

{
  switch (OUTPUT_FLAVOR)
    {
    case bfd_target_ecoff_flavour:
      return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
    case bfd_target_coff_flavour:
      return "pe-mips";
    case bfd_target_elf_flavour:
#ifdef TE_VXWORKS
      if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
       return (target_big_endian
              ? "elf32-bigmips-vxworks"
              : "elf32-littlemips-vxworks");
#endif
#ifdef TE_TMIPS
      /* This is traditional mips.  */
      return (target_big_endian
             ? (HAVE_64BIT_OBJECTS
               ? "elf64-tradbigmips"
               : (HAVE_NEWABI
                  ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
             : (HAVE_64BIT_OBJECTS
               ? "elf64-tradlittlemips"
               : (HAVE_NEWABI
                  ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
#else
      return (target_big_endian
             ? (HAVE_64BIT_OBJECTS
               ? "elf64-bigmips"
               : (HAVE_NEWABI
                  ? "elf32-nbigmips" : "elf32-bigmips"))
             : (HAVE_64BIT_OBJECTS
               ? "elf64-littlemips"
               : (HAVE_NEWABI
                  ? "elf32-nlittlemips" : "elf32-littlemips")));
#endif
    default:
      abort ();
      return NULL;
    }
}
enum mips_pic_level int tc_get_register ( int  frame) [abstract]

Definition at line 5668 of file tc-alpha.c.

{
  int framereg = AXP_REG_SP;

  SKIP_WHITESPACE ();
  if (*input_line_pointer == '$')
    {
      char *s = input_line_pointer;
      char c = get_symbol_end ();
      symbolS *sym = md_undefined_symbol (s);

      *strchr (s, '\0') = c;
      if (sym && (framereg = S_GET_VALUE (sym)) <= 31)
       goto found;
    }
  as_warn (_("frame reg expected, using $%d."), framereg);

found:
  note_gpreg (framereg);
  return framereg;
}

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int tc_mips_regname_to_dw2regnum ( char *  regname)

Definition at line 15006 of file tc-mips.c.

{
  unsigned int regnum = -1;
  unsigned int reg;

  if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
    regnum = reg;

  return regnum;
}

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Variable Documentation

Definition at line 255 of file tc-mips.c.

Definition at line 254 of file tc-mips.c.