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cell-binutils  2.17cvs20070401
tc-mips.c
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00001 /* tc-mips.c -- assemble code for a MIPS chip.
00002    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
00003    2003, 2004, 2005, 2006 Free Software Foundation, Inc.
00004    Contributed by the OSF and Ralph Campbell.
00005    Written by Keith Knowles and Ralph Campbell, working independently.
00006    Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
00007    Support.
00008 
00009    This file is part of GAS.
00010 
00011    GAS is free software; you can redistribute it and/or modify
00012    it under the terms of the GNU General Public License as published by
00013    the Free Software Foundation; either version 2, or (at your option)
00014    any later version.
00015 
00016    GAS is distributed in the hope that it will be useful,
00017    but WITHOUT ANY WARRANTY; without even the implied warranty of
00018    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019    GNU General Public License for more details.
00020 
00021    You should have received a copy of the GNU General Public License
00022    along with GAS; see the file COPYING.  If not, write to the Free
00023    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00024    02110-1301, USA.  */
00025 
00026 #include "as.h"
00027 #include "config.h"
00028 #include "subsegs.h"
00029 #include "safe-ctype.h"
00030 
00031 #include "opcode/mips.h"
00032 #include "itbl-ops.h"
00033 #include "dwarf2dbg.h"
00034 #include "dw2gencfi.h"
00035 
00036 #ifdef DEBUG
00037 #define DBG(x) printf x
00038 #else
00039 #define DBG(x)
00040 #endif
00041 
00042 #ifdef OBJ_MAYBE_ELF
00043 /* Clean up namespace so we can include obj-elf.h too.  */
00044 static int mips_output_flavor (void);
00045 static int mips_output_flavor (void) { return OUTPUT_FLAVOR; }
00046 #undef OBJ_PROCESS_STAB
00047 #undef OUTPUT_FLAVOR
00048 #undef S_GET_ALIGN
00049 #undef S_GET_SIZE
00050 #undef S_SET_ALIGN
00051 #undef S_SET_SIZE
00052 #undef obj_frob_file
00053 #undef obj_frob_file_after_relocs
00054 #undef obj_frob_symbol
00055 #undef obj_pop_insert
00056 #undef obj_sec_sym_ok_for_reloc
00057 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
00058 
00059 #include "obj-elf.h"
00060 /* Fix any of them that we actually care about.  */
00061 #undef OUTPUT_FLAVOR
00062 #define OUTPUT_FLAVOR mips_output_flavor()
00063 #endif
00064 
00065 #if defined (OBJ_ELF)
00066 #include "elf/mips.h"
00067 #endif
00068 
00069 #ifndef ECOFF_DEBUGGING
00070 #define NO_ECOFF_DEBUGGING
00071 #define ECOFF_DEBUGGING 0
00072 #endif
00073 
00074 int mips_flag_mdebug = -1;
00075 
00076 /* Control generation of .pdr sections.  Off by default on IRIX: the native
00077    linker doesn't know about and discards them, but relocations against them
00078    remain, leading to rld crashes.  */
00079 #ifdef TE_IRIX
00080 int mips_flag_pdr = FALSE;
00081 #else
00082 int mips_flag_pdr = TRUE;
00083 #endif
00084 
00085 #include "ecoff.h"
00086 
00087 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
00088 static char *mips_regmask_frag;
00089 #endif
00090 
00091 #define ZERO 0
00092 #define AT  1
00093 #define TREG 24
00094 #define PIC_CALL_REG 25
00095 #define KT0 26
00096 #define KT1 27
00097 #define GP  28
00098 #define SP  29
00099 #define FP  30
00100 #define RA  31
00101 
00102 #define ILLEGAL_REG (32)
00103 
00104 /* Allow override of standard little-endian ECOFF format.  */
00105 
00106 #ifndef ECOFF_LITTLE_FORMAT
00107 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
00108 #endif
00109 
00110 extern int target_big_endian;
00111 
00112 /* The name of the readonly data section.  */
00113 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
00114                          ? ".rdata" \
00115                          : OUTPUT_FLAVOR == bfd_target_coff_flavour \
00116                          ? ".rdata" \
00117                          : OUTPUT_FLAVOR == bfd_target_elf_flavour \
00118                          ? ".rodata" \
00119                          : (abort (), ""))
00120 
00121 /* Information about an instruction, including its format, operands
00122    and fixups.  */
00123 struct mips_cl_insn
00124 {
00125   /* The opcode's entry in mips_opcodes or mips16_opcodes.  */
00126   const struct mips_opcode *insn_mo;
00127 
00128   /* True if this is a mips16 instruction and if we want the extended
00129      form of INSN_MO.  */
00130   bfd_boolean use_extend;
00131 
00132   /* The 16-bit extension instruction to use when USE_EXTEND is true.  */
00133   unsigned short extend;
00134 
00135   /* The 16-bit or 32-bit bitstring of the instruction itself.  This is
00136      a copy of INSN_MO->match with the operands filled in.  */
00137   unsigned long insn_opcode;
00138 
00139   /* The frag that contains the instruction.  */
00140   struct frag *frag;
00141 
00142   /* The offset into FRAG of the first instruction byte.  */
00143   long where;
00144 
00145   /* The relocs associated with the instruction, if any.  */
00146   fixS *fixp[3];
00147 
00148   /* True if this entry cannot be moved from its current position.  */
00149   unsigned int fixed_p : 1;
00150 
00151   /* True if this instruction occurred in a .set noreorder block.  */
00152   unsigned int noreorder_p : 1;
00153 
00154   /* True for mips16 instructions that jump to an absolute address.  */
00155   unsigned int mips16_absolute_jump_p : 1;
00156 };
00157 
00158 /* The ABI to use.  */
00159 enum mips_abi_level
00160 {
00161   NO_ABI = 0,
00162   O32_ABI,
00163   O64_ABI,
00164   N32_ABI,
00165   N64_ABI,
00166   EABI_ABI
00167 };
00168 
00169 /* MIPS ABI we are using for this output file.  */
00170 static enum mips_abi_level mips_abi = NO_ABI;
00171 
00172 /* Whether or not we have code that can call pic code.  */
00173 int mips_abicalls = FALSE;
00174 
00175 /* Whether or not we have code which can be put into a shared
00176    library.  */
00177 static bfd_boolean mips_in_shared = TRUE;
00178 
00179 /* This is the set of options which may be modified by the .set
00180    pseudo-op.  We use a struct so that .set push and .set pop are more
00181    reliable.  */
00182 
00183 struct mips_set_options
00184 {
00185   /* MIPS ISA (Instruction Set Architecture) level.  This is set to -1
00186      if it has not been initialized.  Changed by `.set mipsN', and the
00187      -mipsN command line option, and the default CPU.  */
00188   int isa;
00189   /* Enabled Application Specific Extensions (ASEs).  These are set to -1
00190      if they have not been initialized.  Changed by `.set <asename>', by
00191      command line options, and based on the default architecture.  */
00192   int ase_mips3d;
00193   int ase_mdmx;
00194   int ase_smartmips;
00195   int ase_dsp;
00196   int ase_dspr2;
00197   int ase_mt;
00198   /* Whether we are assembling for the mips16 processor.  0 if we are
00199      not, 1 if we are, and -1 if the value has not been initialized.
00200      Changed by `.set mips16' and `.set nomips16', and the -mips16 and
00201      -nomips16 command line options, and the default CPU.  */
00202   int mips16;
00203   /* Non-zero if we should not reorder instructions.  Changed by `.set
00204      reorder' and `.set noreorder'.  */
00205   int noreorder;
00206   /* Non-zero if we should not permit the $at ($1) register to be used
00207      in instructions.  Changed by `.set at' and `.set noat'.  */
00208   int noat;
00209   /* Non-zero if we should warn when a macro instruction expands into
00210      more than one machine instruction.  Changed by `.set nomacro' and
00211      `.set macro'.  */
00212   int warn_about_macros;
00213   /* Non-zero if we should not move instructions.  Changed by `.set
00214      move', `.set volatile', `.set nomove', and `.set novolatile'.  */
00215   int nomove;
00216   /* Non-zero if we should not optimize branches by moving the target
00217      of the branch into the delay slot.  Actually, we don't perform
00218      this optimization anyhow.  Changed by `.set bopt' and `.set
00219      nobopt'.  */
00220   int nobopt;
00221   /* Non-zero if we should not autoextend mips16 instructions.
00222      Changed by `.set autoextend' and `.set noautoextend'.  */
00223   int noautoextend;
00224   /* Restrict general purpose registers and floating point registers
00225      to 32 bit.  This is initially determined when -mgp32 or -mfp32
00226      is passed but can changed if the assembler code uses .set mipsN.  */
00227   int gp32;
00228   int fp32;
00229   /* MIPS architecture (CPU) type.  Changed by .set arch=FOO, the -march
00230      command line option, and the default CPU.  */
00231   int arch;
00232   /* True if ".set sym32" is in effect.  */
00233   bfd_boolean sym32;
00234 };
00235 
00236 /* True if -mgp32 was passed.  */
00237 static int file_mips_gp32 = -1;
00238 
00239 /* True if -mfp32 was passed.  */
00240 static int file_mips_fp32 = -1;
00241 
00242 /* This is the struct we use to hold the current set of options.  Note
00243    that we must set the isa field to ISA_UNKNOWN and the ASE fields to
00244    -1 to indicate that they have not been initialized.  */
00245 
00246 static struct mips_set_options mips_opts =
00247 {
00248   ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
00249 };
00250 
00251 /* These variables are filled in with the masks of registers used.
00252    The object format code reads them and puts them in the appropriate
00253    place.  */
00254 unsigned long mips_gprmask;
00255 unsigned long mips_cprmask[4];
00256 
00257 /* MIPS ISA we are using for this output file.  */
00258 static int file_mips_isa = ISA_UNKNOWN;
00259 
00260 /* True if -mips16 was passed or implied by arguments passed on the
00261    command line (e.g., by -march).  */
00262 static int file_ase_mips16;
00263 
00264 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32             \
00265                            || mips_opts.isa == ISA_MIPS32R2           \
00266                            || mips_opts.isa == ISA_MIPS64             \
00267                            || mips_opts.isa == ISA_MIPS64R2)
00268 
00269 /* True if -mips3d was passed or implied by arguments passed on the
00270    command line (e.g., by -march).  */
00271 static int file_ase_mips3d;
00272 
00273 /* True if -mdmx was passed or implied by arguments passed on the
00274    command line (e.g., by -march).  */
00275 static int file_ase_mdmx;
00276 
00277 /* True if -msmartmips was passed or implied by arguments passed on the
00278    command line (e.g., by -march).  */
00279 static int file_ase_smartmips;
00280 
00281 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32           \
00282                             || mips_opts.isa == ISA_MIPS32R2)
00283 
00284 /* True if -mdsp was passed or implied by arguments passed on the
00285    command line (e.g., by -march).  */
00286 static int file_ase_dsp;
00287 
00288 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2           \
00289                            || mips_opts.isa == ISA_MIPS64R2)
00290 
00291 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
00292 
00293 /* True if -mdspr2 was passed or implied by arguments passed on the
00294    command line (e.g., by -march).  */
00295 static int file_ase_dspr2;
00296 
00297 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2         \
00298                              || mips_opts.isa == ISA_MIPS64R2)
00299 
00300 /* True if -mmt was passed or implied by arguments passed on the
00301    command line (e.g., by -march).  */
00302 static int file_ase_mt;
00303 
00304 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2            \
00305                           || mips_opts.isa == ISA_MIPS64R2)
00306 
00307 /* The argument of the -march= flag.  The architecture we are assembling.  */
00308 static int file_mips_arch = CPU_UNKNOWN;
00309 static const char *mips_arch_string;
00310 
00311 /* The argument of the -mtune= flag.  The architecture for which we
00312    are optimizing.  */
00313 static int mips_tune = CPU_UNKNOWN;
00314 static const char *mips_tune_string;
00315 
00316 /* True when generating 32-bit code for a 64-bit processor.  */
00317 static int mips_32bitmode = 0;
00318 
00319 /* True if the given ABI requires 32-bit registers.  */
00320 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
00321 
00322 /* Likewise 64-bit registers.  */
00323 #define ABI_NEEDS_64BIT_REGS(ABI)  \
00324   ((ABI) == N32_ABI                \
00325    || (ABI) == N64_ABI                    \
00326    || (ABI) == O64_ABI)
00327 
00328 /*  Return true if ISA supports 64 bit wide gp registers.  */
00329 #define ISA_HAS_64BIT_REGS(ISA)           \
00330   ((ISA) == ISA_MIPS3                     \
00331    || (ISA) == ISA_MIPS4           \
00332    || (ISA) == ISA_MIPS5           \
00333    || (ISA) == ISA_MIPS64          \
00334    || (ISA) == ISA_MIPS64R2)
00335 
00336 /*  Return true if ISA supports 64 bit wide float registers.  */
00337 #define ISA_HAS_64BIT_FPRS(ISA)           \
00338   ((ISA) == ISA_MIPS3                     \
00339    || (ISA) == ISA_MIPS4           \
00340    || (ISA) == ISA_MIPS5           \
00341    || (ISA) == ISA_MIPS32R2        \
00342    || (ISA) == ISA_MIPS64          \
00343    || (ISA) == ISA_MIPS64R2)
00344 
00345 /* Return true if ISA supports 64-bit right rotate (dror et al.)
00346    instructions.  */
00347 #define ISA_HAS_DROR(ISA)          \
00348   ((ISA) == ISA_MIPS64R2)
00349 
00350 /* Return true if ISA supports 32-bit right rotate (ror et al.)
00351    instructions.  */
00352 #define ISA_HAS_ROR(ISA)           \
00353   ((ISA) == ISA_MIPS32R2           \
00354    || (ISA) == ISA_MIPS64R2        \
00355    || mips_opts.ase_smartmips)
00356 
00357 /* Return true if ISA supports single-precision floats in odd registers.  */
00358 #define ISA_HAS_ODD_SINGLE_FPR(ISA)       \
00359   ((ISA) == ISA_MIPS32                    \
00360    || (ISA) == ISA_MIPS32R2        \
00361    || (ISA) == ISA_MIPS64          \
00362    || (ISA) == ISA_MIPS64R2)
00363 
00364 /* Return true if ISA supports move to/from high part of a 64-bit
00365    floating-point register. */
00366 #define ISA_HAS_MXHC1(ISA)         \
00367   ((ISA) == ISA_MIPS32R2           \
00368    || (ISA) == ISA_MIPS64R2)
00369 
00370 #define HAVE_32BIT_GPRS                               \
00371     (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
00372 
00373 #define HAVE_32BIT_FPRS                            \
00374     (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
00375 
00376 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
00377 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
00378 
00379 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
00380 
00381 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
00382 
00383 /* True if relocations are stored in-place.  */
00384 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
00385 
00386 /* The ABI-derived address size.  */
00387 #define HAVE_64BIT_ADDRESSES \
00388   (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
00389 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
00390 
00391 /* The size of symbolic constants (i.e., expressions of the form
00392    "SYMBOL" or "SYMBOL + OFFSET").  */
00393 #define HAVE_32BIT_SYMBOLS \
00394   (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
00395 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
00396 
00397 /* Addresses are loaded in different ways, depending on the address size
00398    in use.  The n32 ABI Documentation also mandates the use of additions
00399    with overflow checking, but existing implementations don't follow it.  */
00400 #define ADDRESS_ADD_INSN                                       \
00401    (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
00402 
00403 #define ADDRESS_ADDI_INSN                                      \
00404    (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
00405 
00406 #define ADDRESS_LOAD_INSN                                      \
00407    (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
00408 
00409 #define ADDRESS_STORE_INSN                                     \
00410    (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
00411 
00412 /* Return true if the given CPU supports the MIPS16 ASE.  */
00413 #define CPU_HAS_MIPS16(cpu)                                    \
00414    (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0        \
00415     || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
00416 
00417 /* True if CPU has a dror instruction.  */
00418 #define CPU_HAS_DROR(CPU)   ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
00419 
00420 /* True if CPU has a ror instruction.  */
00421 #define CPU_HAS_ROR(CPU)    CPU_HAS_DROR (CPU)
00422 
00423 /* True if mflo and mfhi can be immediately followed by instructions
00424    which write to the HI and LO registers.
00425 
00426    According to MIPS specifications, MIPS ISAs I, II, and III need
00427    (at least) two instructions between the reads of HI/LO and
00428    instructions which write them, and later ISAs do not.  Contradicting
00429    the MIPS specifications, some MIPS IV processor user manuals (e.g.
00430    the UM for the NEC Vr5000) document needing the instructions between
00431    HI/LO reads and writes, as well.  Therefore, we declare only MIPS32,
00432    MIPS64 and later ISAs to have the interlocks, plus any specific
00433    earlier-ISA CPUs for which CPU documentation declares that the
00434    instructions are really interlocked.  */
00435 #define hilo_interlocks \
00436   (mips_opts.isa == ISA_MIPS32                        \
00437    || mips_opts.isa == ISA_MIPS32R2                   \
00438    || mips_opts.isa == ISA_MIPS64                     \
00439    || mips_opts.isa == ISA_MIPS64R2                   \
00440    || mips_opts.arch == CPU_R4010                     \
00441    || mips_opts.arch == CPU_R10000                    \
00442    || mips_opts.arch == CPU_R12000                    \
00443    || mips_opts.arch == CPU_RM7000                    \
00444    || mips_opts.arch == CPU_VR5500                    \
00445    )
00446 
00447 /* Whether the processor uses hardware interlocks to protect reads
00448    from the GPRs after they are loaded from memory, and thus does not
00449    require nops to be inserted.  This applies to instructions marked
00450    INSN_LOAD_MEMORY_DELAY.  These nops are only required at MIPS ISA
00451    level I.  */
00452 #define gpr_interlocks \
00453   (mips_opts.isa != ISA_MIPS1  \
00454    || mips_opts.arch == CPU_R3900)
00455 
00456 /* Whether the processor uses hardware interlocks to avoid delays
00457    required by coprocessor instructions, and thus does not require
00458    nops to be inserted.  This applies to instructions marked
00459    INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
00460    between instructions marked INSN_WRITE_COND_CODE and ones marked
00461    INSN_READ_COND_CODE.  These nops are only required at MIPS ISA
00462    levels I, II, and III.  */
00463 /* Itbl support may require additional care here.  */
00464 #define cop_interlocks                                \
00465   ((mips_opts.isa != ISA_MIPS1                        \
00466     && mips_opts.isa != ISA_MIPS2                     \
00467     && mips_opts.isa != ISA_MIPS3)                    \
00468    || mips_opts.arch == CPU_R4300                     \
00469    )
00470 
00471 /* Whether the processor uses hardware interlocks to protect reads
00472    from coprocessor registers after they are loaded from memory, and
00473    thus does not require nops to be inserted.  This applies to
00474    instructions marked INSN_COPROC_MEMORY_DELAY.  These nops are only
00475    requires at MIPS ISA level I.  */
00476 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
00477 
00478 /* Is this a mfhi or mflo instruction?  */
00479 #define MF_HILO_INSN(PINFO) \
00480           ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
00481 
00482 /* MIPS PIC level.  */
00483 
00484 enum mips_pic_level mips_pic;
00485 
00486 /* 1 if we should generate 32 bit offsets from the $gp register in
00487    SVR4_PIC mode.  Currently has no meaning in other modes.  */
00488 static int mips_big_got = 0;
00489 
00490 /* 1 if trap instructions should used for overflow rather than break
00491    instructions.  */
00492 static int mips_trap = 0;
00493 
00494 /* 1 if double width floating point constants should not be constructed
00495    by assembling two single width halves into two single width floating
00496    point registers which just happen to alias the double width destination
00497    register.  On some architectures this aliasing can be disabled by a bit
00498    in the status register, and the setting of this bit cannot be determined
00499    automatically at assemble time.  */
00500 static int mips_disable_float_construction;
00501 
00502 /* Non-zero if any .set noreorder directives were used.  */
00503 
00504 static int mips_any_noreorder;
00505 
00506 /* Non-zero if nops should be inserted when the register referenced in
00507    an mfhi/mflo instruction is read in the next two instructions.  */
00508 static int mips_7000_hilo_fix;
00509 
00510 /* The size of the small data section.  */
00511 static unsigned int g_switch_value = 8;
00512 /* Whether the -G option was used.  */
00513 static int g_switch_seen = 0;
00514 
00515 #define N_RMASK 0xc4
00516 #define N_VFP   0xd4
00517 
00518 /* If we can determine in advance that GP optimization won't be
00519    possible, we can skip the relaxation stuff that tries to produce
00520    GP-relative references.  This makes delay slot optimization work
00521    better.
00522 
00523    This function can only provide a guess, but it seems to work for
00524    gcc output.  It needs to guess right for gcc, otherwise gcc
00525    will put what it thinks is a GP-relative instruction in a branch
00526    delay slot.
00527 
00528    I don't know if a fix is needed for the SVR4_PIC mode.  I've only
00529    fixed it for the non-PIC mode.  KR 95/04/07  */
00530 static int nopic_need_relax (symbolS *, int);
00531 
00532 /* handle of the OPCODE hash table */
00533 static struct hash_control *op_hash = NULL;
00534 
00535 /* The opcode hash table we use for the mips16.  */
00536 static struct hash_control *mips16_op_hash = NULL;
00537 
00538 /* This array holds the chars that always start a comment.  If the
00539     pre-processor is disabled, these aren't very useful */
00540 const char comment_chars[] = "#";
00541 
00542 /* This array holds the chars that only start a comment at the beginning of
00543    a line.  If the line seems to have the form '# 123 filename'
00544    .line and .file directives will appear in the pre-processed output */
00545 /* Note that input_file.c hand checks for '#' at the beginning of the
00546    first line of the input file.  This is because the compiler outputs
00547    #NO_APP at the beginning of its output.  */
00548 /* Also note that C style comments are always supported.  */
00549 const char line_comment_chars[] = "#";
00550 
00551 /* This array holds machine specific line separator characters.  */
00552 const char line_separator_chars[] = ";";
00553 
00554 /* Chars that can be used to separate mant from exp in floating point nums */
00555 const char EXP_CHARS[] = "eE";
00556 
00557 /* Chars that mean this number is a floating point constant */
00558 /* As in 0f12.456 */
00559 /* or    0d1.2345e12 */
00560 const char FLT_CHARS[] = "rRsSfFdDxXpP";
00561 
00562 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
00563    changed in read.c .  Ideally it shouldn't have to know about it at all,
00564    but nothing is ideal around here.
00565  */
00566 
00567 static char *insn_error;
00568 
00569 static int auto_align = 1;
00570 
00571 /* When outputting SVR4 PIC code, the assembler needs to know the
00572    offset in the stack frame from which to restore the $gp register.
00573    This is set by the .cprestore pseudo-op, and saved in this
00574    variable.  */
00575 static offsetT mips_cprestore_offset = -1;
00576 
00577 /* Similar for NewABI PIC code, where $gp is callee-saved.  NewABI has some
00578    more optimizations, it can use a register value instead of a memory-saved
00579    offset and even an other register than $gp as global pointer.  */
00580 static offsetT mips_cpreturn_offset = -1;
00581 static int mips_cpreturn_register = -1;
00582 static int mips_gp_register = GP;
00583 static int mips_gprel_offset = 0;
00584 
00585 /* Whether mips_cprestore_offset has been set in the current function
00586    (or whether it has already been warned about, if not).  */
00587 static int mips_cprestore_valid = 0;
00588 
00589 /* This is the register which holds the stack frame, as set by the
00590    .frame pseudo-op.  This is needed to implement .cprestore.  */
00591 static int mips_frame_reg = SP;
00592 
00593 /* Whether mips_frame_reg has been set in the current function
00594    (or whether it has already been warned about, if not).  */
00595 static int mips_frame_reg_valid = 0;
00596 
00597 /* To output NOP instructions correctly, we need to keep information
00598    about the previous two instructions.  */
00599 
00600 /* Whether we are optimizing.  The default value of 2 means to remove
00601    unneeded NOPs and swap branch instructions when possible.  A value
00602    of 1 means to not swap branches.  A value of 0 means to always
00603    insert NOPs.  */
00604 static int mips_optimize = 2;
00605 
00606 /* Debugging level.  -g sets this to 2.  -gN sets this to N.  -g0 is
00607    equivalent to seeing no -g option at all.  */
00608 static int mips_debug = 0;
00609 
00610 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata.  */
00611 #define MAX_VR4130_NOPS 4
00612 
00613 /* The maximum number of NOPs needed to fill delay slots.  */
00614 #define MAX_DELAY_NOPS 2
00615 
00616 /* The maximum number of NOPs needed for any purpose.  */
00617 #define MAX_NOPS 4
00618 
00619 /* A list of previous instructions, with index 0 being the most recent.
00620    We need to look back MAX_NOPS instructions when filling delay slots
00621    or working around processor errata.  We need to look back one
00622    instruction further if we're thinking about using history[0] to
00623    fill a branch delay slot.  */
00624 static struct mips_cl_insn history[1 + MAX_NOPS];
00625 
00626 /* Nop instructions used by emit_nop.  */
00627 static struct mips_cl_insn nop_insn, mips16_nop_insn;
00628 
00629 /* The appropriate nop for the current mode.  */
00630 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
00631 
00632 /* If this is set, it points to a frag holding nop instructions which
00633    were inserted before the start of a noreorder section.  If those
00634    nops turn out to be unnecessary, the size of the frag can be
00635    decreased.  */
00636 static fragS *prev_nop_frag;
00637 
00638 /* The number of nop instructions we created in prev_nop_frag.  */
00639 static int prev_nop_frag_holds;
00640 
00641 /* The number of nop instructions that we know we need in
00642    prev_nop_frag.  */
00643 static int prev_nop_frag_required;
00644 
00645 /* The number of instructions we've seen since prev_nop_frag.  */
00646 static int prev_nop_frag_since;
00647 
00648 /* For ECOFF and ELF, relocations against symbols are done in two
00649    parts, with a HI relocation and a LO relocation.  Each relocation
00650    has only 16 bits of space to store an addend.  This means that in
00651    order for the linker to handle carries correctly, it must be able
00652    to locate both the HI and the LO relocation.  This means that the
00653    relocations must appear in order in the relocation table.
00654 
00655    In order to implement this, we keep track of each unmatched HI
00656    relocation.  We then sort them so that they immediately precede the
00657    corresponding LO relocation.  */
00658 
00659 struct mips_hi_fixup
00660 {
00661   /* Next HI fixup.  */
00662   struct mips_hi_fixup *next;
00663   /* This fixup.  */
00664   fixS *fixp;
00665   /* The section this fixup is in.  */
00666   segT seg;
00667 };
00668 
00669 /* The list of unmatched HI relocs.  */
00670 
00671 static struct mips_hi_fixup *mips_hi_fixup_list;
00672 
00673 /* The frag containing the last explicit relocation operator.
00674    Null if explicit relocations have not been used.  */
00675 
00676 static fragS *prev_reloc_op_frag;
00677 
00678 /* Map normal MIPS register numbers to mips16 register numbers.  */
00679 
00680 #define X ILLEGAL_REG
00681 static const int mips32_to_16_reg_map[] =
00682 {
00683   X, X, 2, 3, 4, 5, 6, 7,
00684   X, X, X, X, X, X, X, X,
00685   0, 1, X, X, X, X, X, X,
00686   X, X, X, X, X, X, X, X
00687 };
00688 #undef X
00689 
00690 /* Map mips16 register numbers to normal MIPS register numbers.  */
00691 
00692 static const unsigned int mips16_to_32_reg_map[] =
00693 {
00694   16, 17, 2, 3, 4, 5, 6, 7
00695 };
00696 
00697 /* Classifies the kind of instructions we're interested in when
00698    implementing -mfix-vr4120.  */
00699 enum fix_vr4120_class {
00700   FIX_VR4120_MACC,
00701   FIX_VR4120_DMACC,
00702   FIX_VR4120_MULT,
00703   FIX_VR4120_DMULT,
00704   FIX_VR4120_DIV,
00705   FIX_VR4120_MTHILO,
00706   NUM_FIX_VR4120_CLASSES
00707 };
00708 
00709 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
00710    there must be at least one other instruction between an instruction
00711    of type X and an instruction of type Y.  */
00712 static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
00713 
00714 /* True if -mfix-vr4120 is in force.  */
00715 static int mips_fix_vr4120;
00716 
00717 /* ...likewise -mfix-vr4130.  */
00718 static int mips_fix_vr4130;
00719 
00720 /* We don't relax branches by default, since this causes us to expand
00721    `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
00722    fail to compute the offset before expanding the macro to the most
00723    efficient expansion.  */
00724 
00725 static int mips_relax_branch;
00726 
00727 /* The expansion of many macros depends on the type of symbol that
00728    they refer to.  For example, when generating position-dependent code,
00729    a macro that refers to a symbol may have two different expansions,
00730    one which uses GP-relative addresses and one which uses absolute
00731    addresses.  When generating SVR4-style PIC, a macro may have
00732    different expansions for local and global symbols.
00733 
00734    We handle these situations by generating both sequences and putting
00735    them in variant frags.  In position-dependent code, the first sequence
00736    will be the GP-relative one and the second sequence will be the
00737    absolute one.  In SVR4 PIC, the first sequence will be for global
00738    symbols and the second will be for local symbols.
00739 
00740    The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
00741    SECOND are the lengths of the two sequences in bytes.  These fields
00742    can be extracted using RELAX_FIRST() and RELAX_SECOND().  In addition,
00743    the subtype has the following flags:
00744 
00745    RELAX_USE_SECOND
00746        Set if it has been decided that we should use the second
00747        sequence instead of the first.
00748 
00749    RELAX_SECOND_LONGER
00750        Set in the first variant frag if the macro's second implementation
00751        is longer than its first.  This refers to the macro as a whole,
00752        not an individual relaxation.
00753 
00754    RELAX_NOMACRO
00755        Set in the first variant frag if the macro appeared in a .set nomacro
00756        block and if one alternative requires a warning but the other does not.
00757 
00758    RELAX_DELAY_SLOT
00759        Like RELAX_NOMACRO, but indicates that the macro appears in a branch
00760        delay slot.
00761 
00762    The frag's "opcode" points to the first fixup for relaxable code.
00763 
00764    Relaxable macros are generated using a sequence such as:
00765 
00766       relax_start (SYMBOL);
00767       ... generate first expansion ...
00768       relax_switch ();
00769       ... generate second expansion ...
00770       relax_end ();
00771 
00772    The code and fixups for the unwanted alternative are discarded
00773    by md_convert_frag.  */
00774 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
00775 
00776 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
00777 #define RELAX_SECOND(X) ((X) & 0xff)
00778 #define RELAX_USE_SECOND 0x10000
00779 #define RELAX_SECOND_LONGER 0x20000
00780 #define RELAX_NOMACRO 0x40000
00781 #define RELAX_DELAY_SLOT 0x80000
00782 
00783 /* Branch without likely bit.  If label is out of range, we turn:
00784 
00785        beq reg1, reg2, label
00786        delay slot
00787 
00788    into
00789 
00790         bne reg1, reg2, 0f
00791         nop
00792         j label
00793      0: delay slot
00794 
00795    with the following opcode replacements:
00796 
00797        beq <-> bne
00798        blez <-> bgtz
00799        bltz <-> bgez
00800        bc1f <-> bc1t
00801 
00802        bltzal <-> bgezal  (with jal label instead of j label)
00803 
00804    Even though keeping the delay slot instruction in the delay slot of
00805    the branch would be more efficient, it would be very tricky to do
00806    correctly, because we'd have to introduce a variable frag *after*
00807    the delay slot instruction, and expand that instead.  Let's do it
00808    the easy way for now, even if the branch-not-taken case now costs
00809    one additional instruction.  Out-of-range branches are not supposed
00810    to be common, anyway.
00811 
00812    Branch likely.  If label is out of range, we turn:
00813 
00814        beql reg1, reg2, label
00815        delay slot (annulled if branch not taken)
00816 
00817    into
00818 
00819         beql reg1, reg2, 1f
00820         nop
00821         beql $0, $0, 2f
00822         nop
00823      1: j[al] label
00824         delay slot (executed only if branch taken)
00825      2:
00826 
00827    It would be possible to generate a shorter sequence by losing the
00828    likely bit, generating something like:
00829 
00830        bne reg1, reg2, 0f
00831        nop
00832        j[al] label
00833        delay slot (executed only if branch taken)
00834      0:
00835 
00836        beql -> bne
00837        bnel -> beq
00838        blezl -> bgtz
00839        bgtzl -> blez
00840        bltzl -> bgez
00841        bgezl -> bltz
00842        bc1fl -> bc1t
00843        bc1tl -> bc1f
00844 
00845        bltzall -> bgezal  (with jal label instead of j label)
00846        bgezall -> bltzal  (ditto)
00847 
00848 
00849    but it's not clear that it would actually improve performance.  */
00850 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
00851   ((relax_substateT) \
00852    (0xc0000000 \
00853     | ((toofar) ? 1 : 0) \
00854     | ((link) ? 2 : 0) \
00855     | ((likely) ? 4 : 0) \
00856     | ((uncond) ? 8 : 0)))
00857 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
00858 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
00859 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
00860 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
00861 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
00862 
00863 /* For mips16 code, we use an entirely different form of relaxation.
00864    mips16 supports two versions of most instructions which take
00865    immediate values: a small one which takes some small value, and a
00866    larger one which takes a 16 bit value.  Since branches also follow
00867    this pattern, relaxing these values is required.
00868 
00869    We can assemble both mips16 and normal MIPS code in a single
00870    object.  Therefore, we need to support this type of relaxation at
00871    the same time that we support the relaxation described above.  We
00872    use the high bit of the subtype field to distinguish these cases.
00873 
00874    The information we store for this type of relaxation is the
00875    argument code found in the opcode file for this relocation, whether
00876    the user explicitly requested a small or extended form, and whether
00877    the relocation is in a jump or jal delay slot.  That tells us the
00878    size of the value, and how it should be stored.  We also store
00879    whether the fragment is considered to be extended or not.  We also
00880    store whether this is known to be a branch to a different section,
00881    whether we have tried to relax this frag yet, and whether we have
00882    ever extended a PC relative fragment because of a shift count.  */
00883 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot)       \
00884   (0x80000000                                           \
00885    | ((type) & 0xff)                                    \
00886    | ((small) ? 0x100 : 0)                              \
00887    | ((ext) ? 0x200 : 0)                                \
00888    | ((dslot) ? 0x400 : 0)                              \
00889    | ((jal_dslot) ? 0x800 : 0))
00890 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
00891 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
00892 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
00893 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
00894 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
00895 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
00896 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
00897 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
00898 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
00899 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
00900 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
00901 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
00902 
00903 /* Is the given value a sign-extended 32-bit value?  */
00904 #define IS_SEXT_32BIT_NUM(x)                                          \
00905   (((x) &~ (offsetT) 0x7fffffff) == 0                                 \
00906    || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
00907 
00908 /* Is the given value a sign-extended 16-bit value?  */
00909 #define IS_SEXT_16BIT_NUM(x)                                          \
00910   (((x) &~ (offsetT) 0x7fff) == 0                              \
00911    || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
00912 
00913 /* Is the given value a zero-extended 32-bit value?  Or a negated one?  */
00914 #define IS_ZEXT_32BIT_NUM(x)                                          \
00915   (((x) &~ (offsetT) 0xffffffff) == 0                                 \
00916    || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
00917 
00918 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
00919    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
00920 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
00921   (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
00922              | (((VALUE) & (MASK)) << (SHIFT)))
00923 
00924 /* Extract bits MASK << SHIFT from STRUCT and shift them right
00925    SHIFT places.  */
00926 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
00927   (((STRUCT) >> (SHIFT)) & (MASK))
00928 
00929 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
00930    INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
00931 
00932    include/opcode/mips.h specifies operand fields using the macros
00933    OP_MASK_<FIELD> and OP_SH_<FIELD>.  The MIPS16 equivalents start
00934    with "MIPS16OP" instead of "OP".  */
00935 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
00936   INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
00937 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
00938   INSERT_BITS ((INSN).insn_opcode, VALUE, \
00939               MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
00940 
00941 /* Extract the operand given by FIELD from mips_cl_insn INSN.  */
00942 #define EXTRACT_OPERAND(FIELD, INSN) \
00943   EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
00944 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
00945   EXTRACT_BITS ((INSN).insn_opcode, \
00946               MIPS16OP_MASK_##FIELD, \
00947               MIPS16OP_SH_##FIELD)
00948 
00949 /* Global variables used when generating relaxable macros.  See the
00950    comment above RELAX_ENCODE for more details about how relaxation
00951    is used.  */
00952 static struct {
00953   /* 0 if we're not emitting a relaxable macro.
00954      1 if we're emitting the first of the two relaxation alternatives.
00955      2 if we're emitting the second alternative.  */
00956   int sequence;
00957 
00958   /* The first relaxable fixup in the current frag.  (In other words,
00959      the first fixup that refers to relaxable code.)  */
00960   fixS *first_fixup;
00961 
00962   /* sizes[0] says how many bytes of the first alternative are stored in
00963      the current frag.  Likewise sizes[1] for the second alternative.  */
00964   unsigned int sizes[2];
00965 
00966   /* The symbol on which the choice of sequence depends.  */
00967   symbolS *symbol;
00968 } mips_relax;
00969 
00970 /* Global variables used to decide whether a macro needs a warning.  */
00971 static struct {
00972   /* True if the macro is in a branch delay slot.  */
00973   bfd_boolean delay_slot_p;
00974 
00975   /* For relaxable macros, sizes[0] is the length of the first alternative
00976      in bytes and sizes[1] is the length of the second alternative.
00977      For non-relaxable macros, both elements give the length of the
00978      macro in bytes.  */
00979   unsigned int sizes[2];
00980 
00981   /* The first variant frag for this macro.  */
00982   fragS *first_frag;
00983 } mips_macro_warning;
00984 
00985 /* Prototypes for static functions.  */
00986 
00987 #define internalError()                                               \
00988     as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
00989 
00990 enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
00991 
00992 static void append_insn
00993   (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
00994 static void mips_no_prev_insn (void);
00995 static void mips16_macro_build
00996   (expressionS *, const char *, const char *, va_list);
00997 static void load_register (int, expressionS *, int);
00998 static void macro_start (void);
00999 static void macro_end (void);
01000 static void macro (struct mips_cl_insn * ip);
01001 static void mips16_macro (struct mips_cl_insn * ip);
01002 #ifdef LOSING_COMPILER
01003 static void macro2 (struct mips_cl_insn * ip);
01004 #endif
01005 static void mips_ip (char *str, struct mips_cl_insn * ip);
01006 static void mips16_ip (char *str, struct mips_cl_insn * ip);
01007 static void mips16_immed
01008   (char *, unsigned int, int, offsetT, bfd_boolean, bfd_boolean, bfd_boolean,
01009    unsigned long *, bfd_boolean *, unsigned short *);
01010 static size_t my_getSmallExpression
01011   (expressionS *, bfd_reloc_code_real_type *, char *);
01012 static void my_getExpression (expressionS *, char *);
01013 static void s_align (int);
01014 static void s_change_sec (int);
01015 static void s_change_section (int);
01016 static void s_cons (int);
01017 static void s_float_cons (int);
01018 static void s_mips_globl (int);
01019 static void s_option (int);
01020 static void s_mipsset (int);
01021 static void s_abicalls (int);
01022 static void s_cpload (int);
01023 static void s_cpsetup (int);
01024 static void s_cplocal (int);
01025 static void s_cprestore (int);
01026 static void s_cpreturn (int);
01027 static void s_gpvalue (int);
01028 static void s_gpword (int);
01029 static void s_gpdword (int);
01030 static void s_cpadd (int);
01031 static void s_insn (int);
01032 static void md_obj_begin (void);
01033 static void md_obj_end (void);
01034 static void s_mips_ent (int);
01035 static void s_mips_end (int);
01036 static void s_mips_frame (int);
01037 static void s_mips_mask (int reg_type);
01038 static void s_mips_stab (int);
01039 static void s_mips_weakext (int);
01040 static void s_mips_file (int);
01041 static void s_mips_loc (int);
01042 static bfd_boolean pic_need_relax (symbolS *, asection *);
01043 static int relaxed_branch_length (fragS *, asection *, int);
01044 static int validate_mips_insn (const struct mips_opcode *);
01045 
01046 /* Table and functions used to map between CPU/ISA names, and
01047    ISA levels, and CPU numbers.  */
01048 
01049 struct mips_cpu_info
01050 {
01051   const char *name;           /* CPU or ISA name.  */
01052   int flags;                  /* ASEs available, or ISA flag.  */
01053   int isa;                    /* ISA level.  */
01054   int cpu;                    /* CPU number (default CPU if ISA).  */
01055 };
01056 
01057 #define MIPS_CPU_IS_ISA            0x0001 /* Is this an ISA?  (If 0, a CPU.) */
01058 #define MIPS_CPU_ASE_SMARTMIPS     0x0002 /* CPU implements SmartMIPS ASE */
01059 #define MIPS_CPU_ASE_DSP    0x0004 /* CPU implements DSP ASE */
01060 #define MIPS_CPU_ASE_MT            0x0008 /* CPU implements MT ASE */
01061 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
01062 #define MIPS_CPU_ASE_MDMX   0x0020 /* CPU implements MDMX ASE */
01063 #define MIPS_CPU_ASE_DSPR2  0x0040 /* CPU implements DSP R2 ASE */
01064 
01065 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
01066 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
01067 static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
01068 
01069 /* Pseudo-op table.
01070 
01071    The following pseudo-ops from the Kane and Heinrich MIPS book
01072    should be defined here, but are currently unsupported: .alias,
01073    .galive, .gjaldef, .gjrlive, .livereg, .noalias.
01074 
01075    The following pseudo-ops from the Kane and Heinrich MIPS book are
01076    specific to the type of debugging information being generated, and
01077    should be defined by the object format: .aent, .begin, .bend,
01078    .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
01079    .vreg.
01080 
01081    The following pseudo-ops from the Kane and Heinrich MIPS book are
01082    not MIPS CPU specific, but are also not specific to the object file
01083    format.  This file is probably the best place to define them, but
01084    they are not currently supported: .asm0, .endr, .lab, .struct.  */
01085 
01086 static const pseudo_typeS mips_pseudo_table[] =
01087 {
01088   /* MIPS specific pseudo-ops.  */
01089   {"option", s_option, 0},
01090   {"set", s_mipsset, 0},
01091   {"rdata", s_change_sec, 'r'},
01092   {"sdata", s_change_sec, 's'},
01093   {"livereg", s_ignore, 0},
01094   {"abicalls", s_abicalls, 0},
01095   {"cpload", s_cpload, 0},
01096   {"cpsetup", s_cpsetup, 0},
01097   {"cplocal", s_cplocal, 0},
01098   {"cprestore", s_cprestore, 0},
01099   {"cpreturn", s_cpreturn, 0},
01100   {"gpvalue", s_gpvalue, 0},
01101   {"gpword", s_gpword, 0},
01102   {"gpdword", s_gpdword, 0},
01103   {"cpadd", s_cpadd, 0},
01104   {"insn", s_insn, 0},
01105 
01106   /* Relatively generic pseudo-ops that happen to be used on MIPS
01107      chips.  */
01108   {"asciiz", stringer, 1},
01109   {"bss", s_change_sec, 'b'},
01110   {"err", s_err, 0},
01111   {"half", s_cons, 1},
01112   {"dword", s_cons, 3},
01113   {"weakext", s_mips_weakext, 0},
01114   {"origin", s_org, 0},
01115   {"repeat", s_rept, 0},
01116 
01117   /* These pseudo-ops are defined in read.c, but must be overridden
01118      here for one reason or another.  */
01119   {"align", s_align, 0},
01120   {"byte", s_cons, 0},
01121   {"data", s_change_sec, 'd'},
01122   {"double", s_float_cons, 'd'},
01123   {"float", s_float_cons, 'f'},
01124   {"globl", s_mips_globl, 0},
01125   {"global", s_mips_globl, 0},
01126   {"hword", s_cons, 1},
01127   {"int", s_cons, 2},
01128   {"long", s_cons, 2},
01129   {"octa", s_cons, 4},
01130   {"quad", s_cons, 3},
01131   {"section", s_change_section, 0},
01132   {"short", s_cons, 1},
01133   {"single", s_float_cons, 'f'},
01134   {"stabn", s_mips_stab, 'n'},
01135   {"text", s_change_sec, 't'},
01136   {"word", s_cons, 2},
01137 
01138   { "extern", ecoff_directive_extern, 0},
01139 
01140   { NULL, NULL, 0 },
01141 };
01142 
01143 static const pseudo_typeS mips_nonecoff_pseudo_table[] =
01144 {
01145   /* These pseudo-ops should be defined by the object file format.
01146      However, a.out doesn't support them, so we have versions here.  */
01147   {"aent", s_mips_ent, 1},
01148   {"bgnb", s_ignore, 0},
01149   {"end", s_mips_end, 0},
01150   {"endb", s_ignore, 0},
01151   {"ent", s_mips_ent, 0},
01152   {"file", s_mips_file, 0},
01153   {"fmask", s_mips_mask, 'F'},
01154   {"frame", s_mips_frame, 0},
01155   {"loc", s_mips_loc, 0},
01156   {"mask", s_mips_mask, 'R'},
01157   {"verstamp", s_ignore, 0},
01158   { NULL, NULL, 0 },
01159 };
01160 
01161 extern void pop_insert (const pseudo_typeS *);
01162 
01163 void
01164 mips_pop_insert (void)
01165 {
01166   pop_insert (mips_pseudo_table);
01167   if (! ECOFF_DEBUGGING)
01168     pop_insert (mips_nonecoff_pseudo_table);
01169 }
01170 
01171 /* Symbols labelling the current insn.  */
01172 
01173 struct insn_label_list
01174 {
01175   struct insn_label_list *next;
01176   symbolS *label;
01177 };
01178 
01179 static struct insn_label_list *free_insn_labels;
01180 #define label_list tc_segment_info_data
01181 
01182 static void mips_clear_insn_labels (void);
01183 
01184 static inline void
01185 mips_clear_insn_labels (void)
01186 {
01187   register struct insn_label_list **pl;
01188   segment_info_type *si;
01189 
01190   if (now_seg)
01191     {
01192       for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
01193        ;
01194       
01195       si = seg_info (now_seg);
01196       *pl = si->label_list;
01197       si->label_list = NULL;
01198     }
01199 }
01200 
01201 
01202 static char *expr_end;
01203 
01204 /* Expressions which appear in instructions.  These are set by
01205    mips_ip.  */
01206 
01207 static expressionS imm_expr;
01208 static expressionS imm2_expr;
01209 static expressionS offset_expr;
01210 
01211 /* Relocs associated with imm_expr and offset_expr.  */
01212 
01213 static bfd_reloc_code_real_type imm_reloc[3]
01214   = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
01215 static bfd_reloc_code_real_type offset_reloc[3]
01216   = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
01217 
01218 /* These are set by mips16_ip if an explicit extension is used.  */
01219 
01220 static bfd_boolean mips16_small, mips16_ext;
01221 
01222 #ifdef OBJ_ELF
01223 /* The pdr segment for per procedure frame/regmask info.  Not used for
01224    ECOFF debugging.  */
01225 
01226 static segT pdr_seg;
01227 #endif
01228 
01229 /* The default target format to use.  */
01230 
01231 const char *
01232 mips_target_format (void)
01233 {
01234   switch (OUTPUT_FLAVOR)
01235     {
01236     case bfd_target_ecoff_flavour:
01237       return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
01238     case bfd_target_coff_flavour:
01239       return "pe-mips";
01240     case bfd_target_elf_flavour:
01241 #ifdef TE_VXWORKS
01242       if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
01243        return (target_big_endian
01244               ? "elf32-bigmips-vxworks"
01245               : "elf32-littlemips-vxworks");
01246 #endif
01247 #ifdef TE_TMIPS
01248       /* This is traditional mips.  */
01249       return (target_big_endian
01250              ? (HAVE_64BIT_OBJECTS
01251                ? "elf64-tradbigmips"
01252                : (HAVE_NEWABI
01253                   ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
01254              : (HAVE_64BIT_OBJECTS
01255                ? "elf64-tradlittlemips"
01256                : (HAVE_NEWABI
01257                   ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
01258 #else
01259       return (target_big_endian
01260              ? (HAVE_64BIT_OBJECTS
01261                ? "elf64-bigmips"
01262                : (HAVE_NEWABI
01263                   ? "elf32-nbigmips" : "elf32-bigmips"))
01264              : (HAVE_64BIT_OBJECTS
01265                ? "elf64-littlemips"
01266                : (HAVE_NEWABI
01267                   ? "elf32-nlittlemips" : "elf32-littlemips")));
01268 #endif
01269     default:
01270       abort ();
01271       return NULL;
01272     }
01273 }
01274 
01275 /* Return the length of instruction INSN.  */
01276 
01277 static inline unsigned int
01278 insn_length (const struct mips_cl_insn *insn)
01279 {
01280   if (!mips_opts.mips16)
01281     return 4;
01282   return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
01283 }
01284 
01285 /* Initialise INSN from opcode entry MO.  Leave its position unspecified.  */
01286 
01287 static void
01288 create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
01289 {
01290   size_t i;
01291 
01292   insn->insn_mo = mo;
01293   insn->use_extend = FALSE;
01294   insn->extend = 0;
01295   insn->insn_opcode = mo->match;
01296   insn->frag = NULL;
01297   insn->where = 0;
01298   for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
01299     insn->fixp[i] = NULL;
01300   insn->fixed_p = (mips_opts.noreorder > 0);
01301   insn->noreorder_p = (mips_opts.noreorder > 0);
01302   insn->mips16_absolute_jump_p = 0;
01303 }
01304 
01305 /* Install INSN at the location specified by its "frag" and "where" fields.  */
01306 
01307 static void
01308 install_insn (const struct mips_cl_insn *insn)
01309 {
01310   char *f = insn->frag->fr_literal + insn->where;
01311   if (!mips_opts.mips16)
01312     md_number_to_chars (f, insn->insn_opcode, 4);
01313   else if (insn->mips16_absolute_jump_p)
01314     {
01315       md_number_to_chars (f, insn->insn_opcode >> 16, 2);
01316       md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
01317     }
01318   else
01319     {
01320       if (insn->use_extend)
01321        {
01322          md_number_to_chars (f, 0xf000 | insn->extend, 2);
01323          f += 2;
01324        }
01325       md_number_to_chars (f, insn->insn_opcode, 2);
01326     }
01327 }
01328 
01329 /* Move INSN to offset WHERE in FRAG.  Adjust the fixups accordingly
01330    and install the opcode in the new location.  */
01331 
01332 static void
01333 move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
01334 {
01335   size_t i;
01336 
01337   insn->frag = frag;
01338   insn->where = where;
01339   for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
01340     if (insn->fixp[i] != NULL)
01341       {
01342        insn->fixp[i]->fx_frag = frag;
01343        insn->fixp[i]->fx_where = where;
01344       }
01345   install_insn (insn);
01346 }
01347 
01348 /* Add INSN to the end of the output.  */
01349 
01350 static void
01351 add_fixed_insn (struct mips_cl_insn *insn)
01352 {
01353   char *f = frag_more (insn_length (insn));
01354   move_insn (insn, frag_now, f - frag_now->fr_literal);
01355 }
01356 
01357 /* Start a variant frag and move INSN to the start of the variant part,
01358    marking it as fixed.  The other arguments are as for frag_var.  */
01359 
01360 static void
01361 add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
01362                 relax_substateT subtype, symbolS *symbol, offsetT offset)
01363 {
01364   frag_grow (max_chars);
01365   move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
01366   insn->fixed_p = 1;
01367   frag_var (rs_machine_dependent, max_chars, var,
01368            subtype, symbol, offset, NULL);
01369 }
01370 
01371 /* Insert N copies of INSN into the history buffer, starting at
01372    position FIRST.  Neither FIRST nor N need to be clipped.  */
01373 
01374 static void
01375 insert_into_history (unsigned int first, unsigned int n,
01376                    const struct mips_cl_insn *insn)
01377 {
01378   if (mips_relax.sequence != 2)
01379     {
01380       unsigned int i;
01381 
01382       for (i = ARRAY_SIZE (history); i-- > first;)
01383        if (i >= first + n)
01384          history[i] = history[i - n];
01385        else
01386          history[i] = *insn;
01387     }
01388 }
01389 
01390 /* Emit a nop instruction, recording it in the history buffer.  */
01391 
01392 static void
01393 emit_nop (void)
01394 {
01395   add_fixed_insn (NOP_INSN);
01396   insert_into_history (0, 1, NOP_INSN);
01397 }
01398 
01399 /* Initialize vr4120_conflicts.  There is a bit of duplication here:
01400    the idea is to make it obvious at a glance that each errata is
01401    included.  */
01402 
01403 static void
01404 init_vr4120_conflicts (void)
01405 {
01406 #define CONFLICT(FIRST, SECOND) \
01407     vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
01408 
01409   /* Errata 21 - [D]DIV[U] after [D]MACC */
01410   CONFLICT (MACC, DIV);
01411   CONFLICT (DMACC, DIV);
01412 
01413   /* Errata 23 - Continuous DMULT[U]/DMACC instructions.  */
01414   CONFLICT (DMULT, DMULT);
01415   CONFLICT (DMULT, DMACC);
01416   CONFLICT (DMACC, DMULT);
01417   CONFLICT (DMACC, DMACC);
01418 
01419   /* Errata 24 - MT{LO,HI} after [D]MACC */
01420   CONFLICT (MACC, MTHILO);
01421   CONFLICT (DMACC, MTHILO);
01422 
01423   /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
01424      instruction is executed immediately after a MACC or DMACC
01425      instruction, the result of [either instruction] is incorrect."  */
01426   CONFLICT (MACC, MULT);
01427   CONFLICT (MACC, DMULT);
01428   CONFLICT (DMACC, MULT);
01429   CONFLICT (DMACC, DMULT);
01430 
01431   /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
01432      executed immediately after a DMULT, DMULTU, DIV, DIVU,
01433      DDIV or DDIVU instruction, the result of the MACC or
01434      DMACC instruction is incorrect.".  */
01435   CONFLICT (DMULT, MACC);
01436   CONFLICT (DMULT, DMACC);
01437   CONFLICT (DIV, MACC);
01438   CONFLICT (DIV, DMACC);
01439 
01440 #undef CONFLICT
01441 }
01442 
01443 struct regname {
01444   const char *name;
01445   unsigned int num;
01446 };
01447 
01448 #define RTYPE_MASK   0x1ff00
01449 #define RTYPE_NUM    0x00100
01450 #define RTYPE_FPU    0x00200
01451 #define RTYPE_FCC    0x00400
01452 #define RTYPE_VEC    0x00800
01453 #define RTYPE_GP     0x01000
01454 #define RTYPE_CP0    0x02000
01455 #define RTYPE_PC     0x04000
01456 #define RTYPE_ACC    0x08000
01457 #define RTYPE_CCC    0x10000
01458 #define RNUM_MASK    0x000ff
01459 #define RWARN        0x80000
01460 
01461 #define GENERIC_REGISTER_NUMBERS \
01462     {"$0",    RTYPE_NUM | 0},  \
01463     {"$1",    RTYPE_NUM | 1},  \
01464     {"$2",    RTYPE_NUM | 2},  \
01465     {"$3",    RTYPE_NUM | 3},  \
01466     {"$4",    RTYPE_NUM | 4},  \
01467     {"$5",    RTYPE_NUM | 5},  \
01468     {"$6",    RTYPE_NUM | 6},  \
01469     {"$7",    RTYPE_NUM | 7},  \
01470     {"$8",    RTYPE_NUM | 8},  \
01471     {"$9",    RTYPE_NUM | 9},  \
01472     {"$10",   RTYPE_NUM | 10}, \
01473     {"$11",   RTYPE_NUM | 11}, \
01474     {"$12",   RTYPE_NUM | 12}, \
01475     {"$13",   RTYPE_NUM | 13}, \
01476     {"$14",   RTYPE_NUM | 14}, \
01477     {"$15",   RTYPE_NUM | 15}, \
01478     {"$16",   RTYPE_NUM | 16}, \
01479     {"$17",   RTYPE_NUM | 17}, \
01480     {"$18",   RTYPE_NUM | 18}, \
01481     {"$19",   RTYPE_NUM | 19}, \
01482     {"$20",   RTYPE_NUM | 20}, \
01483     {"$21",   RTYPE_NUM | 21}, \
01484     {"$22",   RTYPE_NUM | 22}, \
01485     {"$23",   RTYPE_NUM | 23}, \
01486     {"$24",   RTYPE_NUM | 24}, \
01487     {"$25",   RTYPE_NUM | 25}, \
01488     {"$26",   RTYPE_NUM | 26}, \
01489     {"$27",   RTYPE_NUM | 27}, \
01490     {"$28",   RTYPE_NUM | 28}, \
01491     {"$29",   RTYPE_NUM | 29}, \
01492     {"$30",   RTYPE_NUM | 30}, \
01493     {"$31",   RTYPE_NUM | 31} 
01494 
01495 #define FPU_REGISTER_NAMES       \
01496     {"$f0",   RTYPE_FPU | 0},  \
01497     {"$f1",   RTYPE_FPU | 1},  \
01498     {"$f2",   RTYPE_FPU | 2},  \
01499     {"$f3",   RTYPE_FPU | 3},  \
01500     {"$f4",   RTYPE_FPU | 4},  \
01501     {"$f5",   RTYPE_FPU | 5},  \
01502     {"$f6",   RTYPE_FPU | 6},  \
01503     {"$f7",   RTYPE_FPU | 7},  \
01504     {"$f8",   RTYPE_FPU | 8},  \
01505     {"$f9",   RTYPE_FPU | 9},  \
01506     {"$f10",  RTYPE_FPU | 10}, \
01507     {"$f11",  RTYPE_FPU | 11}, \
01508     {"$f12",  RTYPE_FPU | 12}, \
01509     {"$f13",  RTYPE_FPU | 13}, \
01510     {"$f14",  RTYPE_FPU | 14}, \
01511     {"$f15",  RTYPE_FPU | 15}, \
01512     {"$f16",  RTYPE_FPU | 16}, \
01513     {"$f17",  RTYPE_FPU | 17}, \
01514     {"$f18",  RTYPE_FPU | 18}, \
01515     {"$f19",  RTYPE_FPU | 19}, \
01516     {"$f20",  RTYPE_FPU | 20}, \
01517     {"$f21",  RTYPE_FPU | 21}, \
01518     {"$f22",  RTYPE_FPU | 22}, \
01519     {"$f23",  RTYPE_FPU | 23}, \
01520     {"$f24",  RTYPE_FPU | 24}, \
01521     {"$f25",  RTYPE_FPU | 25}, \
01522     {"$f26",  RTYPE_FPU | 26}, \
01523     {"$f27",  RTYPE_FPU | 27}, \
01524     {"$f28",  RTYPE_FPU | 28}, \
01525     {"$f29",  RTYPE_FPU | 29}, \
01526     {"$f30",  RTYPE_FPU | 30}, \
01527     {"$f31",  RTYPE_FPU | 31}
01528 
01529 #define FPU_CONDITION_CODE_NAMES \
01530     {"$fcc0", RTYPE_FCC | 0},  \
01531     {"$fcc1", RTYPE_FCC | 1},  \
01532     {"$fcc2", RTYPE_FCC | 2},  \
01533     {"$fcc3", RTYPE_FCC | 3},  \
01534     {"$fcc4", RTYPE_FCC | 4},  \
01535     {"$fcc5", RTYPE_FCC | 5},  \
01536     {"$fcc6", RTYPE_FCC | 6},  \
01537     {"$fcc7", RTYPE_FCC | 7}
01538 
01539 #define COPROC_CONDITION_CODE_NAMES         \
01540     {"$cc0",  RTYPE_FCC | RTYPE_CCC | 0}, \
01541     {"$cc1",  RTYPE_FCC | RTYPE_CCC | 1}, \
01542     {"$cc2",  RTYPE_FCC | RTYPE_CCC | 2}, \
01543     {"$cc3",  RTYPE_FCC | RTYPE_CCC | 3}, \
01544     {"$cc4",  RTYPE_FCC | RTYPE_CCC | 4}, \
01545     {"$cc5",  RTYPE_FCC | RTYPE_CCC | 5}, \
01546     {"$cc6",  RTYPE_FCC | RTYPE_CCC | 6}, \
01547     {"$cc7",  RTYPE_FCC | RTYPE_CCC | 7}
01548 
01549 #define N32N64_SYMBOLIC_REGISTER_NAMES \
01550     {"$a4",   RTYPE_GP | 8},  \
01551     {"$a5",   RTYPE_GP | 9},  \
01552     {"$a6",   RTYPE_GP | 10}, \
01553     {"$a7",   RTYPE_GP | 11}, \
01554     {"$ta0",  RTYPE_GP | 8},  /* alias for $a4 */ \
01555     {"$ta1",  RTYPE_GP | 9},  /* alias for $a5 */ \
01556     {"$ta2",  RTYPE_GP | 10}, /* alias for $a6 */ \
01557     {"$ta3",  RTYPE_GP | 11}, /* alias for $a7 */ \
01558     {"$t0",   RTYPE_GP | 12}, \
01559     {"$t1",   RTYPE_GP | 13}, \
01560     {"$t2",   RTYPE_GP | 14}, \
01561     {"$t3",   RTYPE_GP | 15}
01562 
01563 #define O32_SYMBOLIC_REGISTER_NAMES \
01564     {"$t0",   RTYPE_GP | 8},  \
01565     {"$t1",   RTYPE_GP | 9},  \
01566     {"$t2",   RTYPE_GP | 10}, \
01567     {"$t3",   RTYPE_GP | 11}, \
01568     {"$t4",   RTYPE_GP | 12}, \
01569     {"$t5",   RTYPE_GP | 13}, \
01570     {"$t6",   RTYPE_GP | 14}, \
01571     {"$t7",   RTYPE_GP | 15}, \
01572     {"$ta0",  RTYPE_GP | 12}, /* alias for $t4 */ \
01573     {"$ta1",  RTYPE_GP | 13}, /* alias for $t5 */ \
01574     {"$ta2",  RTYPE_GP | 14}, /* alias for $t6 */ \
01575     {"$ta3",  RTYPE_GP | 15}  /* alias for $t7 */ 
01576 
01577 /* Remaining symbolic register names */
01578 #define SYMBOLIC_REGISTER_NAMES \
01579     {"$zero", RTYPE_GP | 0},  \
01580     {"$at",   RTYPE_GP | 1},  \
01581     {"$AT",   RTYPE_GP | 1},  \
01582     {"$v0",   RTYPE_GP | 2},  \
01583     {"$v1",   RTYPE_GP | 3},  \
01584     {"$a0",   RTYPE_GP | 4},  \
01585     {"$a1",   RTYPE_GP | 5},  \
01586     {"$a2",   RTYPE_GP | 6},  \
01587     {"$a3",   RTYPE_GP | 7},  \
01588     {"$s0",   RTYPE_GP | 16}, \
01589     {"$s1",   RTYPE_GP | 17}, \
01590     {"$s2",   RTYPE_GP | 18}, \
01591     {"$s3",   RTYPE_GP | 19}, \
01592     {"$s4",   RTYPE_GP | 20}, \
01593     {"$s5",   RTYPE_GP | 21}, \
01594     {"$s6",   RTYPE_GP | 22}, \
01595     {"$s7",   RTYPE_GP | 23}, \
01596     {"$t8",   RTYPE_GP | 24}, \
01597     {"$t9",   RTYPE_GP | 25}, \
01598     {"$k0",   RTYPE_GP | 26}, \
01599     {"$kt0",  RTYPE_GP | 26}, \
01600     {"$k1",   RTYPE_GP | 27}, \
01601     {"$kt1",  RTYPE_GP | 27}, \
01602     {"$gp",   RTYPE_GP | 28}, \
01603     {"$sp",   RTYPE_GP | 29}, \
01604     {"$s8",   RTYPE_GP | 30}, \
01605     {"$fp",   RTYPE_GP | 30}, \
01606     {"$ra",   RTYPE_GP | 31}
01607 
01608 #define MIPS16_SPECIAL_REGISTER_NAMES \
01609     {"$pc",   RTYPE_PC | 0}
01610 
01611 #define MDMX_VECTOR_REGISTER_NAMES \
01612     /* {"$v0",       RTYPE_VEC | 0},  clash with REG 2 above */ \
01613     /* {"$v1",       RTYPE_VEC | 1},  clash with REG 3 above */ \
01614     {"$v2",   RTYPE_VEC | 2},  \
01615     {"$v3",   RTYPE_VEC | 3},  \
01616     {"$v4",   RTYPE_VEC | 4},  \
01617     {"$v5",   RTYPE_VEC | 5},  \
01618     {"$v6",   RTYPE_VEC | 6},  \
01619     {"$v7",   RTYPE_VEC | 7},  \
01620     {"$v8",   RTYPE_VEC | 8},  \
01621     {"$v9",   RTYPE_VEC | 9},  \
01622     {"$v10",  RTYPE_VEC | 10}, \
01623     {"$v11",  RTYPE_VEC | 11}, \
01624     {"$v12",  RTYPE_VEC | 12}, \
01625     {"$v13",  RTYPE_VEC | 13}, \
01626     {"$v14",  RTYPE_VEC | 14}, \
01627     {"$v15",  RTYPE_VEC | 15}, \
01628     {"$v16",  RTYPE_VEC | 16}, \
01629     {"$v17",  RTYPE_VEC | 17}, \
01630     {"$v18",  RTYPE_VEC | 18}, \
01631     {"$v19",  RTYPE_VEC | 19}, \
01632     {"$v20",  RTYPE_VEC | 20}, \
01633     {"$v21",  RTYPE_VEC | 21}, \
01634     {"$v22",  RTYPE_VEC | 22}, \
01635     {"$v23",  RTYPE_VEC | 23}, \
01636     {"$v24",  RTYPE_VEC | 24}, \
01637     {"$v25",  RTYPE_VEC | 25}, \
01638     {"$v26",  RTYPE_VEC | 26}, \
01639     {"$v27",  RTYPE_VEC | 27}, \
01640     {"$v28",  RTYPE_VEC | 28}, \
01641     {"$v29",  RTYPE_VEC | 29}, \
01642     {"$v30",  RTYPE_VEC | 30}, \
01643     {"$v31",  RTYPE_VEC | 31}
01644 
01645 #define MIPS_DSP_ACCUMULATOR_NAMES \
01646     {"$ac0",  RTYPE_ACC | 0}, \
01647     {"$ac1",  RTYPE_ACC | 1}, \
01648     {"$ac2",  RTYPE_ACC | 2}, \
01649     {"$ac3",  RTYPE_ACC | 3}
01650 
01651 static const struct regname reg_names[] = {
01652   GENERIC_REGISTER_NUMBERS,
01653   FPU_REGISTER_NAMES,
01654   FPU_CONDITION_CODE_NAMES,
01655   COPROC_CONDITION_CODE_NAMES,
01656 
01657   /* The $txx registers depends on the abi,
01658      these will be added later into the symbol table from
01659      one of the tables below once mips_abi is set after 
01660      parsing of arguments from the command line. */
01661   SYMBOLIC_REGISTER_NAMES,
01662 
01663   MIPS16_SPECIAL_REGISTER_NAMES,
01664   MDMX_VECTOR_REGISTER_NAMES,
01665   MIPS_DSP_ACCUMULATOR_NAMES,
01666   {0, 0}
01667 };
01668 
01669 static const struct regname reg_names_o32[] = {
01670   O32_SYMBOLIC_REGISTER_NAMES,
01671   {0, 0}
01672 };
01673 
01674 static const struct regname reg_names_n32n64[] = {
01675   N32N64_SYMBOLIC_REGISTER_NAMES,
01676   {0, 0}
01677 };
01678 
01679 static int
01680 reg_lookup (char **s, unsigned int types, unsigned int *regnop)
01681 {
01682   symbolS *symbolP;
01683   char *e;
01684   char save_c;
01685   int reg = -1;
01686 
01687   /* Find end of name.  */
01688   e = *s;
01689   if (is_name_beginner (*e))
01690     ++e;
01691   while (is_part_of_name (*e))
01692     ++e;
01693 
01694   /* Terminate name.  */
01695   save_c = *e;
01696   *e = '\0';
01697 
01698   /* Look for a register symbol.  */
01699   if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
01700     {
01701       int r = S_GET_VALUE (symbolP);
01702       if (r & types)
01703        reg = r & RNUM_MASK;
01704       else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
01705        /* Convert GP reg $v0/1 to MDMX reg $v0/1!  */
01706        reg = (r & RNUM_MASK) - 2;
01707     }
01708   /* Else see if this is a register defined in an itbl entry.  */
01709   else if ((types & RTYPE_GP) && itbl_have_entries)
01710     {
01711       char *n = *s;
01712       unsigned long r;
01713 
01714       if (*n == '$')
01715        ++n;
01716       if (itbl_get_reg_val (n, &r))
01717        reg = r & RNUM_MASK;
01718     }
01719 
01720   /* Advance to next token if a register was recognised.  */
01721   if (reg >= 0)
01722     *s = e;
01723   else if (types & RWARN)
01724     as_warn ("Unrecognized register name `%s'", *s);
01725 
01726   *e = save_c;
01727   if (regnop)
01728     *regnop = reg;
01729   return reg >= 0;
01730 }
01731 
01732 /* This function is called once, at assembler startup time.  It should set up
01733    all the tables, etc. that the MD part of the assembler will need.  */
01734 
01735 void
01736 md_begin (void)
01737 {
01738   const char *retval = NULL;
01739   int i = 0;
01740   int broken = 0;
01741 
01742   if (mips_pic != NO_PIC)
01743     {
01744       if (g_switch_seen && g_switch_value != 0)
01745        as_bad (_("-G may not be used in position-independent code"));
01746       g_switch_value = 0;
01747     }
01748 
01749   if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
01750     as_warn (_("Could not set architecture and machine"));
01751 
01752   op_hash = hash_new ();
01753 
01754   for (i = 0; i < NUMOPCODES;)
01755     {
01756       const char *name = mips_opcodes[i].name;
01757 
01758       retval = hash_insert (op_hash, name, (void *) &mips_opcodes[i]);
01759       if (retval != NULL)
01760        {
01761          fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
01762                  mips_opcodes[i].name, retval);
01763          /* Probably a memory allocation problem?  Give up now.  */
01764          as_fatal (_("Broken assembler.  No assembly attempted."));
01765        }
01766       do
01767        {
01768          if (mips_opcodes[i].pinfo != INSN_MACRO)
01769            {
01770              if (!validate_mips_insn (&mips_opcodes[i]))
01771               broken = 1;
01772              if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
01773               {
01774                 create_insn (&nop_insn, mips_opcodes + i);
01775                 nop_insn.fixed_p = 1;
01776               }
01777            }
01778          ++i;
01779        }
01780       while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
01781     }
01782 
01783   mips16_op_hash = hash_new ();
01784 
01785   i = 0;
01786   while (i < bfd_mips16_num_opcodes)
01787     {
01788       const char *name = mips16_opcodes[i].name;
01789 
01790       retval = hash_insert (mips16_op_hash, name, (void *) &mips16_opcodes[i]);
01791       if (retval != NULL)
01792        as_fatal (_("internal: can't hash `%s': %s"),
01793                 mips16_opcodes[i].name, retval);
01794       do
01795        {
01796          if (mips16_opcodes[i].pinfo != INSN_MACRO
01797              && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
01798                 != mips16_opcodes[i].match))
01799            {
01800              fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
01801                      mips16_opcodes[i].name, mips16_opcodes[i].args);
01802              broken = 1;
01803            }
01804          if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
01805            {
01806              create_insn (&mips16_nop_insn, mips16_opcodes + i);
01807              mips16_nop_insn.fixed_p = 1;
01808            }
01809          ++i;
01810        }
01811       while (i < bfd_mips16_num_opcodes
01812             && strcmp (mips16_opcodes[i].name, name) == 0);
01813     }
01814 
01815   if (broken)
01816     as_fatal (_("Broken assembler.  No assembly attempted."));
01817 
01818   /* We add all the general register names to the symbol table.  This
01819      helps us detect invalid uses of them.  */
01820   for (i = 0; reg_names[i].name; i++) 
01821     symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
01822                                  reg_names[i].num, // & RNUM_MASK,
01823                                  &zero_address_frag));
01824   if (HAVE_NEWABI)
01825     for (i = 0; reg_names_n32n64[i].name; i++) 
01826       symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
01827                                    reg_names_n32n64[i].num, // & RNUM_MASK,
01828                                    &zero_address_frag));
01829   else
01830     for (i = 0; reg_names_o32[i].name; i++) 
01831       symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
01832                                    reg_names_o32[i].num, // & RNUM_MASK,
01833                                    &zero_address_frag));
01834 
01835   mips_no_prev_insn ();
01836 
01837   mips_gprmask = 0;
01838   mips_cprmask[0] = 0;
01839   mips_cprmask[1] = 0;
01840   mips_cprmask[2] = 0;
01841   mips_cprmask[3] = 0;
01842 
01843   /* set the default alignment for the text section (2**2) */
01844   record_alignment (text_section, 2);
01845 
01846   bfd_set_gp_size (stdoutput, g_switch_value);
01847 
01848 #ifdef OBJ_ELF
01849   if (IS_ELF)
01850     {
01851       /* On a native system other than VxWorks, sections must be aligned
01852         to 16 byte boundaries.  When configured for an embedded ELF
01853         target, we don't bother.  */
01854       if (strcmp (TARGET_OS, "elf") != 0
01855          && strcmp (TARGET_OS, "vxworks") != 0)
01856        {
01857          (void) bfd_set_section_alignment (stdoutput, text_section, 4);
01858          (void) bfd_set_section_alignment (stdoutput, data_section, 4);
01859          (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
01860        }
01861 
01862       /* Create a .reginfo section for register masks and a .mdebug
01863         section for debugging information.  */
01864       {
01865        segT seg;
01866        subsegT subseg;
01867        flagword flags;
01868        segT sec;
01869 
01870        seg = now_seg;
01871        subseg = now_subseg;
01872 
01873        /* The ABI says this section should be loaded so that the
01874           running program can access it.  However, we don't load it
01875           if we are configured for an embedded target */
01876        flags = SEC_READONLY | SEC_DATA;
01877        if (strcmp (TARGET_OS, "elf") != 0)
01878          flags |= SEC_ALLOC | SEC_LOAD;
01879 
01880        if (mips_abi != N64_ABI)
01881          {
01882            sec = subseg_new (".reginfo", (subsegT) 0);
01883 
01884            bfd_set_section_flags (stdoutput, sec, flags);
01885            bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
01886 
01887            mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
01888          }
01889        else
01890          {
01891            /* The 64-bit ABI uses a .MIPS.options section rather than
01892                .reginfo section.  */
01893            sec = subseg_new (".MIPS.options", (subsegT) 0);
01894            bfd_set_section_flags (stdoutput, sec, flags);
01895            bfd_set_section_alignment (stdoutput, sec, 3);
01896 
01897            /* Set up the option header.  */
01898            {
01899              Elf_Internal_Options opthdr;
01900              char *f;
01901 
01902              opthdr.kind = ODK_REGINFO;
01903              opthdr.size = (sizeof (Elf_External_Options)
01904                           + sizeof (Elf64_External_RegInfo));
01905              opthdr.section = 0;
01906              opthdr.info = 0;
01907              f = frag_more (sizeof (Elf_External_Options));
01908              bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
01909                                         (Elf_External_Options *) f);
01910 
01911              mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
01912            }
01913          }
01914 
01915        if (ECOFF_DEBUGGING)
01916          {
01917            sec = subseg_new (".mdebug", (subsegT) 0);
01918            (void) bfd_set_section_flags (stdoutput, sec,
01919                                      SEC_HAS_CONTENTS | SEC_READONLY);
01920            (void) bfd_set_section_alignment (stdoutput, sec, 2);
01921          }
01922        else if (mips_flag_pdr)
01923          {
01924            pdr_seg = subseg_new (".pdr", (subsegT) 0);
01925            (void) bfd_set_section_flags (stdoutput, pdr_seg,
01926                                      SEC_READONLY | SEC_RELOC
01927                                      | SEC_DEBUGGING);
01928            (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
01929          }
01930 
01931        subseg_set (seg, subseg);
01932       }
01933     }
01934 #endif /* OBJ_ELF */
01935 
01936   if (! ECOFF_DEBUGGING)
01937     md_obj_begin ();
01938 
01939   if (mips_fix_vr4120)
01940     init_vr4120_conflicts ();
01941 }
01942 
01943 void
01944 md_mips_end (void)
01945 {
01946   if (! ECOFF_DEBUGGING)
01947     md_obj_end ();
01948 }
01949 
01950 void
01951 md_assemble (char *str)
01952 {
01953   struct mips_cl_insn insn;
01954   bfd_reloc_code_real_type unused_reloc[3]
01955     = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
01956 
01957   imm_expr.X_op = O_absent;
01958   imm2_expr.X_op = O_absent;
01959   offset_expr.X_op = O_absent;
01960   imm_reloc[0] = BFD_RELOC_UNUSED;
01961   imm_reloc[1] = BFD_RELOC_UNUSED;
01962   imm_reloc[2] = BFD_RELOC_UNUSED;
01963   offset_reloc[0] = BFD_RELOC_UNUSED;
01964   offset_reloc[1] = BFD_RELOC_UNUSED;
01965   offset_reloc[2] = BFD_RELOC_UNUSED;
01966 
01967   if (mips_opts.mips16)
01968     mips16_ip (str, &insn);
01969   else
01970     {
01971       mips_ip (str, &insn);
01972       DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
01973            str, insn.insn_opcode));
01974     }
01975 
01976   if (insn_error)
01977     {
01978       as_bad ("%s `%s'", insn_error, str);
01979       return;
01980     }
01981 
01982   if (insn.insn_mo->pinfo == INSN_MACRO)
01983     {
01984       macro_start ();
01985       if (mips_opts.mips16)
01986        mips16_macro (&insn);
01987       else
01988        macro (&insn);
01989       macro_end ();
01990     }
01991   else
01992     {
01993       if (imm_expr.X_op != O_absent)
01994        append_insn (&insn, &imm_expr, imm_reloc);
01995       else if (offset_expr.X_op != O_absent)
01996        append_insn (&insn, &offset_expr, offset_reloc);
01997       else
01998        append_insn (&insn, NULL, unused_reloc);
01999     }
02000 }
02001 
02002 /* Return true if the given relocation might need a matching %lo().
02003    This is only "might" because SVR4 R_MIPS_GOT16 relocations only
02004    need a matching %lo() when applied to local symbols.  */
02005 
02006 static inline bfd_boolean
02007 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
02008 {
02009   return (HAVE_IN_PLACE_ADDENDS
02010          && (reloc == BFD_RELOC_HI16_S
02011              || reloc == BFD_RELOC_MIPS16_HI16_S
02012              /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
02013                all GOT16 relocations evaluate to "G".  */
02014              || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC)));
02015 }
02016 
02017 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
02018    relocation.  */
02019 
02020 static inline bfd_boolean
02021 fixup_has_matching_lo_p (fixS *fixp)
02022 {
02023   return (fixp->fx_next != NULL
02024          && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
02025             || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
02026          && fixp->fx_addsy == fixp->fx_next->fx_addsy
02027          && fixp->fx_offset == fixp->fx_next->fx_offset);
02028 }
02029 
02030 /* See whether instruction IP reads register REG.  CLASS is the type
02031    of register.  */
02032 
02033 static int
02034 insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
02035               enum mips_regclass class)
02036 {
02037   if (class == MIPS16_REG)
02038     {
02039       assert (mips_opts.mips16);
02040       reg = mips16_to_32_reg_map[reg];
02041       class = MIPS_GR_REG;
02042     }
02043 
02044   /* Don't report on general register ZERO, since it never changes.  */
02045   if (class == MIPS_GR_REG && reg == ZERO)
02046     return 0;
02047 
02048   if (class == MIPS_FP_REG)
02049     {
02050       assert (! mips_opts.mips16);
02051       /* If we are called with either $f0 or $f1, we must check $f0.
02052         This is not optimal, because it will introduce an unnecessary
02053         NOP between "lwc1 $f0" and "swc1 $f1".  To fix this we would
02054         need to distinguish reading both $f0 and $f1 or just one of
02055         them.  Note that we don't have to check the other way,
02056         because there is no instruction that sets both $f0 and $f1
02057         and requires a delay.  */
02058       if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
02059          && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
02060              == (reg &~ (unsigned) 1)))
02061        return 1;
02062       if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
02063          && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
02064              == (reg &~ (unsigned) 1)))
02065        return 1;
02066     }
02067   else if (! mips_opts.mips16)
02068     {
02069       if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
02070          && EXTRACT_OPERAND (RS, *ip) == reg)
02071        return 1;
02072       if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
02073          && EXTRACT_OPERAND (RT, *ip) == reg)
02074        return 1;
02075     }
02076   else
02077     {
02078       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
02079          && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
02080        return 1;
02081       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
02082          && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
02083        return 1;
02084       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
02085          && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
02086              == reg))
02087        return 1;
02088       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
02089        return 1;
02090       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
02091        return 1;
02092       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
02093        return 1;
02094       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
02095          && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
02096        return 1;
02097     }
02098 
02099   return 0;
02100 }
02101 
02102 /* This function returns true if modifying a register requires a
02103    delay.  */
02104 
02105 static int
02106 reg_needs_delay (unsigned int reg)
02107 {
02108   unsigned long prev_pinfo;
02109 
02110   prev_pinfo = history[0].insn_mo->pinfo;
02111   if (! mips_opts.noreorder
02112       && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
02113           && ! gpr_interlocks)
02114          || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
02115              && ! cop_interlocks)))
02116     {
02117       /* A load from a coprocessor or from memory.  All load delays
02118         delay the use of general register rt for one instruction.  */
02119       /* Itbl support may require additional care here.  */
02120       know (prev_pinfo & INSN_WRITE_GPR_T);
02121       if (reg == EXTRACT_OPERAND (RT, history[0]))
02122        return 1;
02123     }
02124 
02125   return 0;
02126 }
02127 
02128 /* Move all labels in insn_labels to the current insertion point.  */
02129 
02130 static void
02131 mips_move_labels (void)
02132 {
02133   segment_info_type *si = seg_info (now_seg);
02134   struct insn_label_list *l;
02135   valueT val;
02136 
02137   for (l = si->label_list; l != NULL; l = l->next)
02138     {
02139       assert (S_GET_SEGMENT (l->label) == now_seg);
02140       symbol_set_frag (l->label, frag_now);
02141       val = (valueT) frag_now_fix ();
02142       /* mips16 text labels are stored as odd.  */
02143       if (mips_opts.mips16)
02144        ++val;
02145       S_SET_VALUE (l->label, val);
02146     }
02147 }
02148 
02149 static bfd_boolean
02150 s_is_linkonce (symbolS *sym, segT from_seg)
02151 {
02152   bfd_boolean linkonce = FALSE;
02153   segT symseg = S_GET_SEGMENT (sym);
02154 
02155   if (symseg != from_seg && !S_IS_LOCAL (sym))
02156     {
02157       if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
02158        linkonce = TRUE;
02159 #ifdef OBJ_ELF
02160       /* The GNU toolchain uses an extension for ELF: a section
02161         beginning with the magic string .gnu.linkonce is a
02162         linkonce section.  */
02163       if (strncmp (segment_name (symseg), ".gnu.linkonce",
02164                  sizeof ".gnu.linkonce" - 1) == 0)
02165        linkonce = TRUE;
02166 #endif
02167     }
02168   return linkonce;
02169 }
02170 
02171 /* Mark instruction labels in mips16 mode.  This permits the linker to
02172    handle them specially, such as generating jalx instructions when
02173    needed.  We also make them odd for the duration of the assembly, in
02174    order to generate the right sort of code.  We will make them even
02175    in the adjust_symtab routine, while leaving them marked.  This is
02176    convenient for the debugger and the disassembler.  The linker knows
02177    to make them odd again.  */
02178 
02179 static void
02180 mips16_mark_labels (void)
02181 {
02182   segment_info_type *si = seg_info (now_seg);
02183   struct insn_label_list *l;
02184 
02185   if (!mips_opts.mips16)
02186     return;
02187 
02188   for (l = si->label_list; l != NULL; l = l->next)
02189    {
02190       symbolS *label = l->label;
02191 
02192 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
02193       if (IS_ELF)
02194        S_SET_OTHER (label, STO_MIPS16);
02195 #endif
02196       if ((S_GET_VALUE (label) & 1) == 0
02197        /* Don't adjust the address if the label is global or weak, or
02198           in a link-once section, since we'll be emitting symbol reloc
02199           references to it which will be patched up by the linker, and
02200           the final value of the symbol may or may not be MIPS16.  */
02201          && ! S_IS_WEAK (label)
02202          && ! S_IS_EXTERNAL (label)
02203          && ! s_is_linkonce (label, now_seg))
02204        S_SET_VALUE (label, S_GET_VALUE (label) | 1);
02205     }
02206 }
02207 
02208 /* End the current frag.  Make it a variant frag and record the
02209    relaxation info.  */
02210 
02211 static void
02212 relax_close_frag (void)
02213 {
02214   mips_macro_warning.first_frag = frag_now;
02215   frag_var (rs_machine_dependent, 0, 0,
02216            RELAX_ENCODE (mips_relax.sizes[0], mips_relax.sizes[1]),
02217            mips_relax.symbol, 0, (char *) mips_relax.first_fixup);
02218 
02219   memset (&mips_relax.sizes, 0, sizeof (mips_relax.sizes));
02220   mips_relax.first_fixup = 0;
02221 }
02222 
02223 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
02224    See the comment above RELAX_ENCODE for more details.  */
02225 
02226 static void
02227 relax_start (symbolS *symbol)
02228 {
02229   assert (mips_relax.sequence == 0);
02230   mips_relax.sequence = 1;
02231   mips_relax.symbol = symbol;
02232 }
02233 
02234 /* Start generating the second version of a relaxable sequence.
02235    See the comment above RELAX_ENCODE for more details.  */
02236 
02237 static void
02238 relax_switch (void)
02239 {
02240   assert (mips_relax.sequence == 1);
02241   mips_relax.sequence = 2;
02242 }
02243 
02244 /* End the current relaxable sequence.  */
02245 
02246 static void
02247 relax_end (void)
02248 {
02249   assert (mips_relax.sequence == 2);
02250   relax_close_frag ();
02251   mips_relax.sequence = 0;
02252 }
02253 
02254 /* Classify an instruction according to the FIX_VR4120_* enumeration.
02255    Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
02256    by VR4120 errata.  */
02257 
02258 static unsigned int
02259 classify_vr4120_insn (const char *name)
02260 {
02261   if (strncmp (name, "macc", 4) == 0)
02262     return FIX_VR4120_MACC;
02263   if (strncmp (name, "dmacc", 5) == 0)
02264     return FIX_VR4120_DMACC;
02265   if (strncmp (name, "mult", 4) == 0)
02266     return FIX_VR4120_MULT;
02267   if (strncmp (name, "dmult", 5) == 0)
02268     return FIX_VR4120_DMULT;
02269   if (strstr (name, "div"))
02270     return FIX_VR4120_DIV;
02271   if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
02272     return FIX_VR4120_MTHILO;
02273   return NUM_FIX_VR4120_CLASSES;
02274 }
02275 
02276 /* Return the number of instructions that must separate INSN1 and INSN2,
02277    where INSN1 is the earlier instruction.  Return the worst-case value
02278    for any INSN2 if INSN2 is null.  */
02279 
02280 static unsigned int
02281 insns_between (const struct mips_cl_insn *insn1,
02282               const struct mips_cl_insn *insn2)
02283 {
02284   unsigned long pinfo1, pinfo2;
02285 
02286   /* This function needs to know which pinfo flags are set for INSN2
02287      and which registers INSN2 uses.  The former is stored in PINFO2 and
02288      the latter is tested via INSN2_USES_REG.  If INSN2 is null, PINFO2
02289      will have every flag set and INSN2_USES_REG will always return true.  */
02290   pinfo1 = insn1->insn_mo->pinfo;
02291   pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
02292 
02293 #define INSN2_USES_REG(REG, CLASS) \
02294    (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
02295 
02296   /* For most targets, write-after-read dependencies on the HI and LO
02297      registers must be separated by at least two instructions.  */
02298   if (!hilo_interlocks)
02299     {
02300       if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
02301        return 2;
02302       if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
02303        return 2;
02304     }
02305 
02306   /* If we're working around r7000 errata, there must be two instructions
02307      between an mfhi or mflo and any instruction that uses the result.  */
02308   if (mips_7000_hilo_fix
02309       && MF_HILO_INSN (pinfo1)
02310       && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
02311     return 2;
02312 
02313   /* If working around VR4120 errata, check for combinations that need
02314      a single intervening instruction.  */
02315   if (mips_fix_vr4120)
02316     {
02317       unsigned int class1, class2;
02318 
02319       class1 = classify_vr4120_insn (insn1->insn_mo->name);
02320       if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
02321        {
02322          if (insn2 == NULL)
02323            return 1;
02324          class2 = classify_vr4120_insn (insn2->insn_mo->name);
02325          if (vr4120_conflicts[class1] & (1 << class2))
02326            return 1;
02327        }
02328     }
02329 
02330   if (!mips_opts.mips16)
02331     {
02332       /* Check for GPR or coprocessor load delays.  All such delays
02333         are on the RT register.  */
02334       /* Itbl support may require additional care here.  */
02335       if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
02336          || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
02337        {
02338          know (pinfo1 & INSN_WRITE_GPR_T);
02339          if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
02340            return 1;
02341        }
02342 
02343       /* Check for generic coprocessor hazards.
02344 
02345         This case is not handled very well.  There is no special
02346         knowledge of CP0 handling, and the coprocessors other than
02347         the floating point unit are not distinguished at all.  */
02348       /* Itbl support may require additional care here. FIXME!
02349         Need to modify this to include knowledge about
02350         user specified delays!  */
02351       else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
02352               || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
02353        {
02354          /* Handle cases where INSN1 writes to a known general coprocessor
02355             register.  There must be a one instruction delay before INSN2
02356             if INSN2 reads that register, otherwise no delay is needed.  */
02357          if (pinfo1 & INSN_WRITE_FPR_T)
02358            {
02359              if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
02360               return 1;
02361            }
02362          else if (pinfo1 & INSN_WRITE_FPR_S)
02363            {
02364              if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
02365               return 1;
02366            }
02367          else
02368            {
02369              /* Read-after-write dependencies on the control registers
02370                require a two-instruction gap.  */
02371              if ((pinfo1 & INSN_WRITE_COND_CODE)
02372                 && (pinfo2 & INSN_READ_COND_CODE))
02373               return 2;
02374 
02375              /* We don't know exactly what INSN1 does.  If INSN2 is
02376                also a coprocessor instruction, assume there must be
02377                a one instruction gap.  */
02378              if (pinfo2 & INSN_COP)
02379               return 1;
02380            }
02381        }
02382 
02383       /* Check for read-after-write dependencies on the coprocessor
02384         control registers in cases where INSN1 does not need a general
02385         coprocessor delay.  This means that INSN1 is a floating point
02386         comparison instruction.  */
02387       /* Itbl support may require additional care here.  */
02388       else if (!cop_interlocks
02389               && (pinfo1 & INSN_WRITE_COND_CODE)
02390               && (pinfo2 & INSN_READ_COND_CODE))
02391        return 1;
02392     }
02393 
02394 #undef INSN2_USES_REG
02395 
02396   return 0;
02397 }
02398 
02399 /* Return the number of nops that would be needed to work around the
02400    VR4130 mflo/mfhi errata if instruction INSN immediately followed
02401    the MAX_VR4130_NOPS instructions described by HISTORY.  */
02402 
02403 static int
02404 nops_for_vr4130 (const struct mips_cl_insn *history,
02405                const struct mips_cl_insn *insn)
02406 {
02407   int i, j, reg;
02408 
02409   /* Check if the instruction writes to HI or LO.  MTHI and MTLO
02410      are not affected by the errata.  */
02411   if (insn != 0
02412       && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
02413          || strcmp (insn->insn_mo->name, "mtlo") == 0
02414          || strcmp (insn->insn_mo->name, "mthi") == 0))
02415     return 0;
02416 
02417   /* Search for the first MFLO or MFHI.  */
02418   for (i = 0; i < MAX_VR4130_NOPS; i++)
02419     if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
02420       {
02421        /* Extract the destination register.  */
02422        if (mips_opts.mips16)
02423          reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
02424        else
02425          reg = EXTRACT_OPERAND (RD, history[i]);
02426 
02427        /* No nops are needed if INSN reads that register.  */
02428        if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
02429          return 0;
02430 
02431        /* ...or if any of the intervening instructions do.  */
02432        for (j = 0; j < i; j++)
02433          if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
02434            return 0;
02435 
02436        return MAX_VR4130_NOPS - i;
02437       }
02438   return 0;
02439 }
02440 
02441 /* Return the number of nops that would be needed if instruction INSN
02442    immediately followed the MAX_NOPS instructions given by HISTORY,
02443    where HISTORY[0] is the most recent instruction.  If INSN is null,
02444    return the worse-case number of nops for any instruction.  */
02445 
02446 static int
02447 nops_for_insn (const struct mips_cl_insn *history,
02448               const struct mips_cl_insn *insn)
02449 {
02450   int i, nops, tmp_nops;
02451 
02452   nops = 0;
02453   for (i = 0; i < MAX_DELAY_NOPS; i++)
02454     if (!history[i].noreorder_p)
02455       {
02456        tmp_nops = insns_between (history + i, insn) - i;
02457        if (tmp_nops > nops)
02458          nops = tmp_nops;
02459       }
02460 
02461   if (mips_fix_vr4130)
02462     {
02463       tmp_nops = nops_for_vr4130 (history, insn);
02464       if (tmp_nops > nops)
02465        nops = tmp_nops;
02466     }
02467 
02468   return nops;
02469 }
02470 
02471 /* The variable arguments provide NUM_INSNS extra instructions that
02472    might be added to HISTORY.  Return the largest number of nops that
02473    would be needed after the extended sequence.  */
02474 
02475 static int
02476 nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
02477 {
02478   va_list args;
02479   struct mips_cl_insn buffer[MAX_NOPS];
02480   struct mips_cl_insn *cursor;
02481   int nops;
02482 
02483   va_start (args, history);
02484   cursor = buffer + num_insns;
02485   memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
02486   while (cursor > buffer)
02487     *--cursor = *va_arg (args, const struct mips_cl_insn *);
02488 
02489   nops = nops_for_insn (buffer, NULL);
02490   va_end (args);
02491   return nops;
02492 }
02493 
02494 /* Like nops_for_insn, but if INSN is a branch, take into account the
02495    worst-case delay for the branch target.  */
02496 
02497 static int
02498 nops_for_insn_or_target (const struct mips_cl_insn *history,
02499                       const struct mips_cl_insn *insn)
02500 {
02501   int nops, tmp_nops;
02502 
02503   nops = nops_for_insn (history, insn);
02504   if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
02505                            | INSN_COND_BRANCH_DELAY
02506                            | INSN_COND_BRANCH_LIKELY))
02507     {
02508       tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
02509       if (tmp_nops > nops)
02510        nops = tmp_nops;
02511     }
02512   else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
02513     {
02514       tmp_nops = nops_for_sequence (1, history, insn);
02515       if (tmp_nops > nops)
02516        nops = tmp_nops;
02517     }
02518   return nops;
02519 }
02520 
02521 /* Output an instruction.  IP is the instruction information.
02522    ADDRESS_EXPR is an operand of the instruction to be used with
02523    RELOC_TYPE.  */
02524 
02525 static void
02526 append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
02527             bfd_reloc_code_real_type *reloc_type)
02528 {
02529   unsigned long prev_pinfo, pinfo;
02530   relax_stateT prev_insn_frag_type = 0;
02531   bfd_boolean relaxed_branch = FALSE;
02532   segment_info_type *si = seg_info (now_seg);
02533 
02534   /* Mark instruction labels in mips16 mode.  */
02535   mips16_mark_labels ();
02536 
02537   prev_pinfo = history[0].insn_mo->pinfo;
02538   pinfo = ip->insn_mo->pinfo;
02539 
02540   if (mips_relax.sequence != 2 && !mips_opts.noreorder)
02541     {
02542       /* There are a lot of optimizations we could do that we don't.
02543         In particular, we do not, in general, reorder instructions.
02544         If you use gcc with optimization, it will reorder
02545         instructions and generally do much more optimization then we
02546         do here; repeating all that work in the assembler would only
02547         benefit hand written assembly code, and does not seem worth
02548         it.  */
02549       int nops = (mips_optimize == 0
02550                 ? nops_for_insn (history, NULL)
02551                 : nops_for_insn_or_target (history, ip));
02552       if (nops > 0)
02553        {
02554          fragS *old_frag;
02555          unsigned long old_frag_offset;
02556          int i;
02557 
02558          old_frag = frag_now;
02559          old_frag_offset = frag_now_fix ();
02560 
02561          for (i = 0; i < nops; i++)
02562            emit_nop ();
02563 
02564          if (listing)
02565            {
02566              listing_prev_line ();
02567              /* We may be at the start of a variant frag.  In case we
02568                  are, make sure there is enough space for the frag
02569                  after the frags created by listing_prev_line.  The
02570                  argument to frag_grow here must be at least as large
02571                  as the argument to all other calls to frag_grow in
02572                  this file.  We don't have to worry about being in the
02573                  middle of a variant frag, because the variants insert
02574                  all needed nop instructions themselves.  */
02575              frag_grow (40);
02576            }
02577 
02578          mips_move_labels ();
02579 
02580 #ifndef NO_ECOFF_DEBUGGING
02581          if (ECOFF_DEBUGGING)
02582            ecoff_fix_loc (old_frag, old_frag_offset);
02583 #endif
02584        }
02585     }
02586   else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
02587     {
02588       /* Work out how many nops in prev_nop_frag are needed by IP.  */
02589       int nops = nops_for_insn_or_target (history, ip);
02590       assert (nops <= prev_nop_frag_holds);
02591 
02592       /* Enforce NOPS as a minimum.  */
02593       if (nops > prev_nop_frag_required)
02594        prev_nop_frag_required = nops;
02595 
02596       if (prev_nop_frag_holds == prev_nop_frag_required)
02597        {
02598          /* Settle for the current number of nops.  Update the history
02599             accordingly (for the benefit of any future .set reorder code).  */
02600          prev_nop_frag = NULL;
02601          insert_into_history (prev_nop_frag_since,
02602                             prev_nop_frag_holds, NOP_INSN);
02603        }
02604       else
02605        {
02606          /* Allow this instruction to replace one of the nops that was
02607             tentatively added to prev_nop_frag.  */
02608          prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
02609          prev_nop_frag_holds--;
02610          prev_nop_frag_since++;
02611        }
02612     }
02613 
02614 #ifdef OBJ_ELF
02615   /* The value passed to dwarf2_emit_insn is the distance between
02616      the beginning of the current instruction and the address that
02617      should be recorded in the debug tables.  For MIPS16 debug info
02618      we want to use ISA-encoded addresses, so we pass -1 for an
02619      address higher by one than the current.  */
02620   dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
02621 #endif
02622 
02623   /* Record the frag type before frag_var.  */
02624   if (history[0].frag)
02625     prev_insn_frag_type = history[0].frag->fr_type;
02626 
02627   if (address_expr
02628       && *reloc_type == BFD_RELOC_16_PCREL_S2
02629       && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
02630          || pinfo & INSN_COND_BRANCH_LIKELY)
02631       && mips_relax_branch
02632       /* Don't try branch relaxation within .set nomacro, or within
02633         .set noat if we use $at for PIC computations.  If it turns
02634         out that the branch was out-of-range, we'll get an error.  */
02635       && !mips_opts.warn_about_macros
02636       && !(mips_opts.noat && mips_pic != NO_PIC)
02637       && !mips_opts.mips16)
02638     {
02639       relaxed_branch = TRUE;
02640       add_relaxed_insn (ip, (relaxed_branch_length
02641                           (NULL, NULL,
02642                            (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
02643                            : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
02644                            : 0)), 4,
02645                      RELAX_BRANCH_ENCODE
02646                      (pinfo & INSN_UNCOND_BRANCH_DELAY,
02647                       pinfo & INSN_COND_BRANCH_LIKELY,
02648                       pinfo & INSN_WRITE_GPR_31,
02649                       0),
02650                      address_expr->X_add_symbol,
02651                      address_expr->X_add_number);
02652       *reloc_type = BFD_RELOC_UNUSED;
02653     }
02654   else if (*reloc_type > BFD_RELOC_UNUSED)
02655     {
02656       /* We need to set up a variant frag.  */
02657       assert (mips_opts.mips16 && address_expr != NULL);
02658       add_relaxed_insn (ip, 4, 0,
02659                      RELAX_MIPS16_ENCODE
02660                      (*reloc_type - BFD_RELOC_UNUSED,
02661                       mips16_small, mips16_ext,
02662                       prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
02663                       history[0].mips16_absolute_jump_p),
02664                      make_expr_symbol (address_expr), 0);
02665     }
02666   else if (mips_opts.mips16
02667           && ! ip->use_extend
02668           && *reloc_type != BFD_RELOC_MIPS16_JMP)
02669     {
02670       if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
02671        /* Make sure there is enough room to swap this instruction with
02672           a following jump instruction.  */
02673        frag_grow (6);
02674       add_fixed_insn (ip);
02675     }
02676   else
02677     {
02678       if (mips_opts.mips16
02679          && mips_opts.noreorder
02680          && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
02681        as_warn (_("extended instruction in delay slot"));
02682 
02683       if (mips_relax.sequence)
02684        {
02685          /* If we've reached the end of this frag, turn it into a variant
02686             frag and record the information for the instructions we've
02687             written so far.  */
02688          if (frag_room () < 4)
02689            relax_close_frag ();
02690          mips_relax.sizes[mips_relax.sequence - 1] += 4;
02691        }
02692 
02693       if (mips_relax.sequence != 2)
02694        mips_macro_warning.sizes[0] += 4;
02695       if (mips_relax.sequence != 1)
02696        mips_macro_warning.sizes[1] += 4;
02697 
02698       if (mips_opts.mips16)
02699        {
02700          ip->fixed_p = 1;
02701          ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
02702        }
02703       add_fixed_insn (ip);
02704     }
02705 
02706   if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
02707     {
02708       if (address_expr->X_op == O_constant)
02709        {
02710          unsigned int tmp;
02711 
02712          switch (*reloc_type)
02713            {
02714            case BFD_RELOC_32:
02715              ip->insn_opcode |= address_expr->X_add_number;
02716              break;
02717 
02718            case BFD_RELOC_MIPS_HIGHEST:
02719              tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
02720              ip->insn_opcode |= tmp & 0xffff;
02721              break;
02722 
02723            case BFD_RELOC_MIPS_HIGHER:
02724              tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
02725              ip->insn_opcode |= tmp & 0xffff;
02726              break;
02727 
02728            case BFD_RELOC_HI16_S:
02729              tmp = (address_expr->X_add_number + 0x8000) >> 16;
02730              ip->insn_opcode |= tmp & 0xffff;
02731              break;
02732 
02733            case BFD_RELOC_HI16:
02734              ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
02735              break;
02736 
02737            case BFD_RELOC_UNUSED:
02738            case BFD_RELOC_LO16:
02739            case BFD_RELOC_MIPS_GOT_DISP:
02740              ip->insn_opcode |= address_expr->X_add_number & 0xffff;
02741              break;
02742 
02743            case BFD_RELOC_MIPS_JMP:
02744              if ((address_expr->X_add_number & 3) != 0)
02745               as_bad (_("jump to misaligned address (0x%lx)"),
02746                      (unsigned long) address_expr->X_add_number);
02747              ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
02748              break;
02749 
02750            case BFD_RELOC_MIPS16_JMP:
02751              if ((address_expr->X_add_number & 3) != 0)
02752               as_bad (_("jump to misaligned address (0x%lx)"),
02753                      (unsigned long) address_expr->X_add_number);
02754              ip->insn_opcode |=
02755               (((address_expr->X_add_number & 0x7c0000) << 3)
02756                | ((address_expr->X_add_number & 0xf800000) >> 7)
02757                | ((address_expr->X_add_number & 0x3fffc) >> 2));
02758              break;
02759 
02760            case BFD_RELOC_16_PCREL_S2:
02761              if ((address_expr->X_add_number & 3) != 0)
02762               as_bad (_("branch to misaligned address (0x%lx)"),
02763                      (unsigned long) address_expr->X_add_number);
02764              if (mips_relax_branch)
02765               goto need_reloc;
02766              if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
02767               as_bad (_("branch address range overflow (0x%lx)"),
02768                      (unsigned long) address_expr->X_add_number);
02769              ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
02770              break;
02771 
02772            default:
02773              internalError ();
02774            }
02775        }
02776       else if (*reloc_type < BFD_RELOC_UNUSED)
02777        need_reloc:
02778        {
02779          reloc_howto_type *howto;
02780          int i;
02781 
02782          /* In a compound relocation, it is the final (outermost)
02783             operator that determines the relocated field.  */
02784          for (i = 1; i < 3; i++)
02785            if (reloc_type[i] == BFD_RELOC_UNUSED)
02786              break;
02787 
02788          howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
02789          ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
02790                                  bfd_get_reloc_size (howto),
02791                                  address_expr,
02792                                  reloc_type[0] == BFD_RELOC_16_PCREL_S2,
02793                                  reloc_type[0]);
02794 
02795          /* These relocations can have an addend that won't fit in
02796             4 octets for 64bit assembly.  */
02797          if (HAVE_64BIT_GPRS
02798              && ! howto->partial_inplace
02799              && (reloc_type[0] == BFD_RELOC_16
02800                 || reloc_type[0] == BFD_RELOC_32
02801                 || reloc_type[0] == BFD_RELOC_MIPS_JMP
02802                 || reloc_type[0] == BFD_RELOC_HI16_S
02803                 || reloc_type[0] == BFD_RELOC_LO16
02804                 || reloc_type[0] == BFD_RELOC_GPREL16
02805                 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
02806                 || reloc_type[0] == BFD_RELOC_GPREL32
02807                 || reloc_type[0] == BFD_RELOC_64
02808                 || reloc_type[0] == BFD_RELOC_CTOR
02809                 || reloc_type[0] == BFD_RELOC_MIPS_SUB
02810                 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
02811                 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
02812                 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
02813                 || reloc_type[0] == BFD_RELOC_MIPS_REL16
02814                 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
02815                 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
02816                 || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
02817                 || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
02818            ip->fixp[0]->fx_no_overflow = 1;
02819 
02820          if (mips_relax.sequence)
02821            {
02822              if (mips_relax.first_fixup == 0)
02823               mips_relax.first_fixup = ip->fixp[0];
02824            }
02825          else if (reloc_needs_lo_p (*reloc_type))
02826            {
02827              struct mips_hi_fixup *hi_fixup;
02828 
02829              /* Reuse the last entry if it already has a matching %lo.  */
02830              hi_fixup = mips_hi_fixup_list;
02831              if (hi_fixup == 0
02832                 || !fixup_has_matching_lo_p (hi_fixup->fixp))
02833               {
02834                 hi_fixup = ((struct mips_hi_fixup *)
02835                            xmalloc (sizeof (struct mips_hi_fixup)));
02836                 hi_fixup->next = mips_hi_fixup_list;
02837                 mips_hi_fixup_list = hi_fixup;
02838               }
02839              hi_fixup->fixp = ip->fixp[0];
02840              hi_fixup->seg = now_seg;
02841            }
02842 
02843          /* Add fixups for the second and third relocations, if given.
02844             Note that the ABI allows the second relocation to be
02845             against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC.  At the
02846             moment we only use RSS_UNDEF, but we could add support
02847             for the others if it ever becomes necessary.  */
02848          for (i = 1; i < 3; i++)
02849            if (reloc_type[i] != BFD_RELOC_UNUSED)
02850              {
02851               ip->fixp[i] = fix_new (ip->frag, ip->where,
02852                                    ip->fixp[0]->fx_size, NULL, 0,
02853                                    FALSE, reloc_type[i]);
02854 
02855               /* Use fx_tcbit to mark compound relocs.  */
02856               ip->fixp[0]->fx_tcbit = 1;
02857               ip->fixp[i]->fx_tcbit = 1;
02858              }
02859        }
02860     }
02861   install_insn (ip);
02862 
02863   /* Update the register mask information.  */
02864   if (! mips_opts.mips16)
02865     {
02866       if (pinfo & INSN_WRITE_GPR_D)
02867        mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
02868       if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
02869        mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
02870       if (pinfo & INSN_READ_GPR_S)
02871        mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
02872       if (pinfo & INSN_WRITE_GPR_31)
02873        mips_gprmask |= 1 << RA;
02874       if (pinfo & INSN_WRITE_FPR_D)
02875        mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
02876       if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
02877        mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
02878       if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
02879        mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
02880       if ((pinfo & INSN_READ_FPR_R) != 0)
02881        mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
02882       if (pinfo & INSN_COP)
02883        {
02884          /* We don't keep enough information to sort these cases out.
02885             The itbl support does keep this information however, although
02886             we currently don't support itbl fprmats as part of the cop
02887             instruction.  May want to add this support in the future.  */
02888        }
02889       /* Never set the bit for $0, which is always zero.  */
02890       mips_gprmask &= ~1 << 0;
02891     }
02892   else
02893     {
02894       if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
02895        mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
02896       if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
02897        mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
02898       if (pinfo & MIPS16_INSN_WRITE_Z)
02899        mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
02900       if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
02901        mips_gprmask |= 1 << TREG;
02902       if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
02903        mips_gprmask |= 1 << SP;
02904       if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
02905        mips_gprmask |= 1 << RA;
02906       if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
02907        mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
02908       if (pinfo & MIPS16_INSN_READ_Z)
02909        mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
02910       if (pinfo & MIPS16_INSN_READ_GPR_X)
02911        mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
02912     }
02913 
02914   if (mips_relax.sequence != 2 && !mips_opts.noreorder)
02915     {
02916       /* Filling the branch delay slot is more complex.  We try to
02917         switch the branch with the previous instruction, which we can
02918         do if the previous instruction does not set up a condition
02919         that the branch tests and if the branch is not itself the
02920         target of any branch.  */
02921       if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
02922          || (pinfo & INSN_COND_BRANCH_DELAY))
02923        {
02924          if (mips_optimize < 2
02925              /* If we have seen .set volatile or .set nomove, don't
02926                optimize.  */
02927              || mips_opts.nomove != 0
02928              /* We can't swap if the previous instruction's position
02929                is fixed.  */
02930              || history[0].fixed_p
02931              /* If the previous previous insn was in a .set
02932                noreorder, we can't swap.  Actually, the MIPS
02933                assembler will swap in this situation.  However, gcc
02934                configured -with-gnu-as will generate code like
02935                  .set noreorder
02936                  lw  $4,XXX
02937                  .set       reorder
02938                  INSN
02939                  bne $4,$0,foo
02940                in which we can not swap the bne and INSN.  If gcc is
02941                not configured -with-gnu-as, it does not output the
02942                .set pseudo-ops.  */
02943              || history[1].noreorder_p
02944              /* If the branch is itself the target of a branch, we
02945                can not swap.  We cheat on this; all we check for is
02946                whether there is a label on this instruction.  If
02947                there are any branches to anything other than a
02948                label, users must use .set noreorder.  */
02949              || si->label_list != NULL
02950              /* If the previous instruction is in a variant frag
02951                other than this branch's one, we cannot do the swap.
02952                This does not apply to the mips16, which uses variant
02953                frags for different purposes.  */
02954              || (! mips_opts.mips16
02955                 && prev_insn_frag_type == rs_machine_dependent)
02956              /* Check for conflicts between the branch and the instructions
02957                before the candidate delay slot.  */
02958              || nops_for_insn (history + 1, ip) > 0
02959              /* Check for conflicts between the swapped sequence and the
02960                target of the branch.  */
02961              || nops_for_sequence (2, history + 1, ip, history) > 0
02962              /* We do not swap with a trap instruction, since it
02963                complicates trap handlers to have the trap
02964                instruction be in a delay slot.  */
02965              || (prev_pinfo & INSN_TRAP)
02966              /* If the branch reads a register that the previous
02967                instruction sets, we can not swap.  */
02968              || (! mips_opts.mips16
02969                 && (prev_pinfo & INSN_WRITE_GPR_T)
02970                 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
02971                                 MIPS_GR_REG))
02972              || (! mips_opts.mips16
02973                 && (prev_pinfo & INSN_WRITE_GPR_D)
02974                 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
02975                                 MIPS_GR_REG))
02976              || (mips_opts.mips16
02977                 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
02978                      && (insn_uses_reg
02979                         (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
02980                          MIPS16_REG)))
02981                     || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
02982                        && (insn_uses_reg
02983                            (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
02984                             MIPS16_REG)))
02985                     || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
02986                        && (insn_uses_reg
02987                            (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
02988                             MIPS16_REG)))
02989                     || ((prev_pinfo & MIPS16_INSN_WRITE_T)
02990                        && insn_uses_reg (ip, TREG, MIPS_GR_REG))
02991                     || ((prev_pinfo & MIPS16_INSN_WRITE_31)
02992                        && insn_uses_reg (ip, RA, MIPS_GR_REG))
02993                     || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
02994                        && insn_uses_reg (ip,
02995                                        MIPS16OP_EXTRACT_REG32R
02996                                          (history[0].insn_opcode),
02997                                        MIPS_GR_REG))))
02998              /* If the branch writes a register that the previous
02999                instruction sets, we can not swap (we know that
03000                branches write only to RD or to $31).  */
03001              || (! mips_opts.mips16
03002                 && (prev_pinfo & INSN_WRITE_GPR_T)
03003                 && (((pinfo & INSN_WRITE_GPR_D)
03004                      && (EXTRACT_OPERAND (RT, history[0])
03005                         == EXTRACT_OPERAND (RD, *ip)))
03006                     || ((pinfo & INSN_WRITE_GPR_31)
03007                        && EXTRACT_OPERAND (RT, history[0]) == RA)))
03008              || (! mips_opts.mips16
03009                 && (prev_pinfo & INSN_WRITE_GPR_D)
03010                 && (((pinfo & INSN_WRITE_GPR_D)
03011                      && (EXTRACT_OPERAND (RD, history[0])
03012                         == EXTRACT_OPERAND (RD, *ip)))
03013                     || ((pinfo & INSN_WRITE_GPR_31)
03014                        && EXTRACT_OPERAND (RD, history[0]) == RA)))
03015              || (mips_opts.mips16
03016                 && (pinfo & MIPS16_INSN_WRITE_31)
03017                 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
03018                     || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
03019                        && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
03020                            == RA))))
03021              /* If the branch writes a register that the previous
03022                instruction reads, we can not swap (we know that
03023                branches only write to RD or to $31).  */
03024              || (! mips_opts.mips16
03025                 && (pinfo & INSN_WRITE_GPR_D)
03026                 && insn_uses_reg (&history[0],
03027                                 EXTRACT_OPERAND (RD, *ip),
03028                                 MIPS_GR_REG))
03029              || (! mips_opts.mips16
03030                 && (pinfo & INSN_WRITE_GPR_31)
03031                 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
03032              || (mips_opts.mips16
03033                 && (pinfo & MIPS16_INSN_WRITE_31)
03034                 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
03035              /* If one instruction sets a condition code and the
03036                  other one uses a condition code, we can not swap.  */
03037              || ((pinfo & INSN_READ_COND_CODE)
03038                 && (prev_pinfo & INSN_WRITE_COND_CODE))
03039              || ((pinfo & INSN_WRITE_COND_CODE)
03040                 && (prev_pinfo & INSN_READ_COND_CODE))
03041              /* If the previous instruction uses the PC, we can not
03042                  swap.  */
03043              || (mips_opts.mips16
03044                 && (prev_pinfo & MIPS16_INSN_READ_PC))
03045              /* If the previous instruction had a fixup in mips16
03046                  mode, we can not swap.  This normally means that the
03047                  previous instruction was a 4 byte branch anyhow.  */
03048              || (mips_opts.mips16 && history[0].fixp[0])
03049              /* If the previous instruction is a sync, sync.l, or
03050                sync.p, we can not swap.  */
03051              || (prev_pinfo & INSN_SYNC))
03052            {
03053              if (mips_opts.mips16
03054                 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
03055                 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
03056                 && ISA_SUPPORTS_MIPS16E)
03057               {
03058                 /* Convert MIPS16 jr/jalr into a "compact" jump.  */
03059                 ip->insn_opcode |= 0x0080;
03060                 install_insn (ip);
03061                 insert_into_history (0, 1, ip);
03062               } 
03063              else
03064               {
03065                 /* We could do even better for unconditional branches to
03066                    portions of this object file; we could pick up the
03067                    instruction at the destination, put it in the delay
03068                    slot, and bump the destination address.  */
03069                 insert_into_history (0, 1, ip);
03070                 emit_nop ();
03071               }
03072               
03073              if (mips_relax.sequence)
03074               mips_relax.sizes[mips_relax.sequence - 1] += 4;
03075            }
03076          else
03077            {
03078              /* It looks like we can actually do the swap.  */
03079              struct mips_cl_insn delay = history[0];
03080              if (mips_opts.mips16)
03081               {
03082                 know (delay.frag == ip->frag);
03083                   move_insn (ip, delay.frag, delay.where);
03084                 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
03085               }
03086              else if (relaxed_branch)
03087               {
03088                 /* Add the delay slot instruction to the end of the
03089                    current frag and shrink the fixed part of the
03090                    original frag.  If the branch occupies the tail of
03091                    the latter, move it backwards to cover the gap.  */
03092                 delay.frag->fr_fix -= 4;
03093                 if (delay.frag == ip->frag)
03094                   move_insn (ip, ip->frag, ip->where - 4);
03095                 add_fixed_insn (&delay);
03096               }
03097              else
03098               {
03099                 move_insn (&delay, ip->frag, ip->where);
03100                 move_insn (ip, history[0].frag, history[0].where);
03101               }
03102              history[0] = *ip;
03103              delay.fixed_p = 1;
03104              insert_into_history (0, 1, &delay);
03105            }
03106 
03107          /* If that was an unconditional branch, forget the previous
03108             insn information.  */
03109          if (pinfo & INSN_UNCOND_BRANCH_DELAY)
03110            mips_no_prev_insn ();
03111        }
03112       else if (pinfo & INSN_COND_BRANCH_LIKELY)
03113        {
03114          /* We don't yet optimize a branch likely.  What we should do
03115             is look at the target, copy the instruction found there
03116             into the delay slot, and increment the branch to jump to
03117             the next instruction.  */
03118          insert_into_history (0, 1, ip);
03119          emit_nop ();
03120        }
03121       else
03122        insert_into_history (0, 1, ip);
03123     }
03124   else
03125     insert_into_history (0, 1, ip);
03126 
03127   /* We just output an insn, so the next one doesn't have a label.  */
03128   mips_clear_insn_labels ();
03129 }
03130 
03131 /* Forget that there was any previous instruction or label.  */
03132 
03133 static void
03134 mips_no_prev_insn (void)
03135 {
03136   prev_nop_frag = NULL;
03137   insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
03138   mips_clear_insn_labels ();
03139 }
03140 
03141 /* This function must be called before we emit something other than
03142    instructions.  It is like mips_no_prev_insn except that it inserts
03143    any NOPS that might be needed by previous instructions.  */
03144 
03145 void
03146 mips_emit_delays (void)
03147 {
03148   if (! mips_opts.noreorder)
03149     {
03150       int nops = nops_for_insn (history, NULL);
03151       if (nops > 0)
03152        {
03153          while (nops-- > 0)
03154            add_fixed_insn (NOP_INSN);
03155          mips_move_labels ();
03156        }
03157     }
03158   mips_no_prev_insn ();
03159 }
03160 
03161 /* Start a (possibly nested) noreorder block.  */
03162 
03163 static void
03164 start_noreorder (void)
03165 {
03166   if (mips_opts.noreorder == 0)
03167     {
03168       unsigned int i;
03169       int nops;
03170 
03171       /* None of the instructions before the .set noreorder can be moved.  */
03172       for (i = 0; i < ARRAY_SIZE (history); i++)
03173        history[i].fixed_p = 1;
03174 
03175       /* Insert any nops that might be needed between the .set noreorder
03176         block and the previous instructions.  We will later remove any
03177         nops that turn out not to be needed.  */
03178       nops = nops_for_insn (history, NULL);
03179       if (nops > 0)
03180        {
03181          if (mips_optimize != 0)
03182            {
03183              /* Record the frag which holds the nop instructions, so
03184                  that we can remove them if we don't need them.  */
03185              frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
03186              prev_nop_frag = frag_now;
03187              prev_nop_frag_holds = nops;
03188              prev_nop_frag_required = 0;
03189              prev_nop_frag_since = 0;
03190            }
03191 
03192          for (; nops > 0; --nops)
03193            add_fixed_insn (NOP_INSN);
03194 
03195          /* Move on to a new frag, so that it is safe to simply
03196             decrease the size of prev_nop_frag.  */
03197          frag_wane (frag_now);
03198          frag_new (0);
03199          mips_move_labels ();
03200        }
03201       mips16_mark_labels ();
03202       mips_clear_insn_labels ();
03203     }
03204   mips_opts.noreorder++;
03205   mips_any_noreorder = 1;
03206 }
03207 
03208 /* End a nested noreorder block.  */
03209 
03210 static void
03211 end_noreorder (void)
03212 {
03213   mips_opts.noreorder--;
03214   if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
03215     {
03216       /* Commit to inserting prev_nop_frag_required nops and go back to
03217         handling nop insertion the .set reorder way.  */
03218       prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
03219                             * (mips_opts.mips16 ? 2 : 4));
03220       insert_into_history (prev_nop_frag_since,
03221                         prev_nop_frag_required, NOP_INSN);
03222       prev_nop_frag = NULL;
03223     }
03224 }
03225 
03226 /* Set up global variables for the start of a new macro.  */
03227 
03228 static void
03229 macro_start (void)
03230 {
03231   memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
03232   mips_macro_warning.delay_slot_p = (mips_opts.noreorder
03233                                  && (history[0].insn_mo->pinfo
03234                                     & (INSN_UNCOND_BRANCH_DELAY
03235                                        | INSN_COND_BRANCH_DELAY
03236                                        | INSN_COND_BRANCH_LIKELY)) != 0);
03237 }
03238 
03239 /* Given that a macro is longer than 4 bytes, return the appropriate warning
03240    for it.  Return null if no warning is needed.  SUBTYPE is a bitmask of
03241    RELAX_DELAY_SLOT and RELAX_NOMACRO.  */
03242 
03243 static const char *
03244 macro_warning (relax_substateT subtype)
03245 {
03246   if (subtype & RELAX_DELAY_SLOT)
03247     return _("Macro instruction expanded into multiple instructions"
03248             " in a branch delay slot");
03249   else if (subtype & RELAX_NOMACRO)
03250     return _("Macro instruction expanded into multiple instructions");
03251   else
03252     return 0;
03253 }
03254 
03255 /* Finish up a macro.  Emit warnings as appropriate.  */
03256 
03257 static void
03258 macro_end (void)
03259 {
03260   if (mips_macro_warning.sizes[0] > 4 || mips_macro_warning.sizes[1] > 4)
03261     {
03262       relax_substateT subtype;
03263 
03264       /* Set up the relaxation warning flags.  */
03265       subtype = 0;
03266       if (mips_macro_warning.sizes[1] > mips_macro_warning.sizes[0])
03267        subtype |= RELAX_SECOND_LONGER;
03268       if (mips_opts.warn_about_macros)
03269        subtype |= RELAX_NOMACRO;
03270       if (mips_macro_warning.delay_slot_p)
03271        subtype |= RELAX_DELAY_SLOT;
03272 
03273       if (mips_macro_warning.sizes[0] > 4 && mips_macro_warning.sizes[1] > 4)
03274        {
03275          /* Either the macro has a single implementation or both
03276             implementations are longer than 4 bytes.  Emit the
03277             warning now.  */
03278          const char *msg = macro_warning (subtype);
03279          if (msg != 0)
03280            as_warn (msg);
03281        }
03282       else
03283        {
03284          /* One implementation might need a warning but the other
03285             definitely doesn't.  */
03286          mips_macro_warning.first_frag->fr_subtype |= subtype;
03287        }
03288     }
03289 }
03290 
03291 /* Read a macro's relocation codes from *ARGS and store them in *R.
03292    The first argument in *ARGS will be either the code for a single
03293    relocation or -1 followed by the three codes that make up a
03294    composite relocation.  */
03295 
03296 static void
03297 macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
03298 {
03299   int i, next;
03300 
03301   next = va_arg (*args, int);
03302   if (next >= 0)
03303     r[0] = (bfd_reloc_code_real_type) next;
03304   else
03305     for (i = 0; i < 3; i++)
03306       r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
03307 }
03308 
03309 /* Build an instruction created by a macro expansion.  This is passed
03310    a pointer to the count of instructions created so far, an
03311    expression, the name of the instruction to build, an operand format
03312    string, and corresponding arguments.  */
03313 
03314 static void
03315 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
03316 {
03317   const struct mips_opcode *mo;
03318   struct mips_cl_insn insn;
03319   bfd_reloc_code_real_type r[3];
03320   va_list args;
03321 
03322   va_start (args, fmt);
03323 
03324   if (mips_opts.mips16)
03325     {
03326       mips16_macro_build (ep, name, fmt, args);
03327       va_end (args);
03328       return;
03329     }
03330 
03331   r[0] = BFD_RELOC_UNUSED;
03332   r[1] = BFD_RELOC_UNUSED;
03333   r[2] = BFD_RELOC_UNUSED;
03334   mo = (struct mips_opcode *) hash_find (op_hash, name);
03335   assert (mo);
03336   assert (strcmp (name, mo->name) == 0);
03337 
03338   while (1)
03339     {
03340       /* Search until we get a match for NAME.  It is assumed here that
03341         macros will never generate MDMX, MIPS-3D, or MT instructions.  */
03342       if (strcmp (fmt, mo->args) == 0
03343          && mo->pinfo != INSN_MACRO
03344          && OPCODE_IS_MEMBER (mo,
03345                             (mips_opts.isa
03346                             | (mips_opts.mips16 ? INSN_MIPS16 : 0)
03347                             | (mips_opts.ase_dsp ? INSN_DSP : 0)
03348                             | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
03349                                ? INSN_DSP64 : 0)
03350                             | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
03351                             | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
03352                             mips_opts.arch)
03353          && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
03354        break;
03355 
03356       ++mo;
03357       assert (mo->name);
03358       assert (strcmp (name, mo->name) == 0);
03359     }
03360 
03361   create_insn (&insn, mo);
03362   for (;;)
03363     {
03364       switch (*fmt++)
03365        {
03366        case '\0':
03367          break;
03368 
03369        case ',':
03370        case '(':
03371        case ')':
03372          continue;
03373 
03374        case '+':
03375          switch (*fmt++)
03376            {
03377            case 'A':
03378            case 'E':
03379              INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
03380              continue;
03381 
03382            case 'B':
03383            case 'F':
03384              /* Note that in the macro case, these arguments are already
03385                in MSB form.  (When handling the instruction in the
03386                non-macro case, these arguments are sizes from which
03387                MSB values must be calculated.)  */
03388              INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
03389              continue;
03390 
03391            case 'C':
03392            case 'G':
03393            case 'H':
03394              /* Note that in the macro case, these arguments are already
03395                in MSBD form.  (When handling the instruction in the
03396                non-macro case, these arguments are sizes from which
03397                MSBD values must be calculated.)  */
03398              INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
03399              continue;
03400 
03401            default:
03402              internalError ();
03403            }
03404          continue;
03405 
03406        case '2':
03407          INSERT_OPERAND (BP, insn, va_arg (args, int));
03408          continue;
03409 
03410        case 't':
03411        case 'w':
03412        case 'E':
03413          INSERT_OPERAND (RT, insn, va_arg (args, int));
03414          continue;
03415 
03416        case 'c':
03417          INSERT_OPERAND (CODE, insn, va_arg (args, int));
03418          continue;
03419 
03420        case 'T':
03421        case 'W':
03422          INSERT_OPERAND (FT, insn, va_arg (args, int));
03423          continue;
03424 
03425        case 'd':
03426        case 'G':
03427        case 'K':
03428          INSERT_OPERAND (RD, insn, va_arg (args, int));
03429          continue;
03430 
03431        case 'U':
03432          {
03433            int tmp = va_arg (args, int);
03434 
03435            INSERT_OPERAND (RT, insn, tmp);
03436            INSERT_OPERAND (RD, insn, tmp);
03437            continue;
03438          }
03439 
03440        case 'V':
03441        case 'S':
03442          INSERT_OPERAND (FS, insn, va_arg (args, int));
03443          continue;
03444 
03445        case 'z':
03446          continue;
03447 
03448        case '<':
03449          INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
03450          continue;
03451 
03452        case 'D':
03453          INSERT_OPERAND (FD, insn, va_arg (args, int));
03454          continue;
03455 
03456        case 'B':
03457          INSERT_OPERAND (CODE20, insn, va_arg (args, int));
03458          continue;
03459 
03460        case 'J':
03461          INSERT_OPERAND (CODE19, insn, va_arg (args, int));
03462          continue;
03463 
03464        case 'q':
03465          INSERT_OPERAND (CODE2, insn, va_arg (args, int));
03466          continue;
03467 
03468        case 'b':
03469        case 's':
03470        case 'r':
03471        case 'v':
03472          INSERT_OPERAND (RS, insn, va_arg (args, int));
03473          continue;
03474 
03475        case 'i':
03476        case 'j':
03477        case 'o':
03478          macro_read_relocs (&args, r);
03479          assert (*r == BFD_RELOC_GPREL16
03480                 || *r == BFD_RELOC_MIPS_LITERAL
03481                 || *r == BFD_RELOC_MIPS_HIGHER
03482                 || *r == BFD_RELOC_HI16_S
03483                 || *r == BFD_RELOC_LO16
03484                 || *r == BFD_RELOC_MIPS_GOT16
03485                 || *r == BFD_RELOC_MIPS_CALL16
03486                 || *r == BFD_RELOC_MIPS_GOT_DISP
03487                 || *r == BFD_RELOC_MIPS_GOT_PAGE
03488                 || *r == BFD_RELOC_MIPS_GOT_OFST
03489                 || *r == BFD_RELOC_MIPS_GOT_LO16
03490                 || *r == BFD_RELOC_MIPS_CALL_LO16);
03491          continue;
03492 
03493        case 'u':
03494          macro_read_relocs (&args, r);
03495          assert (ep != NULL
03496                 && (ep->X_op == O_constant
03497                     || (ep->X_op == O_symbol
03498                        && (*r == BFD_RELOC_MIPS_HIGHEST
03499                            || *r == BFD_RELOC_HI16_S
03500                            || *r == BFD_RELOC_HI16
03501                            || *r == BFD_RELOC_GPREL16
03502                            || *r == BFD_RELOC_MIPS_GOT_HI16
03503                            || *r == BFD_RELOC_MIPS_CALL_HI16))));
03504          continue;
03505 
03506        case 'p':
03507          assert (ep != NULL);
03508 
03509          /*
03510           * This allows macro() to pass an immediate expression for
03511           * creating short branches without creating a symbol.
03512           *
03513           * We don't allow branch relaxation for these branches, as
03514           * they should only appear in ".set nomacro" anyway.
03515           */
03516          if (ep->X_op == O_constant)
03517            {
03518              if ((ep->X_add_number & 3) != 0)
03519               as_bad (_("branch to misaligned address (0x%lx)"),
03520                      (unsigned long) ep->X_add_number);
03521              if ((ep->X_add_number + 0x20000) & ~0x3ffff)
03522               as_bad (_("branch address range overflow (0x%lx)"),
03523                      (unsigned long) ep->X_add_number);
03524              insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
03525              ep = NULL;
03526            }
03527          else
03528            *r = BFD_RELOC_16_PCREL_S2;
03529          continue;
03530 
03531        case 'a':
03532          assert (ep != NULL);
03533          *r = BFD_RELOC_MIPS_JMP;
03534          continue;
03535 
03536        case 'C':
03537          INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
03538          continue;
03539 
03540        case 'k':
03541          INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
03542          continue;
03543 
03544        default:
03545          internalError ();
03546        }
03547       break;
03548     }
03549   va_end (args);
03550   assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
03551 
03552   append_insn (&insn, ep, r);
03553 }
03554 
03555 static void
03556 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
03557                   va_list args)
03558 {
03559   struct mips_opcode *mo;
03560   struct mips_cl_insn insn;
03561   bfd_reloc_code_real_type r[3]
03562     = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
03563 
03564   mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
03565   assert (mo);
03566   assert (strcmp (name, mo->name) == 0);
03567 
03568   while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
03569     {
03570       ++mo;
03571       assert (mo->name);
03572       assert (strcmp (name, mo->name) == 0);
03573     }
03574 
03575   create_insn (&insn, mo);
03576   for (;;)
03577     {
03578       int c;
03579 
03580       c = *fmt++;
03581       switch (c)
03582        {
03583        case '\0':
03584          break;
03585 
03586        case ',':
03587        case '(':
03588        case ')':
03589          continue;
03590 
03591        case 'y':
03592        case 'w':
03593          MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
03594          continue;
03595 
03596        case 'x':
03597        case 'v':
03598          MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
03599          continue;
03600 
03601        case 'z':
03602          MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
03603          continue;
03604 
03605        case 'Z':
03606          MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
03607          continue;
03608 
03609        case '0':
03610        case 'S':
03611        case 'P':
03612        case 'R':
03613          continue;
03614 
03615        case 'X':
03616          MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
03617          continue;
03618 
03619        case 'Y':
03620          {
03621            int regno;
03622 
03623            regno = va_arg (args, int);
03624            regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
03625            MIPS16_INSERT_OPERAND (REG32R, insn, regno);
03626          }
03627          continue;
03628 
03629        case '<':
03630        case '>':
03631        case '4':
03632        case '5':
03633        case 'H':
03634        case 'W':
03635        case 'D':
03636        case 'j':
03637        case '8':
03638        case 'V':
03639        case 'C':
03640        case 'U':
03641        case 'k':
03642        case 'K':
03643        case 'p':
03644        case 'q':
03645          {
03646            assert (ep != NULL);
03647 
03648            if (ep->X_op != O_constant)
03649              *r = (int) BFD_RELOC_UNUSED + c;
03650            else
03651              {
03652               mips16_immed (NULL, 0, c, ep->X_add_number, FALSE, FALSE,
03653                            FALSE, &insn.insn_opcode, &insn.use_extend,
03654                            &insn.extend);
03655               ep = NULL;
03656               *r = BFD_RELOC_UNUSED;
03657              }
03658          }
03659          continue;
03660 
03661        case '6':
03662          MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
03663          continue;
03664        }
03665 
03666       break;
03667     }
03668 
03669   assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
03670 
03671   append_insn (&insn, ep, r);
03672 }
03673 
03674 /*
03675  * Sign-extend 32-bit mode constants that have bit 31 set and all
03676  * higher bits unset.
03677  */
03678 static void
03679 normalize_constant_expr (expressionS *ex)
03680 {
03681   if (ex->X_op == O_constant
03682       && IS_ZEXT_32BIT_NUM (ex->X_add_number))
03683     ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
03684                      - 0x80000000);
03685 }
03686 
03687 /*
03688  * Sign-extend 32-bit mode address offsets that have bit 31 set and
03689  * all higher bits unset.
03690  */
03691 static void
03692 normalize_address_expr (expressionS *ex)
03693 {
03694   if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
03695        || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
03696       && IS_ZEXT_32BIT_NUM (ex->X_add_number))
03697     ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
03698                      - 0x80000000);
03699 }
03700 
03701 /*
03702  * Generate a "jalr" instruction with a relocation hint to the called
03703  * function.  This occurs in NewABI PIC code.
03704  */
03705 static void
03706 macro_build_jalr (expressionS *ep)
03707 {
03708   char *f = NULL;
03709 
03710   if (HAVE_NEWABI)
03711     {
03712       frag_grow (8);
03713       f = frag_more (0);
03714     }
03715   macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
03716   if (HAVE_NEWABI)
03717     fix_new_exp (frag_now, f - frag_now->fr_literal,
03718                4, ep, FALSE, BFD_RELOC_MIPS_JALR);
03719 }
03720 
03721 /*
03722  * Generate a "lui" instruction.
03723  */
03724 static void
03725 macro_build_lui (expressionS *ep, int regnum)
03726 {
03727   expressionS high_expr;
03728   const struct mips_opcode *mo;
03729   struct mips_cl_insn insn;
03730   bfd_reloc_code_real_type r[3]
03731     = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
03732   const char *name = "lui";
03733   const char *fmt = "t,u";
03734 
03735   assert (! mips_opts.mips16);
03736 
03737   high_expr = *ep;
03738 
03739   if (high_expr.X_op == O_constant)
03740     {
03741       /* We can compute the instruction now without a relocation entry.  */
03742       high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
03743                             >> 16) & 0xffff;
03744       *r = BFD_RELOC_UNUSED;
03745     }
03746   else
03747     {
03748       assert (ep->X_op == O_symbol);
03749       /* _gp_disp is a special case, used from s_cpload.
03750         __gnu_local_gp is used if mips_no_shared.  */
03751       assert (mips_pic == NO_PIC
03752              || (! HAVE_NEWABI
03753                 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
03754              || (! mips_in_shared
03755                 && strcmp (S_GET_NAME (ep->X_add_symbol),
03756                              "__gnu_local_gp") == 0));
03757       *r = BFD_RELOC_HI16_S;
03758     }
03759 
03760   mo = hash_find (op_hash, name);
03761   assert (strcmp (name, mo->name) == 0);
03762   assert (strcmp (fmt, mo->args) == 0);
03763   create_insn (&insn, mo);
03764 
03765   insn.insn_opcode = insn.insn_mo->match;
03766   INSERT_OPERAND (RT, insn, regnum);
03767   if (*r == BFD_RELOC_UNUSED)
03768     {
03769       insn.insn_opcode |= high_expr.X_add_number;
03770       append_insn (&insn, NULL, r);
03771     }
03772   else
03773     append_insn (&insn, &high_expr, r);
03774 }
03775 
03776 /* Generate a sequence of instructions to do a load or store from a constant
03777    offset off of a base register (breg) into/from a target register (treg),
03778    using AT if necessary.  */
03779 static void
03780 macro_build_ldst_constoffset (expressionS *ep, const char *op,
03781                            int treg, int breg, int dbl)
03782 {
03783   assert (ep->X_op == O_constant);
03784 
03785   /* Sign-extending 32-bit constants makes their handling easier.  */
03786   if (!dbl)
03787     normalize_constant_expr (ep);
03788 
03789   /* Right now, this routine can only handle signed 32-bit constants.  */
03790   if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
03791     as_warn (_("operand overflow"));
03792 
03793   if (IS_SEXT_16BIT_NUM(ep->X_add_number))
03794     {
03795       /* Signed 16-bit offset will fit in the op.  Easy!  */
03796       macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);
03797     }
03798   else
03799     {
03800       /* 32-bit offset, need multiple instructions and AT, like:
03801           lui      $tempreg,const_hi       (BFD_RELOC_HI16_S)
03802           addu     $tempreg,$tempreg,$breg
03803            <op>     $treg,const_lo($tempreg)   (BFD_RELOC_LO16)
03804          to handle the complete offset.  */
03805       macro_build_lui (ep, AT);
03806       macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
03807       macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
03808 
03809       if (mips_opts.noat)
03810        as_bad (_("Macro used $at after \".set noat\""));
03811     }
03812 }
03813 
03814 /*                   set_at()
03815  * Generates code to set the $at register to true (one)
03816  * if reg is less than the immediate expression.
03817  */
03818 static void
03819 set_at (int reg, int unsignedp)
03820 {
03821   if (imm_expr.X_op == O_constant
03822       && imm_expr.X_add_number >= -0x8000
03823       && imm_expr.X_add_number < 0x8000)
03824     macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", "t,r,j",
03825                AT, reg, BFD_RELOC_LO16);
03826   else
03827     {
03828       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
03829       macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
03830     }
03831 }
03832 
03833 /* Warn if an expression is not a constant.  */
03834 
03835 static void
03836 check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
03837 {
03838   if (ex->X_op == O_big)
03839     as_bad (_("unsupported large constant"));
03840   else if (ex->X_op != O_constant)
03841     as_bad (_("Instruction %s requires absolute expression"),
03842            ip->insn_mo->name);
03843 
03844   if (HAVE_32BIT_GPRS)
03845     normalize_constant_expr (ex);
03846 }
03847 
03848 /* Count the leading zeroes by performing a binary chop. This is a
03849    bulky bit of source, but performance is a LOT better for the
03850    majority of values than a simple loop to count the bits:
03851        for (lcnt = 0; (lcnt < 32); lcnt++)
03852          if ((v) & (1 << (31 - lcnt)))
03853            break;
03854   However it is not code size friendly, and the gain will drop a bit
03855   on certain cached systems.
03856 */
03857 #define COUNT_TOP_ZEROES(v)             \
03858   (((v) & ~0xffff) == 0                 \
03859    ? ((v) & ~0xff) == 0                 \
03860      ? ((v) & ~0xf) == 0                \
03861        ? ((v) & ~0x3) == 0              \
03862          ? ((v) & ~0x1) == 0            \
03863            ? !(v)                       \
03864              ? 32                       \
03865              : 31                       \
03866            : 30                         \
03867          : ((v) & ~0x7) == 0            \
03868            ? 29                         \
03869            : 28                         \
03870        : ((v) & ~0x3f) == 0             \
03871          ? ((v) & ~0x1f) == 0           \
03872            ? 27                         \
03873            : 26                         \
03874          : ((v) & ~0x7f) == 0           \
03875            ? 25                         \
03876            : 24                         \
03877      : ((v) & ~0xfff) == 0              \
03878        ? ((v) & ~0x3ff) == 0            \
03879          ? ((v) & ~0x1ff) == 0          \
03880            ? 23                         \
03881            : 22                         \
03882          : ((v) & ~0x7ff) == 0          \
03883            ? 21                         \
03884            : 20                         \
03885        : ((v) & ~0x3fff) == 0           \
03886          ? ((v) & ~0x1fff) == 0         \
03887            ? 19                         \
03888            : 18                         \
03889          : ((v) & ~0x7fff) == 0         \
03890            ? 17                         \
03891            : 16                         \
03892    : ((v) & ~0xffffff) == 0             \
03893      ? ((v) & ~0xfffff) == 0            \
03894        ? ((v) & ~0x3ffff) == 0          \
03895          ? ((v) & ~0x1ffff) == 0        \
03896            ? 15                         \
03897            : 14                         \
03898          : ((v) & ~0x7ffff) == 0        \
03899            ? 13                         \
03900            : 12                         \
03901        : ((v) & ~0x3fffff) == 0         \
03902          ? ((v) & ~0x1fffff) == 0       \
03903            ? 11                         \
03904            : 10                         \
03905          : ((v) & ~0x7fffff) == 0       \
03906            ? 9                          \
03907            : 8                          \
03908      : ((v) & ~0xfffffff) == 0          \
03909        ? ((v) & ~0x3ffffff) == 0        \
03910          ? ((v) & ~0x1ffffff) == 0      \
03911            ? 7                          \
03912            : 6                          \
03913          : ((v) & ~0x7ffffff) == 0      \
03914            ? 5                          \
03915            : 4                          \
03916        : ((v) & ~0x3fffffff) == 0       \
03917          ? ((v) & ~0x1fffffff) == 0     \
03918            ? 3                          \
03919            : 2                          \
03920          : ((v) & ~0x7fffffff) == 0     \
03921            ? 1                          \
03922            : 0)
03923 
03924 /*                   load_register()
03925  *  This routine generates the least number of instructions necessary to load
03926  *  an absolute expression value into a register.
03927  */
03928 static void
03929 load_register (int reg, expressionS *ep, int dbl)
03930 {
03931   int freg;
03932   expressionS hi32, lo32;
03933 
03934   if (ep->X_op != O_big)
03935     {
03936       assert (ep->X_op == O_constant);
03937 
03938       /* Sign-extending 32-bit constants makes their handling easier.  */
03939       if (!dbl)
03940        normalize_constant_expr (ep);
03941 
03942       if (IS_SEXT_16BIT_NUM (ep->X_add_number))
03943        {
03944          /* We can handle 16 bit signed values with an addiu to
03945             $zero.  No need to ever use daddiu here, since $zero and
03946             the result are always correct in 32 bit mode.  */
03947          macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
03948          return;
03949        }
03950       else if (ep->X_add_number >= 0 && ep->X_add_number < 0x10000)
03951        {
03952          /* We can handle 16 bit unsigned values with an ori to
03953              $zero.  */
03954          macro_build (ep, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
03955          return;
03956        }
03957       else if ((IS_SEXT_32BIT_NUM (ep->X_add_number)))
03958        {
03959          /* 32 bit values require an lui.  */
03960          macro_build (ep, "lui", "t,u", reg, BFD_RELOC_HI16);
03961          if ((ep->X_add_number & 0xffff) != 0)
03962            macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
03963          return;
03964        }
03965     }
03966 
03967   /* The value is larger than 32 bits.  */
03968 
03969   if (!dbl || HAVE_32BIT_GPRS)
03970     {
03971       char value[32];
03972 
03973       sprintf_vma (value, ep->X_add_number);
03974       as_bad (_("Number (0x%s) larger than 32 bits"), value);
03975       macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
03976       return;
03977     }
03978 
03979   if (ep->X_op != O_big)
03980     {
03981       hi32 = *ep;
03982       hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
03983       hi32.X_add_number = (valueT) hi32.X_add_number >> 16;
03984       hi32.X_add_number &= 0xffffffff;
03985       lo32 = *ep;
03986       lo32.X_add_number &= 0xffffffff;
03987     }
03988   else
03989     {
03990       assert (ep->X_add_number > 2);
03991       if (ep->X_add_number == 3)
03992        generic_bignum[3] = 0;
03993       else if (ep->X_add_number > 4)
03994        as_bad (_("Number larger than 64 bits"));
03995       lo32.X_op = O_constant;
03996       lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
03997       hi32.X_op = O_constant;
03998       hi32.X_add_number = generic_bignum[2] + (generic_bignum[3] << 16);
03999     }
04000 
04001   if (hi32.X_add_number == 0)
04002     freg = 0;
04003   else
04004     {
04005       int shift, bit;
04006       unsigned long hi, lo;
04007 
04008       if (hi32.X_add_number == (offsetT) 0xffffffff)
04009        {
04010          if ((lo32.X_add_number & 0xffff8000) == 0xffff8000)
04011            {
04012              macro_build (&lo32, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
04013              return;
04014            }
04015          if (lo32.X_add_number & 0x80000000)
04016            {
04017              macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
04018              if (lo32.X_add_number & 0xffff)
04019               macro_build (&lo32, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
04020              return;
04021            }
04022        }
04023 
04024       /* Check for 16bit shifted constant.  We know that hi32 is
04025          non-zero, so start the mask on the first bit of the hi32
04026          value.  */
04027       shift = 17;
04028       do
04029        {
04030          unsigned long himask, lomask;
04031 
04032          if (shift < 32)
04033            {
04034              himask = 0xffff >> (32 - shift);
04035              lomask = (0xffff << shift) & 0xffffffff;
04036            }
04037          else
04038            {
04039              himask = 0xffff << (shift - 32);
04040              lomask = 0;
04041            }
04042          if ((hi32.X_add_number & ~(offsetT) himask) == 0
04043              && (lo32.X_add_number & ~(offsetT) lomask) == 0)
04044            {
04045              expressionS tmp;
04046 
04047              tmp.X_op = O_constant;
04048              if (shift < 32)
04049               tmp.X_add_number = ((hi32.X_add_number << (32 - shift))
04050                                 | (lo32.X_add_number >> shift));
04051              else
04052               tmp.X_add_number = hi32.X_add_number >> (shift - 32);
04053              macro_build (&tmp, "ori", "t,r,i", reg, 0, BFD_RELOC_LO16);
04054              macro_build (NULL, (shift >= 32) ? "dsll32" : "dsll", "d,w,<",
04055                         reg, reg, (shift >= 32) ? shift - 32 : shift);
04056              return;
04057            }
04058          ++shift;
04059        }
04060       while (shift <= (64 - 16));
04061 
04062       /* Find the bit number of the lowest one bit, and store the
04063          shifted value in hi/lo.  */
04064       hi = (unsigned long) (hi32.X_add_number & 0xffffffff);
04065       lo = (unsigned long) (lo32.X_add_number & 0xffffffff);
04066       if (lo != 0)
04067        {
04068          bit = 0;
04069          while ((lo & 1) == 0)
04070            {
04071              lo >>= 1;
04072              ++bit;
04073            }
04074          lo |= (hi & (((unsigned long) 1 << bit) - 1)) << (32 - bit);
04075          hi >>= bit;
04076        }
04077       else
04078        {
04079          bit = 32;
04080          while ((hi & 1) == 0)
04081            {
04082              hi >>= 1;
04083              ++bit;
04084            }
04085          lo = hi;
04086          hi = 0;
04087        }
04088 
04089       /* Optimize if the shifted value is a (power of 2) - 1.  */
04090       if ((hi == 0 && ((lo + 1) & lo) == 0)
04091          || (lo == 0xffffffff && ((hi + 1) & hi) == 0))
04092        {
04093          shift = COUNT_TOP_ZEROES ((unsigned int) hi32.X_add_number);
04094          if (shift != 0)
04095            {
04096              expressionS tmp;
04097 
04098              /* This instruction will set the register to be all
04099                  ones.  */
04100              tmp.X_op = O_constant;
04101              tmp.X_add_number = (offsetT) -1;
04102              macro_build (&tmp, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
04103              if (bit != 0)
04104               {
04105                 bit += shift;
04106                 macro_build (NULL, (bit >= 32) ? "dsll32" : "dsll", "d,w,<",
04107                             reg, reg, (bit >= 32) ? bit - 32 : bit);
04108               }
04109              macro_build (NULL, (shift >= 32) ? "dsrl32" : "dsrl", "d,w,<",
04110                         reg, reg, (shift >= 32) ? shift - 32 : shift);
04111              return;
04112            }
04113        }
04114 
04115       /* Sign extend hi32 before calling load_register, because we can
04116          generally get better code when we load a sign extended value.  */
04117       if ((hi32.X_add_number & 0x80000000) != 0)
04118        hi32.X_add_number |= ~(offsetT) 0xffffffff;
04119       load_register (reg, &hi32, 0);
04120       freg = reg;
04121     }
04122   if ((lo32.X_add_number & 0xffff0000) == 0)
04123     {
04124       if (freg != 0)
04125        {
04126          macro_build (NULL, "dsll32", "d,w,<", reg, freg, 0);
04127          freg = reg;
04128        }
04129     }
04130   else
04131     {
04132       expressionS mid16;
04133 
04134       if ((freg == 0) && (lo32.X_add_number == (offsetT) 0xffffffff))
04135        {
04136          macro_build (&lo32, "lui", "t,u", reg, BFD_RELOC_HI16);
04137          macro_build (NULL, "dsrl32", "d,w,<", reg, reg, 0);
04138          return;
04139        }
04140 
04141       if (freg != 0)
04142        {
04143          macro_build (NULL, "dsll", "d,w,<", reg, freg, 16);
04144          freg = reg;
04145        }
04146       mid16 = lo32;
04147       mid16.X_add_number >>= 16;
04148       macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
04149       macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
04150       freg = reg;
04151     }
04152   if ((lo32.X_add_number & 0xffff) != 0)
04153     macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
04154 }
04155 
04156 static inline void
04157 load_delay_nop (void)
04158 {
04159   if (!gpr_interlocks)
04160     macro_build (NULL, "nop", "");
04161 }
04162 
04163 /* Load an address into a register.  */
04164 
04165 static void
04166 load_address (int reg, expressionS *ep, int *used_at)
04167 {
04168   if (ep->X_op != O_constant
04169       && ep->X_op != O_symbol)
04170     {
04171       as_bad (_("expression too complex"));
04172       ep->X_op = O_constant;
04173     }
04174 
04175   if (ep->X_op == O_constant)
04176     {
04177       load_register (reg, ep, HAVE_64BIT_ADDRESSES);
04178       return;
04179     }
04180 
04181   if (mips_pic == NO_PIC)
04182     {
04183       /* If this is a reference to a GP relative symbol, we want
04184           addiu      $reg,$gp,<sym>              (BFD_RELOC_GPREL16)
04185         Otherwise we want
04186           lui        $reg,<sym>           (BFD_RELOC_HI16_S)
04187           addiu      $reg,$reg,<sym>             (BFD_RELOC_LO16)
04188         If we have an addend, we always use the latter form.
04189 
04190         With 64bit address space and a usable $at we want
04191           lui        $reg,<sym>           (BFD_RELOC_MIPS_HIGHEST)
04192           lui        $at,<sym>            (BFD_RELOC_HI16_S)
04193           daddiu     $reg,<sym>           (BFD_RELOC_MIPS_HIGHER)
04194           daddiu     $at,<sym>            (BFD_RELOC_LO16)
04195           dsll32     $reg,0
04196           daddu      $reg,$reg,$at
04197 
04198         If $at is already in use, we use a path which is suboptimal
04199         on superscalar processors.
04200           lui        $reg,<sym>           (BFD_RELOC_MIPS_HIGHEST)
04201           daddiu     $reg,<sym>           (BFD_RELOC_MIPS_HIGHER)
04202           dsll              $reg,16
04203           daddiu     $reg,<sym>           (BFD_RELOC_HI16_S)
04204           dsll              $reg,16
04205           daddiu     $reg,<sym>           (BFD_RELOC_LO16)
04206 
04207         For GP relative symbols in 64bit address space we can use
04208         the same sequence as in 32bit address space.  */
04209       if (HAVE_64BIT_SYMBOLS)
04210        {
04211          if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
04212              && !nopic_need_relax (ep->X_add_symbol, 1))
04213            {
04214              relax_start (ep->X_add_symbol);
04215              macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
04216                         mips_gp_register, BFD_RELOC_GPREL16);
04217              relax_switch ();
04218            }
04219 
04220          if (*used_at == 0 && !mips_opts.noat)
04221            {
04222              macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
04223              macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
04224              macro_build (ep, "daddiu", "t,r,j", reg, reg,
04225                         BFD_RELOC_MIPS_HIGHER);
04226              macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
04227              macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
04228              macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);
04229              *used_at = 1;
04230            }
04231          else
04232            {
04233              macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
04234              macro_build (ep, "daddiu", "t,r,j", reg, reg,
04235                         BFD_RELOC_MIPS_HIGHER);
04236              macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
04237              macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
04238              macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
04239              macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
04240            }
04241 
04242          if (mips_relax.sequence)
04243            relax_end ();
04244        }
04245       else
04246        {
04247          if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
04248              && !nopic_need_relax (ep->X_add_symbol, 1))
04249            {
04250              relax_start (ep->X_add_symbol);
04251              macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
04252                         mips_gp_register, BFD_RELOC_GPREL16);
04253              relax_switch ();
04254            }
04255          macro_build_lui (ep, reg);
04256          macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
04257                      reg, reg, BFD_RELOC_LO16);
04258          if (mips_relax.sequence)
04259            relax_end ();
04260        }
04261     }
04262   else if (!mips_big_got)
04263     {
04264       expressionS ex;
04265 
04266       /* If this is a reference to an external symbol, we want
04267           lw         $reg,<sym>($gp)             (BFD_RELOC_MIPS_GOT16)
04268         Otherwise we want
04269           lw         $reg,<sym>($gp)             (BFD_RELOC_MIPS_GOT16)
04270           nop
04271           addiu      $reg,$reg,<sym>             (BFD_RELOC_LO16)
04272         If there is a constant, it must be added in after.
04273 
04274         If we have NewABI, we want
04275           lw         $reg,<sym+cst>($gp)  (BFD_RELOC_MIPS_GOT_DISP)
04276          unless we're referencing a global symbol with a non-zero
04277          offset, in which case cst must be added separately.  */
04278       if (HAVE_NEWABI)
04279        {
04280          if (ep->X_add_number)
04281            {
04282              ex.X_add_number = ep->X_add_number;
04283              ep->X_add_number = 0;
04284              relax_start (ep->X_add_symbol);
04285              macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
04286                         BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
04287              if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
04288               as_bad (_("PIC code offset overflow (max 16 signed bits)"));
04289              ex.X_op = O_constant;
04290              macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
04291                         reg, reg, BFD_RELOC_LO16);
04292              ep->X_add_number = ex.X_add_number;
04293              relax_switch ();
04294            }
04295          macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
04296                      BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
04297          if (mips_relax.sequence)
04298            relax_end ();
04299        }
04300       else
04301        {
04302          ex.X_add_number = ep->X_add_number;
04303          ep->X_add_number = 0;
04304          macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
04305                      BFD_RELOC_MIPS_GOT16, mips_gp_register);
04306          load_delay_nop ();
04307          relax_start (ep->X_add_symbol);
04308          relax_switch ();
04309          macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
04310                      BFD_RELOC_LO16);
04311          relax_end ();
04312 
04313          if (ex.X_add_number != 0)
04314            {
04315              if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
04316               as_bad (_("PIC code offset overflow (max 16 signed bits)"));
04317              ex.X_op = O_constant;
04318              macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
04319                         reg, reg, BFD_RELOC_LO16);
04320            }
04321        }
04322     }
04323   else if (mips_big_got)
04324     {
04325       expressionS ex;
04326 
04327       /* This is the large GOT case.  If this is a reference to an
04328         external symbol, we want
04329           lui        $reg,<sym>           (BFD_RELOC_MIPS_GOT_HI16)
04330           addu              $reg,$reg,$gp
04331           lw         $reg,<sym>($reg)     (BFD_RELOC_MIPS_GOT_LO16)
04332 
04333         Otherwise, for a reference to a local symbol in old ABI, we want
04334           lw         $reg,<sym>($gp)             (BFD_RELOC_MIPS_GOT16)
04335           nop
04336           addiu      $reg,$reg,<sym>             (BFD_RELOC_LO16)
04337         If there is a constant, it must be added in after.
04338 
04339         In the NewABI, for local symbols, with or without offsets, we want:
04340           lw         $reg,<sym>($gp)             (BFD_RELOC_MIPS_GOT_PAGE)
04341           addiu      $reg,$reg,<sym>             (BFD_RELOC_MIPS_GOT_OFST)
04342       */
04343       if (HAVE_NEWABI)
04344        {
04345          ex.X_add_number = ep->X_add_number;
04346          ep->X_add_number = 0;
04347          relax_start (ep->X_add_symbol);
04348          macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
04349          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
04350                      reg, reg, mips_gp_register);
04351          macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
04352                      reg, BFD_RELOC_MIPS_GOT_LO16, reg);
04353          if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
04354            as_bad (_("PIC code offset overflow (max 16 signed bits)"));
04355          else if (ex.X_add_number)
04356            {
04357              ex.X_op = O_constant;
04358              macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
04359                         BFD_RELOC_LO16);
04360            }
04361 
04362          ep->X_add_number = ex.X_add_number;
04363          relax_switch ();
04364          macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
04365                      BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
04366          macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
04367                      BFD_RELOC_MIPS_GOT_OFST);
04368          relax_end ();
04369        }
04370       else
04371        {
04372          ex.X_add_number = ep->X_add_number;
04373          ep->X_add_number = 0;
04374          relax_start (ep->X_add_symbol);
04375          macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_GOT_HI16);
04376          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
04377                      reg, reg, mips_gp_register);
04378          macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)",
04379                      reg, BFD_RELOC_MIPS_GOT_LO16, reg);
04380          relax_switch ();
04381          if (reg_needs_delay (mips_gp_register))
04382            {
04383              /* We need a nop before loading from $gp.  This special
04384                check is required because the lui which starts the main
04385                instruction stream does not refer to $gp, and so will not
04386                insert the nop which may be required.  */
04387              macro_build (NULL, "nop", "");
04388            }
04389          macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
04390                      BFD_RELOC_MIPS_GOT16, mips_gp_register);
04391          load_delay_nop ();
04392          macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
04393                      BFD_RELOC_LO16);
04394          relax_end ();
04395 
04396          if (ex.X_add_number != 0)
04397            {
04398              if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
04399               as_bad (_("PIC code offset overflow (max 16 signed bits)"));
04400              ex.X_op = O_constant;
04401              macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
04402                         BFD_RELOC_LO16);
04403            }
04404        }
04405     }
04406   else
04407     abort ();
04408 
04409   if (mips_opts.noat && *used_at == 1)
04410     as_bad (_("Macro used $at after \".set noat\""));
04411 }
04412 
04413 /* Move the contents of register SOURCE into register DEST.  */
04414 
04415 static void
04416 move_register (int dest, int source)
04417 {
04418   macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",
04419               dest, source, 0);
04420 }
04421 
04422 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
04423    LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
04424    The two alternatives are:
04425 
04426    Global symbol            Local sybmol
04427    -------------            ------------
04428    lw DEST,%got(SYMBOL)            lw DEST,%got(SYMBOL + OFFSET)
04429    ...                      ...
04430    addiu DEST,DEST,OFFSET   addiu DEST,DEST,%lo(SYMBOL + OFFSET)
04431 
04432    load_got_offset emits the first instruction and add_got_offset
04433    emits the second for a 16-bit offset or add_got_offset_hilo emits
04434    a sequence to add a 32-bit offset using a scratch register.  */
04435 
04436 static void
04437 load_got_offset (int dest, expressionS *local)
04438 {
04439   expressionS global;
04440 
04441   global = *local;
04442   global.X_add_number = 0;
04443 
04444   relax_start (local->X_add_symbol);
04445   macro_build (&global, ADDRESS_LOAD_INSN, "t,o(b)", dest,
04446               BFD_RELOC_MIPS_GOT16, mips_gp_register);
04447   relax_switch ();
04448   macro_build (local, ADDRESS_LOAD_INSN, "t,o(b)", dest,
04449               BFD_RELOC_MIPS_GOT16, mips_gp_register);
04450   relax_end ();
04451 }
04452 
04453 static void
04454 add_got_offset (int dest, expressionS *local)
04455 {
04456   expressionS global;
04457 
04458   global.X_op = O_constant;
04459   global.X_op_symbol = NULL;
04460   global.X_add_symbol = NULL;
04461   global.X_add_number = local->X_add_number;
04462 
04463   relax_start (local->X_add_symbol);
04464   macro_build (&global, ADDRESS_ADDI_INSN, "t,r,j",
04465               dest, dest, BFD_RELOC_LO16);
04466   relax_switch ();
04467   macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", dest, dest, BFD_RELOC_LO16);
04468   relax_end ();
04469 }
04470 
04471 static void
04472 add_got_offset_hilo (int dest, expressionS *local, int tmp)
04473 {
04474   expressionS global;
04475   int hold_mips_optimize;
04476 
04477   global.X_op = O_constant;
04478   global.X_op_symbol = NULL;
04479   global.X_add_symbol = NULL;
04480   global.X_add_number = local->X_add_number;
04481 
04482   relax_start (local->X_add_symbol);
04483   load_register (tmp, &global, HAVE_64BIT_ADDRESSES);
04484   relax_switch ();
04485   /* Set mips_optimize around the lui instruction to avoid
04486      inserting an unnecessary nop after the lw.  */
04487   hold_mips_optimize = mips_optimize;
04488   mips_optimize = 2;
04489   macro_build_lui (&global, tmp);
04490   mips_optimize = hold_mips_optimize;
04491   macro_build (local, ADDRESS_ADDI_INSN, "t,r,j", tmp, tmp, BFD_RELOC_LO16);
04492   relax_end ();
04493 
04494   macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dest, dest, tmp);
04495 }
04496 
04497 /*
04498  *                   Build macros
04499  *   This routine implements the seemingly endless macro or synthesized
04500  * instructions and addressing modes in the mips assembly language. Many
04501  * of these macros are simple and are similar to each other. These could
04502  * probably be handled by some kind of table or grammar approach instead of
04503  * this verbose method. Others are not simple macros but are more like
04504  * optimizing code generation.
04505  *   One interesting optimization is when several store macros appear
04506  * consecutively that would load AT with the upper half of the same address.
04507  * The ensuing load upper instructions are ommited. This implies some kind
04508  * of global optimization. We currently only optimize within a single macro.
04509  *   For many of the load and store macros if the address is specified as a
04510  * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
04511  * first load register 'at' with zero and use it as the base register. The
04512  * mips assembler simply uses register $zero. Just one tiny optimization
04513  * we're missing.
04514  */
04515 static void
04516 macro (struct mips_cl_insn *ip)
04517 {
04518   int treg, sreg, dreg, breg;
04519   int tempreg;
04520   int mask;
04521   int used_at = 0;
04522   expressionS expr1;
04523   const char *s;
04524   const char *s2;
04525   const char *fmt;
04526   int likely = 0;
04527   int dbl = 0;
04528   int coproc = 0;
04529   int lr = 0;
04530   int imm = 0;
04531   int call = 0;
04532   int off;
04533   offsetT maxnum;
04534   bfd_reloc_code_real_type r;
04535   int hold_mips_optimize;
04536 
04537   assert (! mips_opts.mips16);
04538 
04539   treg = (ip->insn_opcode >> 16) & 0x1f;
04540   dreg = (ip->insn_opcode >> 11) & 0x1f;
04541   sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
04542   mask = ip->insn_mo->mask;
04543 
04544   expr1.X_op = O_constant;
04545   expr1.X_op_symbol = NULL;
04546   expr1.X_add_symbol = NULL;
04547   expr1.X_add_number = 1;
04548 
04549   switch (mask)
04550     {
04551     case M_DABS:
04552       dbl = 1;
04553     case M_ABS:
04554       /* bgez $a0,.+12
04555         move v0,$a0
04556         sub v0,$zero,$a0
04557         */
04558 
04559       start_noreorder ();
04560 
04561       expr1.X_add_number = 8;
04562       macro_build (&expr1, "bgez", "s,p", sreg);
04563       if (dreg == sreg)
04564        macro_build (NULL, "nop", "", 0);
04565       else
04566        move_register (dreg, sreg);
04567       macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
04568 
04569       end_noreorder ();
04570       break;
04571 
04572     case M_ADD_I:
04573       s = "addi";
04574       s2 = "add";
04575       goto do_addi;
04576     case M_ADDU_I:
04577       s = "addiu";
04578       s2 = "addu";
04579       goto do_addi;
04580     case M_DADD_I:
04581       dbl = 1;
04582       s = "daddi";
04583       s2 = "dadd";
04584       goto do_addi;
04585     case M_DADDU_I:
04586       dbl = 1;
04587       s = "daddiu";
04588       s2 = "daddu";
04589     do_addi:
04590       if (imm_expr.X_op == O_constant
04591          && imm_expr.X_add_number >= -0x8000
04592          && imm_expr.X_add_number < 0x8000)
04593        {
04594          macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
04595          break;
04596        }
04597       used_at = 1;
04598       load_register (AT, &imm_expr, dbl);
04599       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
04600       break;
04601 
04602     case M_AND_I:
04603       s = "andi";
04604       s2 = "and";
04605       goto do_bit;
04606     case M_OR_I:
04607       s = "ori";
04608       s2 = "or";
04609       goto do_bit;
04610     case M_NOR_I:
04611       s = "";
04612       s2 = "nor";
04613       goto do_bit;
04614     case M_XOR_I:
04615       s = "xori";
04616       s2 = "xor";
04617     do_bit:
04618       if (imm_expr.X_op == O_constant
04619          && imm_expr.X_add_number >= 0
04620          && imm_expr.X_add_number < 0x10000)
04621        {
04622          if (mask != M_NOR_I)
04623            macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
04624          else
04625            {
04626              macro_build (&imm_expr, "ori", "t,r,i",
04627                         treg, sreg, BFD_RELOC_LO16);
04628              macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
04629            }
04630          break;
04631        }
04632 
04633       used_at = 1;
04634       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
04635       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
04636       break;
04637 
04638     case M_BALIGN:
04639       switch (imm_expr.X_add_number)
04640        {
04641        case 0:
04642          macro_build (NULL, "nop", "");
04643          break;
04644        case 2:
04645          macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
04646          break;
04647        default:
04648          macro_build (NULL, "balign", "t,s,2", treg, sreg,
04649                      (int)imm_expr.X_add_number);
04650          break;
04651        }
04652       break;
04653 
04654     case M_BEQ_I:
04655       s = "beq";
04656       goto beq_i;
04657     case M_BEQL_I:
04658       s = "beql";
04659       likely = 1;
04660       goto beq_i;
04661     case M_BNE_I:
04662       s = "bne";
04663       goto beq_i;
04664     case M_BNEL_I:
04665       s = "bnel";
04666       likely = 1;
04667     beq_i:
04668       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
04669        {
04670          macro_build (&offset_expr, s, "s,t,p", sreg, 0);
04671          break;
04672        }
04673       used_at = 1;
04674       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
04675       macro_build (&offset_expr, s, "s,t,p", sreg, AT);
04676       break;
04677 
04678     case M_BGEL:
04679       likely = 1;
04680     case M_BGE:
04681       if (treg == 0)
04682        {
04683          macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
04684          break;
04685        }
04686       if (sreg == 0)
04687        {
04688          macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
04689          break;
04690        }
04691       used_at = 1;
04692       macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
04693       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
04694       break;
04695 
04696     case M_BGTL_I:
04697       likely = 1;
04698     case M_BGT_I:
04699       /* check for > max integer */
04700       maxnum = 0x7fffffff;
04701       if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
04702        {
04703          maxnum <<= 16;
04704          maxnum |= 0xffff;
04705          maxnum <<= 16;
04706          maxnum |= 0xffff;
04707        }
04708       if (imm_expr.X_op == O_constant
04709          && imm_expr.X_add_number >= maxnum
04710          && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
04711        {
04712        do_false:
04713          /* result is always false */
04714          if (! likely)
04715            macro_build (NULL, "nop", "", 0);
04716          else
04717            macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
04718          break;
04719        }
04720       if (imm_expr.X_op != O_constant)
04721        as_bad (_("Unsupported large constant"));
04722       ++imm_expr.X_add_number;
04723       /* FALLTHROUGH */
04724     case M_BGE_I:
04725     case M_BGEL_I:
04726       if (mask == M_BGEL_I)
04727        likely = 1;
04728       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
04729        {
04730          macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
04731          break;
04732        }
04733       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
04734        {
04735          macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
04736          break;
04737        }
04738       maxnum = 0x7fffffff;
04739       if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
04740        {
04741          maxnum <<= 16;
04742          maxnum |= 0xffff;
04743          maxnum <<= 16;
04744          maxnum |= 0xffff;
04745        }
04746       maxnum = - maxnum - 1;
04747       if (imm_expr.X_op == O_constant
04748          && imm_expr.X_add_number <= maxnum
04749          && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
04750        {
04751        do_true:
04752          /* result is always true */
04753          as_warn (_("Branch %s is always true"), ip->insn_mo->name);
04754          macro_build (&offset_expr, "b", "p");
04755          break;
04756        }
04757       used_at = 1;
04758       set_at (sreg, 0);
04759       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
04760       break;
04761 
04762     case M_BGEUL:
04763       likely = 1;
04764     case M_BGEU:
04765       if (treg == 0)
04766        goto do_true;
04767       if (sreg == 0)
04768        {
04769          macro_build (&offset_expr, likely ? "beql" : "beq",
04770                      "s,t,p", 0, treg);
04771          break;
04772        }
04773       used_at = 1;
04774       macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
04775       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
04776       break;
04777 
04778     case M_BGTUL_I:
04779       likely = 1;
04780     case M_BGTU_I:
04781       if (sreg == 0
04782          || (HAVE_32BIT_GPRS
04783              && imm_expr.X_op == O_constant
04784              && imm_expr.X_add_number == (offsetT) 0xffffffff))
04785        goto do_false;
04786       if (imm_expr.X_op != O_constant)
04787        as_bad (_("Unsupported large constant"));
04788       ++imm_expr.X_add_number;
04789       /* FALLTHROUGH */
04790     case M_BGEU_I:
04791     case M_BGEUL_I:
04792       if (mask == M_BGEUL_I)
04793        likely = 1;
04794       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
04795        goto do_true;
04796       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
04797        {
04798          macro_build (&offset_expr, likely ? "bnel" : "bne",
04799                      "s,t,p", sreg, 0);
04800          break;
04801        }
04802       used_at = 1;
04803       set_at (sreg, 1);
04804       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
04805       break;
04806 
04807     case M_BGTL:
04808       likely = 1;
04809     case M_BGT:
04810       if (treg == 0)
04811        {
04812          macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
04813          break;
04814        }
04815       if (sreg == 0)
04816        {
04817          macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
04818          break;
04819        }
04820       used_at = 1;
04821       macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
04822       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
04823       break;
04824 
04825     case M_BGTUL:
04826       likely = 1;
04827     case M_BGTU:
04828       if (treg == 0)
04829        {
04830          macro_build (&offset_expr, likely ? "bnel" : "bne",
04831                      "s,t,p", sreg, 0);
04832          break;
04833        }
04834       if (sreg == 0)
04835        goto do_false;
04836       used_at = 1;
04837       macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
04838       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
04839       break;
04840 
04841     case M_BLEL:
04842       likely = 1;
04843     case M_BLE:
04844       if (treg == 0)
04845        {
04846          macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
04847          break;
04848        }
04849       if (sreg == 0)
04850        {
04851          macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
04852          break;
04853        }
04854       used_at = 1;
04855       macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
04856       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
04857       break;
04858 
04859     case M_BLEL_I:
04860       likely = 1;
04861     case M_BLE_I:
04862       maxnum = 0x7fffffff;
04863       if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
04864        {
04865          maxnum <<= 16;
04866          maxnum |= 0xffff;
04867          maxnum <<= 16;
04868          maxnum |= 0xffff;
04869        }
04870       if (imm_expr.X_op == O_constant
04871          && imm_expr.X_add_number >= maxnum
04872          && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
04873        goto do_true;
04874       if (imm_expr.X_op != O_constant)
04875        as_bad (_("Unsupported large constant"));
04876       ++imm_expr.X_add_number;
04877       /* FALLTHROUGH */
04878     case M_BLT_I:
04879     case M_BLTL_I:
04880       if (mask == M_BLTL_I)
04881        likely = 1;
04882       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
04883        {
04884          macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
04885          break;
04886        }
04887       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
04888        {
04889          macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
04890          break;
04891        }
04892       used_at = 1;
04893       set_at (sreg, 0);
04894       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
04895       break;
04896 
04897     case M_BLEUL:
04898       likely = 1;
04899     case M_BLEU:
04900       if (treg == 0)
04901        {
04902          macro_build (&offset_expr, likely ? "beql" : "beq",
04903                      "s,t,p", sreg, 0);
04904          break;
04905        }
04906       if (sreg == 0)
04907        goto do_true;
04908       used_at = 1;
04909       macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
04910       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
04911       break;
04912 
04913     case M_BLEUL_I:
04914       likely = 1;
04915     case M_BLEU_I:
04916       if (sreg == 0
04917          || (HAVE_32BIT_GPRS
04918              && imm_expr.X_op == O_constant
04919              && imm_expr.X_add_number == (offsetT) 0xffffffff))
04920        goto do_true;
04921       if (imm_expr.X_op != O_constant)
04922        as_bad (_("Unsupported large constant"));
04923       ++imm_expr.X_add_number;
04924       /* FALLTHROUGH */
04925     case M_BLTU_I:
04926     case M_BLTUL_I:
04927       if (mask == M_BLTUL_I)
04928        likely = 1;
04929       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
04930        goto do_false;
04931       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
04932        {
04933          macro_build (&offset_expr, likely ? "beql" : "beq",
04934                      "s,t,p", sreg, 0);
04935          break;
04936        }
04937       used_at = 1;
04938       set_at (sreg, 1);
04939       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
04940       break;
04941 
04942     case M_BLTL:
04943       likely = 1;
04944     case M_BLT:
04945       if (treg == 0)
04946        {
04947          macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
04948          break;
04949        }
04950       if (sreg == 0)
04951        {
04952          macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
04953          break;
04954        }
04955       used_at = 1;
04956       macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
04957       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
04958       break;
04959 
04960     case M_BLTUL:
04961       likely = 1;
04962     case M_BLTU:
04963       if (treg == 0)
04964        goto do_false;
04965       if (sreg == 0)
04966        {
04967          macro_build (&offset_expr, likely ? "bnel" : "bne",
04968                      "s,t,p", 0, treg);
04969          break;
04970        }
04971       used_at = 1;
04972       macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
04973       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
04974       break;
04975 
04976     case M_DEXT:
04977       {
04978        unsigned long pos;
04979        unsigned long size;
04980 
04981         if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
04982          {
04983            as_bad (_("Unsupported large constant"));
04984            pos = size = 1;
04985          }
04986        else
04987          {
04988            pos = (unsigned long) imm_expr.X_add_number;
04989            size = (unsigned long) imm2_expr.X_add_number;
04990          }
04991 
04992        if (pos > 63)
04993          {
04994            as_bad (_("Improper position (%lu)"), pos);
04995            pos = 1;
04996          }
04997         if (size == 0 || size > 64
04998            || (pos + size - 1) > 63)
04999          {
05000            as_bad (_("Improper extract size (%lu, position %lu)"),
05001                   size, pos);
05002            size = 1;
05003          }
05004 
05005        if (size <= 32 && pos < 32)
05006          {
05007            s = "dext";
05008            fmt = "t,r,+A,+C";
05009          }
05010        else if (size <= 32)
05011          {
05012            s = "dextu";
05013            fmt = "t,r,+E,+H";
05014          }
05015        else
05016          {
05017            s = "dextm";
05018            fmt = "t,r,+A,+G";
05019          }
05020        macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
05021       }
05022       break;
05023 
05024     case M_DINS:
05025       {
05026        unsigned long pos;
05027        unsigned long size;
05028 
05029         if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
05030          {
05031            as_bad (_("Unsupported large constant"));
05032            pos = size = 1;
05033          }
05034        else
05035          {
05036            pos = (unsigned long) imm_expr.X_add_number;
05037            size = (unsigned long) imm2_expr.X_add_number;
05038          }
05039 
05040        if (pos > 63)
05041          {
05042            as_bad (_("Improper position (%lu)"), pos);
05043            pos = 1;
05044          }
05045         if (size == 0 || size > 64
05046            || (pos + size - 1) > 63)
05047          {
05048            as_bad (_("Improper insert size (%lu, position %lu)"),
05049                   size, pos);
05050            size = 1;
05051          }
05052 
05053        if (pos < 32 && (pos + size - 1) < 32)
05054          {
05055            s = "dins";
05056            fmt = "t,r,+A,+B";
05057          }
05058        else if (pos >= 32)
05059          {
05060            s = "dinsu";
05061            fmt = "t,r,+E,+F";
05062          }
05063        else
05064          {
05065            s = "dinsm";
05066            fmt = "t,r,+A,+F";
05067          }
05068        macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
05069                    pos + size - 1);
05070       }
05071       break;
05072 
05073     case M_DDIV_3:
05074       dbl = 1;
05075     case M_DIV_3:
05076       s = "mflo";
05077       goto do_div3;
05078     case M_DREM_3:
05079       dbl = 1;
05080     case M_REM_3:
05081       s = "mfhi";
05082     do_div3:
05083       if (treg == 0)
05084        {
05085          as_warn (_("Divide by zero."));
05086          if (mips_trap)
05087            macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
05088          else
05089            macro_build (NULL, "break", "c", 7);
05090          break;
05091        }
05092 
05093       start_noreorder ();
05094       if (mips_trap)
05095        {
05096          macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
05097          macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
05098        }
05099       else
05100        {
05101          expr1.X_add_number = 8;
05102          macro_build (&expr1, "bne", "s,t,p", treg, 0);
05103          macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
05104          macro_build (NULL, "break", "c", 7);
05105        }
05106       expr1.X_add_number = -1;
05107       used_at = 1;
05108       load_register (AT, &expr1, dbl);
05109       expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
05110       macro_build (&expr1, "bne", "s,t,p", treg, AT);
05111       if (dbl)
05112        {
05113          expr1.X_add_number = 1;
05114          load_register (AT, &expr1, dbl);
05115          macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
05116        }
05117       else
05118        {
05119          expr1.X_add_number = 0x80000000;
05120          macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
05121        }
05122       if (mips_trap)
05123        {
05124          macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
05125          /* We want to close the noreorder block as soon as possible, so
05126             that later insns are available for delay slot filling.  */
05127          end_noreorder ();
05128        }
05129       else
05130        {
05131          expr1.X_add_number = 8;
05132          macro_build (&expr1, "bne", "s,t,p", sreg, AT);
05133          macro_build (NULL, "nop", "", 0);
05134 
05135          /* We want to close the noreorder block as soon as possible, so
05136             that later insns are available for delay slot filling.  */
05137          end_noreorder ();
05138 
05139          macro_build (NULL, "break", "c", 6);
05140        }
05141       macro_build (NULL, s, "d", dreg);
05142       break;
05143 
05144     case M_DIV_3I:
05145       s = "div";
05146       s2 = "mflo";
05147       goto do_divi;
05148     case M_DIVU_3I:
05149       s = "divu";
05150       s2 = "mflo";
05151       goto do_divi;
05152     case M_REM_3I:
05153       s = "div";
05154       s2 = "mfhi";
05155       goto do_divi;
05156     case M_REMU_3I:
05157       s = "divu";
05158       s2 = "mfhi";
05159       goto do_divi;
05160     case M_DDIV_3I:
05161       dbl = 1;
05162       s = "ddiv";
05163       s2 = "mflo";
05164       goto do_divi;
05165     case M_DDIVU_3I:
05166       dbl = 1;
05167       s = "ddivu";
05168       s2 = "mflo";
05169       goto do_divi;
05170     case M_DREM_3I:
05171       dbl = 1;
05172       s = "ddiv";
05173       s2 = "mfhi";
05174       goto do_divi;
05175     case M_DREMU_3I:
05176       dbl = 1;
05177       s = "ddivu";
05178       s2 = "mfhi";
05179     do_divi:
05180       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
05181        {
05182          as_warn (_("Divide by zero."));
05183          if (mips_trap)
05184            macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
05185          else
05186            macro_build (NULL, "break", "c", 7);
05187          break;
05188        }
05189       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
05190        {
05191          if (strcmp (s2, "mflo") == 0)
05192            move_register (dreg, sreg);
05193          else
05194            move_register (dreg, 0);
05195          break;
05196        }
05197       if (imm_expr.X_op == O_constant
05198          && imm_expr.X_add_number == -1
05199          && s[strlen (s) - 1] != 'u')
05200        {
05201          if (strcmp (s2, "mflo") == 0)
05202            {
05203              macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
05204            }
05205          else
05206            move_register (dreg, 0);
05207          break;
05208        }
05209 
05210       used_at = 1;
05211       load_register (AT, &imm_expr, dbl);
05212       macro_build (NULL, s, "z,s,t", sreg, AT);
05213       macro_build (NULL, s2, "d", dreg);
05214       break;
05215 
05216     case M_DIVU_3:
05217       s = "divu";
05218       s2 = "mflo";
05219       goto do_divu3;
05220     case M_REMU_3:
05221       s = "divu";
05222       s2 = "mfhi";
05223       goto do_divu3;
05224     case M_DDIVU_3:
05225       s = "ddivu";
05226       s2 = "mflo";
05227       goto do_divu3;
05228     case M_DREMU_3:
05229       s = "ddivu";
05230       s2 = "mfhi";
05231     do_divu3:
05232       start_noreorder ();
05233       if (mips_trap)
05234        {
05235          macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
05236          macro_build (NULL, s, "z,s,t", sreg, treg);
05237          /* We want to close the noreorder block as soon as possible, so
05238             that later insns are available for delay slot filling.  */
05239          end_noreorder ();
05240        }
05241       else
05242        {
05243          expr1.X_add_number = 8;
05244          macro_build (&expr1, "bne", "s,t,p", treg, 0);
05245          macro_build (NULL, s, "z,s,t", sreg, treg);
05246 
05247          /* We want to close the noreorder block as soon as possible, so
05248             that later insns are available for delay slot filling.  */
05249          end_noreorder ();
05250          macro_build (NULL, "break", "c", 7);
05251        }
05252       macro_build (NULL, s2, "d", dreg);
05253       break;
05254 
05255     case M_DLCA_AB:
05256       dbl = 1;
05257     case M_LCA_AB:
05258       call = 1;
05259       goto do_la;
05260     case M_DLA_AB:
05261       dbl = 1;
05262     case M_LA_AB:
05263     do_la:
05264       /* Load the address of a symbol into a register.  If breg is not
05265         zero, we then add a base register to it.  */
05266 
05267       if (dbl && HAVE_32BIT_GPRS)
05268        as_warn (_("dla used to load 32-bit register"));
05269 
05270       if (! dbl && HAVE_64BIT_OBJECTS)
05271        as_warn (_("la used to load 64-bit address"));
05272 
05273       if (offset_expr.X_op == O_constant
05274          && offset_expr.X_add_number >= -0x8000
05275          && offset_expr.X_add_number < 0x8000)
05276        {
05277          macro_build (&offset_expr, ADDRESS_ADDI_INSN,
05278                      "t,r,j", treg, sreg, BFD_RELOC_LO16);
05279          break;
05280        }
05281 
05282       if (!mips_opts.noat && (treg == breg))
05283        {
05284          tempreg = AT;
05285          used_at = 1;
05286        }
05287       else
05288        {
05289          tempreg = treg;
05290        }
05291 
05292       if (offset_expr.X_op != O_symbol
05293          && offset_expr.X_op != O_constant)
05294        {
05295          as_bad (_("expression too complex"));
05296          offset_expr.X_op = O_constant;
05297        }
05298 
05299       if (offset_expr.X_op == O_constant)
05300        load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
05301       else if (mips_pic == NO_PIC)
05302        {
05303          /* If this is a reference to a GP relative symbol, we want
05304               addiu  $tempreg,$gp,<sym>   (BFD_RELOC_GPREL16)
05305             Otherwise we want
05306               lui    $tempreg,<sym>              (BFD_RELOC_HI16_S)
05307               addiu  $tempreg,$tempreg,<sym>     (BFD_RELOC_LO16)
05308             If we have a constant, we need two instructions anyhow,
05309             so we may as well always use the latter form.
05310 
05311             With 64bit address space and a usable $at we want
05312               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHEST)
05313               lui    $at,<sym>            (BFD_RELOC_HI16_S)
05314               daddiu $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHER)
05315               daddiu $at,<sym>            (BFD_RELOC_LO16)
05316               dsll32 $tempreg,0
05317               daddu  $tempreg,$tempreg,$at
05318 
05319             If $at is already in use, we use a path which is suboptimal
05320             on superscalar processors.
05321               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHEST)
05322               daddiu $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHER)
05323               dsll   $tempreg,16
05324               daddiu $tempreg,<sym>              (BFD_RELOC_HI16_S)
05325               dsll   $tempreg,16
05326               daddiu $tempreg,<sym>              (BFD_RELOC_LO16)
05327 
05328             For GP relative symbols in 64bit address space we can use
05329             the same sequence as in 32bit address space.  */
05330          if (HAVE_64BIT_SYMBOLS)
05331            {
05332              if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
05333                 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
05334               {
05335                 relax_start (offset_expr.X_add_symbol);
05336                 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05337                             tempreg, mips_gp_register, BFD_RELOC_GPREL16);
05338                 relax_switch ();
05339               }
05340 
05341              if (used_at == 0 && !mips_opts.noat)
05342               {
05343                 macro_build (&offset_expr, "lui", "t,u",
05344                             tempreg, BFD_RELOC_MIPS_HIGHEST);
05345                 macro_build (&offset_expr, "lui", "t,u",
05346                             AT, BFD_RELOC_HI16_S);
05347                 macro_build (&offset_expr, "daddiu", "t,r,j",
05348                             tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
05349                 macro_build (&offset_expr, "daddiu", "t,r,j",
05350                             AT, AT, BFD_RELOC_LO16);
05351                 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
05352                 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
05353                 used_at = 1;
05354               }
05355              else
05356               {
05357                 macro_build (&offset_expr, "lui", "t,u",
05358                             tempreg, BFD_RELOC_MIPS_HIGHEST);
05359                 macro_build (&offset_expr, "daddiu", "t,r,j",
05360                             tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
05361                 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
05362                 macro_build (&offset_expr, "daddiu", "t,r,j",
05363                             tempreg, tempreg, BFD_RELOC_HI16_S);
05364                 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
05365                 macro_build (&offset_expr, "daddiu", "t,r,j",
05366                             tempreg, tempreg, BFD_RELOC_LO16);
05367               }
05368 
05369              if (mips_relax.sequence)
05370               relax_end ();
05371            }
05372          else
05373            {
05374              if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
05375                 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
05376               {
05377                 relax_start (offset_expr.X_add_symbol);
05378                 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05379                             tempreg, mips_gp_register, BFD_RELOC_GPREL16);
05380                 relax_switch ();
05381               }
05382              if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
05383               as_bad (_("offset too large"));
05384              macro_build_lui (&offset_expr, tempreg);
05385              macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05386                         tempreg, tempreg, BFD_RELOC_LO16);
05387              if (mips_relax.sequence)
05388               relax_end ();
05389            }
05390        }
05391       else if (!mips_big_got && !HAVE_NEWABI)
05392        {
05393          int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
05394 
05395          /* If this is a reference to an external symbol, and there
05396             is no constant, we want
05397               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05398             or for lca or if tempreg is PIC_CALL_REG
05399               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_CALL16)
05400             For a local symbol, we want
05401               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05402               nop
05403               addiu  $tempreg,$tempreg,<sym>     (BFD_RELOC_LO16)
05404 
05405             If we have a small constant, and this is a reference to
05406             an external symbol, we want
05407               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05408               nop
05409               addiu  $tempreg,$tempreg,<constant>
05410             For a local symbol, we want the same instruction
05411             sequence, but we output a BFD_RELOC_LO16 reloc on the
05412             addiu instruction.
05413 
05414             If we have a large constant, and this is a reference to
05415             an external symbol, we want
05416               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05417               lui    $at,<hiconstant>
05418               addiu  $at,$at,<loconstant>
05419               addu   $tempreg,$tempreg,$at
05420             For a local symbol, we want the same instruction
05421             sequence, but we output a BFD_RELOC_LO16 reloc on the
05422             addiu instruction.
05423           */
05424 
05425          if (offset_expr.X_add_number == 0)
05426            {
05427              if (mips_pic == SVR4_PIC
05428                 && breg == 0
05429                 && (call || tempreg == PIC_CALL_REG))
05430               lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
05431 
05432              relax_start (offset_expr.X_add_symbol);
05433              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05434                         lw_reloc_type, mips_gp_register);
05435              if (breg != 0)
05436               {
05437                 /* We're going to put in an addu instruction using
05438                    tempreg, so we may as well insert the nop right
05439                    now.  */
05440                 load_delay_nop ();
05441               }
05442              relax_switch ();
05443              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05444                         tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
05445              load_delay_nop ();
05446              macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05447                         tempreg, tempreg, BFD_RELOC_LO16);
05448              relax_end ();
05449              /* FIXME: If breg == 0, and the next instruction uses
05450                $tempreg, then if this variant case is used an extra
05451                nop will be generated.  */
05452            }
05453          else if (offset_expr.X_add_number >= -0x8000
05454                  && offset_expr.X_add_number < 0x8000)
05455            {
05456              load_got_offset (tempreg, &offset_expr);
05457              load_delay_nop ();
05458              add_got_offset (tempreg, &offset_expr);
05459            }
05460          else
05461            {
05462              expr1.X_add_number = offset_expr.X_add_number;
05463              offset_expr.X_add_number =
05464               ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
05465              load_got_offset (tempreg, &offset_expr);
05466              offset_expr.X_add_number = expr1.X_add_number;
05467              /* If we are going to add in a base register, and the
05468                target register and the base register are the same,
05469                then we are using AT as a temporary register.  Since
05470                we want to load the constant into AT, we add our
05471                current AT (from the global offset table) and the
05472                register into the register now, and pretend we were
05473                not using a base register.  */
05474              if (breg == treg)
05475               {
05476                 load_delay_nop ();
05477                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05478                             treg, AT, breg);
05479                 breg = 0;
05480                 tempreg = treg;
05481               }
05482              add_got_offset_hilo (tempreg, &offset_expr, AT);
05483              used_at = 1;
05484            }
05485        }
05486       else if (!mips_big_got && HAVE_NEWABI)
05487        {
05488          int add_breg_early = 0;
05489 
05490          /* If this is a reference to an external, and there is no
05491             constant, or local symbol (*), with or without a
05492             constant, we want
05493               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT_DISP)
05494             or for lca or if tempreg is PIC_CALL_REG
05495               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_CALL16)
05496 
05497             If we have a small constant, and this is a reference to
05498             an external symbol, we want
05499               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT_DISP)
05500               addiu  $tempreg,$tempreg,<constant>
05501 
05502             If we have a large constant, and this is a reference to
05503             an external symbol, we want
05504               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT_DISP)
05505               lui    $at,<hiconstant>
05506               addiu  $at,$at,<loconstant>
05507               addu   $tempreg,$tempreg,$at
05508 
05509             (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
05510             local symbols, even though it introduces an additional
05511             instruction.  */
05512 
05513          if (offset_expr.X_add_number)
05514            {
05515              expr1.X_add_number = offset_expr.X_add_number;
05516              offset_expr.X_add_number = 0;
05517 
05518              relax_start (offset_expr.X_add_symbol);
05519              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05520                         BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
05521 
05522              if (expr1.X_add_number >= -0x8000
05523                 && expr1.X_add_number < 0x8000)
05524               {
05525                 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
05526                             tempreg, tempreg, BFD_RELOC_LO16);
05527               }
05528              else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
05529               {
05530                 int dreg;
05531 
05532                 /* If we are going to add in a base register, and the
05533                    target register and the base register are the same,
05534                    then we are using AT as a temporary register.  Since
05535                    we want to load the constant into AT, we add our
05536                    current AT (from the global offset table) and the
05537                    register into the register now, and pretend we were
05538                    not using a base register.  */
05539                 if (breg != treg)
05540                   dreg = tempreg;
05541                 else
05542                   {
05543                     assert (tempreg == AT);
05544                     macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05545                                treg, AT, breg);
05546                     dreg = treg;
05547                     add_breg_early = 1;
05548                   }
05549 
05550                 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
05551                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05552                             dreg, dreg, AT);
05553 
05554                 used_at = 1;
05555               }
05556              else
05557               as_bad (_("PIC code offset overflow (max 32 signed bits)"));
05558 
05559              relax_switch ();
05560              offset_expr.X_add_number = expr1.X_add_number;
05561 
05562              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05563                         BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
05564              if (add_breg_early)
05565               {
05566                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05567                             treg, tempreg, breg);
05568                 breg = 0;
05569                 tempreg = treg;
05570               }
05571              relax_end ();
05572            }
05573          else if (breg == 0 && (call || tempreg == PIC_CALL_REG))
05574            {
05575              relax_start (offset_expr.X_add_symbol);
05576              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05577                         BFD_RELOC_MIPS_CALL16, mips_gp_register);
05578              relax_switch ();
05579              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05580                         BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
05581              relax_end ();
05582            }
05583          else
05584            {
05585              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05586                         BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
05587            }
05588        }
05589       else if (mips_big_got && !HAVE_NEWABI)
05590        {
05591          int gpdelay;
05592          int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
05593          int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
05594          int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
05595 
05596          /* This is the large GOT case.  If this is a reference to an
05597             external symbol, and there is no constant, we want
05598               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
05599               addu   $tempreg,$tempreg,$gp
05600               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
05601             or for lca or if tempreg is PIC_CALL_REG
05602               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_CALL_HI16)
05603               addu   $tempreg,$tempreg,$gp
05604               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
05605             For a local symbol, we want
05606               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05607               nop
05608               addiu  $tempreg,$tempreg,<sym>     (BFD_RELOC_LO16)
05609 
05610             If we have a small constant, and this is a reference to
05611             an external symbol, we want
05612               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
05613               addu   $tempreg,$tempreg,$gp
05614               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
05615               nop
05616               addiu  $tempreg,$tempreg,<constant>
05617             For a local symbol, we want
05618               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05619               nop
05620               addiu  $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
05621 
05622             If we have a large constant, and this is a reference to
05623             an external symbol, we want
05624               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
05625               addu   $tempreg,$tempreg,$gp
05626               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
05627               lui    $at,<hiconstant>
05628               addiu  $at,$at,<loconstant>
05629               addu   $tempreg,$tempreg,$at
05630             For a local symbol, we want
05631               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
05632               lui    $at,<hiconstant>
05633               addiu  $at,$at,<loconstant> (BFD_RELOC_LO16)
05634               addu   $tempreg,$tempreg,$at
05635          */
05636 
05637          expr1.X_add_number = offset_expr.X_add_number;
05638          offset_expr.X_add_number = 0;
05639          relax_start (offset_expr.X_add_symbol);
05640          gpdelay = reg_needs_delay (mips_gp_register);
05641          if (expr1.X_add_number == 0 && breg == 0
05642              && (call || tempreg == PIC_CALL_REG))
05643            {
05644              lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
05645              lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
05646            }
05647          macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
05648          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05649                      tempreg, tempreg, mips_gp_register);
05650          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05651                      tempreg, lw_reloc_type, tempreg);
05652          if (expr1.X_add_number == 0)
05653            {
05654              if (breg != 0)
05655               {
05656                 /* We're going to put in an addu instruction using
05657                    tempreg, so we may as well insert the nop right
05658                    now.  */
05659                 load_delay_nop ();
05660               }
05661            }
05662          else if (expr1.X_add_number >= -0x8000
05663                  && expr1.X_add_number < 0x8000)
05664            {
05665              load_delay_nop ();
05666              macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
05667                         tempreg, tempreg, BFD_RELOC_LO16);
05668            }
05669          else
05670            {
05671              int dreg;
05672 
05673              /* If we are going to add in a base register, and the
05674                target register and the base register are the same,
05675                then we are using AT as a temporary register.  Since
05676                we want to load the constant into AT, we add our
05677                current AT (from the global offset table) and the
05678                register into the register now, and pretend we were
05679                not using a base register.  */
05680              if (breg != treg)
05681               dreg = tempreg;
05682              else
05683               {
05684                 assert (tempreg == AT);
05685                 load_delay_nop ();
05686                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05687                             treg, AT, breg);
05688                 dreg = treg;
05689               }
05690 
05691              load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
05692              macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
05693 
05694              used_at = 1;
05695            }
05696          offset_expr.X_add_number =
05697            ((expr1.X_add_number + 0x8000) & 0xffff) - 0x8000;
05698          relax_switch ();
05699 
05700          if (gpdelay)
05701            {
05702              /* This is needed because this instruction uses $gp, but
05703                the first instruction on the main stream does not.  */
05704              macro_build (NULL, "nop", "");
05705            }
05706 
05707          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05708                      local_reloc_type, mips_gp_register);
05709          if (expr1.X_add_number >= -0x8000
05710              && expr1.X_add_number < 0x8000)
05711            {
05712              load_delay_nop ();
05713              macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05714                         tempreg, tempreg, BFD_RELOC_LO16);
05715              /* FIXME: If add_number is 0, and there was no base
05716                register, the external symbol case ended with a load,
05717                so if the symbol turns out to not be external, and
05718                the next instruction uses tempreg, an unnecessary nop
05719                will be inserted.  */
05720            }
05721          else
05722            {
05723              if (breg == treg)
05724               {
05725                 /* We must add in the base register now, as in the
05726                    external symbol case.  */
05727                 assert (tempreg == AT);
05728                 load_delay_nop ();
05729                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05730                             treg, AT, breg);
05731                 tempreg = treg;
05732                 /* We set breg to 0 because we have arranged to add
05733                    it in in both cases.  */
05734                 breg = 0;
05735               }
05736 
05737              macro_build_lui (&expr1, AT);
05738              macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05739                         AT, AT, BFD_RELOC_LO16);
05740              macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05741                         tempreg, tempreg, AT);
05742              used_at = 1;
05743            }
05744          relax_end ();
05745        }
05746       else if (mips_big_got && HAVE_NEWABI)
05747        {
05748          int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
05749          int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
05750          int add_breg_early = 0;
05751 
05752          /* This is the large GOT case.  If this is a reference to an
05753             external symbol, and there is no constant, we want
05754               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
05755               add    $tempreg,$tempreg,$gp
05756               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
05757             or for lca or if tempreg is PIC_CALL_REG
05758               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_CALL_HI16)
05759               add    $tempreg,$tempreg,$gp
05760               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
05761 
05762             If we have a small constant, and this is a reference to
05763             an external symbol, we want
05764               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
05765               add    $tempreg,$tempreg,$gp
05766               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
05767               addi   $tempreg,$tempreg,<constant>
05768 
05769             If we have a large constant, and this is a reference to
05770             an external symbol, we want
05771               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
05772               addu   $tempreg,$tempreg,$gp
05773               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
05774               lui    $at,<hiconstant>
05775               addi   $at,$at,<loconstant>
05776               add    $tempreg,$tempreg,$at
05777 
05778             If we have NewABI, and we know it's a local symbol, we want
05779               lw     $reg,<sym>($gp)             (BFD_RELOC_MIPS_GOT_PAGE)
05780               addiu  $reg,$reg,<sym>             (BFD_RELOC_MIPS_GOT_OFST)
05781             otherwise we have to resort to GOT_HI16/GOT_LO16.  */
05782 
05783          relax_start (offset_expr.X_add_symbol);
05784 
05785          expr1.X_add_number = offset_expr.X_add_number;
05786          offset_expr.X_add_number = 0;
05787 
05788          if (expr1.X_add_number == 0 && breg == 0
05789              && (call || tempreg == PIC_CALL_REG))
05790            {
05791              lui_reloc_type = (int) BFD_RELOC_MIPS_CALL_HI16;
05792              lw_reloc_type = (int) BFD_RELOC_MIPS_CALL_LO16;
05793            }
05794          macro_build (&offset_expr, "lui", "t,u", tempreg, lui_reloc_type);
05795          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05796                      tempreg, tempreg, mips_gp_register);
05797          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05798                      tempreg, lw_reloc_type, tempreg);
05799 
05800          if (expr1.X_add_number == 0)
05801            ;
05802          else if (expr1.X_add_number >= -0x8000
05803                  && expr1.X_add_number < 0x8000)
05804            {
05805              macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
05806                         tempreg, tempreg, BFD_RELOC_LO16);
05807            }
05808          else if (IS_SEXT_32BIT_NUM (expr1.X_add_number + 0x8000))
05809            {
05810              int dreg;
05811 
05812              /* If we are going to add in a base register, and the
05813                target register and the base register are the same,
05814                then we are using AT as a temporary register.  Since
05815                we want to load the constant into AT, we add our
05816                current AT (from the global offset table) and the
05817                register into the register now, and pretend we were
05818                not using a base register.  */
05819              if (breg != treg)
05820               dreg = tempreg;
05821              else
05822               {
05823                 assert (tempreg == AT);
05824                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05825                             treg, AT, breg);
05826                 dreg = treg;
05827                 add_breg_early = 1;
05828               }
05829 
05830              load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
05831              macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
05832 
05833              used_at = 1;
05834            }
05835          else
05836            as_bad (_("PIC code offset overflow (max 32 signed bits)"));
05837 
05838          relax_switch ();
05839          offset_expr.X_add_number = expr1.X_add_number;
05840          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
05841                      BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
05842          macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
05843                      tempreg, BFD_RELOC_MIPS_GOT_OFST);
05844          if (add_breg_early)
05845            {
05846              macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
05847                         treg, tempreg, breg);
05848              breg = 0;
05849              tempreg = treg;
05850            }
05851          relax_end ();
05852        }
05853       else
05854        abort ();
05855 
05856       if (breg != 0)
05857        macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
05858       break;
05859 
05860     case M_J_A:
05861       /* The j instruction may not be used in PIC code, since it
05862         requires an absolute address.  We convert it to a b
05863         instruction.  */
05864       if (mips_pic == NO_PIC)
05865        macro_build (&offset_expr, "j", "a");
05866       else
05867        macro_build (&offset_expr, "b", "p");
05868       break;
05869 
05870       /* The jal instructions must be handled as macros because when
05871         generating PIC code they expand to multi-instruction
05872         sequences.  Normally they are simple instructions.  */
05873     case M_JAL_1:
05874       dreg = RA;
05875       /* Fall through.  */
05876     case M_JAL_2:
05877       if (mips_pic == NO_PIC)
05878        macro_build (NULL, "jalr", "d,s", dreg, sreg);
05879       else
05880        {
05881          if (sreg != PIC_CALL_REG)
05882            as_warn (_("MIPS PIC call to register other than $25"));
05883 
05884          macro_build (NULL, "jalr", "d,s", dreg, sreg);
05885          if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
05886            {
05887              if (mips_cprestore_offset < 0)
05888               as_warn (_("No .cprestore pseudo-op used in PIC code"));
05889              else
05890               {
05891                 if (! mips_frame_reg_valid)
05892                   {
05893                     as_warn (_("No .frame pseudo-op used in PIC code"));
05894                     /* Quiet this warning.  */
05895                     mips_frame_reg_valid = 1;
05896                   }
05897                 if (! mips_cprestore_valid)
05898                   {
05899                     as_warn (_("No .cprestore pseudo-op used in PIC code"));
05900                     /* Quiet this warning.  */
05901                     mips_cprestore_valid = 1;
05902                   }
05903                 expr1.X_add_number = mips_cprestore_offset;
05904                 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
05905                                           mips_gp_register,
05906                                           mips_frame_reg,
05907                                           HAVE_64BIT_ADDRESSES);
05908               }
05909            }
05910        }
05911 
05912       break;
05913 
05914     case M_JAL_A:
05915       if (mips_pic == NO_PIC)
05916        macro_build (&offset_expr, "jal", "a");
05917       else if (mips_pic == SVR4_PIC)
05918        {
05919          /* If this is a reference to an external symbol, and we are
05920             using a small GOT, we want
05921               lw     $25,<sym>($gp)              (BFD_RELOC_MIPS_CALL16)
05922               nop
05923               jalr   $ra,$25
05924               nop
05925               lw     $gp,cprestore($sp)
05926             The cprestore value is set using the .cprestore
05927             pseudo-op.  If we are using a big GOT, we want
05928               lui    $25,<sym>            (BFD_RELOC_MIPS_CALL_HI16)
05929               addu   $25,$25,$gp
05930               lw     $25,<sym>($25)              (BFD_RELOC_MIPS_CALL_LO16)
05931               nop
05932               jalr   $ra,$25
05933               nop
05934               lw     $gp,cprestore($sp)
05935             If the symbol is not external, we want
05936               lw     $25,<sym>($gp)              (BFD_RELOC_MIPS_GOT16)
05937               nop
05938               addiu  $25,$25,<sym>        (BFD_RELOC_LO16)
05939               jalr   $ra,$25
05940               nop
05941               lw $gp,cprestore($sp)
05942 
05943             For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
05944             sequences above, minus nops, unless the symbol is local,
05945             which enables us to use GOT_PAGE/GOT_OFST (big got) or
05946             GOT_DISP.  */
05947          if (HAVE_NEWABI)
05948            {
05949              if (! mips_big_got)
05950               {
05951                 relax_start (offset_expr.X_add_symbol);
05952                 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05953                             PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
05954                             mips_gp_register);
05955                 relax_switch ();
05956                 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05957                             PIC_CALL_REG, BFD_RELOC_MIPS_GOT_DISP,
05958                             mips_gp_register);
05959                 relax_end ();
05960               }
05961              else
05962               {
05963                 relax_start (offset_expr.X_add_symbol);
05964                 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
05965                             BFD_RELOC_MIPS_CALL_HI16);
05966                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
05967                             PIC_CALL_REG, mips_gp_register);
05968                 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05969                             PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
05970                             PIC_CALL_REG);
05971                 relax_switch ();
05972                 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05973                             PIC_CALL_REG, BFD_RELOC_MIPS_GOT_PAGE,
05974                             mips_gp_register);
05975                 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
05976                             PIC_CALL_REG, PIC_CALL_REG,
05977                             BFD_RELOC_MIPS_GOT_OFST);
05978                 relax_end ();
05979               }
05980 
05981              macro_build_jalr (&offset_expr);
05982            }
05983          else
05984            {
05985              relax_start (offset_expr.X_add_symbol);
05986              if (! mips_big_got)
05987               {
05988                 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
05989                             PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
05990                             mips_gp_register);
05991                 load_delay_nop ();
05992                 relax_switch ();
05993               }
05994              else
05995               {
05996                 int gpdelay;
05997 
05998                 gpdelay = reg_needs_delay (mips_gp_register);
05999                 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
06000                             BFD_RELOC_MIPS_CALL_HI16);
06001                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
06002                             PIC_CALL_REG, mips_gp_register);
06003                 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
06004                             PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
06005                             PIC_CALL_REG);
06006                 load_delay_nop ();
06007                 relax_switch ();
06008                 if (gpdelay)
06009                   macro_build (NULL, "nop", "");
06010               }
06011              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
06012                         PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
06013                         mips_gp_register);
06014              load_delay_nop ();
06015              macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
06016                         PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
06017              relax_end ();
06018              macro_build_jalr (&offset_expr);
06019 
06020              if (mips_cprestore_offset < 0)
06021               as_warn (_("No .cprestore pseudo-op used in PIC code"));
06022              else
06023               {
06024                 if (! mips_frame_reg_valid)
06025                   {
06026                     as_warn (_("No .frame pseudo-op used in PIC code"));
06027                     /* Quiet this warning.  */
06028                     mips_frame_reg_valid = 1;
06029                   }
06030                 if (! mips_cprestore_valid)
06031                   {
06032                     as_warn (_("No .cprestore pseudo-op used in PIC code"));
06033                     /* Quiet this warning.  */
06034                     mips_cprestore_valid = 1;
06035                   }
06036                 if (mips_opts.noreorder)
06037                   macro_build (NULL, "nop", "");
06038                 expr1.X_add_number = mips_cprestore_offset;
06039                 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
06040                                           mips_gp_register,
06041                                           mips_frame_reg,
06042                                           HAVE_64BIT_ADDRESSES);
06043               }
06044            }
06045        }
06046       else if (mips_pic == VXWORKS_PIC)
06047        as_bad (_("Non-PIC jump used in PIC library"));
06048       else
06049        abort ();
06050 
06051       break;
06052 
06053     case M_LB_AB:
06054       s = "lb";
06055       goto ld;
06056     case M_LBU_AB:
06057       s = "lbu";
06058       goto ld;
06059     case M_LH_AB:
06060       s = "lh";
06061       goto ld;
06062     case M_LHU_AB:
06063       s = "lhu";
06064       goto ld;
06065     case M_LW_AB:
06066       s = "lw";
06067       goto ld;
06068     case M_LWC0_AB:
06069       s = "lwc0";
06070       /* Itbl support may require additional care here.  */
06071       coproc = 1;
06072       goto ld;
06073     case M_LWC1_AB:
06074       s = "lwc1";
06075       /* Itbl support may require additional care here.  */
06076       coproc = 1;
06077       goto ld;
06078     case M_LWC2_AB:
06079       s = "lwc2";
06080       /* Itbl support may require additional care here.  */
06081       coproc = 1;
06082       goto ld;
06083     case M_LWC3_AB:
06084       s = "lwc3";
06085       /* Itbl support may require additional care here.  */
06086       coproc = 1;
06087       goto ld;
06088     case M_LWL_AB:
06089       s = "lwl";
06090       lr = 1;
06091       goto ld;
06092     case M_LWR_AB:
06093       s = "lwr";
06094       lr = 1;
06095       goto ld;
06096     case M_LDC1_AB:
06097       if (mips_opts.arch == CPU_R4650)
06098        {
06099          as_bad (_("opcode not supported on this processor"));
06100          break;
06101        }
06102       s = "ldc1";
06103       /* Itbl support may require additional care here.  */
06104       coproc = 1;
06105       goto ld;
06106     case M_LDC2_AB:
06107       s = "ldc2";
06108       /* Itbl support may require additional care here.  */
06109       coproc = 1;
06110       goto ld;
06111     case M_LDC3_AB:
06112       s = "ldc3";
06113       /* Itbl support may require additional care here.  */
06114       coproc = 1;
06115       goto ld;
06116     case M_LDL_AB:
06117       s = "ldl";
06118       lr = 1;
06119       goto ld;
06120     case M_LDR_AB:
06121       s = "ldr";
06122       lr = 1;
06123       goto ld;
06124     case M_LL_AB:
06125       s = "ll";
06126       goto ld;
06127     case M_LLD_AB:
06128       s = "lld";
06129       goto ld;
06130     case M_LWU_AB:
06131       s = "lwu";
06132     ld:
06133       if (breg == treg || coproc || lr)
06134        {
06135          tempreg = AT;
06136          used_at = 1;
06137        }
06138       else
06139        {
06140          tempreg = treg;
06141        }
06142       goto ld_st;
06143     case M_SB_AB:
06144       s = "sb";
06145       goto st;
06146     case M_SH_AB:
06147       s = "sh";
06148       goto st;
06149     case M_SW_AB:
06150       s = "sw";
06151       goto st;
06152     case M_SWC0_AB:
06153       s = "swc0";
06154       /* Itbl support may require additional care here.  */
06155       coproc = 1;
06156       goto st;
06157     case M_SWC1_AB:
06158       s = "swc1";
06159       /* Itbl support may require additional care here.  */
06160       coproc = 1;
06161       goto st;
06162     case M_SWC2_AB:
06163       s = "swc2";
06164       /* Itbl support may require additional care here.  */
06165       coproc = 1;
06166       goto st;
06167     case M_SWC3_AB:
06168       s = "swc3";
06169       /* Itbl support may require additional care here.  */
06170       coproc = 1;
06171       goto st;
06172     case M_SWL_AB:
06173       s = "swl";
06174       goto st;
06175     case M_SWR_AB:
06176       s = "swr";
06177       goto st;
06178     case M_SC_AB:
06179       s = "sc";
06180       goto st;
06181     case M_SCD_AB:
06182       s = "scd";
06183       goto st;
06184     case M_CACHE_AB:
06185       s = "cache";
06186       goto st;
06187     case M_SDC1_AB:
06188       if (mips_opts.arch == CPU_R4650)
06189        {
06190          as_bad (_("opcode not supported on this processor"));
06191          break;
06192        }
06193       s = "sdc1";
06194       coproc = 1;
06195       /* Itbl support may require additional care here.  */
06196       goto st;
06197     case M_SDC2_AB:
06198       s = "sdc2";
06199       /* Itbl support may require additional care here.  */
06200       coproc = 1;
06201       goto st;
06202     case M_SDC3_AB:
06203       s = "sdc3";
06204       /* Itbl support may require additional care here.  */
06205       coproc = 1;
06206       goto st;
06207     case M_SDL_AB:
06208       s = "sdl";
06209       goto st;
06210     case M_SDR_AB:
06211       s = "sdr";
06212     st:
06213       tempreg = AT;
06214       used_at = 1;
06215     ld_st:
06216       /* Itbl support may require additional care here.  */
06217       if (mask == M_LWC1_AB
06218          || mask == M_SWC1_AB
06219          || mask == M_LDC1_AB
06220          || mask == M_SDC1_AB
06221          || mask == M_L_DAB
06222          || mask == M_S_DAB)
06223        fmt = "T,o(b)";
06224       else if (mask == M_CACHE_AB)
06225        fmt = "k,o(b)";
06226       else if (coproc)
06227        fmt = "E,o(b)";
06228       else
06229        fmt = "t,o(b)";
06230 
06231       if (offset_expr.X_op != O_constant
06232          && offset_expr.X_op != O_symbol)
06233        {
06234          as_bad (_("expression too complex"));
06235          offset_expr.X_op = O_constant;
06236        }
06237 
06238       if (HAVE_32BIT_ADDRESSES
06239          && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
06240        {
06241          char value [32];
06242 
06243          sprintf_vma (value, offset_expr.X_add_number);
06244          as_bad (_("Number (0x%s) larger than 32 bits"), value);
06245        }
06246 
06247       /* A constant expression in PIC code can be handled just as it
06248         is in non PIC code.  */
06249       if (offset_expr.X_op == O_constant)
06250        {
06251          expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
06252                             & ~(bfd_vma) 0xffff);
06253          normalize_address_expr (&expr1);
06254          load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
06255          if (breg != 0)
06256            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06257                       tempreg, tempreg, breg);
06258          macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
06259        }
06260       else if (mips_pic == NO_PIC)
06261        {
06262          /* If this is a reference to a GP relative symbol, and there
06263             is no base register, we want
06264               <op>   $treg,<sym>($gp)     (BFD_RELOC_GPREL16)
06265             Otherwise, if there is no base register, we want
06266               lui    $tempreg,<sym>              (BFD_RELOC_HI16_S)
06267               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_LO16)
06268             If we have a constant, we need two instructions anyhow,
06269             so we always use the latter form.
06270 
06271             If we have a base register, and this is a reference to a
06272             GP relative symbol, we want
06273               addu   $tempreg,$breg,$gp
06274               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_GPREL16)
06275             Otherwise we want
06276               lui    $tempreg,<sym>              (BFD_RELOC_HI16_S)
06277               addu   $tempreg,$tempreg,$breg
06278               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_LO16)
06279             With a constant we always use the latter case.
06280 
06281             With 64bit address space and no base register and $at usable,
06282             we want
06283               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHEST)
06284               lui    $at,<sym>            (BFD_RELOC_HI16_S)
06285               daddiu $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHER)
06286               dsll32 $tempreg,0
06287               daddu  $tempreg,$at
06288               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_LO16)
06289             If we have a base register, we want
06290               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHEST)
06291               lui    $at,<sym>            (BFD_RELOC_HI16_S)
06292               daddiu $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHER)
06293               daddu  $at,$breg
06294               dsll32 $tempreg,0
06295               daddu  $tempreg,$at
06296               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_LO16)
06297 
06298             Without $at we can't generate the optimal path for superscalar
06299             processors here since this would require two temporary registers.
06300               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHEST)
06301               daddiu $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHER)
06302               dsll   $tempreg,16
06303               daddiu $tempreg,<sym>              (BFD_RELOC_HI16_S)
06304               dsll   $tempreg,16
06305               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_LO16)
06306             If we have a base register, we want
06307               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHEST)
06308               daddiu $tempreg,<sym>              (BFD_RELOC_MIPS_HIGHER)
06309               dsll   $tempreg,16
06310               daddiu $tempreg,<sym>              (BFD_RELOC_HI16_S)
06311               dsll   $tempreg,16
06312               daddu  $tempreg,$tempreg,$breg
06313               <op>   $treg,<sym>($tempreg)       (BFD_RELOC_LO16)
06314 
06315             For GP relative symbols in 64bit address space we can use
06316             the same sequence as in 32bit address space.  */
06317          if (HAVE_64BIT_SYMBOLS)
06318            {
06319              if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
06320                 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
06321               {
06322                 relax_start (offset_expr.X_add_symbol);
06323                 if (breg == 0)
06324                   {
06325                     macro_build (&offset_expr, s, fmt, treg,
06326                                BFD_RELOC_GPREL16, mips_gp_register);
06327                   }
06328                 else
06329                   {
06330                     macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06331                                tempreg, breg, mips_gp_register);
06332                     macro_build (&offset_expr, s, fmt, treg,
06333                                BFD_RELOC_GPREL16, tempreg);
06334                   }
06335                 relax_switch ();
06336               }
06337 
06338              if (used_at == 0 && !mips_opts.noat)
06339               {
06340                 macro_build (&offset_expr, "lui", "t,u", tempreg,
06341                             BFD_RELOC_MIPS_HIGHEST);
06342                 macro_build (&offset_expr, "lui", "t,u", AT,
06343                             BFD_RELOC_HI16_S);
06344                 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
06345                             tempreg, BFD_RELOC_MIPS_HIGHER);
06346                 if (breg != 0)
06347                   macro_build (NULL, "daddu", "d,v,t", AT, AT, breg);
06348                 macro_build (NULL, "dsll32", "d,w,<", tempreg, tempreg, 0);
06349                 macro_build (NULL, "daddu", "d,v,t", tempreg, tempreg, AT);
06350                 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16,
06351                             tempreg);
06352                 used_at = 1;
06353               }
06354              else
06355               {
06356                 macro_build (&offset_expr, "lui", "t,u", tempreg,
06357                             BFD_RELOC_MIPS_HIGHEST);
06358                 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
06359                             tempreg, BFD_RELOC_MIPS_HIGHER);
06360                 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
06361                 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
06362                             tempreg, BFD_RELOC_HI16_S);
06363                 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
06364                 if (breg != 0)
06365                   macro_build (NULL, "daddu", "d,v,t",
06366                              tempreg, tempreg, breg);
06367                 macro_build (&offset_expr, s, fmt, treg,
06368                             BFD_RELOC_LO16, tempreg);
06369               }
06370 
06371              if (mips_relax.sequence)
06372               relax_end ();
06373              break;
06374            }
06375 
06376          if (breg == 0)
06377            {
06378              if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
06379                 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
06380               {
06381                 relax_start (offset_expr.X_add_symbol);
06382                 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
06383                             mips_gp_register);
06384                 relax_switch ();
06385               }
06386              macro_build_lui (&offset_expr, tempreg);
06387              macro_build (&offset_expr, s, fmt, treg,
06388                         BFD_RELOC_LO16, tempreg);
06389              if (mips_relax.sequence)
06390               relax_end ();
06391            }
06392          else
06393            {
06394              if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
06395                 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
06396               {
06397                 relax_start (offset_expr.X_add_symbol);
06398                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06399                             tempreg, breg, mips_gp_register);
06400                 macro_build (&offset_expr, s, fmt, treg,
06401                             BFD_RELOC_GPREL16, tempreg);
06402                 relax_switch ();
06403               }
06404              macro_build_lui (&offset_expr, tempreg);
06405              macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06406                         tempreg, tempreg, breg);
06407              macro_build (&offset_expr, s, fmt, treg,
06408                         BFD_RELOC_LO16, tempreg);
06409              if (mips_relax.sequence)
06410               relax_end ();
06411            }
06412        }
06413       else if (!mips_big_got)
06414        {
06415          int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
06416 
06417          /* If this is a reference to an external symbol, we want
06418               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
06419               nop
06420               <op>   $treg,0($tempreg)
06421             Otherwise we want
06422               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
06423               nop
06424               addiu  $tempreg,$tempreg,<sym>     (BFD_RELOC_LO16)
06425               <op>   $treg,0($tempreg)
06426 
06427             For NewABI, we want
06428               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT_PAGE)
06429               <op>   $treg,<sym>($tempreg)   (BFD_RELOC_MIPS_GOT_OFST)
06430 
06431             If there is a base register, we add it to $tempreg before
06432             the <op>.  If there is a constant, we stick it in the
06433             <op> instruction.  We don't handle constants larger than
06434             16 bits, because we have no way to load the upper 16 bits
06435             (actually, we could handle them for the subset of cases
06436             in which we are not using $at).  */
06437          assert (offset_expr.X_op == O_symbol);
06438          if (HAVE_NEWABI)
06439            {
06440              macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
06441                         BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
06442              if (breg != 0)
06443               macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06444                           tempreg, tempreg, breg);
06445              macro_build (&offset_expr, s, fmt, treg,
06446                         BFD_RELOC_MIPS_GOT_OFST, tempreg);
06447              break;
06448            }
06449          expr1.X_add_number = offset_expr.X_add_number;
06450          offset_expr.X_add_number = 0;
06451          if (expr1.X_add_number < -0x8000
06452              || expr1.X_add_number >= 0x8000)
06453            as_bad (_("PIC code offset overflow (max 16 signed bits)"));
06454          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
06455                      lw_reloc_type, mips_gp_register);
06456          load_delay_nop ();
06457          relax_start (offset_expr.X_add_symbol);
06458          relax_switch ();
06459          macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
06460                      tempreg, BFD_RELOC_LO16);
06461          relax_end ();
06462          if (breg != 0)
06463            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06464                       tempreg, tempreg, breg);
06465          macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
06466        }
06467       else if (mips_big_got && !HAVE_NEWABI)
06468        {
06469          int gpdelay;
06470 
06471          /* If this is a reference to an external symbol, we want
06472               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
06473               addu   $tempreg,$tempreg,$gp
06474               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
06475               <op>   $treg,0($tempreg)
06476             Otherwise we want
06477               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT16)
06478               nop
06479               addiu  $tempreg,$tempreg,<sym>     (BFD_RELOC_LO16)
06480               <op>   $treg,0($tempreg)
06481             If there is a base register, we add it to $tempreg before
06482             the <op>.  If there is a constant, we stick it in the
06483             <op> instruction.  We don't handle constants larger than
06484             16 bits, because we have no way to load the upper 16 bits
06485             (actually, we could handle them for the subset of cases
06486             in which we are not using $at).  */
06487          assert (offset_expr.X_op == O_symbol);
06488          expr1.X_add_number = offset_expr.X_add_number;
06489          offset_expr.X_add_number = 0;
06490          if (expr1.X_add_number < -0x8000
06491              || expr1.X_add_number >= 0x8000)
06492            as_bad (_("PIC code offset overflow (max 16 signed bits)"));
06493          gpdelay = reg_needs_delay (mips_gp_register);
06494          relax_start (offset_expr.X_add_symbol);
06495          macro_build (&offset_expr, "lui", "t,u", tempreg,
06496                      BFD_RELOC_MIPS_GOT_HI16);
06497          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
06498                      mips_gp_register);
06499          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
06500                      BFD_RELOC_MIPS_GOT_LO16, tempreg);
06501          relax_switch ();
06502          if (gpdelay)
06503            macro_build (NULL, "nop", "");
06504          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
06505                      BFD_RELOC_MIPS_GOT16, mips_gp_register);
06506          load_delay_nop ();
06507          macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
06508                      tempreg, BFD_RELOC_LO16);
06509          relax_end ();
06510 
06511          if (breg != 0)
06512            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06513                       tempreg, tempreg, breg);
06514          macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
06515        }
06516       else if (mips_big_got && HAVE_NEWABI)
06517        {
06518          /* If this is a reference to an external symbol, we want
06519               lui    $tempreg,<sym>              (BFD_RELOC_MIPS_GOT_HI16)
06520               add    $tempreg,$tempreg,$gp
06521               lw     $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
06522               <op>   $treg,<ofst>($tempreg)
06523             Otherwise, for local symbols, we want:
06524               lw     $tempreg,<sym>($gp)  (BFD_RELOC_MIPS_GOT_PAGE)
06525               <op>   $treg,<sym>($tempreg)   (BFD_RELOC_MIPS_GOT_OFST)  */
06526          assert (offset_expr.X_op == O_symbol);
06527          expr1.X_add_number = offset_expr.X_add_number;
06528          offset_expr.X_add_number = 0;
06529          if (expr1.X_add_number < -0x8000
06530              || expr1.X_add_number >= 0x8000)
06531            as_bad (_("PIC code offset overflow (max 16 signed bits)"));
06532          relax_start (offset_expr.X_add_symbol);
06533          macro_build (&offset_expr, "lui", "t,u", tempreg,
06534                      BFD_RELOC_MIPS_GOT_HI16);
06535          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg,
06536                      mips_gp_register);
06537          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
06538                      BFD_RELOC_MIPS_GOT_LO16, tempreg);
06539          if (breg != 0)
06540            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06541                       tempreg, tempreg, breg);
06542          macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
06543 
06544          relax_switch ();
06545          offset_expr.X_add_number = expr1.X_add_number;
06546          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
06547                      BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
06548          if (breg != 0)
06549            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06550                       tempreg, tempreg, breg);
06551          macro_build (&offset_expr, s, fmt, treg,
06552                      BFD_RELOC_MIPS_GOT_OFST, tempreg);
06553          relax_end ();
06554        }
06555       else
06556        abort ();
06557 
06558       break;
06559 
06560     case M_LI:
06561     case M_LI_S:
06562       load_register (treg, &imm_expr, 0);
06563       break;
06564 
06565     case M_DLI:
06566       load_register (treg, &imm_expr, 1);
06567       break;
06568 
06569     case M_LI_SS:
06570       if (imm_expr.X_op == O_constant)
06571        {
06572          used_at = 1;
06573          load_register (AT, &imm_expr, 0);
06574          macro_build (NULL, "mtc1", "t,G", AT, treg);
06575          break;
06576        }
06577       else
06578        {
06579          assert (offset_expr.X_op == O_symbol
06580                 && strcmp (segment_name (S_GET_SEGMENT
06581                                       (offset_expr.X_add_symbol)),
06582                           ".lit4") == 0
06583                 && offset_expr.X_add_number == 0);
06584          macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
06585                      BFD_RELOC_MIPS_LITERAL, mips_gp_register);
06586          break;
06587        }
06588 
06589     case M_LI_D:
06590       /* Check if we have a constant in IMM_EXPR.  If the GPRs are 64 bits
06591          wide, IMM_EXPR is the entire value.  Otherwise IMM_EXPR is the high
06592          order 32 bits of the value and the low order 32 bits are either
06593          zero or in OFFSET_EXPR.  */
06594       if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
06595        {
06596          if (HAVE_64BIT_GPRS)
06597            load_register (treg, &imm_expr, 1);
06598          else
06599            {
06600              int hreg, lreg;
06601 
06602              if (target_big_endian)
06603               {
06604                 hreg = treg;
06605                 lreg = treg + 1;
06606               }
06607              else
06608               {
06609                 hreg = treg + 1;
06610                 lreg = treg;
06611               }
06612 
06613              if (hreg <= 31)
06614               load_register (hreg, &imm_expr, 0);
06615              if (lreg <= 31)
06616               {
06617                 if (offset_expr.X_op == O_absent)
06618                   move_register (lreg, 0);
06619                 else
06620                   {
06621                     assert (offset_expr.X_op == O_constant);
06622                     load_register (lreg, &offset_expr, 0);
06623                   }
06624               }
06625            }
06626          break;
06627        }
06628 
06629       /* We know that sym is in the .rdata section.  First we get the
06630         upper 16 bits of the address.  */
06631       if (mips_pic == NO_PIC)
06632        {
06633          macro_build_lui (&offset_expr, AT);
06634          used_at = 1;
06635        }
06636       else
06637        {
06638          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
06639                      BFD_RELOC_MIPS_GOT16, mips_gp_register);
06640          used_at = 1;
06641        }
06642 
06643       /* Now we load the register(s).  */
06644       if (HAVE_64BIT_GPRS)
06645        {
06646          used_at = 1;
06647          macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
06648        }
06649       else
06650        {
06651          used_at = 1;
06652          macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
06653          if (treg != RA)
06654            {
06655              /* FIXME: How in the world do we deal with the possible
06656                overflow here?  */
06657              offset_expr.X_add_number += 4;
06658              macro_build (&offset_expr, "lw", "t,o(b)",
06659                         treg + 1, BFD_RELOC_LO16, AT);
06660            }
06661        }
06662       break;
06663 
06664     case M_LI_DD:
06665       /* Check if we have a constant in IMM_EXPR.  If the FPRs are 64 bits
06666          wide, IMM_EXPR is the entire value and the GPRs are known to be 64
06667          bits wide as well.  Otherwise IMM_EXPR is the high order 32 bits of
06668          the value and the low order 32 bits are either zero or in
06669          OFFSET_EXPR.  */
06670       if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
06671        {
06672          used_at = 1;
06673          load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
06674          if (HAVE_64BIT_FPRS)
06675            {
06676              assert (HAVE_64BIT_GPRS);
06677              macro_build (NULL, "dmtc1", "t,S", AT, treg);
06678            }
06679          else
06680            {
06681              macro_build (NULL, "mtc1", "t,G", AT, treg + 1);
06682              if (offset_expr.X_op == O_absent)
06683               macro_build (NULL, "mtc1", "t,G", 0, treg);
06684              else
06685               {
06686                 assert (offset_expr.X_op == O_constant);
06687                 load_register (AT, &offset_expr, 0);
06688                 macro_build (NULL, "mtc1", "t,G", AT, treg);
06689               }
06690            }
06691          break;
06692        }
06693 
06694       assert (offset_expr.X_op == O_symbol
06695              && offset_expr.X_add_number == 0);
06696       s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
06697       if (strcmp (s, ".lit8") == 0)
06698        {
06699          if (mips_opts.isa != ISA_MIPS1)
06700            {
06701              macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
06702                         BFD_RELOC_MIPS_LITERAL, mips_gp_register);
06703              break;
06704            }
06705          breg = mips_gp_register;
06706          r = BFD_RELOC_MIPS_LITERAL;
06707          goto dob;
06708        }
06709       else
06710        {
06711          assert (strcmp (s, RDATA_SECTION_NAME) == 0);
06712          used_at = 1;
06713          if (mips_pic != NO_PIC)
06714            macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
06715                       BFD_RELOC_MIPS_GOT16, mips_gp_register);
06716          else
06717            {
06718              /* FIXME: This won't work for a 64 bit address.  */
06719              macro_build_lui (&offset_expr, AT);
06720            }
06721 
06722          if (mips_opts.isa != ISA_MIPS1)
06723            {
06724              macro_build (&offset_expr, "ldc1", "T,o(b)",
06725                         treg, BFD_RELOC_LO16, AT);
06726              break;
06727            }
06728          breg = AT;
06729          r = BFD_RELOC_LO16;
06730          goto dob;
06731        }
06732 
06733     case M_L_DOB:
06734       if (mips_opts.arch == CPU_R4650)
06735        {
06736          as_bad (_("opcode not supported on this processor"));
06737          break;
06738        }
06739       /* Even on a big endian machine $fn comes before $fn+1.  We have
06740         to adjust when loading from memory.  */
06741       r = BFD_RELOC_LO16;
06742     dob:
06743       assert (mips_opts.isa == ISA_MIPS1);
06744       macro_build (&offset_expr, "lwc1", "T,o(b)",
06745                  target_big_endian ? treg + 1 : treg, r, breg);
06746       /* FIXME: A possible overflow which I don't know how to deal
06747         with.  */
06748       offset_expr.X_add_number += 4;
06749       macro_build (&offset_expr, "lwc1", "T,o(b)",
06750                  target_big_endian ? treg : treg + 1, r, breg);
06751       break;
06752 
06753     case M_L_DAB:
06754       /*
06755        * The MIPS assembler seems to check for X_add_number not
06756        * being double aligned and generating:
06757        *      lui    at,%hi(foo+1)
06758        *      addu   at,at,v1
06759        *      addiu  at,at,%lo(foo+1)
06760        *      lwc1   f2,0(at)
06761        *      lwc1   f3,4(at)
06762        * But, the resulting address is the same after relocation so why
06763        * generate the extra instruction?
06764        */
06765       if (mips_opts.arch == CPU_R4650)
06766        {
06767          as_bad (_("opcode not supported on this processor"));
06768          break;
06769        }
06770       /* Itbl support may require additional care here.  */
06771       coproc = 1;
06772       if (mips_opts.isa != ISA_MIPS1)
06773        {
06774          s = "ldc1";
06775          goto ld;
06776        }
06777 
06778       s = "lwc1";
06779       fmt = "T,o(b)";
06780       goto ldd_std;
06781 
06782     case M_S_DAB:
06783       if (mips_opts.arch == CPU_R4650)
06784        {
06785          as_bad (_("opcode not supported on this processor"));
06786          break;
06787        }
06788 
06789       if (mips_opts.isa != ISA_MIPS1)
06790        {
06791          s = "sdc1";
06792          goto st;
06793        }
06794 
06795       s = "swc1";
06796       fmt = "T,o(b)";
06797       /* Itbl support may require additional care here.  */
06798       coproc = 1;
06799       goto ldd_std;
06800 
06801     case M_LD_AB:
06802       if (HAVE_64BIT_GPRS)
06803        {
06804          s = "ld";
06805          goto ld;
06806        }
06807 
06808       s = "lw";
06809       fmt = "t,o(b)";
06810       goto ldd_std;
06811 
06812     case M_SD_AB:
06813       if (HAVE_64BIT_GPRS)
06814        {
06815          s = "sd";
06816          goto st;
06817        }
06818 
06819       s = "sw";
06820       fmt = "t,o(b)";
06821 
06822     ldd_std:
06823       if (offset_expr.X_op != O_symbol
06824          && offset_expr.X_op != O_constant)
06825        {
06826          as_bad (_("expression too complex"));
06827          offset_expr.X_op = O_constant;
06828        }
06829 
06830       if (HAVE_32BIT_ADDRESSES
06831          && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
06832        {
06833          char value [32];
06834 
06835          sprintf_vma (value, offset_expr.X_add_number);
06836          as_bad (_("Number (0x%s) larger than 32 bits"), value);
06837        }
06838 
06839       /* Even on a big endian machine $fn comes before $fn+1.  We have
06840         to adjust when loading from memory.  We set coproc if we must
06841         load $fn+1 first.  */
06842       /* Itbl support may require additional care here.  */
06843       if (! target_big_endian)
06844        coproc = 0;
06845 
06846       if (mips_pic == NO_PIC
06847          || offset_expr.X_op == O_constant)
06848        {
06849          /* If this is a reference to a GP relative symbol, we want
06850               <op>   $treg,<sym>($gp)     (BFD_RELOC_GPREL16)
06851               <op>   $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
06852             If we have a base register, we use this
06853               addu   $at,$breg,$gp
06854               <op>   $treg,<sym>($at)     (BFD_RELOC_GPREL16)
06855               <op>   $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
06856             If this is not a GP relative symbol, we want
06857               lui    $at,<sym>            (BFD_RELOC_HI16_S)
06858               <op>   $treg,<sym>($at)     (BFD_RELOC_LO16)
06859               <op>   $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
06860             If there is a base register, we add it to $at after the
06861             lui instruction.  If there is a constant, we always use
06862             the last case.  */
06863          if (offset_expr.X_op == O_symbol
06864              && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
06865              && !nopic_need_relax (offset_expr.X_add_symbol, 1))
06866            {
06867              relax_start (offset_expr.X_add_symbol);
06868              if (breg == 0)
06869               {
06870                 tempreg = mips_gp_register;
06871               }
06872              else
06873               {
06874                 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
06875                             AT, breg, mips_gp_register);
06876                 tempreg = AT;
06877                 used_at = 1;
06878               }
06879 
06880              /* Itbl support may require additional care here.  */
06881              macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
06882                         BFD_RELOC_GPREL16, tempreg);
06883              offset_expr.X_add_number += 4;
06884 
06885              /* Set mips_optimize to 2 to avoid inserting an
06886                  undesired nop.  */
06887              hold_mips_optimize = mips_optimize;
06888              mips_optimize = 2;
06889              /* Itbl support may require additional care here.  */
06890              macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
06891                         BFD_RELOC_GPREL16, tempreg);
06892              mips_optimize = hold_mips_optimize;
06893 
06894              relax_switch ();
06895 
06896              /* We just generated two relocs.  When tc_gen_reloc
06897                handles this case, it will skip the first reloc and
06898                handle the second.  The second reloc already has an
06899                extra addend of 4, which we added above.  We must
06900                subtract it out, and then subtract another 4 to make
06901                the first reloc come out right.  The second reloc
06902                will come out right because we are going to add 4 to
06903                offset_expr when we build its instruction below.
06904 
06905                If we have a symbol, then we don't want to include
06906                the offset, because it will wind up being included
06907                when we generate the reloc.  */
06908 
06909              if (offset_expr.X_op == O_constant)
06910               offset_expr.X_add_number -= 8;
06911              else
06912               {
06913                 offset_expr.X_add_number = -4;
06914                 offset_expr.X_op = O_constant;
06915               }
06916            }
06917          used_at = 1;
06918          macro_build_lui (&offset_expr, AT);
06919          if (breg != 0)
06920            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
06921          /* Itbl support may require additional care here.  */
06922          macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
06923                      BFD_RELOC_LO16, AT);
06924          /* FIXME: How do we handle overflow here?  */
06925          offset_expr.X_add_number += 4;
06926          /* Itbl support may require additional care here.  */
06927          macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
06928                      BFD_RELOC_LO16, AT);
06929          if (mips_relax.sequence)
06930            relax_end ();
06931        }
06932       else if (!mips_big_got)
06933        {
06934          /* If this is a reference to an external symbol, we want
06935               lw     $at,<sym>($gp)              (BFD_RELOC_MIPS_GOT16)
06936               nop
06937               <op>   $treg,0($at)
06938               <op>   $treg+1,4($at)
06939             Otherwise we want
06940               lw     $at,<sym>($gp)              (BFD_RELOC_MIPS_GOT16)
06941               nop
06942               <op>   $treg,<sym>($at)     (BFD_RELOC_LO16)
06943               <op>   $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
06944             If there is a base register we add it to $at before the
06945             lwc1 instructions.  If there is a constant we include it
06946             in the lwc1 instructions.  */
06947          used_at = 1;
06948          expr1.X_add_number = offset_expr.X_add_number;
06949          if (expr1.X_add_number < -0x8000
06950              || expr1.X_add_number >= 0x8000 - 4)
06951            as_bad (_("PIC code offset overflow (max 16 signed bits)"));
06952          load_got_offset (AT, &offset_expr);
06953          load_delay_nop ();
06954          if (breg != 0)
06955            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
06956 
06957          /* Set mips_optimize to 2 to avoid inserting an undesired
06958              nop.  */
06959          hold_mips_optimize = mips_optimize;
06960          mips_optimize = 2;
06961 
06962          /* Itbl support may require additional care here.  */
06963          relax_start (offset_expr.X_add_symbol);
06964          macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
06965                      BFD_RELOC_LO16, AT);
06966          expr1.X_add_number += 4;
06967          macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
06968                      BFD_RELOC_LO16, AT);
06969          relax_switch ();
06970          macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
06971                      BFD_RELOC_LO16, AT);
06972          offset_expr.X_add_number += 4;
06973          macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
06974                      BFD_RELOC_LO16, AT);
06975          relax_end ();
06976 
06977          mips_optimize = hold_mips_optimize;
06978        }
06979       else if (mips_big_got)
06980        {
06981          int gpdelay;
06982 
06983          /* If this is a reference to an external symbol, we want
06984               lui    $at,<sym>            (BFD_RELOC_MIPS_GOT_HI16)
06985               addu   $at,$at,$gp
06986               lw     $at,<sym>($at)              (BFD_RELOC_MIPS_GOT_LO16)
06987               nop
06988               <op>   $treg,0($at)
06989               <op>   $treg+1,4($at)
06990             Otherwise we want
06991               lw     $at,<sym>($gp)              (BFD_RELOC_MIPS_GOT16)
06992               nop
06993               <op>   $treg,<sym>($at)     (BFD_RELOC_LO16)
06994               <op>   $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
06995             If there is a base register we add it to $at before the
06996             lwc1 instructions.  If there is a constant we include it
06997             in the lwc1 instructions.  */
06998          used_at = 1;
06999          expr1.X_add_number = offset_expr.X_add_number;
07000          offset_expr.X_add_number = 0;
07001          if (expr1.X_add_number < -0x8000
07002              || expr1.X_add_number >= 0x8000 - 4)
07003            as_bad (_("PIC code offset overflow (max 16 signed bits)"));
07004          gpdelay = reg_needs_delay (mips_gp_register);
07005          relax_start (offset_expr.X_add_symbol);
07006          macro_build (&offset_expr, "lui", "t,u",
07007                      AT, BFD_RELOC_MIPS_GOT_HI16);
07008          macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
07009                      AT, AT, mips_gp_register);
07010          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
07011                      AT, BFD_RELOC_MIPS_GOT_LO16, AT);
07012          load_delay_nop ();
07013          if (breg != 0)
07014            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
07015          /* Itbl support may require additional care here.  */
07016          macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
07017                      BFD_RELOC_LO16, AT);
07018          expr1.X_add_number += 4;
07019 
07020          /* Set mips_optimize to 2 to avoid inserting an undesired
07021              nop.  */
07022          hold_mips_optimize = mips_optimize;
07023          mips_optimize = 2;
07024          /* Itbl support may require additional care here.  */
07025          macro_build (&expr1, s, fmt, coproc ? treg : treg + 1,
07026                      BFD_RELOC_LO16, AT);
07027          mips_optimize = hold_mips_optimize;
07028          expr1.X_add_number -= 4;
07029 
07030          relax_switch ();
07031          offset_expr.X_add_number = expr1.X_add_number;
07032          if (gpdelay)
07033            macro_build (NULL, "nop", "");
07034          macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
07035                      BFD_RELOC_MIPS_GOT16, mips_gp_register);
07036          load_delay_nop ();
07037          if (breg != 0)
07038            macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
07039          /* Itbl support may require additional care here.  */
07040          macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
07041                      BFD_RELOC_LO16, AT);
07042          offset_expr.X_add_number += 4;
07043 
07044          /* Set mips_optimize to 2 to avoid inserting an undesired
07045              nop.  */
07046          hold_mips_optimize = mips_optimize;
07047          mips_optimize = 2;
07048          /* Itbl support may require additional care here.  */
07049          macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
07050                      BFD_RELOC_LO16, AT);
07051          mips_optimize = hold_mips_optimize;
07052          relax_end ();
07053        }
07054       else
07055        abort ();
07056 
07057       break;
07058 
07059     case M_LD_OB:
07060       s = "lw";
07061       goto sd_ob;
07062     case M_SD_OB:
07063       s = "sw";
07064     sd_ob:
07065       assert (HAVE_32BIT_ADDRESSES);
07066       macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
07067       offset_expr.X_add_number += 4;
07068       macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
07069       break;
07070 
07071    /* New code added to support COPZ instructions.
07072       This code builds table entries out of the macros in mip_opcodes.
07073       R4000 uses interlocks to handle coproc delays.
07074       Other chips (like the R3000) require nops to be inserted for delays.
07075 
07076       FIXME: Currently, we require that the user handle delays.
07077       In order to fill delay slots for non-interlocked chips,
07078       we must have a way to specify delays based on the coprocessor.
07079       Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
07080       What are the side-effects of the cop instruction?
07081       What cache support might we have and what are its effects?
07082       Both coprocessor & memory require delays. how long???
07083       What registers are read/set/modified?
07084 
07085       If an itbl is provided to interpret cop instructions,
07086       this knowledge can be encoded in the itbl spec.  */
07087 
07088     case M_COP0:
07089       s = "c0";
07090       goto copz;
07091     case M_COP1:
07092       s = "c1";
07093       goto copz;
07094     case M_COP2:
07095       s = "c2";
07096       goto copz;
07097     case M_COP3:
07098       s = "c3";
07099     copz:
07100       /* For now we just do C (same as Cz).  The parameter will be
07101          stored in insn_opcode by mips_ip.  */
07102       macro_build (NULL, s, "C", ip->insn_opcode);
07103       break;
07104 
07105     case M_MOVE:
07106       move_register (dreg, sreg);
07107       break;
07108 
07109 #ifdef LOSING_COMPILER
07110     default:
07111       /* Try and see if this is a new itbl instruction.
07112          This code builds table entries out of the macros in mip_opcodes.
07113          FIXME: For now we just assemble the expression and pass it's
07114          value along as a 32-bit immediate.
07115          We may want to have the assembler assemble this value,
07116          so that we gain the assembler's knowledge of delay slots,
07117          symbols, etc.
07118          Would it be more efficient to use mask (id) here? */
07119       if (itbl_have_entries
07120          && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
07121        {
07122          s = ip->insn_mo->name;
07123          s2 = "cop3";
07124          coproc = ITBL_DECODE_PNUM (immed_expr);;
07125          macro_build (&immed_expr, s, "C");
07126          break;
07127        }
07128       macro2 (ip);
07129       break;
07130     }
07131   if (mips_opts.noat && used_at)
07132     as_bad (_("Macro used $at after \".set noat\""));
07133 }
07134 
07135 static void
07136 macro2 (struct mips_cl_insn *ip)
07137 {
07138   int treg, sreg, dreg, breg;
07139   int tempreg;
07140   int mask;
07141   int used_at;
07142   expressionS expr1;
07143   const char *s;
07144   const char *s2;
07145   const char *fmt;
07146   int likely = 0;
07147   int dbl = 0;
07148   int coproc = 0;
07149   int lr = 0;
07150   int imm = 0;
07151   int off;
07152   offsetT maxnum;
07153   bfd_reloc_code_real_type r;
07154 
07155   treg = (ip->insn_opcode >> 16) & 0x1f;
07156   dreg = (ip->insn_opcode >> 11) & 0x1f;
07157   sreg = breg = (ip->insn_opcode >> 21) & 0x1f;
07158   mask = ip->insn_mo->mask;
07159 
07160   expr1.X_op = O_constant;
07161   expr1.X_op_symbol = NULL;
07162   expr1.X_add_symbol = NULL;
07163   expr1.X_add_number = 1;
07164 
07165   switch (mask)
07166     {
07167 #endif /* LOSING_COMPILER */
07168 
07169     case M_DMUL:
07170       dbl = 1;
07171     case M_MUL:
07172       macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
07173       macro_build (NULL, "mflo", "d", dreg);
07174       break;
07175 
07176     case M_DMUL_I:
07177       dbl = 1;
07178     case M_MUL_I:
07179       /* The MIPS assembler some times generates shifts and adds.  I'm
07180         not trying to be that fancy. GCC should do this for us
07181         anyway.  */
07182       used_at = 1;
07183       load_register (AT, &imm_expr, dbl);
07184       macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
07185       macro_build (NULL, "mflo", "d", dreg);
07186       break;
07187 
07188     case M_DMULO_I:
07189       dbl = 1;
07190     case M_MULO_I:
07191       imm = 1;
07192       goto do_mulo;
07193 
07194     case M_DMULO:
07195       dbl = 1;
07196     case M_MULO:
07197     do_mulo:
07198       start_noreorder ();
07199       used_at = 1;
07200       if (imm)
07201        load_register (AT, &imm_expr, dbl);
07202       macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
07203       macro_build (NULL, "mflo", "d", dreg);
07204       macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
07205       macro_build (NULL, "mfhi", "d", AT);
07206       if (mips_trap)
07207        macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
07208       else
07209        {
07210          expr1.X_add_number = 8;
07211          macro_build (&expr1, "beq", "s,t,p", dreg, AT);
07212          macro_build (NULL, "nop", "", 0);
07213          macro_build (NULL, "break", "c", 6);
07214        }
07215       end_noreorder ();
07216       macro_build (NULL, "mflo", "d", dreg);
07217       break;
07218 
07219     case M_DMULOU_I:
07220       dbl = 1;
07221     case M_MULOU_I:
07222       imm = 1;
07223       goto do_mulou;
07224 
07225     case M_DMULOU:
07226       dbl = 1;
07227     case M_MULOU:
07228     do_mulou:
07229       start_noreorder ();
07230       used_at = 1;
07231       if (imm)
07232        load_register (AT, &imm_expr, dbl);
07233       macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
07234                  sreg, imm ? AT : treg);
07235       macro_build (NULL, "mfhi", "d", AT);
07236       macro_build (NULL, "mflo", "d", dreg);
07237       if (mips_trap)
07238        macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
07239       else
07240        {
07241          expr1.X_add_number = 8;
07242          macro_build (&expr1, "beq", "s,t,p", AT, 0);
07243          macro_build (NULL, "nop", "", 0);
07244          macro_build (NULL, "break", "c", 6);
07245        }
07246       end_noreorder ();
07247       break;
07248 
07249     case M_DROL:
07250       if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
07251        {
07252          if (dreg == sreg)
07253            {
07254              tempreg = AT;
07255              used_at = 1;
07256            }
07257          else
07258            {
07259              tempreg = dreg;
07260            }
07261          macro_build (NULL, "dnegu", "d,w", tempreg, treg);
07262          macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
07263          break;
07264        }
07265       used_at = 1;
07266       macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
07267       macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
07268       macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
07269       macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07270       break;
07271 
07272     case M_ROL:
07273       if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
07274        {
07275          if (dreg == sreg)
07276            {
07277              tempreg = AT;
07278              used_at = 1;
07279            }
07280          else
07281            {
07282              tempreg = dreg;
07283            }
07284          macro_build (NULL, "negu", "d,w", tempreg, treg);
07285          macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
07286          break;
07287        }
07288       used_at = 1;
07289       macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
07290       macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
07291       macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
07292       macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07293       break;
07294 
07295     case M_DROL_I:
07296       {
07297        unsigned int rot;
07298        char *l, *r;
07299 
07300        if (imm_expr.X_op != O_constant)
07301          as_bad (_("Improper rotate count"));
07302        rot = imm_expr.X_add_number & 0x3f;
07303        if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
07304          {
07305            rot = (64 - rot) & 0x3f;
07306            if (rot >= 32)
07307              macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
07308            else
07309              macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
07310            break;
07311          }
07312        if (rot == 0)
07313          {
07314            macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
07315            break;
07316          }
07317        l = (rot < 0x20) ? "dsll" : "dsll32";
07318        r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
07319        rot &= 0x1f;
07320        used_at = 1;
07321        macro_build (NULL, l, "d,w,<", AT, sreg, rot);
07322        macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
07323        macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07324       }
07325       break;
07326 
07327     case M_ROL_I:
07328       {
07329        unsigned int rot;
07330 
07331        if (imm_expr.X_op != O_constant)
07332          as_bad (_("Improper rotate count"));
07333        rot = imm_expr.X_add_number & 0x1f;
07334        if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
07335          {
07336            macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
07337            break;
07338          }
07339        if (rot == 0)
07340          {
07341            macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
07342            break;
07343          }
07344        used_at = 1;
07345        macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
07346        macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
07347        macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07348       }
07349       break;
07350 
07351     case M_DROR:
07352       if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
07353        {
07354          macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
07355          break;
07356        }
07357       used_at = 1;
07358       macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
07359       macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
07360       macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
07361       macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07362       break;
07363 
07364     case M_ROR:
07365       if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
07366        {
07367          macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
07368          break;
07369        }
07370       used_at = 1;
07371       macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
07372       macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
07373       macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
07374       macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07375       break;
07376 
07377     case M_DROR_I:
07378       {
07379        unsigned int rot;
07380        char *l, *r;
07381 
07382        if (imm_expr.X_op != O_constant)
07383          as_bad (_("Improper rotate count"));
07384        rot = imm_expr.X_add_number & 0x3f;
07385        if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
07386          {
07387            if (rot >= 32)
07388              macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
07389            else
07390              macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
07391            break;
07392          }
07393        if (rot == 0)
07394          {
07395            macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
07396            break;
07397          }
07398        r = (rot < 0x20) ? "dsrl" : "dsrl32";
07399        l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
07400        rot &= 0x1f;
07401        used_at = 1;
07402        macro_build (NULL, r, "d,w,<", AT, sreg, rot);
07403        macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
07404        macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07405       }
07406       break;
07407 
07408     case M_ROR_I:
07409       {
07410        unsigned int rot;
07411 
07412        if (imm_expr.X_op != O_constant)
07413          as_bad (_("Improper rotate count"));
07414        rot = imm_expr.X_add_number & 0x1f;
07415        if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
07416          {
07417            macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
07418            break;
07419          }
07420        if (rot == 0)
07421          {
07422            macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
07423            break;
07424          }
07425        used_at = 1;
07426        macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
07427        macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
07428        macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
07429       }
07430       break;
07431 
07432     case M_S_DOB:
07433       if (mips_opts.arch == CPU_R4650)
07434        {
07435          as_bad (_("opcode not supported on this processor"));
07436          break;
07437        }
07438       assert (mips_opts.isa == ISA_MIPS1);
07439       /* Even on a big endian machine $fn comes before $fn+1.  We have
07440         to adjust when storing to memory.  */
07441       macro_build (&offset_expr, "swc1", "T,o(b)",
07442                  target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
07443       offset_expr.X_add_number += 4;
07444       macro_build (&offset_expr, "swc1", "T,o(b)",
07445                  target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
07446       break;
07447 
07448     case M_SEQ:
07449       if (sreg == 0)
07450        macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
07451       else if (treg == 0)
07452        macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
07453       else
07454        {
07455          macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
07456          macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
07457        }
07458       break;
07459 
07460     case M_SEQ_I:
07461       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
07462        {
07463          macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
07464          break;
07465        }
07466       if (sreg == 0)
07467        {
07468          as_warn (_("Instruction %s: result is always false"),
07469                  ip->insn_mo->name);
07470          move_register (dreg, 0);
07471          break;
07472        }
07473       if (imm_expr.X_op == O_constant
07474          && imm_expr.X_add_number >= 0
07475          && imm_expr.X_add_number < 0x10000)
07476        {
07477          macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
07478        }
07479       else if (imm_expr.X_op == O_constant
07480               && imm_expr.X_add_number > -0x8000
07481               && imm_expr.X_add_number < 0)
07482        {
07483          imm_expr.X_add_number = -imm_expr.X_add_number;
07484          macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
07485                      "t,r,j", dreg, sreg, BFD_RELOC_LO16);
07486        }
07487       else
07488        {
07489          load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
07490          macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
07491          used_at = 1;
07492        }
07493       macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
07494       break;
07495 
07496     case M_SGE:             /* sreg >= treg <==> not (sreg < treg) */
07497       s = "slt";
07498       goto sge;
07499     case M_SGEU:
07500       s = "sltu";
07501     sge:
07502       macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
07503       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
07504       break;
07505 
07506     case M_SGE_I:           /* sreg >= I <==> not (sreg < I) */
07507     case M_SGEU_I:
07508       if (imm_expr.X_op == O_constant
07509          && imm_expr.X_add_number >= -0x8000
07510          && imm_expr.X_add_number < 0x8000)
07511        {
07512          macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
07513                      dreg, sreg, BFD_RELOC_LO16);
07514        }
07515       else
07516        {
07517          load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
07518          macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
07519                      dreg, sreg, AT);
07520          used_at = 1;
07521        }
07522       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
07523       break;
07524 
07525     case M_SGT:             /* sreg > treg  <==>  treg < sreg */
07526       s = "slt";
07527       goto sgt;
07528     case M_SGTU:
07529       s = "sltu";
07530     sgt:
07531       macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
07532       break;
07533 
07534     case M_SGT_I:           /* sreg > I  <==>  I < sreg */
07535       s = "slt";
07536       goto sgti;
07537     case M_SGTU_I:
07538       s = "sltu";
07539     sgti:
07540       used_at = 1;
07541       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
07542       macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
07543       break;
07544 
07545     case M_SLE:      /* sreg <= treg  <==>  treg >= sreg  <==>  not (treg < sreg) */
07546       s = "slt";
07547       goto sle;
07548     case M_SLEU:
07549       s = "sltu";
07550     sle:
07551       macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
07552       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
07553       break;
07554 
07555     case M_SLE_I:    /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
07556       s = "slt";
07557       goto slei;
07558     case M_SLEU_I:
07559       s = "sltu";
07560     slei:
07561       used_at = 1;
07562       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
07563       macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
07564       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
07565       break;
07566 
07567     case M_SLT_I:
07568       if (imm_expr.X_op == O_constant
07569          && imm_expr.X_add_number >= -0x8000
07570          && imm_expr.X_add_number < 0x8000)
07571        {
07572          macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
07573          break;
07574        }
07575       used_at = 1;
07576       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
07577       macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
07578       break;
07579 
07580     case M_SLTU_I:
07581       if (imm_expr.X_op == O_constant
07582          && imm_expr.X_add_number >= -0x8000
07583          && imm_expr.X_add_number < 0x8000)
07584        {
07585          macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
07586                      BFD_RELOC_LO16);
07587          break;
07588        }
07589       used_at = 1;
07590       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
07591       macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
07592       break;
07593 
07594     case M_SNE:
07595       if (sreg == 0)
07596        macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
07597       else if (treg == 0)
07598        macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
07599       else
07600        {
07601          macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
07602          macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
07603        }
07604       break;
07605 
07606     case M_SNE_I:
07607       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
07608        {
07609          macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
07610          break;
07611        }
07612       if (sreg == 0)
07613        {
07614          as_warn (_("Instruction %s: result is always true"),
07615                  ip->insn_mo->name);
07616          macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
07617                      dreg, 0, BFD_RELOC_LO16);
07618          break;
07619        }
07620       if (imm_expr.X_op == O_constant
07621          && imm_expr.X_add_number >= 0
07622          && imm_expr.X_add_number < 0x10000)
07623        {
07624          macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);