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cell-binutils  2.17cvs20070401
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tc-mep.c File Reference
#include <stdio.h>
#include "as.h"
#include "dwarf2dbg.h"
#include "subsegs.h"
#include "symcat.h"
#include "opcodes/mep-desc.h"
#include "opcodes/mep-opc.h"
#include "cgen.h"
#include "elf/common.h"
#include "elf/mep.h"
#include "libbfd.h"
#include "xregex.h"

Go to the source code of this file.

Classes

struct  mep_insn
struct  mep_hi_fixup

Defines

#define INSN_VALUE(buf)   (buf)
#define OPTION_EB   (OPTION_MD_BASE + 0)
#define OPTION_EL   (OPTION_MD_BASE + 1)
#define OPTION_CONFIG   (OPTION_MD_BASE + 2)
#define OPTION_AVERAGE   (OPTION_MD_BASE + 3)
#define OPTION_NOAVERAGE   (OPTION_MD_BASE + 4)
#define OPTION_MULT   (OPTION_MD_BASE + 5)
#define OPTION_NOMULT   (OPTION_MD_BASE + 6)
#define OPTION_DIV   (OPTION_MD_BASE + 7)
#define OPTION_NODIV   (OPTION_MD_BASE + 8)
#define OPTION_BITOPS   (OPTION_MD_BASE + 9)
#define OPTION_NOBITOPS   (OPTION_MD_BASE + 10)
#define OPTION_LEADZ   (OPTION_MD_BASE + 11)
#define OPTION_NOLEADZ   (OPTION_MD_BASE + 12)
#define OPTION_ABSDIFF   (OPTION_MD_BASE + 13)
#define OPTION_NOABSDIFF   (OPTION_MD_BASE + 14)
#define OPTION_MINMAX   (OPTION_MD_BASE + 15)
#define OPTION_NOMINMAX   (OPTION_MD_BASE + 16)
#define OPTION_CLIP   (OPTION_MD_BASE + 17)
#define OPTION_NOCLIP   (OPTION_MD_BASE + 18)
#define OPTION_SATUR   (OPTION_MD_BASE + 19)
#define OPTION_NOSATUR   (OPTION_MD_BASE + 20)
#define OPTION_COP32   (OPTION_MD_BASE + 21)
#define OPTION_REPEAT   (OPTION_MD_BASE + 25)
#define OPTION_NOREPEAT   (OPTION_MD_BASE + 26)
#define OPTION_DEBUG   (OPTION_MD_BASE + 27)
#define OPTION_NODEBUG   (OPTION_MD_BASE + 28)
#define OPTION_LIBRARY   (OPTION_MD_BASE + 29)
#define NUM_MAPPINGS   (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
#define MAP(n)   case MEP_OPERAND_n: return BFD_RELOC_MEP_n;
#define FX_OPINFO_R_TYPE(f)   ((f)->fx_cgen.opinfo)
#define MAX_LITTLENUMS   6

Enumerations

enum  MepPseudo64Values { MEP_PSEUDO64_NONE, MEP_PSEUDO64_16BITCC, MEP_PSEUDO64_32BITCC }

Functions

static void mep_switch_to_vliw_mode (int)
static void mep_switch_to_core_mode (int)
static void mep_s_vtext (int)
static void mep_noregerr (int)
int md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
void md_show_usage (FILE *stream)
static void mep_check_for_disabled_registers (mep_insn *insn)
static int mep_machine (void)
static const char * mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want, const char **strP, int opindex, int opinfo, enum cgen_parse_operand_result *resultP, bfd_vma *valueP)
void md_begin ()
static const CGEN_INSN * mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd, const char *str, CGEN_FIELDS *fields, CGEN_INSN_BYTES_PTR buf, const struct cgen_insn *pinsn)
static void mep_save_insn (mep_insn insn)
static void mep_check_parallel32_scheduling (void)
static void mep_check_parallel64_scheduling (void)
static void mep_check_parallel_scheduling (void)
static void mep_process_saved_insns (void)
void md_assemble (char *str)
valueT md_section_align (segT segment, valueT size)
symbolS * md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
void mep_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
static int insn_to_subtype (int insn)
int md_estimate_size_before_relax (fragS *fragP, segT segment)
static int target_address_for (fragS *frag)
void md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, fragS *fragP)
void mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
long md_pcrel_from_section (fixS *fixP, segT sec)
bfd_reloc_code_real_type md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, const CGEN_OPERAND *operand, fixS *fixP)
fixS * mep_cgen_record_fixup_exp (fragS *frag, int where, const CGEN_INSN *insn, int length, const CGEN_OPERAND *operand, int opinfo, expressionS *exp)
void mep_frob_file ()
int mep_force_relocation (fixS *fixp)
void md_number_to_chars (char *buf, valueT val, int n)
char * md_atof (int type, char *litP, int *sizeP)
bfd_boolean mep_fix_adjustable (fixS *fixP)
int mep_elf_section_letter (int letter, char **ptrmsg)
flagword mep_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
static segT mep_vtext_section (void)
static void mep_s_vtext (int ignore ATTRIBUTE_UNUSED)
static void mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED)
static void mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED)
static void mep_noregerr (int i ATTRIBUTE_UNUSED)
int mep_unrecognized_line (int ch)
void mep_cleanup (void)
int mep_flush_pending_output (void)

Variables

static int mode = CORE
static int pluspresent = 0
static int allow_disabled_registers = 0
static int library_flag = 0
static mep_insn saved_insns [MAX_SAVED_FIXUP_CHAINS]
static int num_insns_saved = 0
const char comment_chars [] = "#"
const char line_comment_chars [] = ";#"
const char line_separator_chars [] = ";"
const char EXP_CHARS [] = "eE"
const char FLT_CHARS [] = "dD"
const pseudo_typeS md_pseudo_table []
static struct mep_hi_fixupmep_hi_fixup_list
size_t md_longopts_size = sizeof (md_longopts)
const char * md_shortopts = ""
static int optbits = 0
static int optbitset = 0
const relax_typeS md_relax_table []
struct {
int insn
int growth
int insn_for_extern
subtype_mappings []

Class Documentation

struct mep_insn

Definition at line 36 of file tc-mep.c.

Class Members
char * addr
unsigned char buffer
CGEN_FIELDS fields
fixS * fixups
fragS * frag
int indices
const CGEN_INSN * insn
int num_fixups
const CGEN_INSN * orig_insn
struct mep_hi_fixup

Definition at line 101 of file tc-mep.c.

Collaboration diagram for mep_hi_fixup:
Class Members
fixS * fixp
struct mep_hi_fixup * next
segT seg

Define Documentation

#define FX_OPINFO_R_TYPE (   f)    ((f)->fx_cgen.opinfo)

Definition at line 1569 of file tc-mep.c.

#define INSN_VALUE (   buf)    (buf)

Definition at line 46 of file tc-mep.c.

#define MAP (   n)    case MEP_OPERAND_n: return BFD_RELOC_MEP_n;

Definition at line 1474 of file tc-mep.c.

#define MAX_LITTLENUMS   6

Definition at line 1684 of file tc-mep.c.

#define NUM_MAPPINGS   (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))

Definition at line 1176 of file tc-mep.c.

#define OPTION_ABSDIFF   (OPTION_MD_BASE + 13)

Definition at line 125 of file tc-mep.c.

#define OPTION_AVERAGE   (OPTION_MD_BASE + 3)

Definition at line 115 of file tc-mep.c.

#define OPTION_BITOPS   (OPTION_MD_BASE + 9)

Definition at line 121 of file tc-mep.c.

#define OPTION_CLIP   (OPTION_MD_BASE + 17)

Definition at line 129 of file tc-mep.c.

#define OPTION_CONFIG   (OPTION_MD_BASE + 2)

Definition at line 114 of file tc-mep.c.

#define OPTION_COP32   (OPTION_MD_BASE + 21)

Definition at line 133 of file tc-mep.c.

#define OPTION_DEBUG   (OPTION_MD_BASE + 27)

Definition at line 136 of file tc-mep.c.

#define OPTION_DIV   (OPTION_MD_BASE + 7)

Definition at line 119 of file tc-mep.c.

#define OPTION_EB   (OPTION_MD_BASE + 0)

Definition at line 112 of file tc-mep.c.

#define OPTION_EL   (OPTION_MD_BASE + 1)

Definition at line 113 of file tc-mep.c.

#define OPTION_LEADZ   (OPTION_MD_BASE + 11)

Definition at line 123 of file tc-mep.c.

#define OPTION_LIBRARY   (OPTION_MD_BASE + 29)

Definition at line 138 of file tc-mep.c.

#define OPTION_MINMAX   (OPTION_MD_BASE + 15)

Definition at line 127 of file tc-mep.c.

#define OPTION_MULT   (OPTION_MD_BASE + 5)

Definition at line 117 of file tc-mep.c.

#define OPTION_NOABSDIFF   (OPTION_MD_BASE + 14)

Definition at line 126 of file tc-mep.c.

#define OPTION_NOAVERAGE   (OPTION_MD_BASE + 4)

Definition at line 116 of file tc-mep.c.

#define OPTION_NOBITOPS   (OPTION_MD_BASE + 10)

Definition at line 122 of file tc-mep.c.

#define OPTION_NOCLIP   (OPTION_MD_BASE + 18)

Definition at line 130 of file tc-mep.c.

#define OPTION_NODEBUG   (OPTION_MD_BASE + 28)

Definition at line 137 of file tc-mep.c.

#define OPTION_NODIV   (OPTION_MD_BASE + 8)

Definition at line 120 of file tc-mep.c.

#define OPTION_NOLEADZ   (OPTION_MD_BASE + 12)

Definition at line 124 of file tc-mep.c.

#define OPTION_NOMINMAX   (OPTION_MD_BASE + 16)

Definition at line 128 of file tc-mep.c.

#define OPTION_NOMULT   (OPTION_MD_BASE + 6)

Definition at line 118 of file tc-mep.c.

#define OPTION_NOREPEAT   (OPTION_MD_BASE + 26)

Definition at line 135 of file tc-mep.c.

#define OPTION_NOSATUR   (OPTION_MD_BASE + 20)

Definition at line 132 of file tc-mep.c.

#define OPTION_REPEAT   (OPTION_MD_BASE + 25)

Definition at line 134 of file tc-mep.c.

#define OPTION_SATUR   (OPTION_MD_BASE + 19)

Definition at line 131 of file tc-mep.c.


Enumeration Type Documentation

Enumerator:
MEP_PSEUDO64_NONE 
MEP_PSEUDO64_16BITCC 
MEP_PSEUDO64_32BITCC 

Definition at line 1135 of file tc-mep.c.


Function Documentation

static int insn_to_subtype ( int  insn) [static]

Definition at line 1189 of file tc-mep.c.

{
  unsigned int i;
  for (i=0; i<NUM_MAPPINGS; i++)
    if (insn == subtype_mappings[i].insn)
      return i;
  abort ();
}

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void md_assemble ( char *  str)

Definition at line 910 of file tc-mep.c.

{
  static CGEN_BITSET* isas = NULL;
  char * errmsg;

  /* Initialize GAS's cgen interface for a new instruction.  */
  gas_cgen_init_parse ();

  /* There are two possible modes: core and vliw.  We have to assemble
     differently for each.

     Core Mode:  We assemble normally.  All instructions are on a
                 single line and are made up of one mnemonic and one
                 set of operands.
     VLIW Mode:  Vliw combinations are indicated as follows:

                     core insn
                   + copro insn

                 We want to handle the general case where more than
                 one instruction can be preceeded by a +.  This will
                 happen later if we add support for internally parallel
                 coprocessors.  We'll make the parsing nice and general
                 so that it can handle an arbitrary number of insns
                 with leading +'s.  The actual checking for valid
                 combinations is done elsewhere.  */

  /* Initialize the isa to refer to the core.  */
  if (isas == NULL)
    isas = cgen_bitset_copy (& MEP_CORE_ISA);
  else
    {
      cgen_bitset_clear (isas);
      cgen_bitset_union (isas, & MEP_CORE_ISA, isas);
    }
  gas_cgen_cpu_desc->isas = isas;

  if (mode == VLIW)
    {
      /* VLIW mode.  */

      int thisInsnIsCopro = 0;
      mep_insn insn;
      int i;
      
      /* Initialize the insn buffer */
       
      if (! CGEN_INT_INSN_P)
         for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
            insn.buffer[i]='\0';

      /* Can't tell core / copro insns apart at parse time! */
      cgen_bitset_union (isas, & MEP_COP_ISA, isas);

      /* Assemble the insn so we can examine its attributes. */
      insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
                                     &insn.fields, insn.buffer,
                                     &errmsg);
      if (!insn.insn)
       {
         as_bad ("%s", errmsg);
         return;
       }
      mep_check_for_disabled_registers (&insn);

      /* Check to see if it's a coprocessor instruction. */
      thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);

      if (!thisInsnIsCopro)
       {
         insn.insn = mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc, str,
                                            &insn.fields, insn.buffer,
                                            insn.insn);
         thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
         mep_check_for_disabled_registers (&insn);
       }

      if (pluspresent)
       {
         /* A plus was present. */
         /* Check for a + with a core insn and abort if found. */
         if (!thisInsnIsCopro)
           {
             as_fatal("A core insn cannot be preceeded by a +.\n");
             return;
           }

         if (num_insns_saved > 0)
           {
             /* There are insns in the queue. Add this one. */
             mep_save_insn (insn);
           }
         else
           {
             /* There are no insns in the queue and a plus is present.
               This is a syntax error.  Let's not tolerate this.
               We can relax this later if necessary.  */
             as_bad (_("Invalid use of parallelization operator."));
             return;
           }
       }
      else
       {
         /* No plus was present. */
         if (num_insns_saved > 0)
           {
             /* There are insns saved and we came across an insn without a
               leading +.  That's the signal to process the saved insns
               before proceeding then treat the current insn as the first
               in a new vliw group.  */
             mep_process_saved_insns ();
             num_insns_saved = 0;
             /* mep_save_insn (insn); */
           }
         mep_save_insn (insn);
#if 0
         else
           {

              /* Core Insn. Add it to the beginning of the queue. */
              mep_save_insn (insn);
             /* gas_cgen_save_fixups(num_insns_saved); */
           }
#endif
       }

      pluspresent = 0;
    }
  else
    {
      /* Core mode.  */

      /* Only single instructions are assembled in core mode. */
      mep_insn insn;

      /* If a leading '+' was present, issue an error.
        That's not allowed in core mode. */
      if (pluspresent)
       {
         as_bad (_("Leading plus sign not allowed in core mode"));
         return;
       }

      insn.insn = mep_cgen_assemble_insn
       (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);

      if (!insn.insn)
       {
         as_bad ("%s", errmsg);
         return;
       }
      gas_cgen_finish_insn (insn.insn, insn.buffer,
                         CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
      mep_check_for_disabled_registers (&insn);
    }
}

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char* md_atof ( int type  ,
char *  litP,
int sizeP 
)

Definition at line 1687 of file tc-mep.c.

{
  int              i;
  int              prec;
  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
  char *           t;

  switch (type)
    {
    case 'f':
    case 'F':
    case 's':
    case 'S':
      prec = 2;
      break;

    case 'd':
    case 'D':
    case 'r':
    case 'R':
      prec = 4;
      break;

    /* FIXME: Some targets allow other format chars for bigger sizes here.  */
    default:
      *sizeP = 0;
      return _("Bad call to md_atof()");
    }

  t = atof_ieee (input_line_pointer, type, words);
  if (t)
    input_line_pointer = t;
  * sizeP = prec * sizeof (LITTLENUM_TYPE);

  for (i = 0; i < prec; i++)
    {
      md_number_to_chars (litP, (valueT) words[i],
                       sizeof (LITTLENUM_TYPE));
      litP += sizeof (LITTLENUM_TYPE);
    }

  return 0;
}

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void md_begin ( void  )

Definition at line 427 of file tc-mep.c.

{
  /* Initialize the `cgen' interface.  */

  /* If the user specifies no options, we default to allowing
     everything.  If the user specifies any enabling options, we
     default to allowing only what is specified.  If the user
     specifies only disabling options, we only disable what is
     specified.  If the user specifies options and a config, the
     options modify the config.  */
  if (optbits && mep_config_index == 0)
    MEP_OMASK = optbits;
  else
    MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;

  /* Set the machine number and endian.  */
  gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
                                    CGEN_CPU_OPEN_ENDIAN,
                                    target_big_endian
                                    ? CGEN_ENDIAN_BIG
                                    : CGEN_ENDIAN_LITTLE,
                                    CGEN_CPU_OPEN_ISAS, 0,
                                    CGEN_CPU_OPEN_END);
  mep_cgen_init_asm (gas_cgen_cpu_desc);

  /* This is a callback from cgen to gas to parse operands.  */
  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, mep_parse_operand);

  /* Identify the architecture.  */
  bfd_default_set_arch_mach (stdoutput, bfd_arch_mep, mep_machine ());

  /* Store the configuration number and core.  */
  bfd_set_private_flags (stdoutput, MEP_CPU | MEP_CONFIG | library_flag);

  /* Initialize the array we'll be using to store fixups.  */
  gas_cgen_initialize_saved_fixups_array();
}

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bfd_reloc_code_real_type md_cgen_lookup_reloc ( const CGEN_INSN *insn  ATTRIBUTE_UNUSED,
const CGEN_OPERAND operand,
fixS *  fixP 
)

Definition at line 1478 of file tc-mep.c.

{
  enum bfd_reloc_code_real reloc = fixP->fx_cgen.opinfo;
  static char printed[MEP_OPERAND_MAX] = { 0 };

  /* If there's a reloc here, it's because the parser saw a %foo() and
     is giving us the correct reloc to use, or because we converted to
     a different size reloc below and want to avoid "converting" more
     than once.  */
  if (reloc && reloc != BFD_RELOC_NONE)
    return reloc;

  switch (operand->type)
    {
      MAP (PCREL8A2);       /* beqz */
      MAP (PCREL12A2);      /* bsr16 */
      MAP (PCREL17A2);      /* beqi */
      MAP (PCREL24A2);      /* bsr24 */
      MAP (PCABS24A2);      /* jmp */
      MAP (UIMM24);  /* mov */
      MAP (ADDR24A4);       /* sw/lw */

    /* The rest of the relocs should be generated by the parser,
       for things such as %tprel(), etc. */
    case MEP_OPERAND_SIMM16:
#ifdef OBJ_COMPLEX_RELC
      /* coalescing this into RELOC_MEP_16 is actually a bug,
        since it's a signed operand. let the relc code handle it. */
      return BFD_RELOC_RELC; 
#endif

    case MEP_OPERAND_UIMM16:
    case MEP_OPERAND_SDISP16:
    case MEP_OPERAND_CODE16:
      fixP->fx_where += 2;
      /* to avoid doing the above add twice */
      fixP->fx_cgen.opinfo = BFD_RELOC_MEP_16;
      return BFD_RELOC_MEP_16;

    default:
#ifdef OBJ_COMPLEX_RELC
      /* this is not an error, yet. 
        pass it to the linker. */
      return BFD_RELOC_RELC;
#endif
      if (printed[operand->type])
       return BFD_RELOC_NONE;
      printed[operand->type] = 1;

      as_bad_where (fixP->fx_file, fixP->fx_line,
                  _("Don't know how to relocate plain operands of type %s"),
                  operand->name);

      /* Print some helpful hints for the user.  */
      switch (operand->type)
       {
       case MEP_OPERAND_UDISP7:
       case MEP_OPERAND_UDISP7A2:
       case MEP_OPERAND_UDISP7A4:
         as_bad_where (fixP->fx_file, fixP->fx_line,
                     _("Perhaps you are missing %%tpoff()?"));
         break;
       default:
         break;
       }
      return BFD_RELOC_NONE;
    }
}

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void md_convert_frag ( bfd *abfd  ATTRIBUTE_UNUSED,
segT sec  ATTRIBUTE_UNUSED,
fragS *  fragP 
)

Definition at line 1277 of file tc-mep.c.

{
  int addend, rn, bit = 0;
  int operand;
  int where = fragP->fr_opcode - fragP->fr_literal;
  int e = target_big_endian ? 0 : 1;

  addend = target_address_for (fragP) - (fragP->fr_address + where);

  if (subtype_mappings[fragP->fr_subtype].insn == -1)
    {
      fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
      switch (subtype_mappings[fragP->fr_subtype].insn_for_extern)
       {
       case MEP_PSEUDO64_16BITCC:
         fragP->fr_opcode[1^e] = ((fragP->fr_opcode[1^e] & 1) ^ 1) | 0x06;
         fragP->fr_opcode[2^e] = 0xd8;
         fragP->fr_opcode[3^e] = 0x08;
         fragP->fr_opcode[4^e] = 0;
         fragP->fr_opcode[5^e] = 0;
         where += 2;
         break;
       case MEP_PSEUDO64_32BITCC:
         if (fragP->fr_opcode[0^e] & 0x10)
           fragP->fr_opcode[1^e] ^= 0x01;
         else
           fragP->fr_opcode[1^e] ^= 0x04;
         fragP->fr_opcode[2^e] = 0;
         fragP->fr_opcode[3^e] = 4;
         fragP->fr_opcode[4^e] = 0xd8;
         fragP->fr_opcode[5^e] = 0x08;
         fragP->fr_opcode[6^e] = 0;
         fragP->fr_opcode[7^e] = 0;
         where += 4;
         break;
       default:
         abort ();
       }
      fragP->fr_cgen.insn = (fragP->fr_cgen.insn
                          - fragP->fr_cgen.insn->base->num
                          + MEP_INSN_JMP);
      operand = MEP_OPERAND_PCABS24A2;
    }
  else
    switch (fragP->fr_cgen.insn->base->num)
      {
      case MEP_INSN_BSR12:
       fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
       fragP->fr_opcode[1^e] = 0x01 | (addend & 0xfe);
       operand = MEP_OPERAND_PCREL12A2;
       break;

      case MEP_INSN_BSR24:
       fragP->fr_fix += 2;
       fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
       fragP->fr_opcode[1^e] = 0x09 | ((addend << 3) & 0xf0);
       fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
       fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
       operand = MEP_OPERAND_PCREL24A2;
       break;

      case MEP_INSN_BRA:
       fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
       fragP->fr_opcode[1^e] = 0x00 | (addend & 0xfe);
       operand = MEP_OPERAND_PCREL12A2;
       break;

      case MEP_INSN_BEQ:
       /* The default relax_frag doesn't change the state if there is no
          growth, so we must manually handle converting out-of-range BEQ
          instructions to JMP.  */
       if (addend <= 65535 && addend >= -65536)
         {
           fragP->fr_fix += 2;
           fragP->fr_opcode[0^e] = 0xe0;
           fragP->fr_opcode[1^e] = 0x01;
           fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
           fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
           operand = MEP_OPERAND_PCREL17A2;
           break;
         }
       /* ...FALLTHROUGH... */

      case MEP_INSN_JMP:
       addend = target_address_for (fragP);
       fragP->fr_fix += 2;
       fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
       fragP->fr_opcode[1^e] = 0x08 | ((addend << 3) & 0xf0);
       fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
       fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
       operand = MEP_OPERAND_PCABS24A2;
       break;

      case MEP_INSN_BNEZ:
       bit = 1;
      case MEP_INSN_BEQZ:
       fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
       operand = MEP_OPERAND_PCREL8A2;
       break;

      case MEP_INSN_BNEI:
       bit = 4;
      case MEP_INSN_BEQI:
       if (subtype_mappings[fragP->fr_subtype].growth)
         {
           fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
           rn = fragP->fr_opcode[0^e] & 0x0f;
           fragP->fr_opcode[0^e] = 0xe0 | rn;
           fragP->fr_opcode[1^e] = bit;
         }
       fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
       fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
       operand = MEP_OPERAND_PCREL17A2;
       break;

      case MEP_INSN_BLTI:
      case MEP_INSN_BGEI:
      case MEP_INSN_BCPEQ:
      case MEP_INSN_BCPNE:
      case MEP_INSN_BCPAT:
      case MEP_INSN_BCPAF:
       /* No opcode change needed, just operand.  */
       fragP->fr_opcode[2^e] = (addend >> 9) & 0xff;
       fragP->fr_opcode[3^e] = (addend >> 1) & 0xff;
       operand = MEP_OPERAND_PCREL17A2;
       break;

      default:
       abort ();
      }

  if (S_GET_SEGMENT (fragP->fr_symbol) != sec
      || operand == MEP_OPERAND_PCABS24A2)
    {
      assert (fragP->fr_cgen.insn != 0);
      gas_cgen_record_fixup (fragP,
                          where,
                          fragP->fr_cgen.insn,
                          (fragP->fr_fix - where) * 8,
                          cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
                                                  operand),
                          fragP->fr_cgen.opinfo,
                          fragP->fr_symbol, fragP->fr_offset);
    }
}

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int md_estimate_size_before_relax ( fragS *  fragP,
segT segment   
)

Definition at line 1209 of file tc-mep.c.

{
  if (fragP->fr_subtype == 1)
    fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);

  if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
    {
      int new_insn;

      new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
      fragP->fr_subtype = insn_to_subtype (new_insn);
    }

  if (MEP_VLIW && ! MEP_VLIW64
      && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
    {
      /* Use 32 bit branches for vliw32 so the vliw word is not split.  */
      switch (fragP->fr_cgen.insn->base->num)
       {
       case MEP_INSN_BSR12:
         fragP->fr_subtype = insn_to_subtype 
           (subtype_mappings[fragP->fr_subtype].insn_for_extern);
         break;
       case MEP_INSN_BEQZ:
         fragP->fr_subtype ++;
         break;
       case MEP_INSN_BNEZ:
         fragP->fr_subtype ++;
         break;
       }
    }

  if (fragP->fr_cgen.insn->base
      && fragP->fr_cgen.insn->base->num
         != subtype_mappings[fragP->fr_subtype].insn)
    {
      int new_insn= subtype_mappings[fragP->fr_subtype].insn;
      if (new_insn != -1)
       {
         fragP->fr_cgen.insn = (fragP->fr_cgen.insn
                             - fragP->fr_cgen.insn->base->num
                             + new_insn);
       }
    }

  return subtype_mappings[fragP->fr_subtype].growth;
}

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void md_number_to_chars ( char *  buf,
valueT  val,
int  n 
)

Definition at line 1670 of file tc-mep.c.

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int md_parse_option ( int c  ,
char *arg  ATTRIBUTE_UNUSED 
)

Definition at line 174 of file tc-mep.c.

{
  int i, idx;
  switch (c)
    {
    case OPTION_EB:
      target_big_endian = 1;
      break;
    case OPTION_EL:
      target_big_endian = 0;
      break;
    case OPTION_CONFIG:
      idx = 0;
      for (i=1; mep_config_map[i].name; i++)
       if (strcmp (mep_config_map[i].name, arg) == 0)
         {
           idx = i;
           break;
         }
      if (!idx)
       {
         fprintf (stderr, "Error: unknown configuration %s\n", arg);
         return 0;
       }
      mep_config_index = idx;
      target_big_endian = mep_config_map[idx].big_endian;
      break;
    case OPTION_AVERAGE:
      optbits |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
      break;
    case OPTION_NOAVERAGE:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
      break;
    case OPTION_MULT:
      optbits |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
      break;
    case OPTION_NOMULT:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
      break;
    case OPTION_DIV:
      optbits |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
      break;
    case OPTION_NODIV:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
      break;
    case OPTION_BITOPS:
      optbits |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
      break;
    case OPTION_NOBITOPS:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
      break;
    case OPTION_LEADZ:
      optbits |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
      break;
    case OPTION_NOLEADZ:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
      break;
    case OPTION_ABSDIFF:
      optbits |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
      break;
    case OPTION_NOABSDIFF:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
      break;
    case OPTION_MINMAX:
      optbits |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
      break;
    case OPTION_NOMINMAX:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
      break;
    case OPTION_CLIP:
      optbits |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
      break;
    case OPTION_NOCLIP:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
      break;
    case OPTION_SATUR:
      optbits |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
      break;
    case OPTION_NOSATUR:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
      break;
    case OPTION_COP32:
      optbits |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
      break;
    case OPTION_DEBUG:
      optbits |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
      optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
      break;
    case OPTION_NODEBUG:
      optbits &= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN);
      optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
      break;
    case OPTION_LIBRARY:
      library_flag = EF_MEP_LIBRARY;
      break;
    case OPTION_REPEAT:
    case OPTION_NOREPEAT:
      break;
    default:
      return 0;
    }
  return 1;
}

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long md_pcrel_from_section ( fixS *  fixP,
segT sec   
)

Definition at line 1452 of file tc-mep.c.

{
  if (fixP->fx_addsy != (symbolS *) NULL
      && (! S_IS_DEFINED (fixP->fx_addsy)
         || S_GET_SEGMENT (fixP->fx_addsy) != sec))
    /* The symbol is undefined (or is defined but not in this section).
       Let the linker figure it out.  */
    return 0;

  /* Return the address of the opcode - cgen adjusts for opcode size
     itself, to be consistent with the disassembler, which must do
     so.  */
  return fixP->fx_where + fixP->fx_frag->fr_address;
}

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valueT md_section_align ( segT segment  ,
valueT size   
)

Definition at line 1068 of file tc-mep.c.

{
  int align = bfd_get_section_alignment (stdoutput, segment);
  return ((size + (1 << align) - 1) & (-1 << align));
}

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void md_show_usage ( FILE *  stream)

Definition at line 298 of file tc-mep.c.

{
  fprintf (stream, _("MeP specific command line options:\n\
  -EB                     assemble for a big endian system (default)\n\
  -EL                     assemble for a little endian system\n\
  -mconfig=<name>         specify a chip configuration to use\n\
  -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
  -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
  -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
                          enable/disable the given opcodes\n\
\n\
  If -mconfig is given, the other -m options modify it.  Otherwise,\n\
  if no -m options are given, all core opcodes are enabled;\n\
  if any enabling -m options are given, only those are enabled;\n\
  if only disabling -m options are given, only those are disabled.\n\
"));
  if (mep_config_map[1].name)
    {
      int i;
      fprintf (stream, "  -mconfig=STR            specify the configuration to use\n");
      fprintf (stream, "  Configurations:");
      for (i=0; mep_config_map[i].name; i++)
       fprintf (stream, " %s", mep_config_map[i].name);
      fprintf (stream, "\n");
    }
}

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symbolS* md_undefined_symbol ( char *name  ATTRIBUTE_UNUSED)

Definition at line 1076 of file tc-mep.c.

{
  return 0;
}
void mep_apply_fix ( fixS *  fixP,
valueT valP,
segT seg  ATTRIBUTE_UNUSED 
)

Definition at line 1429 of file tc-mep.c.

{
  /* If we already know the fixup value, adjust it in the same
     way that the linker would have done.  */
  if (fixP->fx_addsy == 0)
    switch (fixP->fx_cgen.opinfo)
      {
      case BFD_RELOC_MEP_LOW16:
       *valP = ((long)(*valP & 0xffff)) << 16 >> 16;
       break;
      case BFD_RELOC_MEP_HI16U:
       *valP >>= 16;
       break;
      case BFD_RELOC_MEP_HI16S:
       *valP = (*valP + 0x8000) >> 16;
       break;
      }

  /* Now call cgen's md_aply_fix.  */
  gas_cgen_md_apply_fix (fixP, valP, seg);
}

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static const CGEN_INSN* mep_cgen_assemble_cop_insn ( CGEN_CPU_DESC  cd,
const char *  str,
CGEN_FIELDS *  fields,
CGEN_INSN_BYTES_PTR  buf,
const struct cgen_insn pinsn 
) [static]

Definition at line 469 of file tc-mep.c.

{
  const char *start;
  CGEN_INSN_LIST *ilist;
  const char *errmsg = NULL;

  /* The instructions are stored in hashed lists. */
  ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, 
                            CGEN_INSN_MNEMONIC (pinsn));

  start = str;
  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
    {
      const CGEN_INSN *insn = ilist->insn;
      if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), 
                CGEN_INSN_MNEMONIC (pinsn)) == 0
         && MEP_INSN_COP_P (ilist->insn)
         && mep_cgen_insn_supported (cd, insn))
       {
         str = start;

         /* skip this insn if str doesn't look right lexically */
         if (CGEN_INSN_RX (insn) != NULL &&
             regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
           continue;

         /* Allow parse/insert handlers to obtain length of insn.  */
         CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);

         errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
         if (errmsg != NULL)
           continue;
         
         errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
                                         (bfd_vma) 0);
         if (errmsg != NULL)
           continue;

         return insn;
       }
    }
  return pinsn;
}

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fixS* mep_cgen_record_fixup_exp ( fragS *  frag,
int  where,
const CGEN_INSN *  insn,
int  length,
const CGEN_OPERAND operand,
int  opinfo,
expressionS exp 
)

Definition at line 1553 of file tc-mep.c.

{
  fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
                                      operand, opinfo, exp);
  return fixP;
}

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static void mep_check_for_disabled_registers ( mep_insn insn) [static]

Definition at line 328 of file tc-mep.c.

{
  static int initted = 0;
  static int has_mul_div = 0;
  static int has_cop = 0;
  static int has_debug = 0;
  unsigned int b, r;

  if (allow_disabled_registers)
    return;

#if !CGEN_INT_INSN_P
  if (target_big_endian)
    b = insn->buffer[0] * 256 + insn->buffer[1];
  else
    b = insn->buffer[1] * 256 + insn->buffer[0];
#else
  b = insn->buffer[0];
#endif

  if ((b & 0xfffff00e) == 0x7008 /* stc */
      || (b & 0xfffff00e) == 0x700a /* ldc */)
    {
      if (!initted)
       {
         initted = 1;
         if ((MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_MUL_INSN))
             || (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)))
           has_mul_div = 1;
         if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN))
           has_debug = 1;
         if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_CP_INSN))
           has_cop = 1;
       }

      r = ((b & 0x00f0) >> 4) | ((b & 0x0001) << 4);
      switch (r)
       {
       case 7: /* $hi */
       case 8: /* $lo */
         if (!has_mul_div)
           as_bad ("$hi and $lo are disabled when MUL and DIV are off");
         break;
       case 12: /* $mb0 */
       case 13: /* $me0 */
       case 14: /* $mb1 */
       case 15: /* $me1 */
         if (!has_cop)
           as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
         break;
       case 24: /* $dbg */
       case 25: /* $depc */
         if (!has_debug)
           as_bad ("$dbg and $depc are disabled when DEBUG is off");
         break;
       }
    }
}

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static void mep_check_parallel32_scheduling ( void  ) [static]

Definition at line 532 of file tc-mep.c.

{
  int insn0iscopro, insn1iscopro, insn0length, insn1length;

  /* More than two instructions means that either someone is referring to
     an internally parallel core or an internally parallel coprocessor,
     neither of which are supported at this time.  */
  if ( num_insns_saved > 2 )
    as_fatal("Internally paralled cores and coprocessors not supported.");

  /* If there are no insns saved, that's ok.  Just return.  This will
     happen when mep_process_saved_insns is called when the end of the
     source file is reached and there are no insns left to be processed.  */
  if (num_insns_saved == 0)
    return;

  /* Check some of the attributes of the first insn.  */
  insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
  insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);

  if (num_insns_saved == 2)
    {
      /* Check some of the attributes of the first insn.  */
      insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
      insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);

      if ((insn0iscopro && !insn1iscopro)
          || (insn1iscopro && !insn0iscopro))
       {
          /* We have one core and one copro insn.  If their sizes
             add up to 32, then the combination is valid.  */
         if (insn0length + insn1length == 32)
           return;
          else
           as_bad ("core and copro insn lengths must total 32 bits.");
       }
      else
        as_bad ("vliw group must consist of 1 core and 1 copro insn."); 
    }
  else
    {
      /* If we arrive here, we have one saved instruction.  There are a
        number of possible cases:

        1.  The instruction is a 32 bit core or coprocessor insn and
             can be executed by itself.  Valid.

         2.  The instrucion is a core instruction for which a cop nop
             exists.  In this case, insert the cop nop into the saved
             insn array after the core insn and return.  Valid.

         3.  The instruction is a coprocessor insn for which a core nop
             exists.  In this case, move the coprocessor insn to the
             second element of the array and put the nop in the first
            element then return.  Valid.

         4. The instruction is a core or coprocessor instruction for
            which there is no matching coprocessor or core nop to use
           to form a valid vliw insn combination.  In this case, we
           we have to abort.  */

      if (insn0length > 32)
       as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");

      if (insn0length == 32)
       return;

      /* Insn is smaller than datapath.  If there are no matching
         nops for this insn, then terminate assembly.  */
      if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
                                CGEN_INSN_VLIW32_NO_MATCHING_NOP))
       as_fatal ("No valid nop.");

      /* At this point we know that we have a single 16-bit insn that has 
        a matching nop.  We have to assemble it and put it into the saved 
         insn and fixup chain arrays. */

      if (insn0iscopro)
       {
          char *errmsg;
          mep_insn insn;
         
          /* Move the insn and it's fixups to the second element of the
             saved insns arrary and insert a 16 bit core nope into the
             first element. */
             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
                                                 &insn.fields, insn.buffer,
                                                 &errmsg);
             if (!insn.insn)
               {
                 as_bad ("%s", errmsg);
                 return;
               }

             /* Move the insn in element 0 to element 1 and insert the
                 nop into element 0.  Move the fixups in element 0 to
                 element 1 and save the current fixups to element 0.  
                 Really there aren't any fixups at this point because we're
                 inserting a nop but we might as well be general so that
                 if there's ever a need to insert a general insn, we'll
                 have an example. */
              saved_insns[1] = saved_insns[0];
              saved_insns[0] = insn;
              num_insns_saved++;
              gas_cgen_swap_fixups (0);
              gas_cgen_save_fixups (1);
       }
      else
       {
          char * errmsg;
          mep_insn insn;
         int insn_num = saved_insns[0].insn->base->num;

         /* Use 32 bit branches and skip the nop.  */
         if (insn_num == MEP_INSN_BSR12
             || insn_num == MEP_INSN_BEQZ
             || insn_num == MEP_INSN_BNEZ)
           return;

          /* Insert a 16-bit coprocessor nop.  Note that at the time */
          /* this was done, no 16-bit coprocessor nop was defined.   */
         insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
                                         &insn.fields, insn.buffer,
                                         &errmsg);
          if (!insn.insn)
            {
              as_bad ("%s", errmsg);
              return;
            }

          /* Now put the insn and fixups into the arrays.  */
          mep_save_insn (insn);
       }
    }
}

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static void mep_check_parallel64_scheduling ( void  ) [static]

Definition at line 669 of file tc-mep.c.

{
  int insn0iscopro, insn1iscopro, insn0length, insn1length;

  /* More than two instructions means that someone is referring to an
     internally parallel core or an internally parallel coprocessor.  */
  /* These are not currently supported.  */
  if (num_insns_saved > 2)
    as_fatal ("Internally parallel cores of coprocessors not supported.");

  /* If there are no insns saved, that's ok.  Just return.  This will
     happen when mep_process_saved_insns is called when the end of the
     source file is reached and there are no insns left to be processed.  */
  if (num_insns_saved == 0)
    return;

  /* Check some of the attributes of the first insn.  */
  insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
  insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);

  if (num_insns_saved == 2)
    {
      /* Check some of the attributes of the first insn. */
      insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
      insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);

      if ((insn0iscopro && !insn1iscopro)
         || (insn1iscopro && !insn0iscopro))
       {
         /* We have one core and one copro insn.  If their sizes
            add up to 64, then the combination is valid.  */
         if (insn0length + insn1length == 64)
            return;
         else
            as_bad ("core and copro insn lengths must total 64 bits.");
       }
      else
        as_bad ("vliw group must consist of 1 core and 1 copro insn.");
    }
  else
    {
      /* If we arrive here, we have one saved instruction.  There are a
        number of possible cases:

         1.  The instruction is a 64 bit coprocessor insn and can be
             executed by itself.  Valid.

         2.  The instrucion is a core instruction for which a cop nop
             exists.  In this case, insert the cop nop into the saved
             insn array after the core insn and return.  Valid.

         3.  The instruction is a coprocessor insn for which a core nop
             exists.  In this case, move the coprocessor insn to the
             second element of the array and put the nop in the first
             element then return.  Valid.

         4.  The instruction is a core or coprocessor instruction for
             which there is no matching coprocessor or core nop to use
             to form a valid vliw insn combination.  In this case, we
            we have to abort.  */

      /* If the insn is 64 bits long, it can run alone.  The size check
        is done indepependantly of whether the insn is core or copro
        in case 64 bit coprocessor insns are added later.  */
      if (insn0length == 64)
        return;

      /* Insn is smaller than datapath.  If there are no matching
        nops for this insn, then terminate assembly.  */
      if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
                            CGEN_INSN_VLIW64_NO_MATCHING_NOP))
       as_fatal ("No valid nop.");

      if (insn0iscopro)
       {
         char *errmsg;
         mep_insn insn;
          int i;

          /* Initialize the insn buffer.  */
          for (i = 0; i < 64; i++)
             insn.buffer[i] = '\0';

         /* We have a coprocessor insn.  At this point in time there
            are is 32-bit core nop.  There is only a 16-bit core
            nop.  The idea is to allow for a relatively arbitrary
            coprocessor to be specified.  We aren't looking at
            trying to cover future changes in the core at this time
            since it is assumed that the core will remain fairly
            static.  If there ever are 32 or 48 bit core nops added,
            they will require entries below.  */

         if (insn0length == 48)
           {
             /* Move the insn and fixups to the second element of the
               arrays then assemble and insert a 16 bit core nop.  */
             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
                                            & insn.fields, insn.buffer,
                                            & errmsg);
           }
          else
            {
              /* If this is reached, then we have a single coprocessor
                 insn that is not 48 bits long, but for which the assembler
                 thinks there is a matching core nop.  If a 32-bit core
                 nop has been added, then make the necessary changes and
                 handle its assembly and insertion here.  Otherwise,
                 go figure out why either:
              
                 1. The assembler thinks that there is a 32-bit core nop
                    to match a 32-bit coprocessor insn, or
                 2. The assembler thinks that there is a 48-bit core nop
                    to match a 16-bit coprocessor insn.  */

              as_fatal ("Assembler expects a non-existent core nop.");
            }

        if (!insn.insn)
          {
            as_bad ("%s", errmsg);
            return;
          }

         /* Move the insn in element 0 to element 1 and insert the
            nop into element 0.  Move the fixups in element 0 to
            element 1 and save the current fixups to element 0. 
           Really there aren't any fixups at this point because we're
           inserting a nop but we might as well be general so that
           if there's ever a need to insert a general insn, we'll
           have an example. */

         saved_insns[1] = saved_insns[0];
         saved_insns[0] = insn;
         num_insns_saved++;
         gas_cgen_swap_fixups(0);
         gas_cgen_save_fixups(1);

       }
      else
       {
         char * errmsg;
         mep_insn insn;
          int i;

          /* Initialize the insn buffer */
          for (i = 0; i < 64; i++)
             insn.buffer[i] = '\0';

         /* We have a core insn.  We have to handle all possible nop
            lengths.  If a coprocessor doesn't have a nop of a certain
            length but there exists core insns that when combined with
             a nop of that length would fill the datapath, those core
             insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
             attribute.  That will ensure that when used in a way that
             requires a nop to be inserted, assembly will terminate
             before reaching this section of code.  This guarantees
             that cases below which would result in the attempted
             insertion of nop that doesn't exist will never be entered.  */
         if (insn0length == 16)
           {
             /* Insert 48 bit coprocessor nop.          */
             /* Assemble it and put it into the arrays. */
             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop48",
                                            &insn.fields, insn.buffer,
                                            &errmsg);
           }
         else if (insn0length == 32)
           {
             /* Insert 32 bit coprocessor nop. */
             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop32",
                                            &insn.fields, insn.buffer,
                                            &errmsg);
           }
         else if (insn0length == 48)
           {
             /* Insert 16 bit coprocessor nop. */
             insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
                                            &insn.fields, insn.buffer,
                                            &errmsg);
           }
         else
           /* Core insn has an invalid length.  Something has gone wrong. */
           as_fatal ("Core insn has invalid length!  Something is wrong!");

         if (!insn.insn)
           {
             as_bad ("%s", errmsg);
             return;
           }

         /* Now put the insn and fixups into the arrays.  */
         mep_save_insn (insn);
       }
    }
}

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static void mep_check_parallel_scheduling ( void  ) [static]

Definition at line 871 of file tc-mep.c.

{
  /* This is where we will eventually read the config information
     and choose which scheduling checking function to call.  */   
  if (MEP_VLIW64)
    mep_check_parallel64_scheduling ();
  else
    mep_check_parallel32_scheduling ();
}

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void mep_cleanup ( void  )

Definition at line 1867 of file tc-mep.c.

{
  /* Take care of any insns left to be parallelized when the file ends.
     This is mainly here to handle the case where the file ends with an
     insn preceeded by a + or the file ends unexpectedly.  */
  if (mode == VLIW)
    mep_process_saved_insns ();
}

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flagword mep_elf_section_flags ( flagword  flags,
int  attr,
int type  ATTRIBUTE_UNUSED 
)

Definition at line 1777 of file tc-mep.c.

{
  if (attr & SHF_MEP_VLIW)
    flags |= SEC_MEP_VLIW;
  return flags;
}
int mep_elf_section_letter ( int  letter,
char **  ptrmsg 
)

Definition at line 1767 of file tc-mep.c.

{
  if (letter == 'v')
    return SHF_MEP_VLIW;

  *ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string");
  return 0;
}
bfd_boolean mep_fix_adjustable ( fixS *  fixP)

Definition at line 1733 of file tc-mep.c.

{
  bfd_reloc_code_real_type reloc_type;

  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
    {
      const CGEN_INSN *insn = NULL;
      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
      const CGEN_OPERAND *operand
       = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
      reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
    }
  else
    reloc_type = fixP->fx_r_type;

  if (fixP->fx_addsy == NULL)
    return 1;

  /* Prevent all adjustments to global symbols. */
  if (S_IS_EXTERNAL (fixP->fx_addsy))
    return 0;

  if (S_IS_WEAK (fixP->fx_addsy))
    return 0;

  /* We need the symbol name for the VTABLE entries */
  if (reloc_type == BFD_RELOC_VTABLE_INHERIT
      || reloc_type == BFD_RELOC_VTABLE_ENTRY)
    return 0;

  return 1;
}

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Definition at line 1877 of file tc-mep.c.

{
  if (mode == VLIW)
    {
      mep_process_saved_insns ();
      pluspresent = 0;
    }

  return 1; 
}

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int mep_force_relocation ( fixS *  fixp)

Definition at line 1654 of file tc-mep.c.

{
  if (   fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
        || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
    return 1;

  /* Allow branches to global symbols to be resolved at assembly time.
     This is consistent with way relaxable branches are handled, since
     branches to both global and local symbols are relaxed.  It also
     corresponds to the assumptions made in md_pcrel_from_section.  */
  return S_FORCE_RELOC (fixp->fx_addsy, !fixp->fx_pcrel);
}

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void mep_frob_file ( void  )

Definition at line 1576 of file tc-mep.c.

{
  struct mep_hi_fixup * l;

  for (l = mep_hi_fixup_list; l != NULL; l = l->next)
    {
      segment_info_type * seginfo;
      int pass;

      assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
             || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);

      /* Check quickly whether the next fixup happens to be a matching low.  */
      if (l->fixp->fx_next != NULL
         && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
         && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
         && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
       continue;

      /* Look through the fixups for this segment for a matching
         `low'.  When we find one, move the high just in front of it.
         We do this in two passes.  In the first pass, we try to find
         a unique `low'.  In the second pass, we permit multiple
         high's relocs for a single `low'.  */
      seginfo = seg_info (l->seg);
      for (pass = 0; pass < 2; pass++)
       {
         fixS * f;
         fixS * prev;

         prev = NULL;
         for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
           {
             /* Check whether this is a `low' fixup which matches l->fixp.  */
             if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
                && f->fx_addsy == l->fixp->fx_addsy
                && f->fx_offset == l->fixp->fx_offset
                && (pass == 1
                    || prev == NULL
                    || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
                    || prev->fx_addsy != f->fx_addsy
                    || prev->fx_offset !=  f->fx_offset))
              {
                fixS ** pf;

                /* Move l->fixp before f.  */
                for (pf = &seginfo->fix_root;
                     * pf != l->fixp;
                     pf = & (* pf)->fx_next)
                  assert (* pf != NULL);

                * pf = l->fixp->fx_next;

                l->fixp->fx_next = f;
                if (prev == NULL)
                  seginfo->fix_root = l->fixp;
                else
                  prev->fx_next = l->fixp;

                break;
              }

             prev = f;
           }

         if (f != NULL)
           break;

         if (pass == 1)
           as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
                        _("Unmatched high relocation"));
       }
    }
}

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static int mep_machine ( void  ) [static]

Definition at line 388 of file tc-mep.c.

{
  switch (MEP_CPU)
    {
    default: break;
    case EF_MEP_CPU_C2: return bfd_mach_mep;
    case EF_MEP_CPU_C3: return bfd_mach_mep;
    case EF_MEP_CPU_C4: return bfd_mach_mep;
    case EF_MEP_CPU_H1: return bfd_mach_mep_h1;
    }

  return bfd_mach_mep;
}

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static void mep_noregerr ( int  ) [static]
static void mep_noregerr ( int i  ATTRIBUTE_UNUSED) [static]

Definition at line 1840 of file tc-mep.c.

static const char* mep_parse_operand ( CGEN_CPU_DESC  cd,
enum cgen_parse_operand_type  want,
const char **  strP,
int  opindex,
int  opinfo,
enum cgen_parse_operand_result resultP,
bfd_vma valueP 
) [static]

Definition at line 408 of file tc-mep.c.

{
  if (want == CGEN_PARSE_OPERAND_INTEGER || want == CGEN_PARSE_OPERAND_ADDRESS)
    {
      const char *next;

      next = *strP;
      while (*next == '(')
       next++;
      if (*next == '$')
       return "Not a valid literal";
    }
  return gas_cgen_parse_operand (cd, want, strP, opindex, opinfo,
                             resultP, valueP);
}

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void mep_prepare_relax_scan ( fragS *  fragP,
offsetT aim,
relax_substateT  this_state 
)

Definition at line 1179 of file tc-mep.c.

{
  symbolS *symbolP = fragP->fr_symbol;
  if (symbolP && !S_IS_DEFINED (symbolP))
    *aim = 0;
  /* Adjust for MeP pcrel not being relative to the next opcode.  */
  *aim += 2 + md_relax_table[this_state].rlx_length;
}

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static void mep_process_saved_insns ( void  ) [static]

Definition at line 882 of file tc-mep.c.

{
  int i;

  gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);

  /* We have to check for valid scheduling here. */
  mep_check_parallel_scheduling ();

  /* If the last call didn't cause assembly to terminate, we have
     a valid vliw insn/insn pair saved. Restore this instructions'
     fixups and process the insns. */
  for (i = 0;i<num_insns_saved;i++)
    {
      gas_cgen_restore_fixups (i);
      gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
                         CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
                         1, NULL);
    }
  gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);

  /* Clear the fixups and reset the number insn saved to 0. */
  gas_cgen_initialize_saved_fixups_array ();
  num_insns_saved = 0;
  listing_prev_line ();
}

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static void mep_s_vtext ( int  ) [static]
static void mep_s_vtext ( int ignore  ATTRIBUTE_UNUSED) [static]

Definition at line 1806 of file tc-mep.c.

{
  int temp;

  /* Record previous_section and previous_subsection.  */
  obj_elf_section_change_hook ();

  temp = get_absolute_expression ();
  subseg_set (mep_vtext_section (), (subsegT) temp);
  demand_empty_rest_of_line ();
}

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static void mep_save_insn ( mep_insn  insn) [static]

Definition at line 518 of file tc-mep.c.

{
  /* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
  if (num_insns_saved < 0 || num_insns_saved >= MAX_SAVED_FIXUP_CHAINS)
    {
      as_fatal("index into saved_insns[] out of bounds.");
      return;
    }
  saved_insns[num_insns_saved] = insn;
  gas_cgen_save_fixups(num_insns_saved);
  num_insns_saved++;
}

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static void mep_switch_to_core_mode ( int  ) [static]
static void mep_switch_to_core_mode ( int dummy  ATTRIBUTE_UNUSED) [static]

Definition at line 1819 of file tc-mep.c.

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static void mep_switch_to_vliw_mode ( int  ) [static]
static void mep_switch_to_vliw_mode ( int dummy  ATTRIBUTE_UNUSED) [static]

Definition at line 1827 of file tc-mep.c.

{
  if (! MEP_VLIW)
    as_bad (_(".vliw unavailable when VLIW is disabled."));
  mode = VLIW;
  /* Switch into .vtext here too. */
  /* mep_s_vtext(); */
}

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Definition at line 1854 of file tc-mep.c.

{
  switch (ch)
    {
    case '+':
      pluspresent = 1;
      return 1; /* '+' indicates an instruction to be parallelized. */
    default:
      return 0; /* If it's not a '+', the line can't be parsed. */
    }
}
static segT mep_vtext_section ( void  ) [static]

Definition at line 1788 of file tc-mep.c.

{
  static segT vtext_section;

  if (! vtext_section)
    {
      flagword applicable = bfd_applicable_section_flags (stdoutput);
      vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
      bfd_set_section_flags (stdoutput, vtext_section,
                          applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
                                      | SEC_CODE | SEC_READONLY
                                      | SEC_MEP_VLIW));
    }

  return vtext_section;
}

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static int target_address_for ( fragS *  frag) [static]

Definition at line 1265 of file tc-mep.c.

{
  int rv = frag->fr_offset;
  symbolS *sym = frag->fr_symbol;

  if (sym)
    rv += S_GET_VALUE (sym);

  return rv;
}

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Variable Documentation

Definition at line 57 of file tc-mep.c.

const char comment_chars[] = "#"

Definition at line 66 of file tc-mep.c.

const char EXP_CHARS[] = "eE"

Definition at line 69 of file tc-mep.c.

const char FLT_CHARS[] = "dD"

Definition at line 70 of file tc-mep.c.

int library_flag = 0 [static]

Definition at line 58 of file tc-mep.c.

const char line_comment_chars[] = ";#"

Definition at line 67 of file tc-mep.c.

Definition at line 68 of file tc-mep.c.

size_t md_longopts_size = sizeof (md_longopts)

Definition at line 167 of file tc-mep.c.

const pseudo_typeS md_pseudo_table[]
Initial value:
{
  { "word",   cons,                          4 },
  { "file",   (void (*) (int)) dwarf2_directive_file,          0 },
  { "loc",    dwarf2_directive_loc,       0 },
  { "vliw",   mep_switch_to_vliw_mode,    0 },
  { "core",   mep_switch_to_core_mode,    0 },
  { "vtext",  mep_s_vtext,                0 },
  { "noregerr",      mep_noregerr,               0 },
  { NULL,     NULL,                       0 }
}

Definition at line 78 of file tc-mep.c.

const relax_typeS md_relax_table[]

Definition at line 1084 of file tc-mep.c.

const char* md_shortopts = ""

Definition at line 169 of file tc-mep.c.

Definition at line 109 of file tc-mep.c.

int mode = CORE [static]

Definition at line 55 of file tc-mep.c.

int num_insns_saved = 0 [static]

Definition at line 64 of file tc-mep.c.

int optbits = 0 [static]

Definition at line 170 of file tc-mep.c.

int optbitset = 0 [static]

Definition at line 171 of file tc-mep.c.

int pluspresent = 0 [static]

Definition at line 56 of file tc-mep.c.

Definition at line 63 of file tc-mep.c.

struct { ... } subtype_mappings[] [static]