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cell-binutils  2.17cvs20070401
tc-m68k.c
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00001 /* tc-m68k.c -- Assemble for the m68k family
00002    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
00003    2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with GAS; see the file COPYING.  If not, write to the Free
00019    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00020    02110-1301, USA.  */
00021 
00022 #include "as.h"
00023 #include "safe-ctype.h"
00024 #include "obstack.h"
00025 #include "subsegs.h"
00026 #include "dwarf2dbg.h"
00027 #include "dw2gencfi.h"
00028 
00029 #include "opcode/m68k.h"
00030 #include "m68k-parse.h"
00031 
00032 #if defined (OBJ_ELF)
00033 #include "elf/m68k.h"
00034 #endif
00035 
00036 #ifdef M68KCOFF
00037 #include "obj-coff.h"
00038 #endif
00039 
00040 /* This string holds the chars that always start a comment.  If the
00041    pre-processor is disabled, these aren't very useful.  The macro
00042    tc_comment_chars points to this.  We use this, rather than the
00043    usual comment_chars, so that the --bitwise-or option will work.  */
00044 #if defined (TE_SVR4) || defined (TE_DELTA)
00045 const char *m68k_comment_chars = "|#";
00046 #else
00047 const char *m68k_comment_chars = "|";
00048 #endif
00049 
00050 /* This array holds the chars that only start a comment at the beginning of
00051    a line.  If the line seems to have the form '# 123 filename'
00052    .line and .file directives will appear in the pre-processed output */
00053 /* Note that input_file.c hand checks for '#' at the beginning of the
00054    first line of the input file.  This is because the compiler outputs
00055    #NO_APP at the beginning of its output.  */
00056 /* Also note that comments like this one will always work.  */
00057 const char line_comment_chars[] = "#*";
00058 
00059 const char line_separator_chars[] = ";";
00060 
00061 /* Chars that can be used to separate mant from exp in floating point nums.  */
00062 const char EXP_CHARS[] = "eE";
00063 
00064 /* Chars that mean this number is a floating point constant, as
00065    in "0f12.456" or "0d1.2345e12".  */
00066 
00067 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
00068 
00069 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
00070    changed in read.c .  Ideally it shouldn't have to know about it at all,
00071    but nothing is ideal around here.  */
00072 
00073 /* Are we trying to generate PIC code?  If so, absolute references
00074    ought to be made into linkage table references or pc-relative
00075    references.  Not implemented.  For ELF there are other means
00076    to denote pic relocations.  */
00077 int flag_want_pic;
00078 
00079 static int flag_short_refs; /* -l option.  */
00080 static int flag_long_jumps; /* -S option.  */
00081 static int flag_keep_pcrel; /* --pcrel option.  */
00082 
00083 #ifdef REGISTER_PREFIX_OPTIONAL
00084 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
00085 #else
00086 int flag_reg_prefix_optional;
00087 #endif
00088 
00089 /* Whether --register-prefix-optional was used on the command line.  */
00090 static int reg_prefix_optional_seen;
00091 
00092 /* The floating point coprocessor to use by default.  */
00093 static enum m68k_register m68k_float_copnum = COP1;
00094 
00095 /* If this is non-zero, then references to number(%pc) will be taken
00096    to refer to number, rather than to %pc + number.  */
00097 static int m68k_abspcadd;
00098 
00099 /* If this is non-zero, then the quick forms of the move, add, and sub
00100    instructions are used when possible.  */
00101 static int m68k_quick = 1;
00102 
00103 /* If this is non-zero, then if the size is not specified for a base
00104    or outer displacement, the assembler assumes that the size should
00105    be 32 bits.  */
00106 static int m68k_rel32 = 1;
00107 
00108 /* This is non-zero if m68k_rel32 was set from the command line.  */
00109 static int m68k_rel32_from_cmdline;
00110 
00111 /* The default width to use for an index register when using a base
00112    displacement.  */
00113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
00114 
00115 /* We want to warn if any text labels are misaligned.  In order to get
00116    the right line number, we need to record the line number for each
00117    label.  */
00118 struct label_line
00119 {
00120   struct label_line *next;
00121   symbolS *label;
00122   char *file;
00123   unsigned int line;
00124   int text;
00125 };
00126 
00127 /* The list of labels.  */
00128 
00129 static struct label_line *labels;
00130 
00131 /* The current label.  */
00132 
00133 static struct label_line *current_label;
00134 
00135 /* Pointer to list holding the opcodes sorted by name.  */
00136 static struct m68k_opcode const ** m68k_sorted_opcodes;
00137 
00138 /* Its an arbitrary name:  This means I don't approve of it.
00139    See flames below.  */
00140 static struct obstack robyn;
00141 
00142 struct m68k_incant
00143   {
00144     const char *m_operands;
00145     unsigned long m_opcode;
00146     short m_opnum;
00147     short m_codenum;
00148     int m_arch;
00149     struct m68k_incant *m_next;
00150   };
00151 
00152 #define getone(x)    ((((x)->m_opcode)>>16)&0xffff)
00153 #define gettwo(x)    (((x)->m_opcode)&0xffff)
00154 
00155 static const enum m68k_register m68000_ctrl[] = { 0 };
00156 static const enum m68k_register m68010_ctrl[] = {
00157   SFC, DFC, USP, VBR,
00158   0
00159 };
00160 static const enum m68k_register m68020_ctrl[] = {
00161   SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
00162   0
00163 };
00164 static const enum m68k_register m68040_ctrl[] = {
00165   SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
00166   USP, VBR, MSP, ISP, MMUSR, URP, SRP,
00167   0
00168 };
00169 static const enum m68k_register m68060_ctrl[] = {
00170   SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
00171   USP, VBR, URP, SRP, PCR,
00172   0
00173 };
00174 static const enum m68k_register mcf_ctrl[] = {
00175   CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
00176   RAMBAR0, RAMBAR1, MBAR,
00177   0
00178 };
00179 static const enum m68k_register mcf5208_ctrl[] = {
00180   CACR, ACR0, ACR1, VBR, RAMBAR1,
00181   0
00182 };
00183 static const enum m68k_register mcf5210a_ctrl[] = {
00184   VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
00185   0
00186 };
00187 static const enum m68k_register mcf5213_ctrl[] = {
00188   VBR, RAMBAR, FLASHBAR,
00189   0
00190 };
00191 static const enum m68k_register mcf5216_ctrl[] = {
00192   VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
00193   0
00194 };
00195 static const enum m68k_register mcf52235_ctrl[] = {
00196   VBR, FLASHBAR, RAMBAR,
00197   0
00198 };
00199 static const enum m68k_register mcf5225_ctrl[] = {
00200   VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR,
00201   0
00202 };
00203 static const enum m68k_register mcf5235_ctrl[] = {
00204   VBR, CACR, ACR0, ACR1, RAMBAR,
00205   0
00206 };
00207 static const enum m68k_register mcf5249_ctrl[] = {
00208   VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
00209   0
00210 };
00211 static const enum m68k_register mcf5250_ctrl[] = {
00212   VBR,
00213   0
00214 };
00215 static const enum m68k_register mcf5271_ctrl[] = {
00216   VBR, CACR, ACR0, ACR1, RAMBAR,
00217   0
00218 };
00219 static const enum m68k_register mcf5272_ctrl[] = {
00220   VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
00221   0
00222 };
00223 static const enum m68k_register mcf5275_ctrl[] = {
00224   VBR, CACR, ACR0, ACR1, RAMBAR,
00225   0
00226 };
00227 static const enum m68k_register mcf5282_ctrl[] = {
00228   VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
00229   0
00230 };
00231 static const enum m68k_register mcf5329_ctrl[] = {
00232   VBR, CACR, ACR0, ACR1, RAMBAR,
00233   0
00234 };
00235 static const enum m68k_register mcf5373_ctrl[] = {
00236   VBR, CACR, ACR0, ACR1, RAMBAR,
00237   0
00238 };
00239 static const enum m68k_register mcfv4e_ctrl[] = {
00240   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
00241   VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
00242   MBAR, SECMBAR,
00243   MPCR /* Multiprocessor Control register */,
00244   EDRAMBAR /* Embedded DRAM Base Address Register */,
00245   /* Permutation control registers.  */
00246   PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
00247   PCR3U0, PCR3L0, PCR3U1, PCR3L1,
00248   /* Legacy names */
00249   TC /* ASID */, BUSCR /* MMUBAR */,
00250   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
00251   MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
00252   ROMBAR /* ROMBAR0 */,
00253   0
00254 };
00255 static const enum m68k_register mcf5475_ctrl[] = {
00256   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
00257   VBR, PC, RAMBAR0, RAMBAR1, MBAR,
00258   /* Legacy names */
00259   TC /* ASID */, BUSCR /* MMUBAR */,
00260   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
00261   MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
00262   0
00263 };
00264 static const enum m68k_register mcf5485_ctrl[] = {
00265   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
00266   VBR, PC, RAMBAR0, RAMBAR1, MBAR,
00267   /* Legacy names */
00268   TC /* ASID */, BUSCR /* MMUBAR */,
00269   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
00270   MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
00271   0
00272 };
00273 static const enum m68k_register fido_ctrl[] = {
00274   SFC, DFC, USP, VBR, CAC, MBB,
00275   0
00276 };
00277 #define cpu32_ctrl m68010_ctrl
00278 
00279 static const enum m68k_register *control_regs;
00280 
00281 /* Internal form of a 68020 instruction.  */
00282 struct m68k_it
00283 {
00284   const char *error;
00285   const char *args;         /* List of opcode info.  */
00286   int numargs;
00287 
00288   int numo;                 /* Number of shorts in opcode.  */
00289   short opcode[11];
00290 
00291   struct m68k_op operands[6];
00292 
00293   int nexp;                 /* Number of exprs in use.  */
00294   struct m68k_exp exprs[4];
00295 
00296   int nfrag;                /* Number of frags we have to produce.  */
00297   struct
00298     {
00299       int fragoff;          /* Where in the current opcode the frag ends.  */
00300       symbolS *fadd;
00301       offsetT foff;
00302       int fragty;
00303     }
00304   fragb[4];
00305 
00306   int nrel;                 /* Num of reloc strucs in use.  */
00307   struct
00308     {
00309       int n;
00310       expressionS exp;
00311       char wid;
00312       char pcrel;
00313       /* In a pc relative address the difference between the address
00314         of the offset and the address that the offset is relative
00315         to.  This depends on the addressing mode.  Basically this
00316         is the value to put in the offset field to address the
00317         first byte of the offset, without regarding the special
00318         significance of some values (in the branch instruction, for
00319         example).  */
00320       int pcrel_fix;
00321 #ifdef OBJ_ELF
00322       /* Whether this expression needs special pic relocation, and if
00323         so, which.  */
00324       enum pic_relocation pic_reloc;
00325 #endif
00326     }
00327   reloc[5];                 /* Five is enough???  */
00328 };
00329 
00330 #define cpu_of_arch(x)             ((x) & (m68000up | mcfisa_a | fido_a))
00331 #define float_of_arch(x)    ((x) & mfloat)
00332 #define mmu_of_arch(x)             ((x) & mmmu)
00333 #define arch_coldfire_p(x)  ((x) & mcfisa_a)
00334 #define arch_coldfire_fpu(x)       ((x) & cfloat)
00335 
00336 /* Macros for determining if cpu supports a specific addressing mode.  */
00337 #define HAVE_LONG_BRANCH(x)     ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
00338 
00339 static struct m68k_it the_ins;     /* The instruction being assembled.  */
00340 
00341 #define op(ex)              ((ex)->exp.X_op)
00342 #define adds(ex)     ((ex)->exp.X_add_symbol)
00343 #define subs(ex)     ((ex)->exp.X_op_symbol)
00344 #define offs(ex)     ((ex)->exp.X_add_number)
00345 
00346 /* Macros for adding things to the m68k_it struct.  */
00347 #define addword(w)   (the_ins.opcode[the_ins.numo++] = (w))
00348 
00349 /* Like addword, but goes BEFORE general operands.  */
00350 
00351 static void
00352 insop (int w, const struct m68k_incant *opcode)
00353 {
00354   int z;
00355   for (z = the_ins.numo; z > opcode->m_codenum; --z)
00356     the_ins.opcode[z] = the_ins.opcode[z - 1];
00357   for (z = 0; z < the_ins.nrel; z++)
00358     the_ins.reloc[z].n += 2;
00359   for (z = 0; z < the_ins.nfrag; z++)
00360     the_ins.fragb[z].fragoff++;
00361   the_ins.opcode[opcode->m_codenum] = w;
00362   the_ins.numo++;
00363 }
00364 
00365 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
00366    Blecch.  */
00367 static void
00368 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
00369 {
00370   the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
00371                                ? the_ins.numo * 2 - 1
00372                                : (width == 'b'
00373                                   ? the_ins.numo * 2 + 1
00374                                   : the_ins.numo * 2));
00375   the_ins.reloc[the_ins.nrel].exp = exp->exp;
00376   the_ins.reloc[the_ins.nrel].wid = width;
00377   the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
00378 #ifdef OBJ_ELF
00379   the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
00380 #endif
00381   the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
00382 }
00383 
00384 /* Cause an extra frag to be generated here, inserting up to 10 bytes
00385    (that value is chosen in the frag_var call in md_assemble).  TYPE
00386    is the subtype of the frag to be generated; its primary type is
00387    rs_machine_dependent.
00388 
00389    The TYPE parameter is also used by md_convert_frag_1 and
00390    md_estimate_size_before_relax.  The appropriate type of fixup will
00391    be emitted by md_convert_frag_1.
00392 
00393    ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
00394 static void
00395 add_frag (symbolS *add, offsetT off, int type)
00396 {
00397   the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
00398   the_ins.fragb[the_ins.nfrag].fadd = add;
00399   the_ins.fragb[the_ins.nfrag].foff = off;
00400   the_ins.fragb[the_ins.nfrag++].fragty = type;
00401 }
00402 
00403 #define isvar(ex) \
00404   (op (ex) != O_constant && op (ex) != O_big)
00405 
00406 static char *crack_operand (char *str, struct m68k_op *opP);
00407 static int get_num (struct m68k_exp *exp, int ok);
00408 static int reverse_16_bits (int in);
00409 static int reverse_8_bits (int in);
00410 static void install_gen_operand (int mode, int val);
00411 static void install_operand (int mode, int val);
00412 static void s_bss (int);
00413 static void s_data1 (int);
00414 static void s_data2 (int);
00415 static void s_even (int);
00416 static void s_proc (int);
00417 static void s_chip (int);
00418 static void s_fopt (int);
00419 static void s_opt (int);
00420 static void s_reg (int);
00421 static void s_restore (int);
00422 static void s_save (int);
00423 static void s_mri_if (int);
00424 static void s_mri_else (int);
00425 static void s_mri_endi (int);
00426 static void s_mri_break (int);
00427 static void s_mri_next (int);
00428 static void s_mri_for (int);
00429 static void s_mri_endf (int);
00430 static void s_mri_repeat (int);
00431 static void s_mri_until (int);
00432 static void s_mri_while (int);
00433 static void s_mri_endw (int);
00434 static void s_m68k_cpu (int);
00435 static void s_m68k_arch (int);
00436 
00437 struct m68k_cpu
00438 {
00439   unsigned long arch;       /* Architecture features.  */
00440   const enum m68k_register *control_regs; /* Control regs on chip */
00441   const char *name;  /* Name */
00442   int alias;         /* Alias for a cannonical name.  If 1, then
00443                         succeeds canonical name, if -1 then
00444                         succeeds canonical name, if <-1 ||>1 this is a
00445                         deprecated name, and the next/previous name
00446                         should be used. */
00447 };
00448 
00449 /* We hold flags for features explicitly enabled and explicitly
00450    disabled.  */
00451 static int current_architecture;
00452 static int not_current_architecture;
00453 static const struct m68k_cpu *selected_arch;
00454 static const struct m68k_cpu *selected_cpu;
00455 static int initialized;
00456 
00457 /* Architecture models.  */
00458 static const struct m68k_cpu m68k_archs[] =
00459 {
00460   {m68000,                                m68000_ctrl, "68000", 0},
00461   {m68010,                                m68010_ctrl, "68010", 0},
00462   {m68020|m68881|m68851,                  m68020_ctrl, "68020", 0},
00463   {m68030|m68881|m68851,                  m68020_ctrl, "68030", 0},
00464   {m68040,                                m68040_ctrl, "68040", 0},
00465   {m68060,                                m68060_ctrl, "68060", 0},
00466   {cpu32|m68881,                          cpu32_ctrl, "cpu32", 0},
00467   {fido_a,                                fido_ctrl, "fidoa", 0},
00468   {mcfisa_a|mcfhwdiv,                            NULL, "isaa", 0},
00469   {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp,           NULL, "isaaplus", 0},
00470   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp,            NULL, "isab", 0},
00471   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp,     mcf_ctrl, "cfv4", 0},
00472   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
00473   {0,0,NULL, 0}
00474 };
00475 
00476 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
00477    for either.  */
00478 static const struct m68k_cpu m68k_extensions[] =
00479 {
00480   {m68851,                                NULL, "68851", -1},
00481   {m68881,                                NULL, "68881", -1},
00482   {m68881,                                NULL, "68882", -1},
00483   
00484   {cfloat|m68881,                         NULL, "float", 0},
00485   
00486   {mcfhwdiv,                              NULL, "div", 1},
00487   {mcfusp,                                NULL, "usp", 1},
00488   {mcfmac,                                NULL, "mac", 1},
00489   {mcfemac,                               NULL, "emac", 1},
00490    
00491   {0,NULL,NULL, 0}
00492 };
00493 
00494 /* Processor list */
00495 static const struct m68k_cpu m68k_cpus[] =
00496 {
00497   {m68000,                                m68000_ctrl, "68000", 0},
00498   {m68000,                                m68000_ctrl, "68ec000", 1},
00499   {m68000,                                m68000_ctrl, "68hc000", 1},
00500   {m68000,                                m68000_ctrl, "68hc001", 1},
00501   {m68000,                                m68000_ctrl, "68008", 1},
00502   {m68000,                                m68000_ctrl, "68302", 1},
00503   {m68000,                                m68000_ctrl, "68306", 1},
00504   {m68000,                                m68000_ctrl, "68307", 1},
00505   {m68000,                                m68000_ctrl, "68322", 1},
00506   {m68000,                                m68000_ctrl, "68356", 1},
00507   {m68010,                                m68010_ctrl, "68010", 0},
00508   {m68020|m68881|m68851,                  m68020_ctrl, "68020", 0},
00509   {m68020|m68881|m68851,                  m68020_ctrl, "68k", 1},
00510   {m68020|m68881|m68851,                  m68020_ctrl, "68ec020", 1},
00511   {m68030|m68881|m68851,                  m68020_ctrl, "68030", 0},
00512   {m68030|m68881|m68851,                  m68020_ctrl, "68ec030", 1},
00513   {m68040,                                m68040_ctrl, "68040", 0},
00514   {m68040,                                m68040_ctrl, "68ec040", 1},
00515   {m68060,                                m68060_ctrl, "68060", 0},
00516   {m68060,                                m68060_ctrl, "68ec060", 1},
00517   
00518   {cpu32|m68881,                          cpu32_ctrl, "cpu32",  0},
00519   {cpu32|m68881,                          cpu32_ctrl, "68330", 1},
00520   {cpu32|m68881,                          cpu32_ctrl, "68331", 1},
00521   {cpu32|m68881,                          cpu32_ctrl, "68332", 1},
00522   {cpu32|m68881,                          cpu32_ctrl, "68333", 1},
00523   {cpu32|m68881,                          cpu32_ctrl, "68334", 1},
00524   {cpu32|m68881,                          cpu32_ctrl, "68336", 1},
00525   {cpu32|m68881,                          cpu32_ctrl, "68340", 1},
00526   {cpu32|m68881,                          cpu32_ctrl, "68341", 1},
00527   {cpu32|m68881,                          cpu32_ctrl, "68349", 1},
00528   {cpu32|m68881,                          cpu32_ctrl, "68360", 1},
00529   
00530   {mcfisa_a,                              mcf_ctrl, "5200", 0},
00531   {mcfisa_a,                              mcf_ctrl, "5202", 1},
00532   {mcfisa_a,                              mcf_ctrl, "5204", 1},
00533   {mcfisa_a,                              mcf_ctrl, "5206", 1},
00534   
00535   {mcfisa_a|mcfhwdiv|mcfmac,                     mcf_ctrl, "5206e", 0},
00536   
00537   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5208_ctrl, "5207", -1},
00538   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5208_ctrl, "5208", 0},
00539   
00540   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,    mcf5210a_ctrl, "5210a", 0},
00541   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,    mcf5210a_ctrl, "5211a", 1},
00542   
00543   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,    mcf5213_ctrl, "5211", -1},
00544   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,    mcf5213_ctrl, "5212", -1},
00545   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,    mcf5213_ctrl, "5213", 0},
00546   
00547   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5216_ctrl, "5214", -1},
00548   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5216_ctrl, "5216", 0},
00549   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5216_ctrl, "521x", 2},
00550 
00551   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52230", -1},
00552   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52233", -1},
00553   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52234", -1},
00554   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52235", 0},
00555   
00556   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5224", -1},
00557   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5225", 0},
00558   
00559   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5235_ctrl, "5232", -1},
00560   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5235_ctrl, "5233", -1},
00561   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5235_ctrl, "5234", -1},
00562   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5235_ctrl, "5235", -1},
00563   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5235_ctrl, "523x", 0},
00564   
00565   {mcfisa_a|mcfhwdiv|mcfemac,                    mcf5249_ctrl, "5249", 0},
00566   {mcfisa_a|mcfhwdiv|mcfemac,                    mcf5250_ctrl, "5250", 0},
00567   
00568   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5271_ctrl, "5270", -1},
00569   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5271_ctrl, "5271", 0},
00570   
00571   {mcfisa_a|mcfhwdiv|mcfmac,                     mcf5272_ctrl, "5272", 0},
00572   
00573   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5275_ctrl, "5274", -1},
00574   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5275_ctrl, "5275", 0},
00575   
00576   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5282_ctrl, "5280", -1},
00577   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5282_ctrl, "5281", -1},
00578   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5282_ctrl, "5282", -1},
00579   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5282_ctrl, "528x", 0},
00580   
00581   {mcfisa_a|mcfhwdiv|mcfmac,                     mcf_ctrl, "5307", 0},
00582   
00583   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5329_ctrl, "5327", -1},
00584   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5329_ctrl, "5328", -1},
00585   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5329_ctrl, "5329", -1},
00586   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5329_ctrl, "532x", 0},
00587   
00588   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5373_ctrl, "5372", -1},
00589   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5373_ctrl, "5373", -1},
00590   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,   mcf5373_ctrl, "537x", 0},
00591   
00592   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac,            mcf_ctrl, "5407",0},
00593   
00594   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
00595   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
00596   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
00597   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
00598   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
00599   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
00600   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
00601   
00602   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
00603   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
00604   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
00605   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
00606   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
00607   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
00608   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
00609   
00610   {fido_a,                         fido_ctrl, "fidoa", 0},
00611   {fido_a,                         fido_ctrl, "fido", 1},
00612 
00613   {0,NULL,NULL, 0}
00614   };
00615 
00616 static const struct m68k_cpu *m68k_lookup_cpu
00617 (const char *, const struct m68k_cpu *, int, int *);
00618 static int m68k_set_arch (const char *, int, int);
00619 static int m68k_set_cpu (const char *, int, int);
00620 static int m68k_set_extension (const char *, int, int);
00621 static void m68k_init_arch (void);
00622 
00623 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
00624    architecture and we have a lot of relaxation modes.  */
00625 
00626 /* Macros used in the relaxation code.  */
00627 #define TAB(x,y)     (((x) << 2) + (y))
00628 #define TABTYPE(x)      ((x) >> 2)
00629 
00630 /* Relaxation states.  */
00631 #define BYTE         0
00632 #define SHORT        1
00633 #define LONG         2
00634 #define SZ_UNDEF     3
00635 
00636 /* Here are all the relaxation modes we support.  First we can relax ordinary
00637    branches.  On 68020 and higher and on CPU32 all branch instructions take
00638    three forms, so on these CPUs all branches always remain as such.  When we
00639    have to expand to the LONG form on a 68000, though, we substitute an
00640    absolute jump instead.  This is a direct replacement for unconditional
00641    branches and a branch over a jump for conditional branches.  However, if the
00642    user requires PIC and disables this with --pcrel, we can only relax between
00643    BYTE and SHORT forms, punting if that isn't enough.  This gives us four
00644    different relaxation modes for branches:  */
00645 
00646 #define BRANCHBWL    0      /* Branch byte, word, or long.  */
00647 #define BRABSJUNC    1      /* Absolute jump for LONG, unconditional.  */
00648 #define BRABSJCOND   2      /* Absolute jump for LONG, conditional.  */
00649 #define BRANCHBW     3      /* Branch byte or word.  */
00650 
00651 /* We also relax coprocessor branches and DBcc's.  All CPUs that support
00652    coprocessor branches support them in word and long forms, so we have only
00653    one relaxation mode for them.  DBcc's are word only on all CPUs.  We can
00654    relax them to the LONG form with a branch-around sequence.  This sequence
00655    can use a long branch (if available) or an absolute jump (if acceptable).
00656    This gives us two relaxation modes.  If long branches are not available and
00657    absolute jumps are not acceptable, we don't relax DBcc's.  */
00658 
00659 #define FBRANCH             4      /* Coprocessor branch.  */
00660 #define DBCCLBR             5      /* DBcc relaxable with a long branch.  */
00661 #define DBCCABSJ     6      /* DBcc relaxable with an absolute jump.  */
00662 
00663 /* That's all for instruction relaxation.  However, we also relax PC-relative
00664    operands.  Specifically, we have three operand relaxation modes.  On the
00665    68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
00666    on CPU32 they may be 16-bit or 32-bit.  For the latter we relax between the
00667    two.  Also PC+displacement+index operands in their simple form (with a non-
00668    suppressed index without memory indirection) are supported on all CPUs, but
00669    on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
00670    and on CPU32 we relax it to SHORT and LONG forms as well using the extended
00671    form of the PC+displacement+index operand.  Finally, some absolute operands
00672    can be relaxed down to 16-bit PC-relative.  */
00673 
00674 #define PCREL1632    7      /* 16-bit or 32-bit PC-relative.  */
00675 #define PCINDEX             8      /* PC + displacement + index. */
00676 #define ABSTOPCREL   9      /* Absolute relax down to 16-bit PC-relative.  */
00677 
00678 /* Note that calls to frag_var need to specify the maximum expansion
00679    needed; this is currently 10 bytes for DBCC.  */
00680 
00681 /* The fields are:
00682    How far Forward this mode will reach:
00683    How far Backward this mode will reach:
00684    How many bytes this mode will add to the size of the frag
00685    Which mode to go to if the offset won't fit in this one
00686 
00687    Please check tc-m68k.h:md_prepare_relax_scan if changing this table.  */
00688 relax_typeS md_relax_table[] =
00689 {
00690   {   127,   -128,  0, TAB (BRANCHBWL, SHORT) },
00691   { 32767, -32768,  2, TAB (BRANCHBWL, LONG) },
00692   {     0,    0,  4, 0 },
00693   {     1,    1,  0, 0 },
00694 
00695   {   127,   -128,  0, TAB (BRABSJUNC, SHORT) },
00696   { 32767, -32768,  2, TAB (BRABSJUNC, LONG) },
00697   {    0,     0,  4, 0 },
00698   {    1,     1,  0, 0 },
00699 
00700   {   127,   -128,  0, TAB (BRABSJCOND, SHORT) },
00701   { 32767, -32768,  2, TAB (BRABSJCOND, LONG) },
00702   {    0,     0,  6, 0 },
00703   {    1,     1,  0, 0 },
00704 
00705   {   127,   -128,  0, TAB (BRANCHBW, SHORT) },
00706   {    0,     0,  2, 0 },
00707   {    1,     1,  0, 0 },
00708   {    1,     1,  0, 0 },
00709 
00710   {    1,     1,  0, 0 },          /* FBRANCH doesn't come BYTE.  */
00711   { 32767, -32768,  2, TAB (FBRANCH, LONG) },
00712   {    0,     0,  4, 0 },
00713   {    1,     1,  0, 0 },
00714 
00715   {    1,     1,  0, 0 },          /* DBCC doesn't come BYTE.  */
00716   { 32767, -32768,  2, TAB (DBCCLBR, LONG) },
00717   {    0,     0, 10, 0 },
00718   {    1,     1,  0, 0 },
00719 
00720   {    1,     1,  0, 0 },          /* DBCC doesn't come BYTE.  */
00721   { 32767, -32768,  2, TAB (DBCCABSJ, LONG) },
00722   {    0,     0, 10, 0 },
00723   {    1,     1,  0, 0 },
00724 
00725   {    1,     1,  0, 0 },          /* PCREL1632 doesn't come BYTE.  */
00726   { 32767, -32768,  2, TAB (PCREL1632, LONG) },
00727   {    0,     0,  6, 0 },
00728   {    1,     1,  0, 0 },
00729 
00730   {   125,   -130,  0, TAB (PCINDEX, SHORT) },
00731   { 32765, -32770,  2, TAB (PCINDEX, LONG) },
00732   {    0,     0,  4, 0 },
00733   {    1,     1,  0, 0 },
00734 
00735   {    1,     1,  0, 0 },          /* ABSTOPCREL doesn't come BYTE.  */
00736   { 32767, -32768,  2, TAB (ABSTOPCREL, LONG) },
00737   {    0,     0,  4, 0 },
00738   {    1,     1,  0, 0 },
00739 };
00740 
00741 /* These are the machine dependent pseudo-ops.  These are included so
00742    the assembler can work on the output from the SUN C compiler, which
00743    generates these.  */
00744 
00745 /* This table describes all the machine specific pseudo-ops the assembler
00746    has to support.  The fields are:
00747    pseudo-op name without dot
00748    function to call to execute this pseudo-op
00749    Integer arg to pass to the function.  */
00750 const pseudo_typeS md_pseudo_table[] =
00751 {
00752   {"data1", s_data1, 0},
00753   {"data2", s_data2, 0},
00754   {"bss", s_bss, 0},
00755   {"even", s_even, 0},
00756   {"skip", s_space, 0},
00757   {"proc", s_proc, 0},
00758 #if defined (TE_SUN3) || defined (OBJ_ELF)
00759   {"align", s_align_bytes, 0},
00760 #endif
00761 #ifdef OBJ_ELF
00762   {"swbeg", s_ignore, 0},
00763 #endif
00764   {"extend", float_cons, 'x'},
00765   {"ldouble", float_cons, 'x'},
00766 
00767   {"arch", s_m68k_arch, 0},
00768   {"cpu", s_m68k_cpu, 0},
00769 
00770   /* The following pseudo-ops are supported for MRI compatibility.  */
00771   {"chip", s_chip, 0},
00772   {"comline", s_space, 1},
00773   {"fopt", s_fopt, 0},
00774   {"mask2", s_ignore, 0},
00775   {"opt", s_opt, 0},
00776   {"reg", s_reg, 0},
00777   {"restore", s_restore, 0},
00778   {"save", s_save, 0},
00779 
00780   {"if", s_mri_if, 0},
00781   {"if.b", s_mri_if, 'b'},
00782   {"if.w", s_mri_if, 'w'},
00783   {"if.l", s_mri_if, 'l'},
00784   {"else", s_mri_else, 0},
00785   {"else.s", s_mri_else, 's'},
00786   {"else.l", s_mri_else, 'l'},
00787   {"endi", s_mri_endi, 0},
00788   {"break", s_mri_break, 0},
00789   {"break.s", s_mri_break, 's'},
00790   {"break.l", s_mri_break, 'l'},
00791   {"next", s_mri_next, 0},
00792   {"next.s", s_mri_next, 's'},
00793   {"next.l", s_mri_next, 'l'},
00794   {"for", s_mri_for, 0},
00795   {"for.b", s_mri_for, 'b'},
00796   {"for.w", s_mri_for, 'w'},
00797   {"for.l", s_mri_for, 'l'},
00798   {"endf", s_mri_endf, 0},
00799   {"repeat", s_mri_repeat, 0},
00800   {"until", s_mri_until, 0},
00801   {"until.b", s_mri_until, 'b'},
00802   {"until.w", s_mri_until, 'w'},
00803   {"until.l", s_mri_until, 'l'},
00804   {"while", s_mri_while, 0},
00805   {"while.b", s_mri_while, 'b'},
00806   {"while.w", s_mri_while, 'w'},
00807   {"while.l", s_mri_while, 'l'},
00808   {"endw", s_mri_endw, 0},
00809 
00810   {0, 0, 0}
00811 };
00812 
00813 /* The mote pseudo ops are put into the opcode table, since they
00814    don't start with a . they look like opcodes to gas.  */
00815 
00816 const pseudo_typeS mote_pseudo_table[] =
00817 {
00818 
00819   {"dcl", cons, 4},
00820   {"dc", cons, 2},
00821   {"dcw", cons, 2},
00822   {"dcb", cons, 1},
00823 
00824   {"dsl", s_space, 4},
00825   {"ds", s_space, 2},
00826   {"dsw", s_space, 2},
00827   {"dsb", s_space, 1},
00828 
00829   {"xdef", s_globl, 0},
00830 #ifdef OBJ_ELF
00831   {"align", s_align_bytes, 0},
00832 #else
00833   {"align", s_align_ptwo, 0},
00834 #endif
00835 #ifdef M68KCOFF
00836   {"sect", obj_coff_section, 0},
00837   {"section", obj_coff_section, 0},
00838 #endif
00839   {0, 0, 0}
00840 };
00841 
00842 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
00843    gives identical results to a 32-bit host.  */
00844 #define TRUNC(X)     ((valueT) (X) & 0xffffffff)
00845 #define SEXT(X)             ((TRUNC (X) ^ 0x80000000) - 0x80000000)
00846 
00847 #define issbyte(x)   ((valueT) SEXT (x) + 0x80 < 0x100)
00848 #define isubyte(x)   ((valueT) TRUNC (x) < 0x100)
00849 #define issword(x)   ((valueT) SEXT (x) + 0x8000 < 0x10000)
00850 #define isuword(x)   ((valueT) TRUNC (x) < 0x10000)
00851 
00852 #define isbyte(x)    ((valueT) SEXT (x) + 0xff < 0x1ff)
00853 #define isword(x)    ((valueT) SEXT (x) + 0xffff < 0x1ffff)
00854 #define islong(x)    (1)
00855 
00856 static char notend_table[256];
00857 static char alt_notend_table[256];
00858 #define notend(s)                                       \
00859   (! (notend_table[(unsigned char) *s]                         \
00860       || (*s == ':'                                     \
00861          && alt_notend_table[(unsigned char) s[1]])))
00862 
00863 #ifdef OBJ_ELF
00864 
00865 /* Return zero if the reference to SYMBOL from within the same segment may
00866    be relaxed.  */
00867 
00868 /* On an ELF system, we can't relax an externally visible symbol,
00869    because it may be overridden by a shared library.  However, if
00870    TARGET_OS is "elf", then we presume that we are assembling for an
00871    embedded system, in which case we don't have to worry about shared
00872    libraries, and we can relax any external sym.  */
00873 
00874 #define relaxable_symbol(symbol) \
00875   (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
00876      || S_IS_WEAK (symbol)))
00877 
00878 /* Compute the relocation code for a fixup of SIZE bytes, using pc
00879    relative relocation if PCREL is non-zero.  PIC says whether a special
00880    pic relocation was requested.  */
00881 
00882 static bfd_reloc_code_real_type
00883 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
00884 {
00885   switch (pic)
00886     {
00887     case pic_got_pcrel:
00888       switch (size)
00889        {
00890        case 1:
00891          return BFD_RELOC_8_GOT_PCREL;
00892        case 2:
00893          return BFD_RELOC_16_GOT_PCREL;
00894        case 4:
00895          return BFD_RELOC_32_GOT_PCREL;
00896        }
00897       break;
00898 
00899     case pic_got_off:
00900       switch (size)
00901        {
00902        case 1:
00903          return BFD_RELOC_8_GOTOFF;
00904        case 2:
00905          return BFD_RELOC_16_GOTOFF;
00906        case 4:
00907          return BFD_RELOC_32_GOTOFF;
00908        }
00909       break;
00910 
00911     case pic_plt_pcrel:
00912       switch (size)
00913        {
00914        case 1:
00915          return BFD_RELOC_8_PLT_PCREL;
00916        case 2:
00917          return BFD_RELOC_16_PLT_PCREL;
00918        case 4:
00919          return BFD_RELOC_32_PLT_PCREL;
00920        }
00921       break;
00922 
00923     case pic_plt_off:
00924       switch (size)
00925        {
00926        case 1:
00927          return BFD_RELOC_8_PLTOFF;
00928        case 2:
00929          return BFD_RELOC_16_PLTOFF;
00930        case 4:
00931          return BFD_RELOC_32_PLTOFF;
00932        }
00933       break;
00934 
00935     case pic_none:
00936       if (pcrel)
00937        {
00938          switch (size)
00939            {
00940            case 1:
00941              return BFD_RELOC_8_PCREL;
00942            case 2:
00943              return BFD_RELOC_16_PCREL;
00944            case 4:
00945              return BFD_RELOC_32_PCREL;
00946            }
00947        }
00948       else
00949        {
00950          switch (size)
00951            {
00952            case 1:
00953              return BFD_RELOC_8;
00954            case 2:
00955              return BFD_RELOC_16;
00956            case 4:
00957              return BFD_RELOC_32;
00958            }
00959        }
00960     }
00961 
00962   if (pcrel)
00963     {
00964       if (pic == pic_none)
00965        as_bad (_("Can not do %d byte pc-relative relocation"), size);
00966       else
00967        as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
00968     }
00969   else
00970     {
00971       if (pic == pic_none)
00972        as_bad (_("Can not do %d byte relocation"), size);
00973       else
00974        as_bad (_("Can not do %d byte pic relocation"), size);
00975     }
00976 
00977   return BFD_RELOC_NONE;
00978 }
00979 
00980 /* Here we decide which fixups can be adjusted to make them relative
00981    to the beginning of the section instead of the symbol.  Basically
00982    we need to make sure that the dynamic relocations are done
00983    correctly, so in some cases we force the original symbol to be
00984    used.  */
00985 int
00986 tc_m68k_fix_adjustable (fixS *fixP)
00987 {
00988   /* Adjust_reloc_syms doesn't know about the GOT.  */
00989   switch (fixP->fx_r_type)
00990     {
00991     case BFD_RELOC_8_GOT_PCREL:
00992     case BFD_RELOC_16_GOT_PCREL:
00993     case BFD_RELOC_32_GOT_PCREL:
00994     case BFD_RELOC_8_GOTOFF:
00995     case BFD_RELOC_16_GOTOFF:
00996     case BFD_RELOC_32_GOTOFF:
00997     case BFD_RELOC_8_PLT_PCREL:
00998     case BFD_RELOC_16_PLT_PCREL:
00999     case BFD_RELOC_32_PLT_PCREL:
01000     case BFD_RELOC_8_PLTOFF:
01001     case BFD_RELOC_16_PLTOFF:
01002     case BFD_RELOC_32_PLTOFF:
01003       return 0;
01004 
01005     case BFD_RELOC_VTABLE_INHERIT:
01006     case BFD_RELOC_VTABLE_ENTRY:
01007       return 0;
01008 
01009     default:
01010       return 1;
01011     }
01012 }
01013 
01014 #else /* !OBJ_ELF */
01015 
01016 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
01017 
01018 #define relaxable_symbol(symbol) 1
01019 
01020 #endif /* OBJ_ELF */
01021 
01022 arelent *
01023 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
01024 {
01025   arelent *reloc;
01026   bfd_reloc_code_real_type code;
01027 
01028   /* If the tcbit is set, then this was a fixup of a negative value
01029      that was never resolved.  We do not have a reloc to handle this,
01030      so just return.  We assume that other code will have detected this
01031      situation and produced a helpful error message, so we just tell the
01032      user that the reloc cannot be produced.  */
01033   if (fixp->fx_tcbit)
01034     {
01035       if (fixp->fx_addsy)
01036        as_bad_where (fixp->fx_file, fixp->fx_line,
01037                     _("Unable to produce reloc against symbol '%s'"),
01038                     S_GET_NAME (fixp->fx_addsy));
01039       return NULL;
01040     }
01041 
01042   if (fixp->fx_r_type != BFD_RELOC_NONE)
01043     {
01044       code = fixp->fx_r_type;
01045 
01046       /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
01047          that fixup_segment converted a non-PC relative reloc into a
01048          PC relative reloc.  In such a case, we need to convert the
01049          reloc code.  */
01050       if (fixp->fx_pcrel)
01051        {
01052          switch (code)
01053            {
01054            case BFD_RELOC_8:
01055              code = BFD_RELOC_8_PCREL;
01056              break;
01057            case BFD_RELOC_16:
01058              code = BFD_RELOC_16_PCREL;
01059              break;
01060            case BFD_RELOC_32:
01061              code = BFD_RELOC_32_PCREL;
01062              break;
01063            case BFD_RELOC_8_PCREL:
01064            case BFD_RELOC_16_PCREL:
01065            case BFD_RELOC_32_PCREL:
01066            case BFD_RELOC_8_GOT_PCREL:
01067            case BFD_RELOC_16_GOT_PCREL:
01068            case BFD_RELOC_32_GOT_PCREL:
01069            case BFD_RELOC_8_GOTOFF:
01070            case BFD_RELOC_16_GOTOFF:
01071            case BFD_RELOC_32_GOTOFF:
01072            case BFD_RELOC_8_PLT_PCREL:
01073            case BFD_RELOC_16_PLT_PCREL:
01074            case BFD_RELOC_32_PLT_PCREL:
01075            case BFD_RELOC_8_PLTOFF:
01076            case BFD_RELOC_16_PLTOFF:
01077            case BFD_RELOC_32_PLTOFF:
01078              break;
01079            default:
01080              as_bad_where (fixp->fx_file, fixp->fx_line,
01081                          _("Cannot make %s relocation PC relative"),
01082                          bfd_get_reloc_code_name (code));
01083            }
01084        }
01085     }
01086   else
01087     {
01088 #define F(SZ,PCREL)         (((SZ) << 1) + (PCREL))
01089       switch (F (fixp->fx_size, fixp->fx_pcrel))
01090        {
01091 #define MAP(SZ,PCREL,TYPE)  case F(SZ,PCREL): code = (TYPE); break
01092          MAP (1, 0, BFD_RELOC_8);
01093          MAP (2, 0, BFD_RELOC_16);
01094          MAP (4, 0, BFD_RELOC_32);
01095          MAP (1, 1, BFD_RELOC_8_PCREL);
01096          MAP (2, 1, BFD_RELOC_16_PCREL);
01097          MAP (4, 1, BFD_RELOC_32_PCREL);
01098        default:
01099          abort ();
01100        }
01101     }
01102 #undef F
01103 #undef MAP
01104 
01105   reloc = (arelent *) xmalloc (sizeof (arelent));
01106   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
01107   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
01108   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
01109 #ifndef OBJ_ELF
01110   if (fixp->fx_pcrel)
01111     reloc->addend = fixp->fx_addnumber;
01112   else
01113     reloc->addend = 0;
01114 #else
01115   if (!fixp->fx_pcrel)
01116     reloc->addend = fixp->fx_addnumber;
01117   else
01118     reloc->addend = (section->vma
01119                    /* Explicit sign extension in case char is
01120                      unsigned.  */
01121                    + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
01122                    + fixp->fx_addnumber
01123                    + md_pcrel_from (fixp));
01124 #endif
01125 
01126   reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
01127   assert (reloc->howto != 0);
01128 
01129   return reloc;
01130 }
01131 
01132 /* Handle of the OPCODE hash table.  NULL means any use before
01133    m68k_ip_begin() will crash.  */
01134 static struct hash_control *op_hash;
01135 
01136 /* Assemble an m68k instruction.  */
01137 
01138 static void
01139 m68k_ip (char *instring)
01140 {
01141   register char *p;
01142   register struct m68k_op *opP;
01143   register const struct m68k_incant *opcode;
01144   register const char *s;
01145   register int tmpreg = 0, baseo = 0, outro = 0, nextword;
01146   char *pdot, *pdotmove;
01147   enum m68k_size siz1, siz2;
01148   char c;
01149   int losing;
01150   int opsfound;
01151   struct m68k_op operands_backup[6];
01152   LITTLENUM_TYPE words[6];
01153   LITTLENUM_TYPE *wordp;
01154   unsigned long ok_arch = 0;
01155 
01156   if (*instring == ' ')
01157     instring++;                    /* Skip leading whitespace.  */
01158 
01159   /* Scan up to end of operation-code, which MUST end in end-of-string
01160      or exactly 1 space.  */
01161   pdot = 0;
01162   for (p = instring; *p != '\0'; p++)
01163     {
01164       if (*p == ' ')
01165        break;
01166       if (*p == '.')
01167        pdot = p;
01168     }
01169 
01170   if (p == instring)
01171     {
01172       the_ins.error = _("No operator");
01173       return;
01174     }
01175 
01176   /* p now points to the end of the opcode name, probably whitespace.
01177      Make sure the name is null terminated by clobbering the
01178      whitespace, look it up in the hash table, then fix it back.
01179      Remove a dot, first, since the opcode tables have none.  */
01180   if (pdot != NULL)
01181     {
01182       for (pdotmove = pdot; pdotmove < p; pdotmove++)
01183        *pdotmove = pdotmove[1];
01184       p--;
01185     }
01186 
01187   c = *p;
01188   *p = '\0';
01189   opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
01190   *p = c;
01191 
01192   if (pdot != NULL)
01193     {
01194       for (pdotmove = p; pdotmove > pdot; pdotmove--)
01195        *pdotmove = pdotmove[-1];
01196       *pdot = '.';
01197       ++p;
01198     }
01199 
01200   if (opcode == NULL)
01201     {
01202       the_ins.error = _("Unknown operator");
01203       return;
01204     }
01205 
01206   /* Found a legitimate opcode, start matching operands.  */
01207   while (*p == ' ')
01208     ++p;
01209 
01210   if (opcode->m_operands == 0)
01211     {
01212       char *old = input_line_pointer;
01213       *old = '\n';
01214       input_line_pointer = p;
01215       /* Ahh - it's a motorola style psuedo op.  */
01216       mote_pseudo_table[opcode->m_opnum].poc_handler
01217        (mote_pseudo_table[opcode->m_opnum].poc_val);
01218       input_line_pointer = old;
01219       *old = 0;
01220 
01221       return;
01222     }
01223 
01224   if (flag_mri && opcode->m_opnum == 0)
01225     {
01226       /* In MRI mode, random garbage is allowed after an instruction
01227          which accepts no operands.  */
01228       the_ins.args = opcode->m_operands;
01229       the_ins.numargs = opcode->m_opnum;
01230       the_ins.numo = opcode->m_codenum;
01231       the_ins.opcode[0] = getone (opcode);
01232       the_ins.opcode[1] = gettwo (opcode);
01233       return;
01234     }
01235 
01236   for (opP = &the_ins.operands[0]; *p; opP++)
01237     {
01238       p = crack_operand (p, opP);
01239 
01240       if (opP->error)
01241        {
01242          the_ins.error = opP->error;
01243          return;
01244        }
01245     }
01246 
01247   opsfound = opP - &the_ins.operands[0];
01248 
01249   /* This ugly hack is to support the floating pt opcodes in their
01250      standard form.  Essentially, we fake a first enty of type COP#1 */
01251   if (opcode->m_operands[0] == 'I')
01252     {
01253       int n;
01254 
01255       for (n = opsfound; n > 0; --n)
01256        the_ins.operands[n] = the_ins.operands[n - 1];
01257 
01258       memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
01259       the_ins.operands[0].mode = CONTROL;
01260       the_ins.operands[0].reg = m68k_float_copnum;
01261       opsfound++;
01262     }
01263 
01264   /* We've got the operands.  Find an opcode that'll accept them.  */
01265   for (losing = 0;;)
01266     {
01267       /* If we didn't get the right number of ops, or we have no
01268         common model with this pattern then reject this pattern.  */
01269 
01270       ok_arch |= opcode->m_arch;
01271       if (opsfound != opcode->m_opnum
01272          || ((opcode->m_arch & current_architecture) == 0))
01273        ++losing;
01274       else
01275        {
01276          int i;
01277 
01278          /* Make a copy of the operands of this insn so that
01279             we can modify them safely, should we want to.  */
01280          assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
01281          for (i = 0; i < opsfound; i++)
01282            operands_backup[i] = the_ins.operands[i];
01283 
01284          for (s = opcode->m_operands, opP = &operands_backup[0];
01285               *s && !losing;
01286               s += 2, opP++)
01287            {
01288              /* Warning: this switch is huge! */
01289              /* I've tried to organize the cases into this order:
01290                non-alpha first, then alpha by letter.  Lower-case
01291                goes directly before uppercase counterpart.  */
01292              /* Code with multiple case ...: gets sorted by the lowest
01293                case ... it belongs to.  I hope this makes sense.  */
01294              switch (*s)
01295               {
01296               case '!':
01297                 switch (opP->mode)
01298                   {
01299                   case IMMED:
01300                   case DREG:
01301                   case AREG:
01302                   case FPREG:
01303                   case CONTROL:
01304                   case AINC:
01305                   case ADEC:
01306                   case REGLST:
01307                     losing++;
01308                     break;
01309                   default:
01310                     break;
01311                   }
01312                 break;
01313 
01314               case '<':
01315                 switch (opP->mode)
01316                   {
01317                   case DREG:
01318                   case AREG:
01319                   case FPREG:
01320                   case CONTROL:
01321                   case IMMED:
01322                   case ADEC:
01323                   case REGLST:
01324                     losing++;
01325                     break;
01326                   default:
01327                     break;
01328                   }
01329                 break;
01330 
01331               case '>':
01332                 switch (opP->mode)
01333                   {
01334                   case DREG:
01335                   case AREG:
01336                   case FPREG:
01337                   case CONTROL:
01338                   case IMMED:
01339                   case AINC:
01340                   case REGLST:
01341                     losing++;
01342                     break;
01343                   case ABSL:
01344                     break;
01345                   default:
01346                     if (opP->reg == PC
01347                        || opP->reg == ZPC)
01348                      losing++;
01349                     break;
01350                   }
01351                 break;
01352 
01353               case 'm':
01354                 switch (opP->mode)
01355                   {
01356                   case DREG:
01357                   case AREG:
01358                   case AINDR:
01359                   case AINC:
01360                   case ADEC:
01361                     break;
01362                   default:
01363                     losing++;
01364                   }
01365                 break;
01366 
01367               case 'n':
01368                 switch (opP->mode)
01369                   {
01370                   case DISP:
01371                     break;
01372                   default:
01373                     losing++;
01374                   }
01375                 break;
01376 
01377               case 'o':
01378                 switch (opP->mode)
01379                   {
01380                   case BASE:
01381                   case ABSL:
01382                   case IMMED:
01383                     break;
01384                   default:
01385                     losing++;
01386                   }
01387                 break;
01388 
01389               case 'p':
01390                 switch (opP->mode)
01391                   {
01392                   case DREG:
01393                   case AREG:
01394                   case AINDR:
01395                   case AINC:
01396                   case ADEC:
01397                     break;
01398                   case DISP:
01399                     if (opP->reg == PC || opP->reg == ZPC)
01400                      losing++;
01401                     break;
01402                   default:
01403                     losing++;
01404                   }
01405                 break;
01406 
01407               case 'q':
01408                 switch (opP->mode)
01409                   {
01410                   case DREG:
01411                   case AINDR:
01412                   case AINC:
01413                   case ADEC:
01414                     break;
01415                   case DISP:
01416                     if (opP->reg == PC || opP->reg == ZPC)
01417                      losing++;
01418                     break;
01419                   default:
01420                     losing++;
01421                     break;
01422                   }
01423                 break;
01424 
01425               case 'v':
01426                 switch (opP->mode)
01427                   {
01428                   case DREG:
01429                   case AINDR:
01430                   case AINC:
01431                   case ADEC:
01432                   case ABSL:
01433                     break;
01434                   case DISP:
01435                     if (opP->reg == PC || opP->reg == ZPC)
01436                      losing++;
01437                     break;
01438                   default:
01439                     losing++;
01440                     break;
01441                   }
01442                 break;
01443 
01444               case '#':
01445                 if (opP->mode != IMMED)
01446                   losing++;
01447                 else if (s[1] == 'b'
01448                         && ! isvar (&opP->disp)
01449                         && (opP->disp.exp.X_op != O_constant
01450                             || ! isbyte (opP->disp.exp.X_add_number)))
01451                   losing++;
01452                 else if (s[1] == 'B'
01453                         && ! isvar (&opP->disp)
01454                         && (opP->disp.exp.X_op != O_constant
01455                             || ! issbyte (opP->disp.exp.X_add_number)))
01456                   losing++;
01457                 else if (s[1] == 'w'
01458                         && ! isvar (&opP->disp)
01459                         && (opP->disp.exp.X_op != O_constant
01460                             || ! isword (opP->disp.exp.X_add_number)))
01461                   losing++;
01462                 else if (s[1] == 'W'
01463                         && ! isvar (&opP->disp)
01464                         && (opP->disp.exp.X_op != O_constant
01465                             || ! issword (opP->disp.exp.X_add_number)))
01466                   losing++;
01467                 break;
01468 
01469               case '^':
01470               case 'T':
01471                 if (opP->mode != IMMED)
01472                   losing++;
01473                 break;
01474 
01475               case '$':
01476                 if (opP->mode == AREG
01477                     || opP->mode == CONTROL
01478                     || opP->mode == FPREG
01479                     || opP->mode == IMMED
01480                     || opP->mode == REGLST
01481                     || (opP->mode != ABSL
01482                        && (opP->reg == PC
01483                            || opP->reg == ZPC)))
01484                   losing++;
01485                 break;
01486 
01487               case '%':
01488                 if (opP->mode == CONTROL
01489                     || opP->mode == FPREG
01490                     || opP->mode == REGLST
01491                     || opP->mode == IMMED
01492                     || (opP->mode != ABSL
01493                        && (opP->reg == PC
01494                            || opP->reg == ZPC)))
01495                   losing++;
01496                 break;
01497 
01498               case '&':
01499                 switch (opP->mode)
01500                   {
01501                   case DREG:
01502                   case AREG:
01503                   case FPREG:
01504                   case CONTROL:
01505                   case IMMED:
01506                   case AINC:
01507                   case ADEC:
01508                   case REGLST:
01509                     losing++;
01510                     break;
01511                   case ABSL:
01512                     break;
01513                   default:
01514                     if (opP->reg == PC
01515                        || opP->reg == ZPC)
01516                      losing++;
01517                     break;
01518                   }
01519                 break;
01520 
01521               case '*':
01522                 if (opP->mode == CONTROL
01523                     || opP->mode == FPREG
01524                     || opP->mode == REGLST)
01525                   losing++;
01526                 break;
01527 
01528               case '+':
01529                 if (opP->mode != AINC)
01530                   losing++;
01531                 break;
01532 
01533               case '-':
01534                 if (opP->mode != ADEC)
01535                   losing++;
01536                 break;
01537 
01538               case '/':
01539                 switch (opP->mode)
01540                   {
01541                   case AREG:
01542                   case CONTROL:
01543                   case FPREG:
01544                   case AINC:
01545                   case ADEC:
01546                   case IMMED:
01547                   case REGLST:
01548                     losing++;
01549                     break;
01550                   default:
01551                     break;
01552                   }
01553                 break;
01554 
01555               case ';':
01556                 switch (opP->mode)
01557                   {
01558                   case AREG:
01559                   case CONTROL:
01560                   case FPREG:
01561                   case REGLST:
01562                     losing++;
01563                     break;
01564                   default:
01565                     break;
01566                   }
01567                 break;
01568 
01569               case '?':
01570                 switch (opP->mode)
01571                   {
01572                   case AREG:
01573                   case CONTROL:
01574                   case FPREG:
01575                   case AINC:
01576                   case ADEC:
01577                   case IMMED:
01578                   case REGLST:
01579                     losing++;
01580                     break;
01581                   case ABSL:
01582                     break;
01583                   default:
01584                     if (opP->reg == PC || opP->reg == ZPC)
01585                      losing++;
01586                     break;
01587                   }
01588                 break;
01589 
01590               case '@':
01591                 switch (opP->mode)
01592                   {
01593                   case AREG:
01594                   case CONTROL:
01595                   case FPREG:
01596                   case IMMED:
01597                   case REGLST:
01598                     losing++;
01599                     break;
01600                   default:
01601                     break;
01602                   }
01603                 break;
01604 
01605               case '~':     /* For now! (JF FOO is this right?) */
01606                 switch (opP->mode)
01607                   {
01608                   case DREG:
01609                   case AREG:
01610                   case CONTROL:
01611                   case FPREG:
01612                   case IMMED:
01613                   case REGLST:
01614                     losing++;
01615                     break;
01616                   case ABSL:
01617                     break;
01618                   default:
01619                     if (opP->reg == PC
01620                        || opP->reg == ZPC)
01621                      losing++;
01622                     break;
01623                   }
01624                 break;
01625 
01626               case '3':
01627                 if (opP->mode != CONTROL
01628                     || (opP->reg != TT0 && opP->reg != TT1))
01629                   losing++;
01630                 break;
01631 
01632               case 'A':
01633                 if (opP->mode != AREG)
01634                   losing++;
01635                 break;
01636 
01637               case 'a':
01638                 if (opP->mode != AINDR)
01639                   ++losing;
01640                 break;
01641 
01642               case '4':
01643                 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
01644                     && (opP->mode != DISP
01645                         || opP->reg < ADDR0
01646                         || opP->reg > ADDR7))
01647                   ++losing;
01648                 break;
01649 
01650               case 'B':     /* FOO */
01651                 if (opP->mode != ABSL
01652                     || (flag_long_jumps
01653                        && strncmp (instring, "jbsr", 4) == 0))
01654                   losing++;
01655                 break;
01656 
01657                 case 'b':
01658                   switch (opP->mode)
01659                     {
01660                     case IMMED:
01661                     case ABSL:
01662                     case AREG:
01663                     case FPREG:
01664                     case CONTROL:
01665                     case POST:
01666                     case PRE:
01667                     case REGLST:
01668                     losing++;
01669                     break;
01670                   default:
01671                     break;
01672                     }
01673                   break;
01674 
01675               case 'C':
01676                 if (opP->mode != CONTROL || opP->reg != CCR)
01677                   losing++;
01678                 break;
01679 
01680               case 'd':
01681                 if (opP->mode != DISP
01682                     || opP->reg < ADDR0
01683                     || opP->reg > ADDR7)
01684                   losing++;
01685                 break;
01686 
01687               case 'D':
01688                 if (opP->mode != DREG)
01689                   losing++;
01690                 break;
01691 
01692               case 'E':
01693                 if (opP->reg != ACC)
01694                   losing++;
01695                 break;
01696 
01697               case 'e':
01698                 if (opP->reg != ACC && opP->reg != ACC1
01699                     && opP->reg != ACC2 && opP->reg != ACC3)
01700                   losing++;
01701                 break;
01702 
01703               case 'F':
01704                 if (opP->mode != FPREG)
01705                   losing++;
01706                 break;
01707 
01708               case 'G':
01709                 if (opP->reg != MACSR)
01710                   losing++;
01711                 break;
01712 
01713               case 'g':
01714                 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
01715                   losing++;
01716                 break;
01717 
01718               case 'H':
01719                 if (opP->reg != MASK)
01720                   losing++;
01721                 break;
01722 
01723               case 'I':
01724                 if (opP->mode != CONTROL
01725                     || opP->reg < COP0
01726                     || opP->reg > COP7)
01727                   losing++;
01728                 break;
01729 
01730               case 'i':
01731                 if (opP->mode != LSH && opP->mode != RSH)
01732                   losing++;
01733                 break;
01734 
01735               case 'J':
01736                 if (opP->mode != CONTROL
01737                     || opP->reg < USP
01738                     || opP->reg > last_movec_reg
01739                     || !control_regs)
01740                   losing++;
01741                 else
01742                   {
01743                     const enum m68k_register *rp;
01744                     
01745                     for (rp = control_regs; *rp; rp++)
01746                      if (*rp == opP->reg)
01747                        break;
01748                     if (*rp == 0)
01749                      losing++;
01750                   }
01751                 break;
01752 
01753               case 'k':
01754                 if (opP->mode != IMMED)
01755                   losing++;
01756                 break;
01757 
01758               case 'l':
01759               case 'L':
01760                 if (opP->mode == DREG
01761                     || opP->mode == AREG
01762                     || opP->mode == FPREG)
01763                   {
01764                     if (s[1] == '8')
01765                      losing++;
01766                     else
01767                      {
01768                        switch (opP->mode)
01769                          {
01770                          case DREG:
01771                            opP->mask = 1 << (opP->reg - DATA0);
01772                            break;
01773                          case AREG:
01774                            opP->mask = 1 << (opP->reg - ADDR0 + 8);
01775                            break;
01776                          case FPREG:
01777                            opP->mask = 1 << (opP->reg - FP0 + 16);
01778                            break;
01779                          default:
01780                            abort ();
01781                          }
01782                        opP->mode = REGLST;
01783                      }
01784                   }
01785                 else if (opP->mode == CONTROL)
01786                   {
01787                     if (s[1] != '8')
01788                      losing++;
01789                     else
01790                      {
01791                        switch (opP->reg)
01792                          {
01793                          case FPI:
01794                            opP->mask = 1 << 24;
01795                            break;
01796                          case FPS:
01797                            opP->mask = 1 << 25;
01798                            break;
01799                          case FPC:
01800                            opP->mask = 1 << 26;
01801                            break;
01802                          default:
01803                            losing++;
01804                            break;
01805                          }
01806                        opP->mode = REGLST;
01807                      }
01808                   }
01809                 else if (opP->mode != REGLST)
01810                   losing++;
01811                 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
01812                   losing++;
01813                 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
01814                   losing++;
01815                 break;
01816 
01817               case 'M':
01818                 if (opP->mode != IMMED)
01819                   losing++;
01820                 else if (opP->disp.exp.X_op != O_constant
01821                         || ! issbyte (opP->disp.exp.X_add_number))
01822                   losing++;
01823                 else if (! m68k_quick
01824                         && instring[3] != 'q'
01825                         && instring[4] != 'q')
01826                   losing++;
01827                 break;
01828 
01829               case 'O':
01830                 if (opP->mode != DREG
01831                     && opP->mode != IMMED
01832                     && opP->mode != ABSL)
01833                   losing++;
01834                 break;
01835 
01836               case 'Q':
01837                 if (opP->mode != IMMED)
01838                   losing++;
01839                 else if (opP->disp.exp.X_op != O_constant
01840                         || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
01841                   losing++;
01842                 else if (! m68k_quick
01843                         && (strncmp (instring, "add", 3) == 0
01844                             || strncmp (instring, "sub", 3) == 0)
01845                         && instring[3] != 'q')
01846                   losing++;
01847                 break;
01848 
01849               case 'R':
01850                 if (opP->mode != DREG && opP->mode != AREG)
01851                   losing++;
01852                 break;
01853 
01854               case 'r':
01855                 if (opP->mode != AINDR
01856                     && (opP->mode != BASE
01857                        || (opP->reg != 0
01858                            && opP->reg != ZADDR0)
01859                        || opP->disp.exp.X_op != O_absent
01860                        || ((opP->index.reg < DATA0
01861                             || opP->index.reg > DATA7)
01862                            && (opP->index.reg < ADDR0
01863                               || opP->index.reg > ADDR7))
01864                        || opP->index.size != SIZE_UNSPEC
01865                        || opP->index.scale != 1))
01866                   losing++;
01867                 break;
01868 
01869               case 's':
01870                 if (opP->mode != CONTROL
01871                     || ! (opP->reg == FPI
01872                          || opP->reg == FPS
01873                          || opP->reg == FPC))
01874                   losing++;
01875                 break;
01876 
01877               case 'S':
01878                 if (opP->mode != CONTROL || opP->reg != SR)
01879                   losing++;
01880                 break;
01881 
01882               case 't':
01883                 if (opP->mode != IMMED)
01884                   losing++;
01885                 else if (opP->disp.exp.X_op != O_constant
01886                         || TRUNC (opP->disp.exp.X_add_number) > 7)
01887                   losing++;
01888                 break;
01889 
01890               case 'U':
01891                 if (opP->mode != CONTROL || opP->reg != USP)
01892                   losing++;
01893                 break;
01894 
01895               case 'x':
01896                 if (opP->mode != IMMED)
01897                   losing++;
01898                 else if (opP->disp.exp.X_op != O_constant
01899                         || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
01900                             && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
01901                   losing++;
01902                 break;
01903 
01904                 /* JF these are out of order.  We could put them
01905                    in order if we were willing to put up with
01906                    bunches of #ifdef m68851s in the code.
01907 
01908                    Don't forget that you need these operands
01909                    to use 68030 MMU instructions.  */
01910 #ifndef NO_68851
01911                 /* Memory addressing mode used by pflushr.  */
01912               case '|':
01913                 if (opP->mode == CONTROL
01914                     || opP->mode == FPREG
01915                     || opP->mode == DREG
01916                     || opP->mode == AREG
01917                     || opP->mode == REGLST)
01918                   losing++;
01919                 /* We should accept immediate operands, but they
01920                      supposedly have to be quad word, and we don't
01921                      handle that.  I would like to see what a Motorola
01922                      assembler does before doing something here.  */
01923                 if (opP->mode == IMMED)
01924                   losing++;
01925                 break;
01926 
01927               case 'f':
01928                 if (opP->mode != CONTROL
01929                     || (opP->reg != SFC && opP->reg != DFC))
01930                   losing++;
01931                 break;
01932 
01933               case '0':
01934                 if (opP->mode != CONTROL || opP->reg != TC)
01935                   losing++;
01936                 break;
01937 
01938               case '1':
01939                 if (opP->mode != CONTROL || opP->reg != AC)
01940                   losing++;
01941                 break;
01942 
01943               case '2':
01944                 if (opP->mode != CONTROL
01945                     || (opP->reg != CAL
01946                        && opP->reg != VAL
01947                        && opP->reg != SCC))
01948                   losing++;
01949                 break;
01950 
01951               case 'V':
01952                 if (opP->mode != CONTROL
01953                     || opP->reg != VAL)
01954                   losing++;
01955                 break;
01956 
01957               case 'W':
01958                 if (opP->mode != CONTROL
01959                     || (opP->reg != DRP
01960                        && opP->reg != SRP
01961                        && opP->reg != CRP))
01962                   losing++;
01963                 break;
01964 
01965               case 'w':
01966                 switch (opP->mode)
01967                   {
01968                     case IMMED:
01969                     case ABSL:
01970                     case AREG:
01971                     case DREG:
01972                     case FPREG:
01973                     case CONTROL:
01974                     case POST:
01975                     case PRE:
01976                     case REGLST:
01977                      losing++;
01978                      break;
01979                     default:
01980                      break;
01981                   }
01982                 break;
01983 
01984               case 'X':
01985                 if (opP->mode != CONTROL
01986                     || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
01987                        && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
01988                   losing++;
01989                 break;
01990 
01991               case 'Y':
01992                 if (opP->mode != CONTROL || opP->reg != PSR)
01993                   losing++;
01994                 break;
01995 
01996               case 'Z':
01997                 if (opP->mode != CONTROL || opP->reg != PCSR)
01998                   losing++;
01999                 break;
02000 #endif
02001               case 'c':
02002                 if (opP->mode != CONTROL
02003                     || (opP->reg != NC
02004                        && opP->reg != IC
02005                        && opP->reg != DC
02006                        && opP->reg != BC))
02007                   losing++;
02008                 break;
02009 
02010               case '_':
02011                 if (opP->mode != ABSL)
02012                   ++losing;
02013                 break;
02014 
02015               case 'u':
02016                 if (opP->reg < DATA0L || opP->reg > ADDR7U)
02017                   losing++;
02018                 /* FIXME: kludge instead of fixing parser:
02019                      upper/lower registers are *not* CONTROL
02020                      registers, but ordinary ones.  */
02021                 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
02022                     || (opP->reg >= DATA0U && opP->reg <= DATA7U))
02023                   opP->mode = DREG;
02024                 else
02025                   opP->mode = AREG;
02026                 break;
02027 
02028                case 'y':
02029                  if (!(opP->mode == AINDR
02030                       || (opP->mode == DISP
02031                           && !(opP->reg == PC || opP->reg == ZPC))))
02032                    losing++;
02033                  break;
02034 
02035                case 'z':
02036                  if (!(opP->mode == AINDR || opP->mode == DISP))
02037                    losing++;
02038                  break;
02039 
02040               default:
02041                 abort ();
02042               }
02043 
02044              if (losing)
02045               break;
02046            }
02047 
02048          /* Since we have found the correct instruction, copy
02049             in the modifications that we may have made.  */
02050          if (!losing)
02051            for (i = 0; i < opsfound; i++)
02052              the_ins.operands[i] = operands_backup[i];
02053        }
02054 
02055       if (!losing)
02056        break;
02057 
02058       opcode = opcode->m_next;
02059 
02060       if (!opcode)
02061        {
02062          if (ok_arch
02063              && !(ok_arch & current_architecture))
02064            {
02065              const struct m68k_cpu *cpu;
02066              int any = 0;
02067              size_t space = 400;
02068              char *buf = xmalloc (space + 1);
02069              size_t len;
02070              int paren = 1;
02071 
02072              the_ins.error = buf;
02073              /* Make sure there's a NUL at the end of the buffer -- strncpy
02074                won't write one when it runs out of buffer */
02075              buf[space] = 0;
02076 #define APPEND(STRING) \
02077   (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
02078 
02079              APPEND (_("invalid instruction for this architecture; needs "));
02080              switch (ok_arch)
02081               {
02082               case mcfisa_a:
02083                 APPEND (_("ColdFire ISA_A"));
02084                 break;
02085               case mcfhwdiv:
02086                 APPEND (_("ColdFire hardware divide"));
02087                 break;
02088               case mcfisa_aa:
02089                 APPEND (_("ColdFire ISA_A+"));
02090                 break;
02091               case mcfisa_b:
02092                 APPEND (_("ColdFire ISA_B"));
02093                 break;
02094               case cfloat:
02095                 APPEND (_("ColdFire fpu"));
02096                 break;
02097               case mfloat:
02098                 APPEND (_("M68K fpu"));
02099                 break;
02100               case mmmu:
02101                 APPEND (_("M68K mmu"));
02102                 break;
02103               case m68020up:
02104                 APPEND (_("68020 or higher"));
02105                 break;
02106               case m68000up:
02107                 APPEND (_("68000 or higher"));
02108                 break;
02109               case m68010up:
02110                 APPEND (_("68010 or higher"));
02111                 break;
02112               default:
02113                 paren = 0;
02114               }
02115              if (paren)
02116               APPEND (" (");
02117 
02118              for (cpu = m68k_cpus; cpu->name; cpu++)
02119               if (!cpu->alias && (cpu->arch & ok_arch))
02120                 {
02121                   const struct m68k_cpu *alias;
02122                   int seen_master = 0;
02123                   
02124                   if (any)
02125                     APPEND (", ");
02126                   any = 0;
02127                   APPEND (cpu->name);
02128                   for (alias = cpu; alias != m68k_cpus; alias--)
02129                     if (alias[-1].alias >= 0)
02130                      break;
02131                   for (; !seen_master || alias->alias > 0; alias++)
02132                      {
02133                        if (!alias->alias)
02134                          seen_master = 1;
02135                        else
02136                          {
02137                            if (any)
02138                             APPEND (", ");
02139                            else
02140                             APPEND (" [");
02141                            APPEND (alias->name);
02142                            any = 1;
02143                          }
02144                      }
02145                   if (any)
02146                     APPEND ("]");
02147                   any = 1;
02148                 }
02149              if (paren)
02150               APPEND (")");
02151 #undef APPEND
02152              if (!space)
02153               {
02154                 /* we ran out of space, so replace the end of the list
02155                    with ellipsis.  */
02156                 buf -= 4;
02157                 while (*buf != ' ')
02158                   buf--;
02159                 strcpy (buf, " ...");
02160               }
02161            }
02162          else
02163            the_ins.error = _("operands mismatch");
02164          return;
02165        }
02166 
02167       losing = 0;
02168     }
02169 
02170   /* Now assemble it.  */
02171   the_ins.args = opcode->m_operands;
02172   the_ins.numargs = opcode->m_opnum;
02173   the_ins.numo = opcode->m_codenum;
02174   the_ins.opcode[0] = getone (opcode);
02175   the_ins.opcode[1] = gettwo (opcode);
02176 
02177   for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
02178     {
02179       /* This switch is a doozy.
02180         Watch the first step; its a big one! */
02181       switch (s[0])
02182        {
02183 
02184        case '*':
02185        case '~':
02186        case '%':
02187        case ';':
02188        case '@':
02189        case '!':
02190        case '&':
02191        case '$':
02192        case '?':
02193        case '/':
02194        case '<':
02195        case '>':
02196        case 'b':
02197        case 'm':
02198        case 'n':
02199        case 'o':
02200        case 'p':
02201        case 'q':
02202        case 'v':
02203        case 'w':
02204        case 'y':
02205        case 'z':
02206        case '4':
02207 #ifndef NO_68851
02208        case '|':
02209 #endif
02210          switch (opP->mode)
02211            {
02212            case IMMED:
02213              tmpreg = 0x3c; /* 7.4 */
02214              if (strchr ("bwl", s[1]))
02215               nextword = get_num (&opP->disp, 90);
02216              else
02217               nextword = get_num (&opP->disp, 0);
02218              if (isvar (&opP->disp))
02219               add_fix (s[1], &opP->disp, 0, 0);
02220              switch (s[1])
02221               {
02222               case 'b':
02223                 if (!isbyte (nextword))
02224                   opP->error = _("operand out of range");
02225                 addword (nextword);
02226                 baseo = 0;
02227                 break;
02228               case 'w':
02229                 if (!isword (nextword))
02230                   opP->error = _("operand out of range");
02231                 addword (nextword);
02232                 baseo = 0;
02233                 break;
02234               case 'W':
02235                 if (!issword (nextword))
02236                   opP->error = _("operand out of range");
02237                 addword (nextword);
02238                 baseo = 0;
02239                 break;
02240               case 'l':
02241                 addword (nextword >> 16);
02242                 addword (nextword);
02243                 baseo = 0;
02244                 break;
02245 
02246               case 'f':
02247                 baseo = 2;
02248                 outro = 8;
02249                 break;
02250               case 'F':
02251                 baseo = 4;
02252                 outro = 11;
02253                 break;
02254               case 'x':
02255                 baseo = 6;
02256                 outro = 15;
02257                 break;
02258               case 'p':
02259                 baseo = 6;
02260                 outro = -1;
02261                 break;
02262               default:
02263                 abort ();
02264               }
02265              if (!baseo)
02266               break;
02267 
02268              /* We gotta put out some float.  */
02269              if (op (&opP->disp) != O_big)
02270               {
02271                 valueT val;
02272                 int gencnt;
02273 
02274                 /* Can other cases happen here?  */
02275                 if (op (&opP->disp) != O_constant)
02276                   abort ();
02277 
02278                 val = (valueT) offs (&opP->disp);
02279                 gencnt = 0;
02280                 do
02281                   {
02282                     generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
02283                     val >>= LITTLENUM_NUMBER_OF_BITS;
02284                     ++gencnt;
02285                   }
02286                 while (val != 0);
02287                 offs (&opP->disp) = gencnt;
02288               }
02289              if (offs (&opP->disp) > 0)
02290               {
02291                 if (offs (&opP->disp) > baseo)
02292                   {
02293                     as_warn (_("Bignum too big for %c format; truncated"),
02294                             s[1]);
02295                     offs (&opP->disp) = baseo;
02296                   }
02297                 baseo -= offs (&opP->disp);
02298                 while (baseo--)
02299                   addword (0);
02300                 for (wordp = generic_bignum + offs (&opP->disp) - 1;
02301                      offs (&opP->disp)--;
02302                      --wordp)
02303                   addword (*wordp);
02304                 break;
02305               }
02306              gen_to_words (words, baseo, (long) outro);
02307              for (wordp = words; baseo--; wordp++)
02308               addword (*wordp);
02309              break;
02310            case DREG:
02311              tmpreg = opP->reg - DATA;    /* 0.dreg */
02312              break;
02313            case AREG:
02314              tmpreg = 0x08 + opP->reg - ADDR;    /* 1.areg */
02315              break;
02316            case AINDR:
02317              tmpreg = 0x10 + opP->reg - ADDR;    /* 2.areg */
02318              break;
02319            case ADEC:
02320              tmpreg = 0x20 + opP->reg - ADDR;    /* 4.areg */
02321              break;
02322            case AINC:
02323              tmpreg = 0x18 + opP->reg - ADDR;    /* 3.areg */
02324              break;
02325            case DISP:
02326 
02327              nextword = get_num (&opP->disp, 90);
02328 
02329              /* Convert mode 5 addressing with a zero offset into
02330                mode 2 addressing to reduce the instruction size by a
02331                word.  */
02332              if (! isvar (&opP->disp)
02333                 && (nextword == 0)
02334                 && (opP->disp.size == SIZE_UNSPEC)
02335                 && (opP->reg >= ADDR0)
02336                 && (opP->reg <= ADDR7))
02337               {
02338                 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
02339                 break;
02340               }
02341 
02342              if (opP->reg == PC
02343                 && ! isvar (&opP->disp)
02344                 && m68k_abspcadd)
02345               {
02346                 opP->disp.exp.X_op = O_symbol;
02347                 opP->disp.exp.X_add_symbol =
02348                   section_symbol (absolute_section);
02349               }
02350 
02351              /* Force into index mode.  Hope this works.  */
02352 
02353              /* We do the first bit for 32-bit displacements, and the
02354                second bit for 16 bit ones.  It is possible that we
02355                should make the default be WORD instead of LONG, but
02356                I think that'd break GCC, so we put up with a little
02357                inefficiency for the sake of working output.  */
02358 
02359              if (!issword (nextword)
02360                 || (isvar (&opP->disp)
02361                     && ((opP->disp.size == SIZE_UNSPEC
02362                         && flag_short_refs == 0
02363                         && cpu_of_arch (current_architecture) >= m68020
02364                         && ! arch_coldfire_p (current_architecture))
02365                        || opP->disp.size == SIZE_LONG)))
02366               {
02367                 if (cpu_of_arch (current_architecture) < m68020
02368                     || arch_coldfire_p (current_architecture))
02369                   opP->error =
02370                     _("displacement too large for this architecture; needs 68020 or higher");
02371                 if (opP->reg == PC)
02372                   tmpreg = 0x3B;   /* 7.3 */
02373                 else
02374                   tmpreg = 0x30 + opP->reg - ADDR;      /* 6.areg */
02375                 if (isvar (&opP->disp))
02376                   {
02377                     if (opP->reg == PC)
02378                      {
02379                        if (opP->disp.size == SIZE_LONG
02380 #ifdef OBJ_ELF
02381                            /* If the displacement needs pic
02382                              relocation it cannot be relaxed.  */
02383                            || opP->disp.pic_reloc != pic_none
02384 #endif
02385                            )
02386                          {
02387                            addword (0x0170);
02388                            add_fix ('l', &opP->disp, 1, 2);
02389                          }
02390                        else
02391                          {
02392                            add_frag (adds (&opP->disp),
02393                                    SEXT (offs (&opP->disp)),
02394                                    TAB (PCREL1632, SZ_UNDEF));
02395                            break;
02396                          }
02397                      }
02398                     else
02399                      {
02400                        addword (0x0170);
02401                        add_fix ('l', &opP->disp, 0, 0);
02402                      }
02403                   }
02404                 else
02405                   addword (0x0170);
02406                 addword (nextword >> 16);
02407               }
02408              else
02409               {
02410                 if (opP->reg == PC)
02411                   tmpreg = 0x3A;   /* 7.2 */
02412                 else
02413                   tmpreg = 0x28 + opP->reg - ADDR;      /* 5.areg */
02414 
02415                 if (isvar (&opP->disp))
02416                   {
02417                     if (opP->reg == PC)
02418                      {
02419                        add_fix ('w', &opP->disp, 1, 0);
02420                      }
02421                     else
02422                      add_fix ('w', &opP->disp, 0, 0);
02423                   }
02424               }
02425              addword (nextword);
02426              break;
02427 
02428            case POST:
02429            case PRE:
02430            case BASE:
02431              nextword = 0;
02432              baseo = get_num (&opP->disp, 90);
02433              if (opP->mode == POST || opP->mode == PRE)
02434               outro = get_num (&opP->odisp, 90);
02435              /* Figure out the `addressing mode'.
02436                Also turn on the BASE_DISABLE bit, if needed.  */
02437              if (opP->reg == PC || opP->reg == ZPC)
02438               {
02439                 tmpreg = 0x3b;     /* 7.3 */
02440                 if (opP->reg == ZPC)
02441                   nextword |= 0x80;
02442               }
02443              else if (opP->reg == 0)
02444               {
02445                 nextword |= 0x80;
02446                 tmpreg = 0x30;     /* 6.garbage */
02447               }
02448              else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
02449               {
02450                 nextword |= 0x80;
02451                 tmpreg = 0x30 + opP->reg - ZADDR0;
02452               }
02453              else
02454               tmpreg = 0x30 + opP->reg - ADDR;   /* 6.areg */
02455 
02456              siz1 = opP->disp.size;
02457              if (opP->mode == POST || opP->mode == PRE)
02458               siz2 = opP->odisp.size;
02459              else
02460               siz2 = SIZE_UNSPEC;
02461 
02462              /* Index register stuff.  */
02463              if (opP->index.reg != 0
02464                 && opP->index.reg >= DATA
02465                 && opP->index.reg <= ADDR7)
02466               {
02467                 nextword |= (opP->index.reg - DATA) << 12;
02468 
02469                 if (opP->index.size == SIZE_LONG
02470                     || (opP->index.size == SIZE_UNSPEC
02471                        && m68k_index_width_default == SIZE_LONG))
02472                   nextword |= 0x800;
02473 
02474                 if ((opP->index.scale != 1
02475                      && cpu_of_arch (current_architecture) < m68020)
02476                     || (opP->index.scale == 8
02477                        && (arch_coldfire_p (current_architecture)
02478                               && !arch_coldfire_fpu (current_architecture))))
02479                   {
02480                     opP->error =
02481                      _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
02482                   }
02483 
02484                 if (arch_coldfire_p (current_architecture)
02485                     && opP->index.size == SIZE_WORD)
02486                   opP->error = _("invalid index size for coldfire");
02487 
02488                 switch (opP->index.scale)
02489                   {
02490                   case 1:
02491                     break;
02492                   case 2:
02493                     nextword |= 0x200;
02494                     break;
02495                   case 4:
02496                     nextword |= 0x400;
02497                     break;
02498                   case 8:
02499                     nextword |= 0x600;
02500                     break;
02501                   default:
02502                     abort ();
02503                   }
02504                 /* IF its simple,
02505                    GET US OUT OF HERE! */
02506 
02507                 /* Must be INDEX, with an index register.  Address
02508                    register cannot be ZERO-PC, and either :b was
02509                    forced, or we know it will fit.  For a 68000 or
02510                    68010, force this mode anyways, because the
02511                    larger modes aren't supported.  */
02512                 if (opP->mode == BASE
02513                     && ((opP->reg >= ADDR0
02514                         && opP->reg <= ADDR7)
02515                        || opP->reg == PC))
02516                   {
02517                     if (siz1 == SIZE_BYTE
02518                        || cpu_of_arch (current_architecture) < m68020
02519                        || arch_coldfire_p (current_architecture)
02520                        || (siz1 == SIZE_UNSPEC
02521                            && ! isvar (&opP->disp)
02522                            && issbyte (baseo)))
02523                      {
02524                        nextword += baseo & 0xff;
02525                        addword (nextword);
02526                        if (isvar (&opP->disp))
02527                          {
02528                            /* Do a byte relocation.  If it doesn't
02529                              fit (possible on m68000) let the
02530                              fixup processing complain later.  */
02531                            if (opP->reg == PC)
02532                             add_fix ('B', &opP->disp, 1, 1);
02533                            else
02534                             add_fix ('B', &opP->disp, 0, 0);
02535                          }
02536                        else if (siz1 != SIZE_BYTE)
02537                          {
02538                            if (siz1 != SIZE_UNSPEC)
02539                             as_warn (_("Forcing byte displacement"));
02540                            if (! issbyte (baseo))
02541                             opP->error = _("byte displacement out of range");
02542                          }
02543 
02544                        break;
02545                      }
02546                     else if (siz1 == SIZE_UNSPEC
02547                             && opP->reg == PC
02548                             && isvar (&opP->disp)
02549                             && subs (&opP->disp) == NULL
02550 #ifdef OBJ_ELF
02551                             /* If the displacement needs pic
02552                               relocation it cannot be relaxed.  */
02553                             && opP->disp.pic_reloc == pic_none
02554 #endif
02555                             )
02556                      {
02557                        /* The code in md_convert_frag_1 needs to be
02558                              able to adjust nextword.  Call frag_grow
02559                              to ensure that we have enough space in
02560                              the frag obstack to make all the bytes
02561                              contiguous.  */
02562                        frag_grow (14);
02563                        nextword += baseo & 0xff;
02564                        addword (nextword);
02565                        add_frag (adds (&opP->disp),
02566                                 SEXT (offs (&opP->disp)),
02567                                 TAB (PCINDEX, SZ_UNDEF));
02568 
02569                        break;
02570                      }
02571                   }
02572               }
02573              else
02574               {
02575                 nextword |= 0x40;  /* No index reg.  */
02576                 if (opP->index.reg >= ZDATA0
02577                     && opP->index.reg <= ZDATA7)
02578                   nextword |= (opP->index.reg - ZDATA0) << 12;
02579                 else if (opP->index.reg >= ZADDR0
02580                         || opP->index.reg <= ZADDR7)
02581                   nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
02582               }
02583 
02584              /* It isn't simple.  */
02585 
02586              if (cpu_of_arch (current_architecture) < m68020
02587                 || arch_coldfire_p (current_architecture))
02588               opP->error =
02589                 _("invalid operand mode for this architecture; needs 68020 or higher");
02590 
02591              nextword |= 0x100;
02592              /* If the guy specified a width, we assume that it is
02593                wide enough.  Maybe it isn't.  If so, we lose.  */
02594              switch (siz1)
02595               {
02596               case SIZE_UNSPEC:
02597                 if (isvar (&opP->disp)
02598                     ? m68k_rel32
02599                     : ! issword (baseo))
02600                   {
02601                     siz1 = SIZE_LONG;
02602                     nextword |= 0x30;
02603                   }
02604                 else if (! isvar (&opP->disp) && baseo == 0)
02605                   nextword |= 0x10;
02606                 else
02607                   {
02608                     nextword |= 0x20;
02609                     siz1 = SIZE_WORD;
02610                   }
02611                 break;
02612               case SIZE_BYTE:
02613                 as_warn (_(":b not permitted; defaulting to :w"));
02614                 /* Fall through.  */
02615               case SIZE_WORD:
02616                 nextword |= 0x20;
02617                 break;
02618               case SIZE_LONG:
02619                 nextword |= 0x30;
02620                 break;
02621               }
02622 
02623              /* Figure out inner displacement stuff.  */
02624              if (opP->mode == POST || opP->mode == PRE)
02625               {
02626                 if (cpu_of_arch (current_architecture) & cpu32)
02627                   opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
02628                 switch (siz2)
02629                   {
02630                   case SIZE_UNSPEC:
02631                     if (isvar (&opP->odisp)
02632                        ? m68k_rel32
02633                        : ! issword (outro))
02634                      {
02635                        siz2 = SIZE_LONG;
02636                        nextword |= 0x3;
02637                      }
02638                     else if (! isvar (&opP->odisp) && outro == 0)
02639                      nextword |= 0x1;
02640                     else
02641                      {
02642                        nextword |= 0x2;
02643                        siz2 = SIZE_WORD;
02644                      }
02645                     break;
02646                   case 1:
02647                     as_warn (_(":b not permitted; defaulting to :w"));
02648                     /* Fall through.  */
02649                   case 2:
02650                     nextword |= 0x2;
02651                     break;
02652                   case 3:
02653                     nextword |= 0x3;
02654                     break;
02655                   }
02656                 if (opP->mode == POST
02657                     && (nextword & 0x40) == 0)
02658                   nextword |= 0x04;
02659               }
02660              addword (nextword);
02661 
02662              if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
02663               {
02664                 if (opP->reg == PC || opP->reg == ZPC)
02665                   add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
02666                 else
02667                   add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
02668               }
02669              if (siz1 == SIZE_LONG)
02670               addword (baseo >> 16);
02671              if (siz1 != SIZE_UNSPEC)
02672               addword (baseo);
02673 
02674              if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
02675               add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
02676              if (siz2 == SIZE_LONG)
02677               addword (outro >> 16);
02678              if (siz2 != SIZE_UNSPEC)
02679               addword (outro);
02680 
02681              break;
02682 
02683            case ABSL:
02684              nextword = get_num (&opP->disp, 90);
02685              switch (opP->disp.size)
02686               {
02687               default:
02688                 abort ();
02689               case SIZE_UNSPEC:
02690                 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
02691                   {
02692                     tmpreg = 0x38; /* 7.0 */
02693                     addword (nextword);
02694                     break;
02695                   }
02696                 if (isvar (&opP->disp)
02697                     && !subs (&opP->disp)
02698                     && adds (&opP->disp)
02699 #ifdef OBJ_ELF
02700                     /* If the displacement needs pic relocation it
02701                       cannot be relaxed.  */
02702                     && opP->disp.pic_reloc == pic_none
02703 #endif
02704                     && !flag_long_jumps
02705                     && !strchr ("~%&$?", s[0]))
02706                   {
02707                     tmpreg = 0x3A; /* 7.2 */
02708                     add_frag (adds (&opP->disp),
02709                             SEXT (offs (&opP->disp)),
02710                             TAB (ABSTOPCREL, SZ_UNDEF));
02711                     break;
02712                   }
02713                 /* Fall through into long.  */
02714               case SIZE_LONG:
02715                 if (isvar (&opP->disp))
02716                   add_fix ('l', &opP->disp, 0, 0);
02717 
02718                 tmpreg = 0x39;/* 7.1 mode */
02719                 addword (nextword >> 16);
02720                 addword (nextword);
02721                 break;
02722 
02723               case SIZE_BYTE:
02724                 as_bad (_("unsupported byte value; use a different suffix"));
02725                 /* Fall through.  */
02726 
02727               case SIZE_WORD:
02728                 if (isvar (&opP->disp))
02729                   add_fix ('w', &opP->disp, 0, 0);
02730 
02731                 tmpreg = 0x38;/* 7.0 mode */
02732                 addword (nextword);
02733                 break;
02734               }
02735              break;
02736            case CONTROL:
02737            case FPREG:
02738            default:
02739              as_bad (_("unknown/incorrect operand"));
02740              /* abort (); */
02741            }
02742 
02743          /* If s[0] is '4', then this is for the mac instructions
02744             that can have a trailing_ampersand set.  If so, set 0x100
02745             bit on tmpreg so install_gen_operand can check for it and
02746             set the appropriate bit (word2, bit 5).  */
02747          if (s[0] == '4')
02748            {
02749              if (opP->trailing_ampersand)
02750               tmpreg |= 0x100;
02751            }
02752          install_gen_operand (s[1], tmpreg);
02753          break;
02754 
02755        case '#':
02756        case '^':
02757          switch (s[1])
02758            {                /* JF: I hate floating point! */
02759            case 'j':
02760              tmpreg = 70;
02761              break;
02762            case '8':
02763              tmpreg = 20;
02764              break;
02765            case 'C':
02766              tmpreg = 50;
02767              break;
02768            case '3':
02769            default:
02770              tmpreg = 90;
02771              break;
02772            }
02773          tmpreg = get_num (&opP->disp, tmpreg);
02774          if (isvar (&opP->disp))
02775            add_fix (s[1], &opP->disp, 0, 0);
02776          switch (s[1])
02777            {
02778            case 'b':        /* Danger:  These do no check for
02779                                certain types of overflow.
02780                                user beware! */
02781              if (!isbyte (tmpreg))
02782               opP->error = _("out of range");
02783              insop (tmpreg, opcode);
02784              if (isvar (&opP->disp))
02785               the_ins.reloc[the_ins.nrel - 1].n =
02786                 (opcode->m_codenum) * 2 + 1;
02787              break;
02788            case 'B':
02789              if (!issbyte (tmpreg))
02790               opP->error = _("out of range");
02791              the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
02792              if (isvar (&opP->disp))
02793               the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
02794              break;
02795            case 'w':
02796              if (!isword (tmpreg))
02797               opP->error = _("out of range");
02798              insop (tmpreg, opcode);
02799              if (isvar (&opP->disp))
02800               the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
02801              break;
02802            case 'W':
02803              if (!issword (tmpreg))
02804               opP->error = _("out of range");
02805              insop (tmpreg, opcode);
02806              if (isvar (&opP->disp))
02807               the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
02808              break;
02809            case 'l':
02810              /* Because of the way insop works, we put these two out
02811                backwards.  */
02812              insop (tmpreg, opcode);
02813              insop (tmpreg >> 16, opcode);
02814              if (isvar (&opP->disp))
02815               the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
02816              break;
02817            case '3':
02818              tmpreg &= 0xFF;
02819            case '8':
02820            case 'C':
02821            case 'j':
02822              install_operand (s[1], tmpreg);
02823              break;
02824            default:
02825              abort ();
02826            }
02827          break;
02828 
02829        case '+':
02830        case '-':
02831        case 'A':
02832        case 'a':
02833          install_operand (s[1], opP->reg - ADDR);
02834          break;
02835 
02836        case 'B':
02837          tmpreg = get_num (&opP->disp, 90);
02838          switch (s[1])
02839            {
02840            case 'B':
02841              add_fix ('B', &opP->disp, 1, -1);
02842              break;
02843            case 'W':
02844              add_fix ('w', &opP->disp, 1, 0);
02845              addword (0);
02846              break;
02847            case 'L':
02848            long_branch:
02849              if (! HAVE_LONG_BRANCH (current_architecture))
02850               as_warn (_("Can't use long branches on 68000/68010/5200"));
02851              the_ins.opcode[0] |= 0xff;
02852              add_fix ('l', &opP->disp, 1, 0);
02853              addword (0);
02854              addword (0);
02855              break;
02856            case 'g':
02857              if (subs (&opP->disp))       /* We can't relax it.  */
02858               goto long_branch;
02859 
02860 #ifdef OBJ_ELF
02861              /* If the displacement needs pic relocation it cannot be
02862                relaxed.  */
02863              if (opP->disp.pic_reloc != pic_none)
02864               goto long_branch;
02865 #endif
02866              /* This could either be a symbol, or an absolute
02867                address.  If it's an absolute address, turn it into
02868                an absolute jump right here and keep it out of the
02869                relaxer.  */
02870              if (adds (&opP->disp) == 0)
02871               {
02872                 if (the_ins.opcode[0] == 0x6000) /* jbra */
02873                   the_ins.opcode[0] = 0x4EF9;
02874                 else if (the_ins.opcode[0] == 0x6100)   /* jbsr */
02875                   the_ins.opcode[0] = 0x4EB9;
02876                 else                             /* jCC */
02877                   {
02878                     the_ins.opcode[0] ^= 0x0100;
02879                     the_ins.opcode[0] |= 0x0006;
02880                     addword (0x4EF9);
02881                   }
02882                 add_fix ('l', &opP->disp, 0, 0);
02883                 addword (0);
02884                 addword (0);
02885                 break;
02886               }
02887 
02888              /* Now we know it's going into the relaxer.  Now figure
02889                out which mode.  We try in this order of preference:
02890                long branch, absolute jump, byte/word branches only.  */
02891              if (HAVE_LONG_BRANCH (current_architecture))
02892               add_frag (adds (&opP->disp),
02893                        SEXT (offs (&opP->disp)),
02894                        TAB (BRANCHBWL, SZ_UNDEF));
02895              else if (! flag_keep_pcrel)
02896               {
02897                 if ((the_ins.opcode[0] == 0x6000)
02898                     || (the_ins.opcode[0] == 0x6100))
02899                   add_frag (adds (&opP->disp),
02900                            SEXT (offs (&opP->disp)),
02901                            TAB (BRABSJUNC, SZ_UNDEF));
02902                 else
02903                   add_frag (adds (&opP->disp),
02904                            SEXT (offs (&opP->disp)),
02905                            TAB (BRABSJCOND, SZ_UNDEF));
02906               }
02907              else
02908               add_frag (adds (&opP->disp),
02909                        SEXT (offs (&opP->disp)),
02910                        TAB (BRANCHBW, SZ_UNDEF));
02911              break;
02912            case 'w':
02913              if (isvar (&opP->disp))
02914               {
02915                 /* Check for DBcc instructions.  We can relax them,
02916                    but only if we have long branches and/or absolute
02917                    jumps.  */
02918                 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
02919                     && (HAVE_LONG_BRANCH (current_architecture)
02920                        || (! flag_keep_pcrel)))
02921                   {
02922                     if (HAVE_LONG_BRANCH (current_architecture))
02923                      add_frag (adds (&opP->disp),
02924                               SEXT (offs (&opP->disp)),
02925                               TAB (DBCCLBR, SZ_UNDEF));
02926                     else
02927                      add_frag (adds (&opP->disp),
02928                               SEXT (offs (&opP->disp)),
02929                               TAB (DBCCABSJ, SZ_UNDEF));
02930                     break;
02931                   }
02932                 add_fix ('w', &opP->disp, 1, 0);
02933               }
02934              addword (0);
02935              break;
02936            case 'C':        /* Fixed size LONG coproc branches.  */
02937              add_fix ('l', &opP->disp, 1, 0);
02938              addword (0);
02939              addword (0);
02940              break;
02941            case 'c':        /* Var size Coprocesssor branches.  */
02942              if (subs (&opP->disp) || (adds (&opP->disp) == 0))
02943               {
02944                 the_ins.opcode[the_ins.numo - 1] |= 0x40;
02945                 add_fix ('l', &opP->disp, 1, 0);
02946                 addword (0);
02947                 addword (0);
02948               }
02949              else
02950               add_frag (adds (&opP->disp),
02951                        SEXT (offs (&opP->disp)),
02952                        TAB (FBRANCH, SZ_UNDEF));
02953              break;
02954            default:
02955              abort ();
02956            }
02957          break;
02958 
02959        case 'C':            /* Ignore it.  */
02960          break;
02961 
02962        case 'd':            /* JF this is a kludge.  */
02963          install_operand ('s', opP->reg - ADDR);
02964          tmpreg = get_num (&opP->disp, 90);
02965          if (!issword (tmpreg))
02966            {
02967              as_warn (_("Expression out of range, using 0"));
02968              tmpreg = 0;
02969            }
02970          addword (tmpreg);
02971          break;
02972 
02973        case 'D':
02974          install_operand (s[1], opP->reg - DATA);
02975          break;
02976 
02977        case 'e':  /* EMAC ACCx, reg/reg.  */
02978          install_operand (s[1], opP->reg - ACC);
02979          break;
02980          
02981        case 'E':            /* Ignore it.  */
02982          break;
02983 
02984        case 'F':
02985          install_operand (s[1], opP->reg - FP0);
02986          break;
02987 
02988        case 'g':  /* EMAC ACCEXTx.  */
02989          install_operand (s[1], opP->reg - ACCEXT01);
02990          break;
02991 
02992        case 'G':            /* Ignore it.  */
02993        case 'H':
02994          break;
02995 
02996        case 'I':
02997          tmpreg = opP->reg - COP0;
02998          install_operand (s[1], tmpreg);
02999          break;
03000 
03001        case 'i':  /* MAC/EMAC scale factor.  */
03002          install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
03003          break;
03004 
03005        case 'J':            /* JF foo.  */
03006          switch (opP->reg)
03007            {
03008            case SFC:
03009              tmpreg = 0x000;
03010              break;
03011            case DFC:
03012              tmpreg = 0x001;
03013              break;
03014            case CACR:
03015              tmpreg = 0x002;
03016              break;
03017            case TC:
03018            case ASID:
03019              tmpreg = 0x003;
03020              break;
03021            case ACR0:
03022            case ITT0:
03023              tmpreg = 0x004;
03024              break;
03025            case ACR1:
03026            case ITT1:
03027              tmpreg = 0x005;
03028              break;
03029            case ACR2:
03030            case DTT0:
03031              tmpreg = 0x006;
03032              break;
03033            case ACR3:
03034            case DTT1:
03035              tmpreg = 0x007;
03036              break;
03037            case BUSCR:
03038            case MMUBAR:
03039              tmpreg = 0x008;
03040              break;
03041 
03042            case USP:
03043              tmpreg = 0x800;
03044              break;
03045            case VBR:
03046              tmpreg = 0x801;
03047              break;
03048            case CAAR:
03049              tmpreg = 0x802;
03050              break;
03051            case MSP:
03052              tmpreg = 0x803;
03053              break;
03054            case ISP:
03055              tmpreg = 0x804;
03056              break;
03057            case MMUSR:
03058              tmpreg = 0x805;
03059              break;
03060            case URP:
03061              tmpreg = 0x806;
03062              break;
03063            case SRP:
03064              tmpreg = 0x807;
03065              break;
03066            case PCR:
03067              tmpreg = 0x808;
03068              break;
03069             case ROMBAR:
03070             case ROMBAR0:
03071              tmpreg = 0xC00;
03072              break;
03073             case ROMBAR1:
03074               tmpreg = 0xC01;
03075               break;
03076            case FLASHBAR:
03077            case RAMBAR0:
03078              tmpreg = 0xC04;
03079              break;
03080            case RAMBAR:
03081            case RAMBAR1:
03082              tmpreg = 0xC05;
03083              break;
03084             case MPCR:
03085               tmpreg = 0xC0C;
03086               break;
03087             case EDRAMBAR:
03088               tmpreg = 0xC0D;
03089               break;
03090             case MBAR0:
03091             case MBAR2:
03092             case SECMBAR:
03093               tmpreg = 0xC0E;
03094               break;
03095             case MBAR1:
03096            case MBAR:
03097              tmpreg = 0xC0F;
03098              break;
03099             case PCR1U0:
03100               tmpreg = 0xD02;
03101               break;
03102             case PCR1L0:
03103               tmpreg = 0xD03;
03104               break;
03105             case PCR2U0:
03106               tmpreg = 0xD04;
03107               break;
03108             case PCR2L0:
03109               tmpreg = 0xD05;
03110               break;
03111             case PCR3U0:
03112               tmpreg = 0xD06;
03113               break;
03114             case PCR3L0:
03115               tmpreg = 0xD07;
03116               break;
03117             case PCR1L1:
03118               tmpreg = 0xD0A;
03119               break;
03120             case PCR1U1:
03121               tmpreg = 0xD0B;
03122               break;
03123             case PCR2L1:
03124               tmpreg = 0xD0C;
03125               break;
03126             case PCR2U1:
03127               tmpreg = 0xD0D;
03128               break;
03129             case PCR3L1:
03130               tmpreg = 0xD0E;
03131               break;
03132             case PCR3U1:
03133               tmpreg = 0xD0F;
03134               break;
03135             case CAC:
03136               tmpreg = 0xFFE;
03137               break;
03138             case MBB:
03139               tmpreg = 0xFFF;
03140               break;
03141            default:
03142              abort ();
03143            }
03144          install_operand (s[1], tmpreg);
03145          break;
03146 
03147        case 'k':
03148          tmpreg = get_num (&opP->disp, 55);
03149          install_operand (s[1], tmpreg & 0x7f);
03150          break;
03151 
03152        case 'l':
03153          tmpreg = opP->mask;
03154          if (s[1] == 'w')
03155            {
03156              if (tmpreg & 0x7FF0000)
03157               as_bad (_("Floating point register in register list"));
03158              insop (reverse_16_bits (tmpreg), opcode);
03159            }
03160          else
03161            {
03162              if (tmpreg & 0x700FFFF)
03163               as_bad (_("Wrong register in floating-point reglist"));
03164              install_operand (s[1], reverse_8_bits (tmpreg >> 16));
03165            }
03166          break;
03167 
03168        case 'L':
03169          tmpreg = opP->mask;
03170          if (s[1] == 'w')
03171            {
03172              if (tmpreg & 0x7FF0000)
03173               as_bad (_("Floating point register in register list"));
03174              insop (tmpreg, opcode);
03175            }
03176          else if (s[1] == '8')
03177            {
03178              if (tmpreg & 0x0FFFFFF)
03179               as_bad (_("incorrect register in reglist"));
03180              install_operand (s[1], tmpreg >> 24);
03181            }
03182          else
03183            {
03184              if (tmpreg & 0x700FFFF)
03185               as_bad (_("wrong register in floating-point reglist"));
03186              else
03187               install_operand (s[1], tmpreg >> 16);
03188            }
03189          break;
03190 
03191        case 'M':
03192          install_operand (s[1], get_num (&opP->disp, 60));
03193          break;
03194 
03195        case 'O':
03196          tmpreg = ((opP->mode == DREG)
03197                   ? 0x20 + (int) (opP->reg - DATA)
03198                   : (get_num (&opP->disp, 40) & 0x1F));
03199          install_operand (s[1], tmpreg);
03200          break;
03201 
03202        case 'Q':
03203          tmpreg = get_num (&opP->disp, 10);
03204          if (tmpreg == 8)
03205            tmpreg = 0;
03206          install_operand (s[1], tmpreg);
03207          break;
03208 
03209        case 'R':
03210          /* This depends on the fact that ADDR registers are eight
03211             more than their corresponding DATA regs, so the result
03212             will have the ADDR_REG bit set.  */
03213          install_operand (s[1], opP->reg - DATA);
03214          break;
03215 
03216        case 'r':
03217          if (opP->mode == AINDR)
03218            install_operand (s[1], opP->reg - DATA);
03219          else
03220            install_operand (s[1], opP->index.reg - DATA);
03221          break;
03222 
03223        case 's':
03224          if (opP->reg == FPI)
03225            tmpreg = 0x1;
03226          else if (opP->reg == FPS)
03227            tmpreg = 0x2;
03228          else if (opP->reg == FPC)
03229            tmpreg = 0x4;
03230          else
03231            abort ();
03232          install_operand (s[1], tmpreg);
03233          break;
03234 
03235        case 'S':            /* Ignore it.  */
03236          break;
03237 
03238        case 'T':
03239          install_operand (s[1], get_num (&opP->disp, 30));
03240          break;
03241 
03242        case 'U':            /* Ignore it.  */
03243          break;
03244 
03245        case 'c':
03246          switch (opP->reg)
03247            {
03248            case NC:
03249              tmpreg = 0;
03250              break;
03251            case DC:
03252              tmpreg = 1;
03253              break;
03254            case IC:
03255              tmpreg = 2;
03256              break;
03257            case BC:
03258              tmpreg = 3;
03259              break;
03260            default:
03261              as_fatal (_("failed sanity check"));
03262            }                /* switch on cache token.  */
03263          install_operand (s[1], tmpreg);
03264          break;
03265 #ifndef NO_68851
03266          /* JF: These are out of order, I fear.  */
03267        case 'f':
03268          switch (opP->reg)
03269            {
03270            case SFC:
03271              tmpreg = 0;
03272              break;
03273            case DFC:
03274              tmpreg = 1;
03275              break;
03276            default:
03277              abort ();
03278            }
03279          install_operand (s[1], tmpreg);
03280          break;
03281 
03282        case '0':
03283        case '1':
03284        case '2':
03285          switch (opP->reg)
03286            {
03287            case TC:
03288              tmpreg = 0;
03289              break;
03290            case CAL:
03291              tmpreg = 4;
03292              break;
03293            case VAL:
03294              tmpreg = 5;
03295              break;
03296            case SCC:
03297              tmpreg = 6;
03298              break;
03299            case AC:
03300              tmpreg = 7;
03301              break;
03302            default:
03303              abort ();
03304            }
03305          install_operand (s[1], tmpreg);
03306          break;
03307 
03308        case 'V':
03309          if (opP->reg == VAL)
03310            break;
03311          abort ();
03312 
03313        case 'W':
03314          switch (opP->reg)
03315            {
03316            case DRP:
03317              tmpreg = 1;
03318              break;
03319            case SRP:
03320              tmpreg = 2;
03321              break;
03322            case CRP:
03323              tmpreg = 3;
03324              break;
03325            default:
03326              abort ();
03327            }
03328          install_operand (s[1], tmpreg);
03329          break;
03330 
03331        case 'X':
03332          switch (opP->reg)
03333            {
03334            case BAD:
03335            case BAD + 1:
03336            case BAD + 2:
03337            case BAD + 3:
03338            case BAD + 4:
03339            case BAD + 5:
03340            case BAD + 6:
03341            case BAD + 7:
03342              tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
03343              break;
03344 
03345            case BAC:
03346            case BAC + 1:
03347            case BAC + 2:
03348            case BAC + 3:
03349            case BAC + 4:
03350            case BAC + 5:
03351            case BAC + 6:
03352            case BAC + 7:
03353              tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
03354              break;
03355 
03356            default:
03357              abort ();
03358            }
03359          install_operand (s[1], tmpreg);
03360          break;
03361        case 'Y':
03362          know (opP->reg == PSR);
03363          break;
03364        case 'Z':
03365          know (opP->reg == PCSR);
03366          break;
03367 #endif /* m68851 */
03368        case '3':
03369          switch (opP->reg)
03370            {
03371            case TT0:
03372              tmpreg = 2;
03373              break;
03374            case TT1:
03375              tmpreg = 3;
03376              break;
03377            default:
03378              abort ();
03379            }
03380          install_operand (s[1], tmpreg);
03381          break;
03382        case 't':
03383          tmpreg = get_num (&opP->disp, 20);
03384          install_operand (s[1], tmpreg);
03385          break;
03386        case '_':     /* used only for move16 absolute 32-bit address.  */
03387          if (isvar (&opP->disp))
03388            add_fix ('l', &opP->disp, 0, 0);
03389          tmpreg = get_num (&opP->disp, 90);
03390          addword (tmpreg >> 16);
03391          addword (tmpreg & 0xFFFF);
03392          break;
03393        case 'u':
03394          install_operand (s[1], opP->reg - DATA0L);
03395          opP->reg -= (DATA0L);
03396          opP->reg &= 0x0F;  /* remove upper/lower bit.  */
03397          break;
03398        case 'x':
03399          tmpreg = get_num (&opP->disp, 80);
03400          if (tmpreg == -1)
03401            tmpreg = 0;
03402          install_operand (s[1], tmpreg);
03403          break;
03404        default:
03405          abort ();
03406        }
03407     }
03408 
03409   /* By the time whe get here (FINALLY) the_ins contains the complete
03410      instruction, ready to be emitted. . .  */
03411 }
03412 
03413 static int
03414 reverse_16_bits (int in)
03415 {
03416   int out = 0;
03417   int n;
03418 
03419   static int mask[16] =
03420   {
03421     0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
03422     0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
03423   };
03424   for (n = 0; n < 16; n++)
03425     {
03426       if (in & mask[n])
03427        out |= mask[15 - n];
03428     }
03429   return out;
03430 }                           /* reverse_16_bits() */
03431 
03432 static int
03433 reverse_8_bits (int in)
03434 {
03435   int out = 0;
03436   int n;
03437 
03438   static int mask[8] =
03439   {
03440     0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
03441   };
03442 
03443   for (n = 0; n < 8; n++)
03444     {
03445       if (in & mask[n])
03446        out |= mask[7 - n];
03447     }
03448   return out;
03449 }                           /* reverse_8_bits() */
03450 
03451 /* Cause an extra frag to be generated here, inserting up to 10 bytes
03452    (that value is chosen in the frag_var call in md_assemble).  TYPE
03453    is the subtype of the frag to be generated; its primary type is
03454    rs_machine_dependent.
03455 
03456    The TYPE parameter is also used by md_convert_frag_1 and
03457    md_estimate_size_before_relax.  The appropriate type of fixup will
03458    be emitted by md_convert_frag_1.
03459 
03460    ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
03461 static void
03462 install_operand (int mode, int val)
03463 {
03464   switch (mode)
03465     {
03466     case 's':
03467       the_ins.opcode[0] |= val & 0xFF;    /* JF FF is for M kludge.  */
03468       break;
03469     case 'd':
03470       the_ins.opcode[0] |= val << 9;
03471       break;
03472     case '1':
03473       the_ins.opcode[1] |= val << 12;
03474       break;
03475     case '2':
03476       the_ins.opcode[1] |= val << 6;
03477       break;
03478     case '3':
03479       the_ins.opcode[1] |= val;
03480       break;
03481     case '4':
03482       the_ins.opcode[2] |= val << 12;
03483       break;
03484     case '5':
03485       the_ins.opcode[2] |= val << 6;
03486       break;
03487     case '6':
03488       /* DANGER!  This is a hack to force cas2l and cas2w cmds to be
03489         three words long! */
03490       the_ins.numo++;
03491       the_ins.opcode[2] |= val;
03492       break;
03493     case '7':
03494       the_ins.opcode[1] |= val << 7;
03495       break;
03496     case '8':
03497       the_ins.opcode[1] |= val << 10;
03498       break;
03499 #ifndef NO_68851
03500     case '9':
03501       the_ins.opcode[1] |= val << 5;
03502       break;
03503 #endif
03504 
03505     case 't':
03506       the_ins.opcode[1] |= (val << 10) | (val << 7);
03507       break;
03508     case 'D':
03509       the_ins.opcode[1] |= (val << 12) | val;
03510       break;
03511     case 'g':
03512       the_ins.opcode[0] |= val = 0xff;
03513       break;
03514     case 'i':
03515       the_ins.opcode[0] |= val << 9;
03516       break;
03517     case 'C':
03518       the_ins.opcode[1] |= val;
03519       break;
03520     case 'j':
03521       the_ins.opcode[1] |= val;
03522       the_ins.numo++;              /* What a hack.  */
03523       break;
03524     case 'k':
03525       the_ins.opcode[1] |= val << 4;
03526       break;
03527     case 'b':
03528     case 'w':
03529     case 'W':
03530     case 'l':
03531       break;
03532     case 'e':
03533       the_ins.opcode[0] |= (val << 6);
03534       break;
03535     case 'L':
03536       the_ins.opcode[1] = (val >> 16);
03537       the_ins.opcode[2] = val & 0xffff;
03538       break;
03539     case 'm':
03540       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
03541       the_ins.opcode[0] |= ((val & 0x7) << 9);
03542       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
03543       break;
03544     case 'n': /* MAC/EMAC Rx on !load.  */
03545       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
03546       the_ins.opcode[0] |= ((val & 0x7) << 9);
03547       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
03548       break;
03549     case 'o': /* MAC/EMAC Rx on load.  */
03550       the_ins.opcode[1] |= val << 12;
03551       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
03552       break;
03553     case 'M': /* MAC/EMAC Ry on !load.  */
03554       the_ins.opcode[0] |= (val & 0xF);
03555       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
03556       break;
03557     case 'N': /* MAC/EMAC Ry on load.  */
03558       the_ins.opcode[1] |= (val & 0xF);
03559       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
03560       break;
03561     case 'h':
03562       the_ins.opcode[1] |= ((val != 1) << 10);
03563       break;
03564     case 'F':
03565       the_ins.opcode[0] |= ((val & 0x3) << 9);
03566       break;
03567     case 'f':
03568       the_ins.opcode[0] |= ((val & 0x3) << 0);
03569       break;
03570     case 'G':  /* EMAC accumulator in a EMAC load instruction.  */
03571       the_ins.opcode[0] |= ((~val & 0x1) << 7);
03572       the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
03573       break;
03574     case 'H':  /* EMAC accumulator in a EMAC non-load instruction.  */
03575       the_ins.opcode[0] |= ((val & 0x1) << 7);
03576       the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
03577       break;
03578     case 'I':
03579       the_ins.opcode[1] |= ((val & 0x3) << 9);
03580       break;
03581     case ']':
03582       the_ins.opcode[0] |= (val & 0x1) <<10;
03583       break;
03584     case 'c':
03585     default:
03586       as_fatal (_("failed sanity check."));
03587     }
03588 }
03589 
03590 static void
03591 install_gen_operand (int mode, int val)
03592 {
03593   switch (mode)
03594     {
03595     case '/':  /* Special for mask loads for mac/msac insns with
03596                 possible mask; trailing_ampersend set in bit 8.  */
03597       the_ins.opcode[0] |= (val & 0x3f);
03598       the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
03599       break;
03600     case 's':
03601       the_ins.opcode[0] |= val;
03602       break;
03603     case 'd':
03604       /* This is a kludge!!! */
03605       the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
03606       break;
03607     case 'b':
03608     case 'w':
03609     case 'l':
03610     case 'f':
03611     case 'F':
03612     case 'x':
03613     case 'p':
03614       the_ins.opcode[0] |= val;
03615       break;
03616       /* more stuff goes here.  */
03617     default:
03618       as_fatal (_("failed sanity check."));
03619     }
03620 }
03621 
03622 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
03623    then deal with the bitfield hack.  */
03624 
03625 static char *
03626 crack_operand (char *str, struct m68k_op *opP)
03627 {
03628   register int parens;
03629   register int c;
03630   register char *beg_str;
03631   int inquote = 0;
03632 
03633   if (!str)
03634     {
03635       return str;
03636     }
03637   beg_str = str;
03638   for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
03639     {
03640       if (! inquote)
03641        {
03642          if (*str == '(')
03643            parens++;
03644          else if (*str == ')')
03645            {
03646              if (!parens)
03647               {                    /* ERROR.  */
03648                 opP->error = _("Extra )");
03649                 return str;
03650               }
03651              --parens;
03652            }
03653        }
03654       if (flag_mri && *str == '\'')
03655        inquote = ! inquote;
03656     }
03657   if (!*str && parens)
03658     {                       /* ERROR.  */
03659       opP->error = _("Missing )");
03660       return str;
03661     }
03662   c = *str;
03663   *str = '\0';
03664   if (m68k_ip_op (beg_str, opP) != 0)
03665     {
03666       *str = c;
03667       return str;
03668     }
03669   *str = c;
03670   if (c == '}')
03671     c = *++str;                    /* JF bitfield hack.  */
03672   if (c)
03673     {
03674       c = *++str;
03675       if (!c)
03676        as_bad (_("Missing operand"));
03677     }
03678 
03679   /* Detect MRI REG symbols and convert them to REGLSTs.  */
03680   if (opP->mode == CONTROL && (int)opP->reg < 0)
03681     {
03682       opP->mode = REGLST;
03683       opP->mask = ~(int)opP->reg;
03684       opP->reg = 0;
03685     }
03686 
03687   return str;
03688 }
03689 
03690 /* This is the guts of the machine-dependent assembler.  STR points to a
03691    machine dependent instruction.  This function is supposed to emit
03692    the frags/bytes it assembles to.
03693    */
03694 
03695 static void
03696 insert_reg (const char *regname, int regnum)
03697 {
03698   char buf[100];
03699   int i;
03700 
03701 #ifdef REGISTER_PREFIX
03702   if (!flag_reg_prefix_optional)
03703     {
03704       buf[0] = REGISTER_PREFIX;
03705       strcpy (buf + 1, regname);
03706       regname = buf;
03707     }
03708 #endif
03709 
03710   symbol_table_insert (symbol_new (regname, reg_section, regnum,
03711                                &zero_address_frag));
03712 
03713   for (i = 0; regname[i]; i++)
03714     buf[i] = TOUPPER (regname[i]);
03715   buf[i] = '\0';
03716 
03717   symbol_table_insert (symbol_new (buf, reg_section, regnum,
03718                                &zero_address_frag));
03719 }
03720 
03721 struct init_entry
03722   {
03723     const char *name;
03724     int number;
03725   };
03726 
03727 static const struct init_entry init_table[] =
03728 {
03729   { "d0", DATA0 },
03730   { "d1", DATA1 },
03731   { "d2", DATA2 },
03732   { "d3", DATA3 },
03733   { "d4", DATA4 },
03734   { "d5", DATA5 },
03735   { "d6", DATA6 },
03736   { "d7", DATA7 },
03737   { "a0", ADDR0 },
03738   { "a1", ADDR1 },
03739   { "a2", ADDR2 },
03740   { "a3", ADDR3 },
03741   { "a4", ADDR4 },
03742   { "a5", ADDR5 },
03743   { "a6", ADDR6 },
03744   { "fp", ADDR6 },
03745   { "a7", ADDR7 },
03746   { "sp", ADDR7 },
03747   { "ssp", ADDR7 },
03748   { "fp0", FP0 },
03749   { "fp1", FP1 },
03750   { "fp2", FP2 },
03751   { "fp3", FP3 },
03752   { "fp4", FP4 },
03753   { "fp5", FP5 },
03754   { "fp6", FP6 },
03755   { "fp7", FP7 },
03756   { "fpi", FPI },
03757   { "fpiar", FPI },
03758   { "fpc", FPI },
03759   { "fps", FPS },
03760   { "fpsr", FPS },
03761   { "fpc", FPC },
03762   { "fpcr", FPC },
03763   { "control", FPC },
03764   { "status", FPS },
03765   { "iaddr", FPI },
03766 
03767   { "cop0", COP0 },
03768   { "cop1", COP1 },
03769   { "cop2", COP2 },
03770   { "cop3", COP3 },
03771   { "cop4", COP4 },
03772   { "cop5", COP5 },
03773   { "cop6", COP6 },
03774   { "cop7", COP7 },
03775   { "pc", PC },
03776   { "zpc", ZPC },
03777   { "sr", SR },
03778 
03779   { "ccr", CCR },
03780   { "cc", CCR },
03781 
03782   { "acc", ACC },
03783   { "acc0", ACC },
03784   { "acc1", ACC1 },
03785   { "acc2", ACC2 },
03786   { "acc3", ACC3 },
03787   { "accext01", ACCEXT01 },
03788   { "accext23", ACCEXT23 },
03789   { "macsr", MACSR },
03790   { "mask", MASK },
03791 
03792   /* Control registers.  */
03793   { "sfc", SFC },           /* Source Function Code.  */
03794   { "sfcr", SFC },
03795   { "dfc", DFC },           /* Destination Function Code.  */
03796   { "dfcr", DFC },
03797   { "cacr", CACR },         /* Cache Control Register.  */
03798   { "caar", CAAR },         /* Cache Address Register.  */
03799 
03800   { "usp", USP },           /* User Stack Pointer.  */
03801   { "vbr", VBR },           /* Vector Base Register.  */
03802   { "msp", MSP },           /* Master Stack Pointer.  */
03803   { "isp", ISP },           /* Interrupt Stack Pointer.  */
03804 
03805   { "itt0", ITT0 },         /* Instruction Transparent Translation Reg 0.  */
03806   { "itt1", ITT1 },         /* Instruction Transparent Translation Reg 1.  */
03807   { "dtt0", DTT0 },         /* Data Transparent Translation Register 0.  */
03808   { "dtt1", DTT1 },         /* Data Transparent Translation Register 1.  */
03809 
03810   /* 68ec040 versions of same */
03811   { "iacr0", ITT0 },        /* Instruction Access Control Register 0.  */
03812   { "iacr1", ITT1 },        /* Instruction Access Control Register 0.  */
03813   { "dacr0", DTT0 },        /* Data Access Control Register 0.  */
03814   { "dacr1", DTT1 },        /* Data Access Control Register 0.  */
03815 
03816   /* Coldfire versions of same.  The ColdFire programmer's reference
03817      manual indicated that the order is 2,3,0,1, but Ken Rose
03818      <rose@netcom.com> says that 0,1,2,3 is the correct order.  */
03819   { "acr0", ACR0 },         /* Access Control Unit 0.  */
03820   { "acr1", ACR1 },         /* Access Control Unit 1.  */
03821   { "acr2", ACR2 },         /* Access Control Unit 2.  */
03822   { "acr3", ACR3 },         /* Access Control Unit 3.  */
03823 
03824   { "tc", TC },                    /* MMU Translation Control Register.  */
03825   { "tcr", TC },
03826   { "asid", ASID },
03827 
03828   { "mmusr", MMUSR },              /* MMU Status Register.  */
03829   { "srp", SRP },           /* User Root Pointer.  */
03830   { "urp", URP },           /* Supervisor Root Pointer.  */
03831 
03832   { "buscr", BUSCR },
03833   { "mmubar", MMUBAR },
03834   { "pcr", PCR },
03835 
03836   { "rombar", ROMBAR },            /* ROM Base Address Register.  */
03837   { "rambar0", RAMBAR0 },   /* ROM Base Address Register.  */
03838   { "rambar1", RAMBAR1 },   /* ROM Base Address Register.  */
03839   { "mbar", MBAR },         /* Module Base Address Register.  */
03840 
03841   { "mbar0",    MBAR0 },    /* mcfv4e registers.  */
03842   { "mbar1",    MBAR1 },    /* mcfv4e registers.  */
03843   { "rombar0",  ROMBAR0 },  /* mcfv4e registers.  */
03844   { "rombar1",  ROMBAR1 },  /* mcfv4e registers.  */
03845   { "mpcr",     MPCR },            /* mcfv4e registers.  */
03846   { "edrambar", EDRAMBAR }, /* mcfv4e registers.  */
03847   { "secmbar",  SECMBAR },  /* mcfv4e registers.  */
03848   { "asid",     TC },              /* mcfv4e registers.  */
03849   { "mmubar",   BUSCR },    /* mcfv4e registers.  */
03850   { "pcr1u0",   PCR1U0 },   /* mcfv4e registers.  */
03851   { "pcr1l0",   PCR1L0 },   /* mcfv4e registers.  */
03852   { "pcr2u0",   PCR2U0 },   /* mcfv4e registers.  */
03853   { "pcr2l0",   PCR2L0 },   /* mcfv4e registers.  */
03854   { "pcr3u0",   PCR3U0 },   /* mcfv4e registers.  */
03855   { "pcr3l0",   PCR3L0 },   /* mcfv4e registers.  */
03856   { "pcr1u1",   PCR1U1 },   /* mcfv4e registers.  */
03857   { "pcr1l1",   PCR1L1 },   /* mcfv4e registers.  */
03858   { "pcr2u1",   PCR2U1 },   /* mcfv4e registers.  */
03859   { "pcr2l1",   PCR2L1 },   /* mcfv4e registers.  */
03860   { "pcr3u1",   PCR3U1 },   /* mcfv4e registers.  */
03861   { "pcr3l1",   PCR3L1 },   /* mcfv4e registers.  */
03862 
03863   { "flashbar", FLASHBAR },        /* mcf528x registers.  */
03864   { "rambar",   RAMBAR },   /* mcf528x registers.  */
03865 
03866   { "mbar2",    MBAR2 },    /* mcf5249 registers.  */
03867 
03868   { "cac",    CAC },               /* fido registers.  */
03869   { "mbb",    MBB },               /* fido registers.  */
03870   /* End of control registers.  */
03871 
03872   { "ac", AC },
03873   { "bc", BC },
03874   { "cal", CAL },
03875   { "crp", CRP },
03876   { "drp", DRP },
03877   { "pcsr", PCSR },
03878   { "psr", PSR },
03879   { "scc", SCC },
03880   { "val", VAL },
03881   { "bad0", BAD0 },
03882   { "bad1", BAD1 },
03883   { "bad2", BAD2 },
03884   { "bad3", BAD3 },
03885   { "bad4", BAD4 },
03886   { "bad5", BAD5 },
03887   { "bad6", BAD6 },
03888   { "bad7", BAD7 },
03889   { "bac0", BAC0 },
03890   { "bac1", BAC1 },
03891   { "bac2", BAC2 },
03892   { "bac3", BAC3 },
03893   { "bac4", BAC4 },
03894   { "bac5", BAC5 },
03895   { "bac6", BAC6 },
03896   { "bac7", BAC7 },
03897 
03898   { "ic", IC },
03899   { "dc", DC },
03900   { "nc", NC },
03901 
03902   { "tt0", TT0 },
03903   { "tt1", TT1 },
03904   /* 68ec030 versions of same.  */
03905   { "ac0", TT0 },
03906   { "ac1", TT1 },
03907   /* 68ec030 access control unit, identical to 030 MMU status reg.  */
03908   { "acusr", PSR },
03909 
03910   /* Suppressed data and address registers.  */
03911   { "zd0", ZDATA0 },
03912   { "zd1", ZDATA1 },
03913   { "zd2", ZDATA2 },
03914   { "zd3", ZDATA3 },
03915   { "zd4", ZDATA4 },
03916   { "zd5", ZDATA5 },
03917   { "zd6", ZDATA6 },
03918   { "zd7", ZDATA7 },
03919   { "za0", ZADDR0 },
03920   { "za1", ZADDR1 },
03921   { "za2", ZADDR2 },
03922   { "za3", ZADDR3 },
03923   { "za4", ZADDR4 },
03924   { "za5", ZADDR5 },
03925   { "za6", ZADDR6 },
03926   { "za7", ZADDR7 },
03927 
03928   /* Upper and lower data and address registers, used by macw and msacw.  */
03929   { "d0l", DATA0L },
03930   { "d1l", DATA1L },
03931   { "d2l", DATA2L },
03932   { "d3l", DATA3L },
03933   { "d4l", DATA4L },
03934   { "d5l", DATA5L },
03935   { "d6l", DATA6L },
03936   { "d7l", DATA7L },
03937 
03938   { "a0l", ADDR0L },
03939   { "a1l", ADDR1L },
03940   { "a2l", ADDR2L },
03941   { "a3l", ADDR3L },
03942   { "a4l", ADDR4L },
03943   { "a5l", ADDR5L },
03944   { "a6l", ADDR6L },
03945   { "a7l", ADDR7L },
03946 
03947   { "d0u", DATA0U },
03948   { "d1u", DATA1U },
03949   { "d2u", DATA2U },
03950   { "d3u", DATA3U },
03951   { "d4u", DATA4U },
03952   { "d5u", DATA5U },
03953   { "d6u", DATA6U },
03954   { "d7u", DATA7U },
03955 
03956   { "a0u", ADDR0U },
03957   { "a1u", ADDR1U },
03958   { "a2u", ADDR2U },
03959   { "a3u", ADDR3U },
03960   { "a4u", ADDR4U },
03961   { "a5u", ADDR5U },
03962   { "a6u", ADDR6U },
03963   { "a7u", ADDR7U },
03964 
03965   { 0, 0 }
03966 };
03967 
03968 static void
03969 init_regtable (void)
03970 {
03971   int i;
03972   for (i = 0; init_table[i].name; i++)
03973     insert_reg (init_table[i].name, init_table[i].number);
03974 }
03975 
03976 void
03977 md_assemble (char *str)
03978 {
03979   const char *er;
03980   short *fromP;
03981   char *toP = NULL;
03982   int m, n = 0;
03983   char *to_beg_P;
03984   int shorts_this_frag;
03985   fixS *fixP;
03986 
03987   if (!selected_cpu && !selected_arch)
03988     {
03989       /* We've not selected an architecture yet.  Set the default
03990         now.  We do this lazily so that an initial .cpu or .arch directive
03991         can specify.  */
03992       if (!m68k_set_cpu (TARGET_CPU, 1, 1))
03993        as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
03994     }
03995   if (!initialized)
03996     m68k_init_arch ();
03997   
03998   /* In MRI mode, the instruction and operands are separated by a
03999      space.  Anything following the operands is a comment.  The label
04000      has already been removed.  */
04001   if (flag_mri)
04002     {
04003       char *s;
04004       int fields = 0;
04005       int infield = 0;
04006       int inquote = 0;
04007 
04008       for (s = str; *s != '\0'; s++)
04009        {
04010          if ((*s == ' ' || *s == '\t') && ! inquote)
04011            {
04012              if (infield)
04013               {
04014                 ++fields;
04015                 if (fields >= 2)
04016                   {
04017                     *s = '\0';
04018                     break;
04019                   }
04020                 infield = 0;
04021               }
04022            }
04023          else
04024            {
04025              if (! infield)
04026               infield = 1;
04027              if (*s == '\'')
04028               inquote = ! inquote;
04029            }
04030        }
04031     }
04032 
04033   memset (&the_ins, '\0', sizeof (the_ins));
04034   m68k_ip (str);
04035   er = the_ins.error;
04036   if (!er)
04037     {
04038       for (n = 0; n < the_ins.numargs; n++)
04039        if (the_ins.operands[n].error)
04040          {
04041            er = the_ins.operands[n].error;
04042            break;
04043          }
04044     }
04045   if (er)
04046     {
04047       as_bad (_("%s -- statement `%s' ignored"), er, str);
04048       return;
04049     }
04050 
04051   /* If there is a current label, record that it marks an instruction.  */
04052   if (current_label != NULL)
04053     {
04054       current_label->text = 1;
04055       current_label = NULL;
04056     }
04057 
04058 #ifdef OBJ_ELF
04059   /* Tie dwarf2 debug info to the address at the start of the insn.  */
04060   dwarf2_emit_insn (0);
04061 #endif
04062 
04063   if (the_ins.nfrag == 0)
04064     {
04065       /* No frag hacking involved; just put it out.  */
04066       toP = frag_more (2 * the_ins.numo);
04067       fromP = &the_ins.opcode[0];
04068       for (m = the_ins.numo; m; --m)
04069        {
04070          md_number_to_chars (toP, (long) (*fromP), 2);
04071          toP += 2;
04072          fromP++;
04073        }
04074       /* Put out symbol-dependent info.  */
04075       for (m = 0; m < the_ins.nrel; m++)
04076        {
04077          switch (the_ins.reloc[m].wid)
04078            {
04079            case 'B':
04080              n = 1;
04081              break;
04082            case 'b':
04083              n = 1;
04084              break;
04085            case '3':
04086              n = 1;
04087              break;
04088            case 'w':
04089            case 'W':
04090              n = 2;
04091              break;
04092            case 'l':
04093              n = 4;
04094              break;
04095            default:
04096              as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
04097                      the_ins.reloc[m].wid);
04098            }
04099 
04100          fixP = fix_new_exp (frag_now,
04101                            ((toP - frag_now->fr_literal)
04102                             - the_ins.numo * 2 + the_ins.reloc[m].n),
04103                            n,
04104                            &the_ins.reloc[m].exp,
04105                            the_ins.reloc[m].pcrel,
04106                            get_reloc_code (n, the_ins.reloc[m].pcrel,
04107                                          the_ins.reloc[m].pic_reloc));
04108          fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
04109          if (the_ins.reloc[m].wid == 'B')
04110            fixP->fx_signed = 1;
04111        }
04112       return;
04113     }
04114 
04115   /* There's some frag hacking.  */
04116   {
04117     /* Calculate the max frag size.  */
04118     int wid;
04119 
04120     wid = 2 * the_ins.fragb[0].fragoff;
04121     for (n = 1; n < the_ins.nfrag; n++)
04122       wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
04123     /* frag_var part.  */
04124     wid += 10;
04125     /* Make sure the whole insn fits in one chunk, in particular that
04126        the var part is attached, as we access one byte before the
04127        variable frag for byte branches.  */
04128     frag_grow (wid);
04129   }
04130 
04131   for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
04132     {
04133       int wid;
04134 
04135       if (n == 0)
04136        wid = 2 * the_ins.fragb[n].fragoff;
04137       else
04138        wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
04139       toP = frag_more (wid);
04140       to_beg_P = toP;
04141       shorts_this_frag = 0;
04142       for (m = wid / 2; m; --m)
04143        {
04144          md_number_to_chars (toP, (long) (*fromP), 2);
04145          toP += 2;
04146          fromP++;
04147          shorts_this_frag++;
04148        }
04149       for (m = 0; m < the_ins.nrel; m++)
04150        {
04151          if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
04152            {
04153              the_ins.reloc[m].n -= 2 * shorts_this_frag;
04154              break;
04155            }
04156          wid = the_ins.reloc[m].wid;
04157          if (wid == 0)
04158            continue;
04159          the_ins.reloc[m].wid = 0;
04160          wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
04161 
04162          fixP = fix_new_exp (frag_now,
04163                            ((toP - frag_now->fr_literal)
04164                             - the_ins.numo * 2 + the_ins.reloc[m].n),
04165                            wid,
04166                            &the_ins.reloc[m].exp,
04167                            the_ins.reloc[m].pcrel,
04168                            get_reloc_code (wid, the_ins.reloc[m].pcrel,
04169                                          the_ins.reloc[m].pic_reloc));
04170          fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
04171        }
04172       (void) frag_var (rs_machine_dependent, 10, 0,
04173                      (relax_substateT) (the_ins.fragb[n].fragty),
04174                      the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
04175     }
04176   n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
04177   shorts_this_frag = 0;
04178   if (n)
04179     {
04180       toP = frag_more (n * 2);
04181       while (n--)
04182        {
04183          md_number_to_chars (toP, (long) (*fromP), 2);
04184          toP += 2;
04185          fromP++;
04186          shorts_this_frag++;
04187        }
04188     }
04189   for (m = 0; m < the_ins.nrel; m++)
04190     {
04191       int wid;
04192 
04193       wid = the_ins.reloc[m].wid;
04194       if (wid == 0)
04195        continue;
04196       the_ins.reloc[m].wid = 0;
04197       wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
04198 
04199       fixP = fix_new_exp (frag_now,
04200                        ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
04201                         - shorts_this_frag * 2),
04202                        wid,
04203                        &the_ins.reloc[m].exp,
04204                        the_ins.reloc[m].pcrel,
04205                        get_reloc_code (wid, the_ins.reloc[m].pcrel,
04206                                      the_ins.reloc[m].pic_reloc));
04207       fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
04208     }
04209 }
04210 
04211 /* Comparison function used by qsort to rank the opcode entries by name.  */
04212 
04213 static int
04214 m68k_compare_opcode (const void * v1, const void * v2)
04215 {
04216   struct m68k_opcode * op1, * op2;
04217   int ret;
04218 
04219   if (v1 == v2)
04220     return 0;
04221 
04222   op1 = *(struct m68k_opcode **) v1;
04223   op2 = *(struct m68k_opcode **) v2;
04224 
04225   /* Compare the two names.  If different, return the comparison.
04226      If the same, return the order they are in the opcode table.  */
04227   ret = strcmp (op1->name, op2->name);
04228   if (ret)
04229     return ret;
04230   if (op1 < op2)
04231     return -1;
04232   return 1;
04233 }
04234 
04235 void
04236 md_begin (void)
04237 {
04238   const struct m68k_opcode *ins;
04239   struct m68k_incant *hack, *slak;
04240   const char *retval = 0;   /* Empty string, or error msg text.  */
04241   int i;
04242 
04243   /* Set up hash tables with 68000 instructions.
04244      similar to what the vax assembler does.  */
04245   /* RMS claims the thing to do is take the m68k-opcode.h table, and make
04246      a copy of it at runtime, adding in the information we want but isn't
04247      there.  I think it'd be better to have an awk script hack the table
04248      at compile time.  Or even just xstr the table and use it as-is.  But
04249      my lord ghod hath spoken, so we do it this way.  Excuse the ugly var
04250      names.  */
04251 
04252   if (flag_mri)
04253     {
04254       flag_reg_prefix_optional = 1;
04255       m68k_abspcadd = 1;
04256       if (! m68k_rel32_from_cmdline)
04257        m68k_rel32 = 0;
04258     }
04259 
04260   /* First sort the opcode table into alphabetical order to seperate
04261      the order that the assembler wants to see the opcodes from the
04262      order that the disassembler wants to see them.  */
04263   m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
04264   if (!m68k_sorted_opcodes)
04265     as_fatal (_("Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"),
04266              m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
04267 
04268   for (i = m68k_numopcodes; i--;)
04269     m68k_sorted_opcodes[i] = m68k_opcodes + i;
04270 
04271   qsort (m68k_sorted_opcodes, m68k_numopcodes,
04272         sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
04273 
04274   op_hash = hash_new ();
04275 
04276   obstack_begin (&robyn, 4000);
04277   for (i = 0; i < m68k_numopcodes; i++)
04278     {
04279       hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
04280       do
04281        {
04282          ins = m68k_sorted_opcodes[i];
04283 
04284          /* We *could* ignore insns that don't match our
04285             arch here by just leaving them out of the hash.  */
04286          slak->m_operands = ins->args;
04287          slak->m_opnum = strlen (slak->m_operands) / 2;
04288          slak->m_arch = ins->arch;
04289          slak->m_opcode = ins->opcode;
04290          /* This is kludgey.  */
04291          slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
04292          if (i + 1 != m68k_numopcodes
04293              && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
04294            {
04295              slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
04296              i++;
04297            }
04298          else
04299            slak->m_next = 0;
04300          slak = slak->m_next;
04301        }
04302       while (slak);
04303 
04304       retval = hash_insert (op_hash, ins->name, (char *) hack);
04305       if (retval)
04306        as_fatal (_("Internal Error:  Can't hash %s: %s"), ins->name, retval);
04307     }
04308 
04309   for (i = 0; i < m68k_numaliases; i++)
04310     {
04311       const char *name = m68k_opcode_aliases[i].primary;
04312       const char *alias = m68k_opcode_aliases[i].alias;
04313       PTR val = hash_find (op_hash, name);
04314 
04315       if (!val)
04316        as_fatal (_("Internal Error: Can't find %s in hash table"), name);
04317       retval = hash_insert (op_hash, alias, val);
04318       if (retval)
04319        as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
04320     }
04321 
04322   /* In MRI mode, all unsized branches are variable sized.  Normally,
04323      they are word sized.  */
04324   if (flag_mri)
04325     {
04326       static struct m68k_opcode_alias mri_aliases[] =
04327        {
04328          { "bhi",    "jhi", },
04329          { "bls",    "jls", },
04330          { "bcc",    "jcc", },
04331          { "bcs",    "jcs", },
04332          { "bne",    "jne", },
04333          { "beq",    "jeq", },
04334          { "bvc",    "jvc", },
04335          { "bvs",    "jvs", },
04336          { "bpl",    "jpl", },
04337          { "bmi",    "jmi", },
04338          { "bge",    "jge", },
04339          { "blt",    "jlt", },
04340          { "bgt",    "jgt", },
04341          { "ble",    "jle", },
04342          { "bra",    "jra", },
04343          { "bsr",    "jbsr", },
04344        };
04345 
04346       for (i = 0;
04347           i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
04348           i++)
04349        {
04350          const char *name = mri_aliases[i].primary;
04351          const char *alias = mri_aliases[i].alias;
04352          PTR val = hash_find (op_hash, name);
04353 
04354          if (!val)
04355            as_fatal (_("Internal Error: Can't find %s in hash table"), name);
04356          retval = hash_jam (op_hash, alias, val);
04357          if (retval)
04358            as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
04359        }
04360     }
04361 
04362   for (i = 0; i < (int) sizeof (notend_table); i++)
04363     {
04364       notend_table[i] = 0;
04365       alt_notend_table[i] = 0;
04366     }
04367 
04368   notend_table[','] = 1;
04369   notend_table['{'] = 1;
04370   notend_table['}'] = 1;
04371   alt_notend_table['a'] = 1;
04372   alt_notend_table['A'] = 1;
04373   alt_notend_table['d'] = 1;
04374   alt_notend_table['D'] = 1;
04375   alt_notend_table['#'] = 1;
04376   alt_notend_table['&'] = 1;
04377   alt_notend_table['f'] = 1;
04378   alt_notend_table['F'] = 1;
04379 #ifdef REGISTER_PREFIX
04380   alt_notend_table[REGISTER_PREFIX] = 1;
04381 #endif
04382 
04383   /* We need to put '(' in alt_notend_table to handle
04384        cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)  */
04385   alt_notend_table['('] = 1;
04386 
04387   /* We need to put '@' in alt_notend_table to handle
04388        cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)  */
04389   alt_notend_table['@'] = 1;
04390 
04391   /* We need to put digits in alt_notend_table to handle
04392        bfextu %d0{24:1},%d0  */
04393   alt_notend_table['0'] = 1;
04394   alt_notend_table['1'] = 1;
04395   alt_notend_table['2'] = 1;
04396   alt_notend_table['3'] = 1;
04397   alt_notend_table['4'] = 1;
04398   alt_notend_table['5'] = 1;
04399   alt_notend_table['6'] = 1;
04400   alt_notend_table['7'] = 1;
04401   alt_notend_table['8'] = 1;
04402   alt_notend_table['9'] = 1;
04403 
04404 #ifndef MIT_SYNTAX_ONLY
04405   /* Insert pseudo ops, these have to go into the opcode table since
04406      gas expects pseudo ops to start with a dot.  */
04407   {
04408     int n = 0;
04409 
04410     while (mote_pseudo_table[n].poc_name)
04411       {
04412        hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
04413        hash_insert (op_hash,
04414                    mote_pseudo_table[n].poc_name, (char *) hack);
04415        hack->m_operands = 0;
04416        hack->m_opnum = n;
04417        n++;
04418       }
04419   }
04420 #endif
04421 
04422   init_regtable ();
04423 
04424 #ifdef OBJ_ELF
04425   record_alignment (text_section, 2);
04426   record_alignment (data_section, 2);
04427   record_alignment (bss_section, 2);
04428 #endif
04429 }
04430 
04431 
04432 /* This is called when a label is defined.  */
04433 
04434 void
04435 m68k_frob_label (symbolS *sym)
04436 {
04437   struct label_line *n;
04438 
04439   n = (struct label_line *) xmalloc (sizeof *n);
04440   n->next = labels;
04441   n->label = sym;
04442   as_where (&n->file, &n->line);
04443   n->text = 0;
04444   labels = n;
04445   current_label = n;
04446 
04447 #ifdef OBJ_ELF
04448   dwarf2_emit_label (sym);
04449 #endif
04450 }
04451 
04452 /* This is called when a value that is not an instruction is emitted.  */
04453 
04454 void
04455 m68k_flush_pending_output (void)
04456 {
04457   current_label = NULL;
04458 }
04459 
04460 /* This is called at the end of the assembly, when the final value of
04461    the label is known.  We warn if this is a text symbol aligned at an
04462    odd location.  */
04463 
04464 void
04465 m68k_frob_symbol (symbolS *sym)
04466 {
04467   if (S_GET_SEGMENT (sym) == reg_section
04468       && (int) S_GET_VALUE (sym) < 0)
04469     {
04470       S_SET_SEGMENT (sym, absolute_section);
04471       S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
04472     }
04473   else if ((S_GET_VALUE (sym) & 1) != 0)
04474     {
04475       struct label_line *l;
04476 
04477       for (l = labels; l != NULL; l = l->next)
04478        {
04479          if (l->label == sym)
04480            {
04481              if (l->text)
04482               as_warn_where (l->file, l->line,
04483                             _("text label `%s' aligned to odd boundary"),
04484                             S_GET_NAME (sym));
04485              break;
04486            }
04487        }
04488     }
04489 }
04490 
04491 /* This is called if we go in or out of MRI mode because of the .mri
04492    pseudo-op.  */
04493 
04494 void
04495 m68k_mri_mode_change (int on)
04496 {
04497   if (on)
04498     {
04499       if (! flag_reg_prefix_optional)
04500        {
04501          flag_reg_prefix_optional = 1;
04502 #ifdef REGISTER_PREFIX
04503          init_regtable ();
04504 #endif
04505        }
04506       m68k_abspcadd = 1;
04507       if (! m68k_rel32_from_cmdline)
04508        m68k_rel32 = 0;
04509     }
04510   else
04511     {
04512       if (! reg_prefix_optional_seen)
04513        {
04514 #ifdef REGISTER_PREFIX_OPTIONAL
04515          flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
04516 #else
04517          flag_reg_prefix_optional = 0;
04518 #endif
04519 #ifdef REGISTER_PREFIX
04520          init_regtable ();
04521 #endif
04522        }
04523       m68k_abspcadd = 0;
04524       if (! m68k_rel32_from_cmdline)
04525        m68k_rel32 = 1;
04526     }
04527 }
04528 
04529 /* Equal to MAX_PRECISION in atof-ieee.c.  */
04530 #define MAX_LITTLENUMS 6
04531 
04532 /* Turn a string in input_line_pointer into a floating point constant
04533    of type TYPE, and store the appropriate bytes in *LITP.  The number
04534    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
04535    returned, or NULL on OK.  */
04536 
04537 char *
04538 md_atof (int type, char *litP, int *sizeP)
04539 {
04540   int prec;
04541   LITTLENUM_TYPE words[MAX_LITTLENUMS];
04542   LITTLENUM_TYPE *wordP;
04543   char *t;
04544 
04545   switch (type)
04546     {
04547     case 'f':
04548     case 'F':
04549     case 's':
04550     case 'S':
04551       prec = 2;
04552       break;
04553 
04554     case 'd':
04555     case 'D':
04556     case 'r':
04557     case 'R':
04558       prec = 4;
04559       break;
04560 
04561     case 'x':
04562     case 'X':
04563       prec = 6;
04564       break;
04565 
04566     case 'p':
04567     case 'P':
04568       prec = 6;
04569       break;
04570 
04571     default:
04572       *sizeP = 0;
04573       return _("Bad call to MD_ATOF()");
04574     }
04575   t = atof_ieee (input_line_pointer, type, words);
04576   if (t)
04577     input_line_pointer = t;
04578 
04579   *sizeP = prec * sizeof (LITTLENUM_TYPE);
04580   for (wordP = words; prec--;)
04581     {
04582       md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
04583       litP += sizeof (LITTLENUM_TYPE);
04584     }
04585   return 0;
04586 }
04587 
04588 void
04589 md_number_to_chars (char *buf, valueT val, int n)
04590 {
04591   number_to_chars_bigendian (buf, val, n);
04592 }
04593 
04594 void
04595 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
04596 {
04597   offsetT val = *valP;
04598   addressT upper_limit;
04599   offsetT lower_limit;
04600 
04601   /* This is unnecessary but it convinces the native rs6000 compiler
04602      to generate the code we want.  */
04603   char *buf = fixP->fx_frag->fr_literal;
04604   buf += fixP->fx_where;
04605   /* End ibm compiler workaround.  */
04606 
04607   val = SEXT (val);
04608 
04609   if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
04610     fixP->fx_done = 1;
04611 
04612 #ifdef OBJ_ELF
04613   if (fixP->fx_addsy)
04614     {
04615       memset (buf, 0, fixP->fx_size);
04616       fixP->fx_addnumber = val;    /* Remember value for emit_reloc.  */
04617 
04618       if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
04619          && !S_IS_DEFINED (fixP->fx_addsy)
04620          && !S_IS_WEAK (fixP->fx_addsy))
04621        S_SET_WEAK (fixP->fx_addsy);
04622       return;
04623     }
04624 #endif
04625 
04626   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
04627       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
04628     return;
04629 
04630   switch (fixP->fx_size)
04631     {
04632       /* The cast to offsetT below are necessary to make code
04633         correct for machines where ints are smaller than offsetT.  */
04634     case 1:
04635       *buf++ = val;
04636       upper_limit = 0x7f;
04637       lower_limit = - (offsetT) 0x80;
04638       break;
04639     case 2:
04640       *buf++ = (val >> 8);
04641       *buf++ = val;
04642       upper_limit = 0x7fff;
04643       lower_limit = - (offsetT) 0x8000;
04644       break;
04645     case 4:
04646       *buf++ = (val >> 24);
04647       *buf++ = (val >> 16);
04648       *buf++ = (val >> 8);
04649       *buf++ = val;
04650       upper_limit = 0x7fffffff;
04651       lower_limit = - (offsetT) 0x7fffffff - 1;  /* Avoid constant overflow.  */
04652       break;
04653     default:
04654       BAD_CASE (fixP->fx_size);
04655     }
04656 
04657   /* Fix up a negative reloc.  */
04658   if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
04659     {
04660       fixP->fx_addsy = fixP->fx_subsy;
04661       fixP->fx_subsy = NULL;
04662       fixP->fx_tcbit = 1;
04663     }
04664 
04665   /* For non-pc-relative values, it's conceivable we might get something
04666      like "0xff" for a byte field.  So extend the upper part of the range
04667      to accept such numbers.  We arbitrarily disallow "-0xff" or "0xff+0xff",
04668      so that we can do any range checking at all.  */
04669   if (! fixP->fx_pcrel && ! fixP->fx_signed)
04670     upper_limit = upper_limit * 2 + 1;
04671 
04672   if ((addressT) val > upper_limit
04673       && (val > 0 || val < lower_limit))
04674     as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
04675 
04676   /* A one byte PC-relative reloc means a short branch.  We can't use
04677      a short branch with a value of 0 or -1, because those indicate
04678      different opcodes (branches with longer offsets).  fixup_segment
04679      in write.c may have clobbered fx_pcrel, so we need to examine the
04680      reloc type.  */
04681   if ((fixP->fx_pcrel
04682        || fixP->fx_r_type == BFD_RELOC_8_PCREL)
04683       && fixP->fx_size == 1
04684       && (fixP->fx_addsy == NULL
04685          || S_IS_DEFINED (fixP->fx_addsy))
04686       && (val == 0 || val == -1))
04687     as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
04688 }
04689 
04690 /* *fragP has been relaxed to its final size, and now needs to have
04691    the bytes inside it modified to conform to the new size  There is UGLY
04692    MAGIC here. ..
04693    */
04694 static void
04695 md_convert_frag_1 (fragS *fragP)
04696 {
04697   long disp;
04698   fixS *fixP;
04699 
04700   /* Address in object code of the displacement.  */
04701   register int object_address = fragP->fr_fix + fragP->fr_address;
04702 
04703   /* Address in gas core of the place to store the displacement.  */
04704   /* This convinces the native rs6000 compiler to generate the code we
04705      want.  */
04706   register char *buffer_address = fragP->fr_literal;
04707   buffer_address += fragP->fr_fix;
04708   /* End ibm compiler workaround.  */
04709 
04710   /* The displacement of the address, from current location.  */
04711   disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
04712   disp = (disp + fragP->fr_offset) - object_address;
04713 
04714   switch (fragP->fr_subtype)
04715     {
04716     case TAB (BRANCHBWL, BYTE):
04717     case TAB (BRABSJUNC, BYTE):
04718     case TAB (BRABSJCOND, BYTE):
04719     case TAB (BRANCHBW, BYTE):
04720       know (issbyte (disp));
04721       if (disp == 0)
04722        as_bad_where (fragP->fr_file, fragP->fr_line,
04723                     _("short branch with zero offset: use :w"));
04724       fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
04725                     fragP->fr_offset, 1, RELAX_RELOC_PC8);
04726       fixP->fx_pcrel_adjust = -1;
04727       break;
04728     case TAB (BRANCHBWL, SHORT):
04729     case TAB (BRABSJUNC, SHORT):
04730     case TAB (BRABSJCOND, SHORT):
04731     case TAB (BRANCHBW, SHORT):
04732       fragP->fr_opcode[1] = 0x00;
04733       fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
04734               1, RELAX_RELOC_PC16);
04735       fragP->fr_fix += 2;
04736       break;
04737     case TAB (BRANCHBWL, LONG):
04738       fragP->fr_opcode[1] = (char) 0xFF;
04739       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
04740               1, RELAX_RELOC_PC32);
04741       fragP->fr_fix += 4;
04742       break;
04743     case TAB (BRABSJUNC, LONG):
04744       if (fragP->fr_opcode[0] == 0x61)           /* jbsr */
04745        {
04746          if (flag_keep_pcrel)
04747            as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
04748          fragP->fr_opcode[0] = 0x4E;
04749          fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand.  */
04750          fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
04751                  0, RELAX_RELOC_ABS32);
04752          fragP->fr_fix += 4;
04753        }
04754       else if (fragP->fr_opcode[0] == 0x60)      /* jbra */
04755        {
04756          if (flag_keep_pcrel)
04757            as_fatal (_("Tried to convert PC relative branch to absolute jump"));
04758          fragP->fr_opcode[0] = 0x4E;
04759          fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand.  */
04760          fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
04761                  0, RELAX_RELOC_ABS32);
04762          fragP->fr_fix += 4;
04763        }
04764       else
04765        {
04766          /* This cannot happen, because jbsr and jbra are the only two
04767             unconditional branches.  */
04768          abort ();
04769        }
04770       break;
04771     case TAB (BRABSJCOND, LONG):
04772       if (flag_keep_pcrel)
04773        as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
04774 
04775       /* Only Bcc 68000 instructions can come here
04776         Change bcc into b!cc/jmp absl long.  */
04777       fragP->fr_opcode[0] ^= 0x01; /* Invert bcc.  */
04778       fragP->fr_opcode[1]  = 0x06; /* Branch offset = 6.  */
04779 
04780       /* JF: these used to be fr_opcode[2,3], but they may be in a
04781           different frag, in which case referring to them is a no-no.
04782           Only fr_opcode[0,1] are guaranteed to work.  */
04783       *buffer_address++ = 0x4e;    /* put in jmp long (0x4ef9) */
04784       *buffer_address++ = (char) 0xf9;
04785       fragP->fr_fix += 2;   /* Account for jmp instruction.  */
04786       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
04787               fragP->fr_offset, 0, RELAX_RELOC_ABS32);
04788       fragP->fr_fix += 4;
04789       break;
04790     case TAB (FBRANCH, SHORT):
04791       know ((fragP->fr_opcode[1] & 0x40) == 0);
04792       fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
04793               1, RELAX_RELOC_PC16);
04794       fragP->fr_fix += 2;
04795       break;
04796     case TAB (FBRANCH, LONG):
04797       fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit.  */
04798       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
04799               1, RELAX_RELOC_PC32);
04800       fragP->fr_fix += 4;
04801       break;
04802     case TAB (DBCCLBR, SHORT):
04803     case TAB (DBCCABSJ, SHORT):
04804       fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
04805               1, RELAX_RELOC_PC16);
04806       fragP->fr_fix += 2;
04807       break;
04808     case TAB (DBCCLBR, LONG):
04809       /* Only DBcc instructions can come here.
04810         Change dbcc into dbcc/bral.
04811         JF: these used to be fr_opcode[2-7], but that's wrong.  */
04812       if (flag_keep_pcrel)
04813        as_fatal (_("Tried to convert DBcc to absolute jump"));
04814 
04815       *buffer_address++ = 0x00;    /* Branch offset = 4.  */
04816       *buffer_address++ = 0x04;
04817       *buffer_address++ = 0x60;    /* Put in bra pc+6.  */
04818       *buffer_address++ = 0x06;
04819       *buffer_address++ = 0x60;     /* Put in bral (0x60ff).  */
04820       *buffer_address++ = (char) 0xff;
04821 
04822       fragP->fr_fix += 6;   /* Account for bra/jmp instructions.  */
04823       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
04824               RELAX_RELOC_PC32);
04825       fragP->fr_fix += 4;
04826       break;
04827     case TAB (DBCCABSJ, LONG):
04828       /* Only DBcc instructions can come here.
04829         Change dbcc into dbcc/jmp.
04830         JF: these used to be fr_opcode[2-7], but that's wrong.  */
04831       if (flag_keep_pcrel)
04832        as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
04833 
04834       *buffer_address++ = 0x00;           /* Branch offset = 4.  */
04835       *buffer_address++ = 0x04;
04836       *buffer_address++ = 0x60;           /* Put in bra pc + 6.  */
04837       *buffer_address++ = 0x06;
04838       *buffer_address++ = 0x4e;           /* Put in jmp long (0x4ef9).  */
04839       *buffer_address++ = (char) 0xf9;
04840 
04841       fragP->fr_fix += 6;          /* Account for bra/jmp instructions.  */
04842       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
04843               RELAX_RELOC_ABS32);
04844       fragP->fr_fix += 4;
04845       break;
04846     case TAB (PCREL1632, SHORT):
04847       fragP->fr_opcode[1] &= ~0x3F;
04848       fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
04849       fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
04850               fragP->fr_offset, 1, RELAX_RELOC_PC16);
04851       fragP->fr_fix += 2;
04852       break;
04853     case TAB (PCREL1632, LONG):
04854       /* Already set to mode 7.3; this indicates: PC indirect with
04855         suppressed index, 32-bit displacement.  */
04856       *buffer_address++ = 0x01;
04857       *buffer_address++ = 0x70;
04858       fragP->fr_fix += 2;
04859       fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
04860                     fragP->fr_offset, 1, RELAX_RELOC_PC32);
04861       fixP->fx_pcrel_adjust = 2;
04862       fragP->fr_fix += 4;
04863       break;
04864     case TAB (PCINDEX, BYTE):
04865       assert (fragP->fr_fix >= 2);
04866       buffer_address[-2] &= ~1;
04867       fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
04868                     fragP->fr_offset, 1, RELAX_RELOC_PC8);
04869       fixP->fx_pcrel_adjust = 1;
04870       break;
04871     case TAB (PCINDEX, SHORT):
04872       assert (fragP->fr_fix >= 2);
04873       buffer_address[-2] |= 0x1;
04874       buffer_address[-1] = 0x20;
04875       fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
04876                     fragP->fr_offset, 1, RELAX_RELOC_PC16);
04877       fixP->fx_pcrel_adjust = 2;
04878       fragP->fr_fix += 2;
04879       break;
04880     case TAB (PCINDEX, LONG):
04881       assert (fragP->fr_fix >= 2);
04882       buffer_address[-2] |= 0x1;
04883       buffer_address[-1] = 0x30;
04884       fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
04885                     fragP->fr_offset, 1, RELAX_RELOC_PC32);
04886       fixP->fx_pcrel_adjust = 2;
04887       fragP->fr_fix += 4;
04888       break;
04889     case TAB (ABSTOPCREL, SHORT):
04890       fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
04891               1, RELAX_RELOC_PC16);
04892       fragP->fr_fix += 2;
04893       break;
04894     case TAB (ABSTOPCREL, LONG):
04895       if (flag_keep_pcrel)
04896        as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
04897       /* The thing to do here is force it to ABSOLUTE LONG, since
04898         ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway.  */
04899       if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
04900        abort ();
04901       fragP->fr_opcode[1] &= ~0x3F;
04902       fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
04903       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
04904               0, RELAX_RELOC_ABS32);
04905       fragP->fr_fix += 4;
04906       break;
04907     }
04908 }
04909 
04910 void
04911 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
04912                segT sec ATTRIBUTE_UNUSED,
04913                fragS *fragP)
04914 {
04915   md_convert_frag_1 (fragP);
04916 }
04917 
04918 /* Force truly undefined symbols to their maximum size, and generally set up
04919    the frag list to be relaxed
04920    */
04921 int
04922 md_estimate_size_before_relax (fragS *fragP, segT segment)
04923 {
04924   /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT.  */
04925   switch (fragP->fr_subtype)
04926     {
04927     case TAB (BRANCHBWL, SZ_UNDEF):
04928     case TAB (BRABSJUNC, SZ_UNDEF):
04929     case TAB (BRABSJCOND, SZ_UNDEF):
04930       {
04931        if (S_GET_SEGMENT (fragP->fr_symbol) == segment
04932            && relaxable_symbol (fragP->fr_symbol))
04933          {
04934            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
04935          }
04936        else if (flag_short_refs)
04937          {
04938            /* Symbol is undefined and we want short ref.  */
04939            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
04940          }
04941        else
04942          {
04943            /* Symbol is still undefined.  Make it LONG.  */
04944            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
04945          }
04946        break;
04947       }
04948 
04949     case TAB (BRANCHBW, SZ_UNDEF):
04950       {
04951        if (S_GET_SEGMENT (fragP->fr_symbol) == segment
04952            && relaxable_symbol (fragP->fr_symbol))
04953          {
04954            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
04955          }
04956        else
04957          {
04958            /* Symbol is undefined and we don't have long branches.  */
04959            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
04960          }
04961        break;
04962       }
04963 
04964     case TAB (FBRANCH, SZ_UNDEF):
04965     case TAB (DBCCLBR, SZ_UNDEF):
04966     case TAB (DBCCABSJ, SZ_UNDEF):
04967     case TAB (PCREL1632, SZ_UNDEF):
04968       {
04969        if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
04970             && relaxable_symbol (fragP->fr_symbol))
04971            || flag_short_refs)
04972          {
04973            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
04974          }
04975        else
04976          {
04977            fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
04978          }
04979        break;
04980       }
04981 
04982     case TAB (PCINDEX, SZ_UNDEF):
04983       if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
04984           && relaxable_symbol (fragP->fr_symbol)))
04985        {
04986          fragP->fr_subtype = TAB (PCINDEX, BYTE);
04987        }
04988       else
04989        {
04990          fragP->fr_subtype = TAB (PCINDEX, LONG);
04991        }
04992       break;
04993 
04994     case TAB (ABSTOPCREL, SZ_UNDEF):
04995       {
04996        if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
04997             && relaxable_symbol (fragP->fr_symbol)))
04998          {
04999            fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
05000          }
05001        else
05002          {
05003            fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
05004          }
05005        break;
05006       }
05007 
05008     default:
05009       break;
05010     }
05011 
05012   /* Now that SZ_UNDEF are taken care of, check others.  */
05013   switch (fragP->fr_subtype)
05014     {
05015     case TAB (BRANCHBWL, BYTE):
05016     case TAB (BRABSJUNC, BYTE):
05017     case TAB (BRABSJCOND, BYTE):
05018     case TAB (BRANCHBW, BYTE):
05019       /* We can't do a short jump to the next instruction, so in that
05020         case we force word mode.  If the symbol is at the start of a
05021         frag, and it is the next frag with any data in it (usually
05022         this is just the next frag, but assembler listings may
05023         introduce empty frags), we must use word mode.  */
05024       if (fragP->fr_symbol)
05025        {
05026          fragS *sym_frag;
05027 
05028          sym_frag = symbol_get_frag (fragP->fr_symbol);
05029          if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
05030            {
05031              fragS *l;
05032 
05033              for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
05034               if (l->fr_fix != 0)
05035                 break;
05036              if (l == sym_frag)
05037               fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
05038            }
05039        }
05040       break;
05041     default:
05042       break;
05043     }
05044   return md_relax_table[fragP->fr_subtype].rlx_length;
05045 }
05046 
05047 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
05048 /* the bit-field entries in the relocation_info struct plays hell
05049    with the byte-order problems of cross-assembly.  So as a hack,
05050    I added this mach. dependent ri twiddler.  Ugly, but it gets
05051    you there. -KWK  */
05052 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
05053    are symbolnum, most sig. byte first.  Last byte is broken up with
05054    bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
05055    nibble as nuthin. (on Sun 3 at least) */
05056 /* Translate the internal relocation information into target-specific
05057    format.  */
05058 #ifdef comment
05059 void
05060 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
05061 {
05062   /* This is easy.  */
05063   md_number_to_chars (the_bytes, ri->r_address, 4);
05064   /* Now the fun stuff.  */
05065   the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
05066   the_bytes[5] = (ri->r_symbolnum >>  8) & 0x0ff;
05067   the_bytes[6] =  ri->r_symbolnum        & 0x0ff;
05068   the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
05069                 | ((ri->r_length << 5) & 0x60)
05070                 | ((ri->r_extern << 4) & 0x10));
05071 }
05072 
05073 #endif
05074 
05075 #endif /* OBJ_AOUT or OBJ_BOUT */
05076 
05077 #ifndef WORKING_DOT_WORD
05078 int md_short_jump_size = 4;
05079 int md_long_jump_size = 6;
05080 
05081 void
05082 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
05083                     fragS *frag ATTRIBUTE_UNUSED,
05084                     symbolS *to_symbol ATTRIBUTE_UNUSED)
05085 {
05086   valueT offset;
05087 
05088   offset = to_addr - (from_addr + 2);
05089 
05090   md_number_to_chars (ptr, (valueT) 0x6000, 2);
05091   md_number_to_chars (ptr + 2, (valueT) offset, 2);
05092 }
05093 
05094 void
05095 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
05096                    fragS *frag, symbolS *to_symbol)
05097 {
05098   valueT offset;
05099 
05100   if (!HAVE_LONG_BRANCH (current_architecture))
05101     {
05102       if (flag_keep_pcrel)
05103        as_fatal (_("Tried to convert PC relative branch to absolute jump"));
05104       offset = to_addr - S_GET_VALUE (to_symbol);
05105       md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
05106       md_number_to_chars (ptr + 2, (valueT) offset, 4);
05107       fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
05108               0, NO_RELOC);
05109     }
05110   else
05111     {
05112       offset = to_addr - (from_addr + 2);
05113       md_number_to_chars (ptr, (valueT) 0x60ff, 2);
05114       md_number_to_chars (ptr + 2, (valueT) offset, 4);
05115     }
05116 }
05117 
05118 #endif
05119 
05120 /* Different values of OK tell what its OK to return.  Things that
05121    aren't OK are an error (what a shock, no?)
05122 
05123    0:  Everything is OK
05124    10:  Absolute 1:8    only
05125    20:  Absolute 0:7    only
05126    30:  absolute 0:15          only
05127    40:  Absolute 0:31          only
05128    50:  absolute 0:127         only
05129    55:  absolute -64:63    only
05130    60:  absolute -128:127  only
05131    70:  absolute 0:4095        only
05132    80:  absolute -1, 1:7   only
05133    90:  No bignums.          */
05134 
05135 static int
05136 get_num (struct m68k_exp *exp, int ok)
05137 {
05138   if (exp->exp.X_op == O_absent)
05139     {
05140       /* Do the same thing the VAX asm does.  */
05141       op (exp) = O_constant;
05142       adds (exp) = 0;
05143       subs (exp) = 0;
05144       offs (exp) = 0;
05145       if (ok == 10)
05146        {
05147          as_warn (_("expression out of range: defaulting to 1"));
05148          offs (exp) = 1;
05149        }
05150     }
05151   else if (exp->exp.X_op == O_constant)
05152     {
05153       switch (ok)
05154        {
05155        case 10:
05156          if ((valueT) TRUNC (offs (exp)) - 1 > 7)
05157            {
05158              as_warn (_("expression out of range: defaulting to 1"));
05159              offs (exp) = 1;
05160            }
05161          break;
05162        case 20:
05163          if ((valueT) TRUNC (offs (exp)) > 7)
05164            goto outrange;
05165          break;
05166        case 30:
05167          if ((valueT) TRUNC (offs (exp)) > 15)
05168            goto outrange;
05169          break;
05170        case 40:
05171          if ((valueT) TRUNC (offs (exp)) > 32)
05172            goto outrange;
05173          break;
05174        case 50:
05175          if ((valueT) TRUNC (offs (exp)) > 127)
05176            goto outrange;
05177          break;
05178        case 55:
05179          if ((valueT) SEXT (offs (exp)) + 64 > 127)
05180            goto outrange;
05181          break;
05182        case 60:
05183          if ((valueT) SEXT (offs (exp)) + 128 > 255)
05184            goto outrange;
05185          break;
05186        case 70:
05187          if ((valueT) TRUNC (offs (exp)) > 4095)
05188            {
05189            outrange:
05190              as_warn (_("expression out of range: defaulting to 0"));
05191              offs (exp) = 0;
05192            }
05193          break;
05194        case 80:
05195          if ((valueT) TRUNC (offs (exp)) != 0xffffffff
05196               && (valueT) TRUNC (offs (exp)) - 1 > 6)
05197            {
05198              as_warn (_("expression out of range: defaulting to 1"));
05199              offs (exp) = 1;
05200            }
05201          break;
05202        default:
05203          break;
05204        }
05205     }
05206   else if (exp->exp.X_op == O_big)
05207     {
05208       if (offs (exp) <= 0   /* flonum.  */
05209          && (ok == 90              /* no bignums */
05210              || (ok > 10    /* Small-int ranges including 0 ok.  */
05211                 /* If we have a flonum zero, a zero integer should
05212                    do as well (e.g., in moveq).  */
05213                 && generic_floating_point_number.exponent == 0
05214                 && generic_floating_point_number.low[0] == 0)))
05215        {
05216          /* HACK! Turn it into a long.  */
05217          LITTLENUM_TYPE words[6];
05218 
05219          gen_to_words (words, 2, 8L);     /* These numbers are magic!  */
05220          op (exp) = O_constant;
05221          adds (exp) = 0;
05222          subs (exp) = 0;
05223          offs (exp) = words[1] | (words[0] << 16);
05224        }
05225       else if (ok != 0)
05226        {
05227          op (exp) = O_constant;
05228          adds (exp) = 0;
05229          subs (exp) = 0;
05230          offs (exp) = (ok == 10) ? 1 : 0;
05231          as_warn (_("Can't deal with expression; defaulting to %ld"),
05232                  (long) offs (exp));
05233        }
05234     }
05235   else
05236     {
05237       if (ok >= 10 && ok <= 80)
05238        {
05239          op (exp) = O_constant;
05240          adds (exp) = 0;
05241          subs (exp) = 0;
05242          offs (exp) = (ok == 10) ? 1 : 0;
05243          as_warn (_("Can't deal with expression; defaulting to %ld"),
05244                  (long) offs (exp));
05245        }
05246     }
05247 
05248   if (exp->size != SIZE_UNSPEC)
05249     {
05250       switch (exp->size)
05251        {
05252        case SIZE_UNSPEC:
05253        case SIZE_LONG:
05254          break;
05255        case SIZE_BYTE:
05256          if (!isbyte (offs (exp)))
05257            as_warn (_("expression doesn't fit in BYTE"));
05258          break;
05259        case SIZE_WORD:
05260          if (!isword (offs (exp)))
05261            as_warn (_("expression doesn't fit in WORD"));
05262          break;
05263        }
05264     }
05265 
05266   return offs (exp);
05267 }
05268 
05269 /* These are the back-ends for the various machine dependent pseudo-ops.  */
05270 
05271 static void
05272 s_data1 (int ignore ATTRIBUTE_UNUSED)
05273 {
05274   subseg_set (data_section, 1);
05275   demand_empty_rest_of_line ();
05276 }
05277 
05278 static void
05279 s_data2 (int ignore ATTRIBUTE_UNUSED)
05280 {
05281   subseg_set (data_section, 2);
05282   demand_empty_rest_of_line ();
05283 }
05284 
05285 static void
05286 s_bss (int ignore ATTRIBUTE_UNUSED)
05287 {
05288   /* We don't support putting frags in the BSS segment, we fake it
05289      by marking in_bss, then looking at s_skip for clues.  */
05290 
05291   subseg_set (bss_section, 0);
05292   demand_empty_rest_of_line ();
05293 }
05294 
05295 static void
05296 s_even (int ignore ATTRIBUTE_UNUSED)
05297 {
05298   register int temp;
05299   register long temp_fill;
05300 
05301   temp = 1;                 /* JF should be 2? */
05302   temp_fill = get_absolute_expression ();
05303   if (!need_pass_2)         /* Never make frag if expect extra pass.  */
05304     frag_align (temp, (int) temp_fill, 0);
05305   demand_empty_rest_of_line ();
05306   record_alignment (now_seg, temp);
05307 }
05308 
05309 static void
05310 s_proc (int ignore ATTRIBUTE_UNUSED)
05311 {
05312   demand_empty_rest_of_line ();
05313 }
05314 
05315 /* Pseudo-ops handled for MRI compatibility.  */
05316 
05317 /* This function returns non-zero if the argument is a conditional
05318    pseudo-op.  This is called when checking whether a pending
05319    alignment is needed.  */
05320 
05321 int
05322 m68k_conditional_pseudoop (pseudo_typeS *pop)
05323 {
05324   return (pop->poc_handler == s_mri_if
05325          || pop->poc_handler == s_mri_else);
05326 }
05327 
05328 /* Handle an MRI style chip specification.  */
05329 
05330 static void
05331 mri_chip (void)
05332 {
05333   char *s;
05334   char c;
05335   int i;
05336 
05337   s = input_line_pointer;
05338   /* We can't use get_symbol_end since the processor names are not proper
05339      symbols.  */
05340   while (is_part_of_name (c = *input_line_pointer++))
05341     ;
05342   *--input_line_pointer = 0;
05343   for (i = 0; m68k_cpus[i].name; i++)
05344     if (strcasecmp (s, m68k_cpus[i].name) == 0)
05345       break;
05346   if (!m68k_cpus[i].name)
05347     {
05348       as_bad (_("%s: unrecognized processor name"), s);
05349       *input_line_pointer = c;
05350       ignore_rest_of_line ();
05351       return;
05352     }
05353   *input_line_pointer = c;
05354 
05355   if (*input_line_pointer == '/')
05356     current_architecture = 0;
05357   else
05358     current_architecture &= m68881 | m68851;
05359   current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
05360   control_regs = m68k_cpus[i].control_regs;
05361 
05362   while (*input_line_pointer == '/')
05363     {
05364       ++input_line_pointer;
05365       s = input_line_pointer;
05366       /* We can't use get_symbol_end since the processor names are not
05367         proper symbols.  */
05368       while (is_part_of_name (c = *input_line_pointer++))
05369        ;
05370       *--input_line_pointer = 0;
05371       if (strcmp (s, "68881") == 0)
05372        current_architecture |= m68881;
05373       else if (strcmp (s, "68851") == 0)
05374        current_architecture |= m68851;
05375       *input_line_pointer = c;
05376     }
05377 }
05378 
05379 /* The MRI CHIP pseudo-op.  */
05380 
05381 static void
05382 s_chip (int ignore ATTRIBUTE_UNUSED)
05383 {
05384   char *stop = NULL;
05385   char stopc;
05386 
05387   if (flag_mri)
05388     stop = mri_comment_field (&stopc);
05389   mri_chip ();
05390   if (flag_mri)
05391     mri_comment_end (stop, stopc);
05392   demand_empty_rest_of_line ();
05393 }
05394 
05395 /* The MRI FOPT pseudo-op.  */
05396 
05397 static void
05398 s_fopt (int ignore ATTRIBUTE_UNUSED)
05399 {
05400   SKIP_WHITESPACE ();
05401 
05402   if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
05403     {
05404       int temp;
05405 
05406       input_line_pointer += 3;
05407       temp = get_absolute_expression ();
05408       if (temp < 0 || temp > 7)
05409        as_bad (_("bad coprocessor id"));
05410       else
05411        m68k_float_copnum = COP0 + temp;
05412     }
05413   else
05414     {
05415       as_bad (_("unrecognized fopt option"));
05416       ignore_rest_of_line ();
05417       return;
05418     }
05419 
05420   demand_empty_rest_of_line ();
05421 }
05422 
05423 /* The structure used to handle the MRI OPT pseudo-op.  */
05424 
05425 struct opt_action
05426 {
05427   /* The name of the option.  */
05428   const char *name;
05429 
05430   /* If this is not NULL, just call this function.  The first argument
05431      is the ARG field of this structure, the second argument is
05432      whether the option was negated.  */
05433   void (*pfn) (int arg, int on);
05434 
05435   /* If this is not NULL, and the PFN field is NULL, set the variable
05436      this points to.  Set it to the ARG field if the option was not
05437      negated, and the NOTARG field otherwise.  */
05438   int *pvar;
05439 
05440   /* The value to pass to PFN or to assign to *PVAR.  */
05441   int arg;
05442 
05443   /* The value to assign to *PVAR if the option is negated.  If PFN is
05444      NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
05445      the option may not be negated.  */
05446   int notarg;
05447 };
05448 
05449 /* The table used to handle the MRI OPT pseudo-op.  */
05450 
05451 static void skip_to_comma (int, int);
05452 static void opt_nest (int, int);
05453 static void opt_chip (int, int);
05454 static void opt_list (int, int);
05455 static void opt_list_symbols (int, int);
05456 
05457 static const struct opt_action opt_table[] =
05458 {
05459   { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
05460 
05461   /* We do relaxing, so there is little use for these options.  */
05462   { "b", 0, 0, 0, 0 },
05463   { "brs", 0, 0, 0, 0 },
05464   { "brb", 0, 0, 0, 0 },
05465   { "brl", 0, 0, 0, 0 },
05466   { "brw", 0, 0, 0, 0 },
05467 
05468   { "c", 0, 0, 0, 0 },
05469   { "cex", 0, 0, 0, 0 },
05470   { "case", 0, &symbols_case_sensitive, 1, 0 },
05471   { "cl", 0, 0, 0, 0 },
05472   { "cre", 0, 0, 0, 0 },
05473   { "d", 0, &flag_keep_locals, 1, 0 },
05474   { "e", 0, 0, 0, 0 },
05475   { "f", 0, &flag_short_refs, 1, 0 },
05476   { "frs", 0, &flag_short_refs, 1, 0 },
05477   { "frl", 0, &flag_short_refs, 0, 1 },
05478   { "g", 0, 0, 0, 0 },
05479   { "i", 0, 0, 0, 0 },
05480   { "m", 0, 0, 0, 0 },
05481   { "mex", 0, 0, 0, 0 },
05482   { "mc", 0, 0, 0, 0 },
05483   { "md", 0, 0, 0, 0 },
05484   { "nest", opt_nest, 0, 0, 0 },
05485   { "next", skip_to_comma, 0, 0, 0 },
05486   { "o", 0, 0, 0, 0 },
05487   { "old", 0, 0, 0, 0 },
05488   { "op", skip_to_comma, 0, 0, 0 },
05489   { "pco", 0, 0, 0, 0 },
05490   { "p", opt_chip, 0, 0, 0 },
05491   { "pcr", 0, 0, 0, 0 },
05492   { "pcs", 0, 0, 0, 0 },
05493   { "r", 0, 0, 0, 0 },
05494   { "quick", 0, &m68k_quick, 1, 0 },
05495   { "rel32", 0, &m68k_rel32, 1, 0 },
05496   { "s", opt_list, 0, 0, 0 },
05497   { "t", opt_list_symbols, 0, 0, 0 },
05498   { "w", 0, &flag_no_warnings, 0, 1 },
05499   { "x", 0, 0, 0, 0 }
05500 };
05501 
05502 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
05503 
05504 /* The MRI OPT pseudo-op.  */
05505 
05506 static void
05507 s_opt (int ignore ATTRIBUTE_UNUSED)
05508 {
05509   do
05510     {
05511       int t;
05512       char *s;
05513       char c;
05514       int i;
05515       const struct opt_action *o;
05516 
05517       SKIP_WHITESPACE ();
05518 
05519       t = 1;
05520       if (*input_line_pointer == '-')
05521        {
05522          ++input_line_pointer;
05523          t = 0;
05524        }
05525       else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
05526        {
05527          input_line_pointer += 2;
05528          t = 0;
05529        }
05530 
05531       s = input_line_pointer;
05532       c = get_symbol_end ();
05533 
05534       for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
05535        {
05536          if (strcasecmp (s, o->name) == 0)
05537            {
05538              if (o->pfn)
05539               {
05540                 /* Restore input_line_pointer now in case the option
05541                    takes arguments.  */
05542                 *input_line_pointer = c;
05543                 (*o->pfn) (o->arg, t);
05544               }
05545              else if (o->pvar != NULL)
05546               {
05547                 if (! t && o->arg == o->notarg)
05548                   as_bad (_("option `%s' may not be negated"), s);
05549                 *input_line_pointer = c;
05550                 *o->pvar = t ? o->arg : o->notarg;
05551               }
05552              else
05553               *input_line_pointer = c;
05554              break;
05555            }
05556        }
05557       if (i >= OPTCOUNT)
05558        {
05559          as_bad (_("option `%s' not recognized"), s);
05560          *input_line_pointer = c;
05561        }
05562     }
05563   while (*input_line_pointer++ == ',');
05564 
05565   /* Move back to terminating character.  */
05566   --input_line_pointer;
05567   demand_empty_rest_of_line ();
05568 }
05569 
05570 /* Skip ahead to a comma.  This is used for OPT options which we do
05571    not support and which take arguments.  */
05572 
05573 static void
05574 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
05575 {
05576   while (*input_line_pointer != ','
05577         && ! is_end_of_line[(unsigned char) *input_line_pointer])
05578     ++input_line_pointer;
05579 }
05580 
05581 /* Handle the OPT NEST=depth option.  */
05582 
05583 static void
05584 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
05585 {
05586   if (*input_line_pointer != '=')
05587     {
05588       as_bad (_("bad format of OPT NEST=depth"));
05589       return;
05590     }
05591 
05592   ++input_line_pointer;
05593   max_macro_nest = get_absolute_expression ();
05594 }
05595 
05596 /* Handle the OPT P=chip option.  */
05597 
05598 static void
05599 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
05600 {
05601   if (*input_line_pointer != '=')
05602     {
05603       /* This is just OPT P, which we do not support.  */
05604       return;
05605     }
05606 
05607   ++input_line_pointer;
05608   mri_chip ();
05609 }
05610 
05611 /* Handle the OPT S option.  */
05612 
05613 static void
05614 opt_list (int arg ATTRIBUTE_UNUSED, int on)
05615 {
05616   listing_list (on);
05617 }
05618 
05619 /* Handle the OPT T option.  */
05620 
05621 static void
05622 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
05623 {
05624   if (on)
05625     listing |= LISTING_SYMBOLS;
05626   else
05627     listing &= ~LISTING_SYMBOLS;
05628 }
05629 
05630 /* Handle the MRI REG pseudo-op.  */
05631 
05632 static void
05633 s_reg (int ignore ATTRIBUTE_UNUSED)
05634 {
05635   char *s;
05636   int c;
05637   struct m68k_op rop;
05638   int mask;
05639   char *stop = NULL;
05640   char stopc;
05641 
05642   if (line_label == NULL)
05643     {
05644       as_bad (_("missing label"));
05645       ignore_rest_of_line ();
05646       return;
05647     }
05648 
05649   if (flag_mri)
05650     stop = mri_comment_field (&stopc);
05651 
05652   SKIP_WHITESPACE ();
05653 
05654   s = input_line_pointer;
05655   while (ISALNUM (*input_line_pointer)
05656 #ifdef REGISTER_PREFIX
05657         || *input_line_pointer == REGISTER_PREFIX
05658 #endif
05659         || *input_line_pointer == '/'
05660         || *input_line_pointer == '-')
05661     ++input_line_pointer;
05662   c = *input_line_pointer;
05663   *input_line_pointer = '\0';
05664 
05665   if (m68k_ip_op (s, &rop) != 0)
05666     {
05667       if (rop.error == NULL)
05668        as_bad (_("bad register list"));
05669       else
05670        as_bad (_("bad register list: %s"), rop.error);
05671       *input_line_pointer = c;
05672       ignore_rest_of_line ();
05673       return;
05674     }
05675 
05676   *input_line_pointer = c;
05677 
05678   if (rop.mode == REGLST)
05679     mask = rop.mask;
05680   else if (rop.mode == DREG)
05681     mask = 1 << (rop.reg - DATA0);
05682   else if (rop.mode == AREG)
05683     mask = 1 << (rop.reg - ADDR0 + 8);
05684   else if (rop.mode == FPREG)
05685     mask = 1 << (rop.reg - FP0 + 16);
05686   else if (rop.mode == CONTROL
05687           && rop.reg == FPI)
05688     mask = 1 << 24;
05689   else if (rop.mode == CONTROL
05690           && rop.reg == FPS)
05691     mask = 1 << 25;
05692   else if (rop.mode == CONTROL
05693           && rop.reg == FPC)
05694     mask = 1 << 26;
05695   else
05696     {
05697       as_bad (_("bad register list"));
05698       ignore_rest_of_line ();
05699       return;
05700     }
05701 
05702   S_SET_SEGMENT (line_label, reg_section);
05703   S_SET_VALUE (line_label, ~mask);
05704   symbol_set_frag (line_label, &zero_address_frag);
05705 
05706   if (flag_mri)
05707     mri_comment_end (stop, stopc);
05708 
05709   demand_empty_rest_of_line ();
05710 }
05711 
05712 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops.  */
05713 
05714 struct save_opts
05715 {
05716   struct save_opts *next;
05717   int abspcadd;
05718   int symbols_case_sensitive;
05719   int keep_locals;
05720   int short_refs;
05721   int architecture;
05722   const enum m68k_register *control_regs;
05723   int quick;
05724   int rel32;
05725   int listing;
05726   int no_warnings;
05727   /* FIXME: We don't save OPT S.  */
05728 };
05729 
05730 /* This variable holds the stack of saved options.  */
05731 
05732 static struct save_opts *save_stack;
05733 
05734 /* The MRI SAVE pseudo-op.  */
05735 
05736 static void
05737 s_save (int ignore ATTRIBUTE_UNUSED)
05738 {
05739   struct save_opts *s;
05740 
05741   s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
05742   s->abspcadd = m68k_abspcadd;
05743   s->symbols_case_sensitive = symbols_case_sensitive;
05744   s->keep_locals = flag_keep_locals;
05745   s->short_refs = flag_short_refs;
05746   s->architecture = current_architecture;
05747   s->control_regs = control_regs;
05748   s->quick = m68k_quick;
05749   s->rel32 = m68k_rel32;
05750   s->listing = listing;
05751   s->no_warnings = flag_no_warnings;
05752 
05753   s->next = save_stack;
05754   save_stack = s;
05755 
05756   demand_empty_rest_of_line ();
05757 }
05758 
05759 /* The MRI RESTORE pseudo-op.  */
05760 
05761 static void
05762 s_restore (int ignore ATTRIBUTE_UNUSED)
05763 {
05764   struct save_opts *s;
05765 
05766   if (save_stack == NULL)
05767     {
05768       as_bad (_("restore without save"));
05769       ignore_rest_of_line ();
05770       return;
05771     }
05772 
05773   s = save_stack;
05774   save_stack = s->next;
05775 
05776   m68k_abspcadd = s->abspcadd;
05777   symbols_case_sensitive = s->symbols_case_sensitive;
05778   flag_keep_locals = s->keep_locals;
05779   flag_short_refs = s->short_refs;
05780   current_architecture = s->architecture;
05781   control_regs = s->control_regs;
05782   m68k_quick = s->quick;
05783   m68k_rel32 = s->rel32;
05784   listing = s->listing;
05785   flag_no_warnings = s->no_warnings;
05786 
05787   free (s);
05788 
05789   demand_empty_rest_of_line ();
05790 }
05791 
05792 /* Types of MRI structured control directives.  */
05793 
05794 enum mri_control_type
05795 {
05796   mri_for,
05797   mri_if,
05798   mri_repeat,
05799   mri_while
05800 };
05801 
05802 /* This structure is used to stack the MRI structured control
05803    directives.  */
05804 
05805 struct mri_control_info
05806 {
05807   /* The directive within which this one is enclosed.  */
05808   struct mri_control_info *outer;
05809 
05810   /* The type of directive.  */
05811   enum mri_control_type type;
05812 
05813   /* Whether an ELSE has been in an IF.  */
05814   int else_seen;
05815 
05816   /* The add or sub statement at the end of a FOR.  */
05817   char *incr;
05818 
05819   /* The label of the top of a FOR or REPEAT loop.  */
05820   char *top;
05821 
05822   /* The label to jump to for the next iteration, or the else
05823      expression of a conditional.  */
05824   char *next;
05825 
05826   /* The label to jump to to break out of the loop, or the label past
05827      the end of a conditional.  */
05828   char *bottom;
05829 };
05830 
05831 /* The stack of MRI structured control directives.  */
05832 
05833 static struct mri_control_info *mri_control_stack;
05834 
05835 /* The current MRI structured control directive index number, used to
05836    generate label names.  */
05837 
05838 static int mri_control_index;
05839 
05840 /* Assemble an instruction for an MRI structured control directive.  */
05841 
05842 static void
05843 mri_assemble (char *str)
05844 {
05845   char *s;
05846 
05847   /* md_assemble expects the opcode to be in lower case.  */
05848   for (s = str; *s != ' ' && *s != '\0'; s++)
05849     *s = TOLOWER (*s);
05850 
05851   md_assemble (str);
05852 }
05853 
05854 /* Generate a new MRI label structured control directive label name.  */
05855 
05856 static char *
05857 mri_control_label (void)
05858 {
05859   char *n;
05860 
05861   n = (char *) xmalloc (20);
05862   sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
05863   ++mri_control_index;
05864   return n;
05865 }
05866 
05867 /* Create a new MRI structured control directive.  */
05868 
05869 static struct mri_control_info *
05870 push_mri_control (enum mri_control_type type)
05871 {
05872   struct mri_control_info *n;
05873 
05874   n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
05875 
05876   n->type = type;
05877   n->else_seen = 0;
05878   if (type == mri_if || type == mri_while)
05879     n->top = NULL;
05880   else
05881     n->top = mri_control_label ();
05882   n->next = mri_control_label ();
05883   n->bottom = mri_control_label ();
05884 
05885   n->outer = mri_control_stack;
05886   mri_control_stack = n;
05887 
05888   return n;
05889 }
05890 
05891 /* Pop off the stack of MRI structured control directives.  */
05892 
05893 static void
05894 pop_mri_control (void)
05895 {
05896   struct mri_control_info *n;
05897 
05898   n = mri_control_stack;
05899   mri_control_stack = n->outer;
05900   if (n->top != NULL)
05901     free (n->top);
05902   free (n->next);
05903   free (n->bottom);
05904   free (n);
05905 }
05906 
05907 /* Recognize a condition code in an MRI structured control expression.  */
05908 
05909 static int
05910 parse_mri_condition (int *pcc)
05911 {
05912   char c1, c2;
05913 
05914   know (*input_line_pointer == '<');
05915 
05916   ++input_line_pointer;
05917   c1 = *input_line_pointer++;
05918   c2 = *input_line_pointer++;
05919 
05920   if (*input_line_pointer != '>')
05921     {
05922       as_bad (_("syntax error in structured control directive"));
05923       return 0;
05924     }
05925 
05926   ++input_line_pointer;
05927   SKIP_WHITESPACE ();
05928 
05929   c1 = TOLOWER (c1);
05930   c2 = TOLOWER (c2);
05931 
05932   *pcc = (c1 << 8) | c2;
05933 
05934   return 1;
05935 }
05936 
05937 /* Parse a single operand in an MRI structured control expression.  */
05938 
05939 static int
05940 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
05941                         char **rightstart, char **rightstop)
05942 {
05943   char *s;
05944 
05945   SKIP_WHITESPACE ();
05946 
05947   *pcc = -1;
05948   *leftstart = NULL;
05949   *leftstop = NULL;
05950   *rightstart = NULL;
05951   *rightstop = NULL;
05952 
05953   if (*input_line_pointer == '<')
05954     {
05955       /* It's just a condition code.  */
05956       return parse_mri_condition (pcc);
05957     }
05958 
05959   /* Look ahead for the condition code.  */
05960   for (s = input_line_pointer; *s != '\0'; ++s)
05961     {
05962       if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
05963        break;
05964     }
05965   if (*s == '\0')
05966     {
05967       as_bad (_("missing condition code in structured control directive"));
05968       return 0;
05969     }
05970 
05971   *leftstart = input_line_pointer;
05972   *leftstop = s;
05973   if (*leftstop > *leftstart
05974       && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
05975     --*leftstop;
05976 
05977   input_line_pointer = s;
05978   if (! parse_mri_condition (pcc))
05979     return 0;
05980 
05981   /* Look ahead for AND or OR or end of line.  */
05982   for (s = input_line_pointer; *s != '\0'; ++s)
05983     {
05984       /* We must make sure we don't misinterpret AND/OR at the end of labels!
05985          if d0 <eq> #FOOAND and d1 <ne> #BAROR then
05986                         ^^^                 ^^ */
05987       if ((s == input_line_pointer
05988           || *(s-1) == ' '
05989           || *(s-1) == '\t')
05990          && ((strncasecmp (s, "AND", 3) == 0
05991               && (s[3] == '.' || ! is_part_of_name (s[3])))
05992              || (strncasecmp (s, "OR", 2) == 0
05993                 && (s[2] == '.' || ! is_part_of_name (s[2])))))
05994        break;
05995     }
05996 
05997   *rightstart = input_line_pointer;
05998   *rightstop = s;
05999   if (*rightstop > *rightstart
06000       && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
06001     --*rightstop;
06002 
06003   input_line_pointer = s;
06004 
06005   return 1;
06006 }
06007 
06008 #define MCC(b1, b2) (((b1) << 8) | (b2))
06009 
06010 /* Swap the sense of a condition.  This changes the condition so that
06011    it generates the same result when the operands are swapped.  */
06012 
06013 static int
06014 swap_mri_condition (int cc)
06015 {
06016   switch (cc)
06017     {
06018     case MCC ('h', 'i'): return MCC ('c', 's');
06019     case MCC ('l', 's'): return MCC ('c', 'c');
06020     /* <HS> is an alias for <CC>.  */
06021     case MCC ('h', 's'):
06022     case MCC ('c', 'c'): return MCC ('l', 's');
06023     /* <LO> is an alias for <CS>.  */
06024     case MCC ('l', 'o'):
06025     case MCC ('c', 's'): return MCC ('h', 'i');
06026     case MCC ('p', 'l'): return MCC ('m', 'i');
06027     case MCC ('m', 'i'): return MCC ('p', 'l');
06028     case MCC ('g', 'e'): return MCC ('l', 'e');
06029     case MCC ('l', 't'): return MCC ('g', 't');
06030     case MCC ('g', 't'): return MCC ('l', 't');
06031     case MCC ('l', 'e'): return MCC ('g', 'e');
06032     /* Issue a warning for conditions we can not swap.  */
06033     case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
06034     case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
06035     case MCC ('v', 'c'):
06036     case MCC ('v', 's'):
06037     default :
06038           as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
06039                        (char) (cc >> 8), (char) (cc));
06040       break;
06041     }
06042   return cc;
06043 }
06044 
06045 /* Reverse the sense of a condition.  */
06046 
06047 static int
06048 reverse_mri_condition (int cc)
06049 {
06050   switch (cc)
06051     {
06052     case MCC ('h', 'i'): return MCC ('l', 's');
06053     case MCC ('l', 's'): return MCC ('h', 'i');
06054     /* <HS> is an alias for <CC> */
06055     case MCC ('h', 's'): return MCC ('l', 'o');
06056     case MCC ('c', 'c'): return MCC ('c', 's');
06057     /* <LO> is an alias for <CS> */
06058     case MCC ('l', 'o'): return MCC ('h', 's');
06059     case MCC ('c', 's'): return MCC ('c', 'c');
06060     case MCC ('n', 'e'): return MCC ('e', 'q');
06061     case MCC ('e', 'q'): return MCC ('n', 'e');
06062     case MCC ('v', 'c'): return MCC ('v', 's');
06063     case MCC ('v', 's'): return MCC ('v', 'c');
06064     case MCC ('p', 'l'): return MCC ('m', 'i');
06065     case MCC ('m', 'i'): return MCC ('p', 'l');
06066     case MCC ('g', 'e'): return MCC ('l', 't');
06067     case MCC ('l', 't'): return MCC ('g', 'e');
06068     case MCC ('g', 't'): return MCC ('l', 'e');
06069     case MCC ('l', 'e'): return MCC ('g', 't');
06070     }
06071   return cc;
06072 }
06073 
06074 /* Build an MRI structured control expression.  This generates test
06075    and branch instructions.  It goes to TRUELAB if the condition is
06076    true, and to FALSELAB if the condition is false.  Exactly one of
06077    TRUELAB and FALSELAB will be NULL, meaning to fall through.  QUAL
06078    is the size qualifier for the expression.  EXTENT is the size to
06079    use for the branch.  */
06080 
06081 static void
06082 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
06083                         char *rightstart, char *rightstop,
06084                         const char *truelab, const char *falselab,
06085                         int extent)
06086 {
06087   char *buf;
06088   char *s;
06089 
06090   if (leftstart != NULL)
06091     {
06092       struct m68k_op leftop, rightop;
06093       char c;
06094 
06095       /* Swap the compare operands, if necessary, to produce a legal
06096         m68k compare instruction.  Comparing a register operand with
06097         a non-register operand requires the register to be on the
06098         right (cmp, cmpa).  Comparing an immediate value with
06099         anything requires the immediate value to be on the left
06100         (cmpi).  */
06101 
06102       c = *leftstop;
06103       *leftstop = '\0';
06104       (void) m68k_ip_op (leftstart, &leftop);
06105       *leftstop = c;
06106 
06107       c = *rightstop;
06108       *rightstop = '\0';
06109       (void) m68k_ip_op (rightstart, &rightop);
06110       *rightstop = c;
06111 
06112       if (rightop.mode == IMMED
06113          || ((leftop.mode == DREG || leftop.mode == AREG)
06114              && (rightop.mode != DREG && rightop.mode != AREG)))
06115        {
06116          char *temp;
06117 
06118          /* Correct conditional handling:
06119             if #1 <lt> d0 then  ;means if (1 < d0)
06120               ...
06121             endi
06122 
06123             should assemble to:
06124 
06125               cmp #1,d0        if we do *not* swap the operands
06126               bgt true         we need the swapped condition!
06127               ble false
06128             true:
06129               ...
06130             false:
06131          */
06132          temp = leftstart;
06133          leftstart = rightstart;
06134          rightstart = temp;
06135          temp = leftstop;
06136          leftstop = rightstop;
06137          rightstop = temp;
06138        }
06139       else
06140        {
06141          cc = swap_mri_condition (cc);
06142        }
06143     }
06144 
06145   if (truelab == NULL)
06146     {
06147       cc = reverse_mri_condition (cc);
06148       truelab = falselab;
06149     }
06150 
06151   if (leftstart != NULL)
06152     {
06153       buf = (char *) xmalloc (20
06154                            + (leftstop - leftstart)
06155                            + (rightstop - rightstart));
06156       s = buf;
06157       *s++ = 'c';
06158       *s++ = 'm';
06159       *s++ = 'p';
06160       if (qual != '\0')
06161        *s++ = TOLOWER (qual);
06162       *s++ = ' ';
06163       memcpy (s, leftstart, leftstop - leftstart);
06164       s += leftstop - leftstart;
06165       *s++ = ',';
06166       memcpy (s, rightstart, rightstop - rightstart);
06167       s += rightstop - rightstart;
06168       *s = '\0';
06169       mri_assemble (buf);
06170       free (buf);
06171     }
06172 
06173   buf = (char *) xmalloc (20 + strlen (truelab));
06174   s = buf;
06175   *s++ = 'b';
06176   *s++ = cc >> 8;
06177   *s++ = cc & 0xff;
06178   if (extent != '\0')
06179     *s++ = TOLOWER (extent);
06180   *s++ = ' ';
06181   strcpy (s, truelab);
06182   mri_assemble (buf);
06183   free (buf);
06184 }
06185 
06186 /* Parse an MRI structured control expression.  This generates test
06187    and branch instructions.  STOP is where the expression ends.  It
06188    goes to TRUELAB if the condition is true, and to FALSELAB if the
06189    condition is false.  Exactly one of TRUELAB and FALSELAB will be
06190    NULL, meaning to fall through.  QUAL is the size qualifier for the
06191    expression.  EXTENT is the size to use for the branch.  */
06192 
06193 static void
06194 parse_mri_control_expression (char *stop, int qual, const char *truelab,
06195                            const char *falselab, int extent)
06196 {
06197   int c;
06198   int cc;
06199   char *leftstart;
06200   char *leftstop;
06201   char *rightstart;
06202   char *rightstop;
06203 
06204   c = *stop;
06205   *stop = '\0';
06206 
06207   if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
06208                                &rightstart, &rightstop))
06209     {
06210       *stop = c;
06211       return;
06212     }
06213 
06214   if (strncasecmp (input_line_pointer, "AND", 3) == 0)
06215     {
06216       const char *flab;
06217 
06218       if (falselab != NULL)
06219        flab = falselab;
06220       else
06221        flab = mri_control_label ();
06222 
06223       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
06224                              rightstop, (const char *) NULL, flab, extent);
06225 
06226       input_line_pointer += 3;
06227       if (*input_line_pointer != '.'
06228          || input_line_pointer[1] == '\0')
06229        qual = '\0';
06230       else
06231        {
06232          qual = input_line_pointer[1];
06233          input_line_pointer += 2;
06234        }
06235 
06236       if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
06237                                    &rightstart, &rightstop))
06238        {
06239          *stop = c;
06240          return;
06241        }
06242 
06243       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
06244                              rightstop, truelab, falselab, extent);
06245 
06246       if (falselab == NULL)
06247        colon (flab);
06248     }
06249   else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
06250     {
06251       const char *tlab;
06252 
06253       if (truelab != NULL)
06254        tlab = truelab;
06255       else
06256        tlab = mri_control_label ();
06257 
06258       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
06259                              rightstop, tlab, (const char *) NULL, extent);
06260 
06261       input_line_pointer += 2;
06262       if (*input_line_pointer != '.'
06263          || input_line_pointer[1] == '\0')
06264        qual = '\0';
06265       else
06266        {
06267          qual = input_line_pointer[1];
06268          input_line_pointer += 2;
06269        }
06270 
06271       if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
06272                                    &rightstart, &rightstop))
06273        {
06274          *stop = c;
06275          return;
06276        }
06277 
06278       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
06279                              rightstop, truelab, falselab, extent);
06280 
06281       if (truelab == NULL)
06282        colon (tlab);
06283     }
06284   else
06285     {
06286       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
06287                              rightstop, truelab, falselab, extent);
06288     }
06289 
06290   *stop = c;
06291   if (input_line_pointer != stop)
06292     as_bad (_("syntax error in structured control directive"));
06293 }
06294 
06295 /* Handle the MRI IF pseudo-op.  This may be a structured control
06296    directive, or it may be a regular assembler conditional, depending
06297    on its operands.  */
06298 
06299 static void
06300 s_mri_if (int qual)
06301 {
06302   char *s;
06303   int c;
06304   struct mri_control_info *n;
06305 
06306   /* A structured control directive must end with THEN with an
06307      optional qualifier.  */
06308   s = input_line_pointer;
06309   /* We only accept '*' as introduction of comments if preceded by white space
06310      or at first column of a line (I think this can't actually happen here?)
06311      This is important when assembling:
06312        if d0 <ne> 12(a0,d0*2) then
06313        if d0 <ne> #CONST*20   then.  */
06314   while (! (is_end_of_line[(unsigned char) *s]
06315             || (flag_mri
06316                 && *s == '*'
06317                 && (s == input_line_pointer
06318                     || *(s-1) == ' '
06319                     || *(s-1) == '\t'))))
06320     ++s;
06321   --s;
06322   while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
06323     --s;
06324 
06325   if (s - input_line_pointer > 1
06326       && s[-1] == '.')
06327     s -= 2;
06328 
06329   if (s - input_line_pointer < 3
06330       || strncasecmp (s - 3, "THEN", 4) != 0)
06331     {
06332       if (qual != '\0')
06333        {
06334          as_bad (_("missing then"));
06335          ignore_rest_of_line ();
06336          return;
06337        }
06338 
06339       /* It's a conditional.  */
06340       s_if (O_ne);
06341       return;
06342     }
06343 
06344   /* Since this might be a conditional if, this pseudo-op will be
06345      called even if we are supported to be ignoring input.  Double
06346      check now.  Clobber *input_line_pointer so that ignore_input
06347      thinks that this is not a special pseudo-op.  */
06348   c = *input_line_pointer;
06349   *input_line_pointer = 0;
06350   if (ignore_input ())
06351     {
06352       *input_line_pointer = c;
06353       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06354        ++input_line_pointer;
06355       demand_empty_rest_of_line ();
06356       return;
06357     }
06358   *input_line_pointer = c;
06359 
06360   n = push_mri_control (mri_if);
06361 
06362   parse_mri_control_expression (s - 3, qual, (const char *) NULL,
06363                             n->next, s[1] == '.' ? s[2] : '\0');
06364 
06365   if (s[1] == '.')
06366     input_line_pointer = s + 3;
06367   else
06368     input_line_pointer = s + 1;
06369 
06370   if (flag_mri)
06371     {
06372       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06373        ++input_line_pointer;
06374     }
06375 
06376   demand_empty_rest_of_line ();
06377 }
06378 
06379 /* Handle the MRI else pseudo-op.  If we are currently doing an MRI
06380    structured IF, associate the ELSE with the IF.  Otherwise, assume
06381    it is a conditional else.  */
06382 
06383 static void
06384 s_mri_else (int qual)
06385 {
06386   int c;
06387   char *buf;
06388   char q[2];
06389 
06390   if (qual == '\0'
06391       && (mri_control_stack == NULL
06392          || mri_control_stack->type != mri_if
06393          || mri_control_stack->else_seen))
06394     {
06395       s_else (0);
06396       return;
06397     }
06398 
06399   c = *input_line_pointer;
06400   *input_line_pointer = 0;
06401   if (ignore_input ())
06402     {
06403       *input_line_pointer = c;
06404       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06405        ++input_line_pointer;
06406       demand_empty_rest_of_line ();
06407       return;
06408     }
06409   *input_line_pointer = c;
06410 
06411   if (mri_control_stack == NULL
06412       || mri_control_stack->type != mri_if
06413       || mri_control_stack->else_seen)
06414     {
06415       as_bad (_("else without matching if"));
06416       ignore_rest_of_line ();
06417       return;
06418     }
06419 
06420   mri_control_stack->else_seen = 1;
06421 
06422   buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
06423   q[0] = TOLOWER (qual);
06424   q[1] = '\0';
06425   sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
06426   mri_assemble (buf);
06427   free (buf);
06428 
06429   colon (mri_control_stack->next);
06430 
06431   if (flag_mri)
06432     {
06433       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06434        ++input_line_pointer;
06435     }
06436 
06437   demand_empty_rest_of_line ();
06438 }
06439 
06440 /* Handle the MRI ENDI pseudo-op.  */
06441 
06442 static void
06443 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
06444 {
06445   if (mri_control_stack == NULL
06446       || mri_control_stack->type != mri_if)
06447     {
06448       as_bad (_("endi without matching if"));
06449       ignore_rest_of_line ();
06450       return;
06451     }
06452 
06453   /* ignore_input will not return true for ENDI, so we don't need to
06454      worry about checking it again here.  */
06455 
06456   if (! mri_control_stack->else_seen)
06457     colon (mri_control_stack->next);
06458   colon (mri_control_stack->bottom);
06459 
06460   pop_mri_control ();
06461 
06462   if (flag_mri)
06463     {
06464       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06465        ++input_line_pointer;
06466     }
06467 
06468   demand_empty_rest_of_line ();
06469 }
06470 
06471 /* Handle the MRI BREAK pseudo-op.  */
06472 
06473 static void
06474 s_mri_break (int extent)
06475 {
06476   struct mri_control_info *n;
06477   char *buf;
06478   char ex[2];
06479 
06480   n = mri_control_stack;
06481   while (n != NULL
06482         && n->type != mri_for
06483         && n->type != mri_repeat
06484         && n->type != mri_while)
06485     n = n->outer;
06486   if (n == NULL)
06487     {
06488       as_bad (_("break outside of structured loop"));
06489       ignore_rest_of_line ();
06490       return;
06491     }
06492 
06493   buf = (char *) xmalloc (20 + strlen (n->bottom));
06494   ex[0] = TOLOWER (extent);
06495   ex[1] = '\0';
06496   sprintf (buf, "bra%s %s", ex, n->bottom);
06497   mri_assemble (buf);
06498   free (buf);
06499 
06500   if (flag_mri)
06501     {
06502       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06503        ++input_line_pointer;
06504     }
06505 
06506   demand_empty_rest_of_line ();
06507 }
06508 
06509 /* Handle the MRI NEXT pseudo-op.  */
06510 
06511 static void
06512 s_mri_next (int extent)
06513 {
06514   struct mri_control_info *n;
06515   char *buf;
06516   char ex[2];
06517 
06518   n = mri_control_stack;
06519   while (n != NULL
06520         && n->type != mri_for
06521         && n->type != mri_repeat
06522         && n->type != mri_while)
06523     n = n->outer;
06524   if (n == NULL)
06525     {
06526       as_bad (_("next outside of structured loop"));
06527       ignore_rest_of_line ();
06528       return;
06529     }
06530 
06531   buf = (char *) xmalloc (20 + strlen (n->next));
06532   ex[0] = TOLOWER (extent);
06533   ex[1] = '\0';
06534   sprintf (buf, "bra%s %s", ex, n->next);
06535   mri_assemble (buf);
06536   free (buf);
06537 
06538   if (flag_mri)
06539     {
06540       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06541        ++input_line_pointer;
06542     }
06543 
06544   demand_empty_rest_of_line ();
06545 }
06546 
06547 /* Handle the MRI FOR pseudo-op.  */
06548 
06549 static void
06550 s_mri_for (int qual)
06551 {
06552   const char *varstart, *varstop;
06553   const char *initstart, *initstop;
06554   const char *endstart, *endstop;
06555   const char *bystart, *bystop;
06556   int up;
06557   int by;
06558   int extent;
06559   struct mri_control_info *n;
06560   char *buf;
06561   char *s;
06562   char ex[2];
06563 
06564   /* The syntax is
06565        FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
06566      */
06567 
06568   SKIP_WHITESPACE ();
06569   varstart = input_line_pointer;
06570 
06571   /* Look for the '='.  */
06572   while (! is_end_of_line[(unsigned char) *input_line_pointer]
06573         && *input_line_pointer != '=')
06574     ++input_line_pointer;
06575   if (*input_line_pointer != '=')
06576     {
06577       as_bad (_("missing ="));
06578       ignore_rest_of_line ();
06579       return;
06580     }
06581 
06582   varstop = input_line_pointer;
06583   if (varstop > varstart
06584       && (varstop[-1] == ' ' || varstop[-1] == '\t'))
06585     --varstop;
06586 
06587   ++input_line_pointer;
06588 
06589   initstart = input_line_pointer;
06590 
06591   /* Look for TO or DOWNTO.  */
06592   up = 1;
06593   initstop = NULL;
06594   while (! is_end_of_line[(unsigned char) *input_line_pointer])
06595     {
06596       if (strncasecmp (input_line_pointer, "TO", 2) == 0
06597          && ! is_part_of_name (input_line_pointer[2]))
06598        {
06599          initstop = input_line_pointer;
06600          input_line_pointer += 2;
06601          break;
06602        }
06603       if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
06604          && ! is_part_of_name (input_line_pointer[6]))
06605        {
06606          initstop = input_line_pointer;
06607          up = 0;
06608          input_line_pointer += 6;
06609          break;
06610        }
06611       ++input_line_pointer;
06612     }
06613   if (initstop == NULL)
06614     {
06615       as_bad (_("missing to or downto"));
06616       ignore_rest_of_line ();
06617       return;
06618     }
06619   if (initstop > initstart
06620       && (initstop[-1] == ' ' || initstop[-1] == '\t'))
06621     --initstop;
06622 
06623   SKIP_WHITESPACE ();
06624   endstart = input_line_pointer;
06625 
06626   /* Look for BY or DO.  */
06627   by = 0;
06628   endstop = NULL;
06629   while (! is_end_of_line[(unsigned char) *input_line_pointer])
06630     {
06631       if (strncasecmp (input_line_pointer, "BY", 2) == 0
06632          && ! is_part_of_name (input_line_pointer[2]))
06633        {
06634          endstop = input_line_pointer;
06635          by = 1;
06636          input_line_pointer += 2;
06637          break;
06638        }
06639       if (strncasecmp (input_line_pointer, "DO", 2) == 0
06640          && (input_line_pointer[2] == '.'
06641              || ! is_part_of_name (input_line_pointer[2])))
06642        {
06643          endstop = input_line_pointer;
06644          input_line_pointer += 2;
06645          break;
06646        }
06647       ++input_line_pointer;
06648     }
06649   if (endstop == NULL)
06650     {
06651       as_bad (_("missing do"));
06652       ignore_rest_of_line ();
06653       return;
06654     }
06655   if (endstop > endstart
06656       && (endstop[-1] == ' ' || endstop[-1] == '\t'))
06657     --endstop;
06658 
06659   if (! by)
06660     {
06661       bystart = "#1";
06662       bystop = bystart + 2;
06663     }
06664   else
06665     {
06666       SKIP_WHITESPACE ();
06667       bystart = input_line_pointer;
06668 
06669       /* Look for DO.  */
06670       bystop = NULL;
06671       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06672        {
06673          if (strncasecmp (input_line_pointer, "DO", 2) == 0
06674              && (input_line_pointer[2] == '.'
06675                 || ! is_part_of_name (input_line_pointer[2])))
06676            {
06677              bystop = input_line_pointer;
06678              input_line_pointer += 2;
06679              break;
06680            }
06681          ++input_line_pointer;
06682        }
06683       if (bystop == NULL)
06684        {
06685          as_bad (_("missing do"));
06686          ignore_rest_of_line ();
06687          return;
06688        }
06689       if (bystop > bystart
06690          && (bystop[-1] == ' ' || bystop[-1] == '\t'))
06691        --bystop;
06692     }
06693 
06694   if (*input_line_pointer != '.')
06695     extent = '\0';
06696   else
06697     {
06698       extent = input_line_pointer[1];
06699       input_line_pointer += 2;
06700     }
06701 
06702   /* We have fully parsed the FOR operands.  Now build the loop.  */
06703   n = push_mri_control (mri_for);
06704 
06705   buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
06706 
06707   /* Move init,var.  */
06708   s = buf;
06709   *s++ = 'm';
06710   *s++ = 'o';
06711   *s++ = 'v';
06712   *s++ = 'e';
06713   if (qual != '\0')
06714     *s++ = TOLOWER (qual);
06715   *s++ = ' ';
06716   memcpy (s, initstart, initstop - initstart);
06717   s += initstop - initstart;
06718   *s++ = ',';
06719   memcpy (s, varstart, varstop - varstart);
06720   s += varstop - varstart;
06721   *s = '\0';
06722   mri_assemble (buf);
06723 
06724   colon (n->top);
06725 
06726   /* cmp end,var.  */
06727   s = buf;
06728   *s++ = 'c';
06729   *s++ = 'm';
06730   *s++ = 'p';
06731   if (qual != '\0')
06732     *s++ = TOLOWER (qual);
06733   *s++ = ' ';
06734   memcpy (s, endstart, endstop - endstart);
06735   s += endstop - endstart;
06736   *s++ = ',';
06737   memcpy (s, varstart, varstop - varstart);
06738   s += varstop - varstart;
06739   *s = '\0';
06740   mri_assemble (buf);
06741 
06742   /* bcc bottom.  */
06743   ex[0] = TOLOWER (extent);
06744   ex[1] = '\0';
06745   if (up)
06746     sprintf (buf, "blt%s %s", ex, n->bottom);
06747   else
06748     sprintf (buf, "bgt%s %s", ex, n->bottom);
06749   mri_assemble (buf);
06750 
06751   /* Put together the add or sub instruction used by ENDF.  */
06752   s = buf;
06753   if (up)
06754     strcpy (s, "add");
06755   else
06756     strcpy (s, "sub");
06757   s += 3;
06758   if (qual != '\0')
06759     *s++ = TOLOWER (qual);
06760   *s++ = ' ';
06761   memcpy (s, bystart, bystop - bystart);
06762   s += bystop - bystart;
06763   *s++ = ',';
06764   memcpy (s, varstart, varstop - varstart);
06765   s += varstop - varstart;
06766   *s = '\0';
06767   n->incr = buf;
06768 
06769   if (flag_mri)
06770     {
06771       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06772        ++input_line_pointer;
06773     }
06774 
06775   demand_empty_rest_of_line ();
06776 }
06777 
06778 /* Handle the MRI ENDF pseudo-op.  */
06779 
06780 static void
06781 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
06782 {
06783   if (mri_control_stack == NULL
06784       || mri_control_stack->type != mri_for)
06785     {
06786       as_bad (_("endf without for"));
06787       ignore_rest_of_line ();
06788       return;
06789     }
06790 
06791   colon (mri_control_stack->next);
06792 
06793   mri_assemble (mri_control_stack->incr);
06794 
06795   sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
06796   mri_assemble (mri_control_stack->incr);
06797 
06798   free (mri_control_stack->incr);
06799 
06800   colon (mri_control_stack->bottom);
06801 
06802   pop_mri_control ();
06803 
06804   if (flag_mri)
06805     {
06806       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06807        ++input_line_pointer;
06808     }
06809 
06810   demand_empty_rest_of_line ();
06811 }
06812 
06813 /* Handle the MRI REPEAT pseudo-op.  */
06814 
06815 static void
06816 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
06817 {
06818   struct mri_control_info *n;
06819 
06820   n = push_mri_control (mri_repeat);
06821   colon (n->top);
06822   if (flag_mri)
06823     {
06824       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06825        ++input_line_pointer;
06826     }
06827   demand_empty_rest_of_line ();
06828 }
06829 
06830 /* Handle the MRI UNTIL pseudo-op.  */
06831 
06832 static void
06833 s_mri_until (int qual)
06834 {
06835   char *s;
06836 
06837   if (mri_control_stack == NULL
06838       || mri_control_stack->type != mri_repeat)
06839     {
06840       as_bad (_("until without repeat"));
06841       ignore_rest_of_line ();
06842       return;
06843     }
06844 
06845   colon (mri_control_stack->next);
06846 
06847   for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
06848     ;
06849 
06850   parse_mri_control_expression (s, qual, (const char *) NULL,
06851                             mri_control_stack->top, '\0');
06852 
06853   colon (mri_control_stack->bottom);
06854 
06855   input_line_pointer = s;
06856 
06857   pop_mri_control ();
06858 
06859   if (flag_mri)
06860     {
06861       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06862        ++input_line_pointer;
06863     }
06864 
06865   demand_empty_rest_of_line ();
06866 }
06867 
06868 /* Handle the MRI WHILE pseudo-op.  */
06869 
06870 static void
06871 s_mri_while (int qual)
06872 {
06873   char *s;
06874 
06875   struct mri_control_info *n;
06876 
06877   s = input_line_pointer;
06878   /* We only accept '*' as introduction of comments if preceded by white space
06879      or at first column of a line (I think this can't actually happen here?)
06880      This is important when assembling:
06881        while d0 <ne> 12(a0,d0*2) do
06882        while d0 <ne> #CONST*20   do.  */
06883   while (! (is_end_of_line[(unsigned char) *s]
06884            || (flag_mri
06885               && *s == '*'
06886               && (s == input_line_pointer
06887                   || *(s-1) == ' '
06888                   || *(s-1) == '\t'))))
06889     s++;
06890   --s;
06891   while (*s == ' ' || *s == '\t')
06892     --s;
06893   if (s - input_line_pointer > 1
06894       && s[-1] == '.')
06895     s -= 2;
06896   if (s - input_line_pointer < 2
06897       || strncasecmp (s - 1, "DO", 2) != 0)
06898     {
06899       as_bad (_("missing do"));
06900       ignore_rest_of_line ();
06901       return;
06902     }
06903 
06904   n = push_mri_control (mri_while);
06905 
06906   colon (n->next);
06907 
06908   parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
06909                             s[1] == '.' ? s[2] : '\0');
06910 
06911   input_line_pointer = s + 1;
06912   if (*input_line_pointer == '.')
06913     input_line_pointer += 2;
06914 
06915   if (flag_mri)
06916     {
06917       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06918        ++input_line_pointer;
06919     }
06920 
06921   demand_empty_rest_of_line ();
06922 }
06923 
06924 /* Handle the MRI ENDW pseudo-op.  */
06925 
06926 static void
06927 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
06928 {
06929   char *buf;
06930 
06931   if (mri_control_stack == NULL
06932       || mri_control_stack->type != mri_while)
06933     {
06934       as_bad (_("endw without while"));
06935       ignore_rest_of_line ();
06936       return;
06937     }
06938 
06939   buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
06940   sprintf (buf, "bra %s", mri_control_stack->next);
06941   mri_assemble (buf);
06942   free (buf);
06943 
06944   colon (mri_control_stack->bottom);
06945 
06946   pop_mri_control ();
06947 
06948   if (flag_mri)
06949     {
06950       while (! is_end_of_line[(unsigned char) *input_line_pointer])
06951        ++input_line_pointer;
06952     }
06953 
06954   demand_empty_rest_of_line ();
06955 }
06956 
06957 /* Parse a .cpu directive.  */
06958 
06959 static void
06960 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
06961 {
06962   char saved_char;
06963   char *name;
06964 
06965   if (initialized)
06966     {
06967       as_bad (_("already assembled instructions"));
06968       ignore_rest_of_line ();
06969       return;
06970     }
06971   
06972   name = input_line_pointer;
06973   while (*input_line_pointer && !ISSPACE(*input_line_pointer))
06974     input_line_pointer++;
06975   saved_char = *input_line_pointer;
06976   *input_line_pointer = 0;
06977 
06978   m68k_set_cpu (name, 1, 0);
06979   
06980   *input_line_pointer = saved_char;
06981   demand_empty_rest_of_line ();
06982   return;
06983 }
06984 
06985 /* Parse a .arch directive.  */
06986 
06987 static void
06988 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
06989 {
06990   char saved_char;
06991   char *name;
06992 
06993   if (initialized)
06994     {
06995       as_bad (_("already assembled instructions"));
06996       ignore_rest_of_line ();
06997       return;
06998     }
06999   
07000   name = input_line_pointer;
07001   while (*input_line_pointer && *input_line_pointer != ','
07002         && !ISSPACE (*input_line_pointer))
07003     input_line_pointer++;
07004   saved_char = *input_line_pointer;
07005   *input_line_pointer = 0;
07006 
07007   if (m68k_set_arch (name, 1, 0))
07008     {
07009       /* Scan extensions. */
07010       do
07011        {
07012          *input_line_pointer++ = saved_char;
07013          if (!*input_line_pointer || ISSPACE (*input_line_pointer))
07014            break;
07015          name = input_line_pointer;
07016          while (*input_line_pointer && *input_line_pointer != ','
07017                && !ISSPACE (*input_line_pointer))
07018            input_line_pointer++;
07019          saved_char = *input_line_pointer;
07020          *input_line_pointer = 0;
07021        }
07022       while (m68k_set_extension (name, 1, 0));
07023     }
07024   
07025   *input_line_pointer = saved_char;
07026   demand_empty_rest_of_line ();
07027   return;
07028 }
07029 
07030 /* Lookup a cpu name in TABLE and return the slot found.  Return NULL
07031    if none is found, the caller is responsible for emitting an error
07032    message.  If ALLOW_M is non-zero, we allow an initial 'm' on the
07033    cpu name, if it begins with a '6' (possibly skipping an intervening
07034    'c'.  We also allow a 'c' in the same place.  if NEGATED is
07035    non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
07036    the option is indeed negated.  */
07037 
07038 static const struct m68k_cpu *
07039 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
07040                int allow_m, int *negated)
07041 {
07042   /* allow negated value? */
07043   if (negated)
07044     {
07045       *negated = 0;
07046 
07047       if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
07048        {
07049          arg += 3;
07050          *negated = 1;
07051        }
07052     }
07053   
07054   /* Remove 'm' or 'mc' prefix from 68k variants.  */
07055   if (allow_m)
07056     {
07057       if (arg[0] == 'm')
07058        {
07059          if (arg[1] == '6')
07060            arg += 1;
07061          else if (arg[1] == 'c'  && arg[2] == '6')
07062            arg += 2;
07063        }
07064     }
07065   else if (arg[0] == 'c' && arg[1] == '6')
07066     arg += 1;
07067 
07068   for (; table->name; table++)
07069     if (!strcmp (arg, table->name))
07070       {
07071        if (table->alias < -1 || table->alias > 1)
07072          as_bad (_("`%s' is deprecated, use `%s'"),
07073                 table->name, table[table->alias < 0 ? 1 : -1].name);
07074        return table;
07075       }
07076   return 0;
07077 }
07078 
07079 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
07080 
07081 static int
07082 m68k_set_cpu (char const *name, int allow_m, int silent)
07083 {
07084   const struct m68k_cpu *cpu;
07085 
07086   cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
07087 
07088   if (!cpu)
07089     {
07090       if (!silent)
07091        as_bad (_("cpu `%s' unrecognized"), name);
07092       return 0;
07093     }
07094       
07095   if (selected_cpu && selected_cpu != cpu)
07096     {
07097       as_bad (_("already selected `%s' processor"),
07098              selected_cpu->name);
07099       return 0;
07100     }
07101   selected_cpu = cpu;
07102   return 1;
07103 }
07104 
07105 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
07106 
07107 static int
07108 m68k_set_arch (char const *name, int allow_m, int silent)
07109 {
07110   const struct m68k_cpu *arch;
07111 
07112   arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
07113 
07114   if (!arch)
07115     {
07116       if (!silent)
07117        as_bad (_("architecture `%s' unrecognized"), name);
07118       return 0;
07119     }
07120       
07121   if (selected_arch && selected_arch != arch)
07122     {
07123       as_bad (_("already selected `%s' architecture"),
07124              selected_arch->name);
07125       return 0;
07126     }
07127   
07128   selected_arch = arch;
07129   return 1;
07130 }
07131 
07132 /* Set the architecture extension, issuing errors if it is
07133    unrecognized, or invalid */
07134 
07135 static int
07136 m68k_set_extension (char const *name, int allow_m, int silent)
07137 {
07138   int negated;
07139   const struct m68k_cpu *ext;
07140 
07141   ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
07142 
07143   if (!ext)
07144     {
07145       if (!silent)
07146        as_bad (_("extension `%s' unrecognized"), name);
07147       return 0;
07148     }
07149 
07150   if (negated)
07151     not_current_architecture |= ext->arch;
07152   else
07153     current_architecture |= ext->arch;
07154   return 1;
07155 }
07156 
07157 /* md_parse_option
07158    Invocation line includes a switch not recognized by the base assembler.
07159  */
07160 
07161 #ifdef OBJ_ELF
07162 const char *md_shortopts = "lSA:m:kQ:V";
07163 #else
07164 const char *md_shortopts = "lSA:m:k";
07165 #endif
07166 
07167 struct option md_longopts[] = {
07168 #define OPTION_PIC (OPTION_MD_BASE)
07169   {"pic", no_argument, NULL, OPTION_PIC},
07170 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
07171   {"register-prefix-optional", no_argument, NULL,
07172      OPTION_REGISTER_PREFIX_OPTIONAL},
07173 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
07174   {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
07175 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
07176   {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
07177 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
07178   {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
07179 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
07180   {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
07181 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
07182   {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
07183 #define OPTION_PCREL (OPTION_MD_BASE + 7)
07184   {"pcrel", no_argument, NULL, OPTION_PCREL},
07185   {NULL, no_argument, NULL, 0}
07186 };
07187 size_t md_longopts_size = sizeof (md_longopts);
07188 
07189 int
07190 md_parse_option (int c, char *arg)
07191 {
07192   switch (c)
07193     {
07194     case 'l':               /* -l means keep external to 2 bit offset
07195                                rather than 16 bit one.  */
07196       flag_short_refs = 1;
07197       break;
07198 
07199     case 'S':               /* -S means that jbsr's always turn into
07200                                jsr's.  */
07201       flag_long_jumps = 1;
07202       break;
07203 
07204     case OPTION_PCREL:             /* --pcrel means never turn PC-relative
07205                                branches into absolute jumps.  */
07206       flag_keep_pcrel = 1;
07207       break;
07208 
07209     case OPTION_PIC:
07210     case 'k':
07211       flag_want_pic = 1;
07212       break;                /* -pic, Position Independent Code.  */
07213 
07214     case OPTION_REGISTER_PREFIX_OPTIONAL:
07215       flag_reg_prefix_optional = 1;
07216       reg_prefix_optional_seen = 1;
07217       break;
07218 
07219       /* -V: SVR4 argument to print version ID.  */
07220     case 'V':
07221       print_version_id ();
07222       break;
07223 
07224       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
07225         should be emitted or not.  FIXME: Not implemented.  */
07226     case 'Q':
07227       break;
07228 
07229     case OPTION_BITWISE_OR:
07230       {
07231        char *n, *t;
07232        const char *s;
07233 
07234        n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
07235        t = n;
07236        for (s = m68k_comment_chars; *s != '\0'; s++)
07237          if (*s != '|')
07238            *t++ = *s;
07239        *t = '\0';
07240        m68k_comment_chars = n;
07241       }
07242       break;
07243 
07244     case OPTION_BASE_SIZE_DEFAULT_16:
07245       m68k_index_width_default = SIZE_WORD;
07246       break;
07247 
07248     case OPTION_BASE_SIZE_DEFAULT_32:
07249       m68k_index_width_default = SIZE_LONG;
07250       break;
07251 
07252     case OPTION_DISP_SIZE_DEFAULT_16:
07253       m68k_rel32 = 0;
07254       m68k_rel32_from_cmdline = 1;
07255       break;
07256 
07257     case OPTION_DISP_SIZE_DEFAULT_32:
07258       m68k_rel32 = 1;
07259       m68k_rel32_from_cmdline = 1;
07260       break;
07261 
07262     case 'A':
07263 #if WARN_DEPRECATED
07264       as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
07265                   arg, arg));
07266 #endif
07267       /* Intentional fall-through.  */
07268     case 'm':
07269       if (!strncmp (arg, "arch=", 5))
07270        m68k_set_arch (arg + 5, 1, 0);
07271       else if (!strncmp (arg, "cpu=", 4))
07272        m68k_set_cpu (arg + 4, 1, 0);
07273       else if (m68k_set_extension (arg, 0, 1))
07274        ;
07275       else if (m68k_set_arch (arg, 0, 1))
07276        ;
07277       else if (m68k_set_cpu (arg, 0, 1))
07278        ;
07279       else
07280        return 0;
07281       break;
07282 
07283     default:
07284       return 0;
07285     }
07286 
07287   return 1;
07288 }
07289 
07290 /* Setup tables from the selected arch and/or cpu */
07291 
07292 static void
07293 m68k_init_arch (void)
07294 {
07295   if (not_current_architecture & current_architecture)
07296     {
07297       as_bad (_("architecture features both enabled and disabled"));
07298       not_current_architecture &= ~current_architecture;
07299     }
07300   if (selected_arch)
07301     {
07302       current_architecture |= selected_arch->arch;
07303       control_regs = selected_arch->control_regs;
07304     }
07305   else
07306     current_architecture |= selected_cpu->arch;
07307   
07308   current_architecture &= ~not_current_architecture;
07309 
07310   if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
07311     {
07312       /* Determine which float is really meant.  */
07313       if (current_architecture & (m68k_mask & ~m68881))
07314        current_architecture ^= cfloat;
07315       else
07316        current_architecture ^= m68881;
07317     }
07318 
07319   if (selected_cpu)
07320     {
07321       control_regs = selected_cpu->control_regs;
07322       if (current_architecture & ~selected_cpu->arch)
07323        {
07324          as_bad (_("selected processor does not have all features of selected architecture"));
07325          current_architecture
07326            = selected_cpu->arch & ~not_current_architecture;
07327        }
07328     }
07329 
07330   if ((current_architecture & m68k_mask)
07331       && (current_architecture & ~m68k_mask))
07332     {
07333       as_bad (_ ("m68k and cf features both selected"));
07334       if (current_architecture & m68k_mask)
07335        current_architecture &= m68k_mask;
07336       else
07337        current_architecture &= ~m68k_mask;
07338     }
07339   
07340   /* Permit m68881 specification with all cpus; those that can't work
07341      with a coprocessor could be doing emulation.  */
07342   if (current_architecture & m68851)
07343     {
07344       if (current_architecture & m68040)
07345        as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
07346     }
07347   /* What other incompatibilities could we check for?  */
07348 
07349   if (cpu_of_arch (current_architecture) < m68020
07350       || arch_coldfire_p (current_architecture))
07351     md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
07352   
07353   initialized = 1;
07354 }
07355 
07356 void
07357 md_show_usage (FILE *stream)
07358 {
07359   const char *default_cpu = TARGET_CPU;
07360   int i;
07361   unsigned int default_arch;
07362 
07363   /* Get the canonical name for the default target CPU.  */
07364   if (*default_cpu == 'm')
07365     default_cpu++;
07366   for (i = 0; m68k_cpus[i].name; i++)
07367     {
07368       if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
07369        {
07370          default_arch = m68k_cpus[i].arch;
07371          while (m68k_cpus[i].alias > 0)
07372            i--;
07373          while (m68k_cpus[i].alias < 0)
07374            i++;
07375          default_cpu = m68k_cpus[i].name;
07376        }
07377     }
07378 
07379   fprintf (stream, _("\
07380 -march=<arch>        set architecture\n\
07381 -mcpu=<cpu>          set cpu [default %s]\n\
07382 "), default_cpu);
07383   for (i = 0; m68k_extensions[i].name; i++)
07384     fprintf (stream, _("\
07385 -m[no-]%-16s enable/disable%s architecture extension\n\
07386 "), m68k_extensions[i].name,
07387             m68k_extensions[i].alias > 0 ? " ColdFire"
07388             : m68k_extensions[i].alias < 0 ? " m68k" : "");
07389   
07390   fprintf (stream, _("\
07391 -l                   use 1 word for refs to undefined symbols [default 2]\n\
07392 -pic, -k             generate position independent code\n\
07393 -S                   turn jbsr into jsr\n\
07394 --pcrel                 never turn PC-relative branches into absolute jumps\n\
07395 --register-prefix-optional\n\
07396                      recognize register names without prefix character\n\
07397 --bitwise-or         do not treat `|' as a comment character\n\
07398 --base-size-default-16      base reg without size is 16 bits\n\
07399 --base-size-default-32      base reg without size is 32 bits (default)\n\
07400 --disp-size-default-16      displacement with unknown size is 16 bits\n\
07401 --disp-size-default-32      displacement with unknown size is 32 bits (default)\n\
07402 "));
07403   
07404   fprintf (stream, _("Architecture variants are: "));
07405   for (i = 0; m68k_archs[i].name; i++)
07406     {
07407       if (i)
07408        fprintf (stream, " | ");
07409       fprintf (stream, m68k_archs[i].name);
07410     }
07411   fprintf (stream, "\n");
07412 
07413   fprintf (stream, _("Processor variants are: "));
07414   for (i = 0; m68k_cpus[i].name; i++)
07415     {
07416       if (i)
07417        fprintf (stream, " | ");
07418       fprintf (stream, m68k_cpus[i].name);
07419     }
07420   fprintf (stream, _("\n"));
07421 }
07422 
07423 #ifdef TEST2
07424 
07425 /* TEST2:  Test md_assemble() */
07426 /* Warning, this routine probably doesn't work anymore.  */
07427 int
07428 main (void)
07429 {
07430   struct m68k_it the_ins;
07431   char buf[120];
07432   char *cp;
07433   int n;
07434 
07435   m68k_ip_begin ();
07436   for (;;)
07437     {
07438       if (!gets (buf) || !*buf)
07439        break;
07440       if (buf[0] == '|' || buf[1] == '.')
07441        continue;
07442       for (cp = buf; *cp; cp++)
07443        if (*cp == '\t')
07444          *cp = ' ';
07445       if (is_label (buf))
07446        continue;
07447       memset (&the_ins, '\0', sizeof (the_ins));
07448       m68k_ip (&the_ins, buf);
07449       if (the_ins.error)
07450        {
07451          printf (_("Error %s in %s\n"), the_ins.error, buf);
07452        }
07453       else
07454        {
07455          printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
07456          for (n = 0; n < the_ins.numo; n++)
07457            printf (" 0x%x", the_ins.opcode[n] & 0xffff);
07458          printf ("    ");
07459          print_the_insn (&the_ins.opcode[0], stdout);
07460          (void) putchar ('\n');
07461        }
07462       for (n = 0; n < strlen (the_ins.args) / 2; n++)
07463        {
07464          if (the_ins.operands[n].error)
07465            {
07466              printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
07467              continue;
07468            }
07469          printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
07470                 the_ins.operands[n].reg);
07471          if (the_ins.operands[n].b_const)
07472            printf ("Constant: '%.*s', ",
07473                   1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
07474                   the_ins.operands[n].b_const);
07475          printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
07476                 the_ins.operands[n].isiz, the_ins.operands[n].imul);
07477          if (the_ins.operands[n].b_iadd)
07478            printf ("Iadd: '%.*s',",
07479                   1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
07480                   the_ins.operands[n].b_iadd);
07481          putchar ('\n');
07482        }
07483     }
07484   m68k_ip_end ();
07485   return 0;
07486 }
07487 
07488 int
07489 is_label (char *str)
07490 {
07491   while (*str == ' ')
07492     str++;
07493   while (*str && *str != ' ')
07494     str++;
07495   if (str[-1] == ':' || str[1] == '=')
07496     return 1;
07497   return 0;
07498 }
07499 
07500 #endif
07501 
07502 /* Possible states for relaxation:
07503 
07504    0 0 branch offset byte   (bra, etc)
07505    0 1               word
07506    0 2               long
07507 
07508    1 0 indexed offsets      byte   a0@(32,d4:w:1) etc
07509    1 1               word
07510    1 2               long
07511 
07512    2 0 two-offset index word-word a0@(32,d4)@(45) etc
07513    2 1               word-long
07514    2 2               long-word
07515    2 3               long-long
07516 
07517    */
07518 
07519 /* We have no need to default values of symbols.  */
07520 
07521 symbolS *
07522 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
07523 {
07524   return 0;
07525 }
07526 
07527 /* Round up a section size to the appropriate boundary.  */
07528 valueT
07529 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
07530 {
07531 #ifdef OBJ_AOUT
07532   /* For a.out, force the section size to be aligned.  If we don't do
07533      this, BFD will align it for us, but it will not write out the
07534      final bytes of the section.  This may be a bug in BFD, but it is
07535      easier to fix it here since that is how the other a.out targets
07536      work.  */
07537   int align;
07538 
07539   align = bfd_get_section_alignment (stdoutput, segment);
07540   size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
07541 #endif
07542 
07543   return size;
07544 }
07545 
07546 /* Exactly what point is a PC-relative offset relative TO?
07547    On the 68k, it is relative to the address of the first extension
07548    word.  The difference between the addresses of the offset and the
07549    first extension word is stored in fx_pcrel_adjust.  */
07550 long
07551 md_pcrel_from (fixS *fixP)
07552 {
07553   int adjust;
07554 
07555   /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
07556      sign extend the value here.  */
07557   adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
07558   if (adjust == 64)
07559     adjust = -1;
07560   return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
07561 }
07562 
07563 #ifdef OBJ_ELF
07564 void
07565 m68k_elf_final_processing (void)
07566 {
07567   unsigned flags = 0;
07568   
07569   if (arch_coldfire_fpu (current_architecture))
07570     flags |= EF_M68K_CFV4E;
07571   /* Set file-specific flags if this is a cpu32 processor.  */
07572   if (cpu_of_arch (current_architecture) & cpu32)
07573     flags |= EF_M68K_CPU32;
07574   else if (cpu_of_arch (current_architecture) & fido_a)
07575     flags |= EF_M68K_FIDO;
07576   else if ((cpu_of_arch (current_architecture) & m68000up)
07577           && !(cpu_of_arch (current_architecture) & m68020up))
07578     flags |= EF_M68K_M68000;
07579   
07580   if (current_architecture & mcfisa_a)
07581     {
07582       static const unsigned isa_features[][2] =
07583       {
07584        {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
07585        {EF_M68K_CF_ISA_A,   mcfisa_a|mcfhwdiv},
07586        {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
07587        {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
07588        {EF_M68K_CF_ISA_B,   mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
07589        {0,0},
07590       };
07591       static const unsigned mac_features[][2] =
07592       {
07593        {EF_M68K_CF_MAC, mcfmac},
07594        {EF_M68K_CF_EMAC, mcfemac},
07595        {0,0},
07596       };
07597       unsigned ix;
07598       unsigned pattern;
07599       
07600       pattern = (current_architecture
07601                & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
07602       for (ix = 0; isa_features[ix][1]; ix++)
07603        {
07604          if (pattern == isa_features[ix][1])
07605            {
07606              flags |= isa_features[ix][0];
07607              break;
07608            }
07609        }
07610       if (!isa_features[ix][1])
07611        {
07612        cf_bad:
07613          as_warn (_("Not a defined coldfire architecture"));
07614        }
07615       else
07616        {
07617          if (current_architecture & cfloat)
07618            flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
07619 
07620          pattern = current_architecture & (mcfmac|mcfemac);
07621          if (pattern)
07622            {
07623              for (ix = 0; mac_features[ix][1]; ix++)
07624               {
07625                 if (pattern == mac_features[ix][1])
07626                   {
07627                     flags |= mac_features[ix][0];
07628                     break;
07629                   }
07630               }
07631              if (!mac_features[ix][1])
07632               goto cf_bad;
07633            }
07634        }
07635     }
07636   elf_elfheader (stdoutput)->e_flags |= flags;
07637 }
07638 #endif
07639 
07640 int
07641 tc_m68k_regname_to_dw2regnum (char *regname)
07642 {
07643   unsigned int regnum;
07644   static const char *const regnames[] =
07645     {
07646       "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
07647       "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
07648       "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
07649       "pc"
07650     };
07651 
07652   for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
07653     if (strcmp (regname, regnames[regnum]) == 0)
07654       return regnum;
07655 
07656   return -1;
07657 }
07658 
07659 void
07660 tc_m68k_frame_initial_instructions (void)
07661 {
07662   static int sp_regno = -1;
07663 
07664   if (sp_regno < 0)
07665     sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
07666 
07667   cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
07668   cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
07669 }