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cell-binutils  2.17cvs20070401
tc-m32r.c
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00001 /* tc-m32r.c -- Assembler for the Renesas M32R.
00002    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
00003    2006 Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with GAS; see the file COPYING.  If not, write to
00019    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
00020    Boston, MA 02110-1301, USA.  */
00021 
00022 #include "as.h"
00023 #include "safe-ctype.h"
00024 #include "subsegs.h"
00025 #include "symcat.h"
00026 #include "opcodes/m32r-desc.h"
00027 #include "opcodes/m32r-opc.h"
00028 #include "cgen.h"
00029 #include "elf/m32r.h"
00030 
00031 /* Linked list of symbols that are debugging symbols to be defined as the
00032    beginning of the current instruction.  */
00033 typedef struct sym_link
00034 {
00035   struct sym_link *next;
00036   symbolS *symbol;
00037 } sym_linkS;
00038 
00039 static sym_linkS *debug_sym_link = (sym_linkS *) 0;
00040 
00041 /* Structure to hold all of the different components describing
00042    an individual instruction.  */
00043 typedef struct
00044 {
00045   const CGEN_INSN *insn;
00046   const CGEN_INSN *orig_insn;
00047   CGEN_FIELDS fields;
00048 #if CGEN_INT_INSN_P
00049   CGEN_INSN_INT buffer[1];
00050 #define INSN_VALUE(buf) (*(buf))
00051 #else
00052   unsigned char buffer[CGEN_MAX_INSN_SIZE];
00053 #define INSN_VALUE(buf) (buf)
00054 #endif
00055   char *addr;
00056   fragS *frag;
00057   int num_fixups;
00058   fixS *fixups[GAS_CGEN_MAX_FIXUPS];
00059   int indices[MAX_OPERAND_INSTANCES];
00060   sym_linkS *debug_sym_link;
00061 }
00062 m32r_insn;
00063 
00064 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
00065    boundary (i.e. was the first of two 16 bit insns).  */
00066 static m32r_insn prev_insn;
00067 
00068 /* Non-zero if we've seen a relaxable insn since the last 32 bit
00069    alignment request.  */
00070 static int seen_relaxable_p = 0;
00071 
00072 /* Non-zero if we are generating PIC code.  */
00073 int pic_code;
00074 
00075 /* Non-zero if -relax specified, in which case sufficient relocs are output
00076    for the linker to do relaxing.
00077    We do simple forms of relaxing internally, but they are always done.
00078    This flag does not apply to them.  */
00079 static int m32r_relax;
00080 
00081 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
00082    Each high/shigh reloc must be paired with it's low cousin in order to
00083    properly calculate the addend in a relocatable link (since there is a
00084    potential carry from the low to the high/shigh).
00085    This option is off by default though for user-written assembler code it
00086    might make sense to make the default be on (i.e. have gcc pass a flag
00087    to turn it off).  This warning must not be on for GCC created code as
00088    optimization may delete the low but not the high/shigh (at least we
00089    shouldn't assume or require it to).  */
00090 static int warn_unmatched_high = 0;
00091 
00092 /* 1 if -m32rx has been specified, in which case support for
00093      the extended M32RX instruction set should be enabled.
00094    2 if -m32r2 has been specified, in which case support for
00095      the extended M32R2 instruction set should be enabled.  */
00096 static int enable_m32rx = 0; /* Default to M32R.  */
00097 
00098 /* Non-zero if -m32rx -hidden has been specified, in which case support for
00099    the special M32RX instruction set should be enabled.  */
00100 static int enable_special = 0;
00101 
00102 /* Non-zero if -bitinst has been specified, in which case support
00103    for extended M32R bit-field instruction set should be enabled.  */
00104 static int enable_special_m32r = 1;
00105 
00106 /* Non-zero if -float has been specified, in which case support for
00107    extended M32R floating point instruction set should be enabled.  */
00108 static int enable_special_float = 0;
00109 
00110 /* Non-zero if the programmer should be warned when an explicit parallel
00111    instruction might have constraint violations.  */
00112 static int warn_explicit_parallel_conflicts = 1;
00113 
00114 /* Non-zero if the programmer should not receive any messages about
00115    parallel instruction with potential or real constraint violations.
00116    The ability to suppress these messages is intended only for hardware
00117    vendors testing the chip.  It superceedes
00118    warn_explicit_parallel_conflicts.  */
00119 static int ignore_parallel_conflicts = 0;
00120 
00121 /* Non-zero if insns can be made parallel.  */
00122 static int use_parallel = 0;
00123 
00124 /* Non-zero if optimizations should be performed.  */
00125 static int optimize;
00126 
00127 /* m32r er_flags.  */
00128 static int m32r_flags = 0;
00129 
00130 /* Stuff for .scomm symbols.  */
00131 static segT     sbss_section;
00132 static asection scom_section;
00133 static asymbol  scom_symbol;
00134 
00135 const char comment_chars[]        = ";";
00136 const char line_comment_chars[]   = "#";
00137 const char line_separator_chars[] = "!";
00138 const char EXP_CHARS[]            = "eE";
00139 const char FLT_CHARS[]            = "dD";
00140 
00141 /* Relocations against symbols are done in two
00142    parts, with a HI relocation and a LO relocation.  Each relocation
00143    has only 16 bits of space to store an addend.  This means that in
00144    order for the linker to handle carries correctly, it must be able
00145    to locate both the HI and the LO relocation.  This means that the
00146    relocations must appear in order in the relocation table.
00147 
00148    In order to implement this, we keep track of each unmatched HI
00149    relocation.  We then sort them so that they immediately precede the
00150    corresponding LO relocation.  */
00151 
00152 struct m32r_hi_fixup
00153 {
00154   /* Next HI fixup.  */
00155   struct m32r_hi_fixup *next;
00156 
00157   /* This fixup.  */
00158   fixS *fixp;
00159 
00160   /* The section this fixup is in.  */
00161   segT seg;
00162 };
00163 
00164 /* The list of unmatched HI relocs.  */
00165 
00166 static struct m32r_hi_fixup *m32r_hi_fixup_list;
00167 
00168 struct
00169 {
00170   enum bfd_architecture bfd_mach;
00171   int mach_flags;
00172 } mach_table[] =
00173 {
00174   { bfd_mach_m32r,  (1<<MACH_M32R) },
00175   { bfd_mach_m32rx, (1<<MACH_M32RX) },
00176   { bfd_mach_m32r2, (1<<MACH_M32R2) }
00177 };
00178 
00179 static void
00180 allow_m32rx (int on)
00181 {
00182   enable_m32rx = on;
00183 
00184   if (stdoutput != NULL)
00185     bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach);
00186 
00187   if (gas_cgen_cpu_desc != NULL)
00188     gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
00189 }
00190 
00191 #define M32R_SHORTOPTS "O::K:"
00192 
00193 const char *md_shortopts = M32R_SHORTOPTS;
00194 
00195 enum md_option_enums
00196 {
00197   OPTION_M32R = OPTION_MD_BASE,
00198   OPTION_M32RX,
00199   OPTION_M32R2,
00200   OPTION_BIG,
00201   OPTION_LITTLE,
00202   OPTION_PARALLEL,
00203   OPTION_NO_PARALLEL,
00204   OPTION_WARN_PARALLEL,
00205   OPTION_NO_WARN_PARALLEL,
00206   OPTION_IGNORE_PARALLEL,
00207   OPTION_NO_IGNORE_PARALLEL,
00208   OPTION_SPECIAL,
00209   OPTION_SPECIAL_M32R,
00210   OPTION_NO_SPECIAL_M32R,
00211   OPTION_SPECIAL_FLOAT,
00212   OPTION_WARN_UNMATCHED,
00213   OPTION_NO_WARN_UNMATCHED
00214 };
00215 
00216 struct option md_longopts[] =
00217 {
00218   {"m32r",  no_argument, NULL, OPTION_M32R},
00219   {"m32rx", no_argument, NULL, OPTION_M32RX},
00220   {"m32r2", no_argument, NULL, OPTION_M32R2},
00221   {"big", no_argument, NULL, OPTION_BIG},
00222   {"little", no_argument, NULL, OPTION_LITTLE},
00223   {"EB", no_argument, NULL, OPTION_BIG},
00224   {"EL", no_argument, NULL, OPTION_LITTLE},
00225   {"parallel", no_argument, NULL, OPTION_PARALLEL},
00226   {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL},
00227   {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
00228   {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
00229   {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
00230   {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
00231   {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL},
00232   {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL},
00233   {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
00234   {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
00235   {"hidden", no_argument, NULL, OPTION_SPECIAL},
00236   {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
00237   {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
00238   {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
00239   /* Sigh.  I guess all warnings must now have both variants.  */
00240   {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
00241   {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
00242   {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
00243   {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
00244   {NULL, no_argument, NULL, 0}
00245 };
00246 
00247 size_t md_longopts_size = sizeof (md_longopts);
00248 
00249 static void
00250 little (int on)
00251 {
00252   target_big_endian = ! on;
00253 }
00254 
00255 /* Use parallel execution.  */
00256 
00257 static int
00258 parallel (void)
00259 {
00260   if (! enable_m32rx)
00261     return 0;
00262 
00263   if (use_parallel == 1)
00264     return 1;
00265 
00266   return 0;
00267 }
00268 
00269 int
00270 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
00271 {
00272   switch (c)
00273     {
00274     case 'O':
00275       optimize = 1;
00276       use_parallel = 1;
00277       break;
00278 
00279     case OPTION_M32R:
00280       allow_m32rx (0);
00281       break;
00282 
00283     case OPTION_M32RX:
00284       allow_m32rx (1);
00285       break;
00286 
00287     case OPTION_M32R2:
00288       allow_m32rx (2);
00289       enable_special = 1;
00290       enable_special_m32r = 1;
00291       break;
00292 
00293     case OPTION_BIG:
00294       target_big_endian = 1;
00295       break;
00296 
00297     case OPTION_LITTLE:
00298       target_big_endian = 0;
00299       break;
00300 
00301     case OPTION_PARALLEL:
00302       use_parallel = 1;
00303       break;
00304 
00305     case OPTION_NO_PARALLEL:
00306       use_parallel = 0;
00307       break;
00308 
00309     case OPTION_WARN_PARALLEL:
00310       warn_explicit_parallel_conflicts = 1;
00311       break;
00312 
00313     case OPTION_NO_WARN_PARALLEL:
00314       warn_explicit_parallel_conflicts = 0;
00315       break;
00316 
00317     case OPTION_IGNORE_PARALLEL:
00318       ignore_parallel_conflicts = 1;
00319       break;
00320 
00321     case OPTION_NO_IGNORE_PARALLEL:
00322       ignore_parallel_conflicts = 0;
00323       break;
00324 
00325     case OPTION_SPECIAL:
00326       if (enable_m32rx)
00327        enable_special = 1;
00328       else
00329        {
00330          /* Pretend that we do not recognise this option.  */
00331          as_bad (_("Unrecognised option: -hidden"));
00332          return 0;
00333        }
00334       break;
00335 
00336     case OPTION_SPECIAL_M32R:
00337       enable_special_m32r = 1;
00338       break;
00339 
00340     case OPTION_NO_SPECIAL_M32R:
00341       enable_special_m32r = 0;
00342       break;
00343 
00344     case OPTION_SPECIAL_FLOAT:
00345       enable_special_float = 1;
00346       break;
00347 
00348     case OPTION_WARN_UNMATCHED:
00349       warn_unmatched_high = 1;
00350       break;
00351 
00352     case OPTION_NO_WARN_UNMATCHED:
00353       warn_unmatched_high = 0;
00354       break;
00355 
00356     case 'K':
00357       if (strcmp (arg, "PIC") != 0)
00358         as_warn (_("Unrecognized option following -K"));
00359       else
00360         pic_code = 1;
00361       break;
00362 
00363     default:
00364       return 0;
00365     }
00366 
00367   return 1;
00368 }
00369 
00370 void
00371 md_show_usage (FILE *stream)
00372 {
00373   fprintf (stream, _(" M32R specific command line options:\n"));
00374 
00375   fprintf (stream, _("\
00376   -m32r                   disable support for the m32rx instruction set\n"));
00377   fprintf (stream, _("\
00378   -m32rx                  support the extended m32rx instruction set\n"));
00379   fprintf (stream, _("\
00380   -m32r2                  support the extended m32r2 instruction set\n"));
00381   fprintf (stream, _("\
00382   -EL,-little             produce little endian code and data\n"));
00383   fprintf (stream, _("\
00384   -EB,-big                produce big endian code and data\n"));
00385   fprintf (stream, _("\
00386   -parallel               try to combine instructions in parallel\n"));
00387   fprintf (stream, _("\
00388   -no-parallel            disable -parallel\n"));
00389   fprintf (stream, _("\
00390   -no-bitinst             disallow the M32R2's extended bit-field instructions\n"));
00391   fprintf (stream, _("\
00392   -O                      try to optimize code.  Implies -parallel\n"));
00393 
00394   fprintf (stream, _("\
00395   -warn-explicit-parallel-conflicts     warn when parallel instructions\n"));
00396   fprintf (stream, _("\
00397                                          might violate contraints\n"));
00398   fprintf (stream, _("\
00399   -no-warn-explicit-parallel-conflicts  do not warn when parallel\n"));
00400   fprintf (stream, _("\
00401                                          instructions might violate contraints\n"));
00402   fprintf (stream, _("\
00403   -Wp                     synonym for -warn-explicit-parallel-conflicts\n"));
00404   fprintf (stream, _("\
00405   -Wnp                    synonym for -no-warn-explicit-parallel-conflicts\n"));
00406   fprintf (stream, _("\
00407   -ignore-parallel-conflicts            do not check parallel instructions\n"));
00408   fprintf (stream, _("\
00409                                          fo contraint violations\n"));
00410   fprintf (stream, _("\
00411   -no-ignore-parallel-conflicts         check parallel instructions for\n"));
00412   fprintf (stream, _("\
00413                                          contraint violations\n"));
00414   fprintf (stream, _("\
00415   -Ip                     synonym for -ignore-parallel-conflicts\n"));
00416   fprintf (stream, _("\
00417   -nIp                    synonym for -no-ignore-parallel-conflicts\n"));
00418 
00419   fprintf (stream, _("\
00420   -warn-unmatched-high    warn when an (s)high reloc has no matching low reloc\n"));
00421   fprintf (stream, _("\
00422   -no-warn-unmatched-high do not warn about missing low relocs\n"));
00423   fprintf (stream, _("\
00424   -Wuh                    synonym for -warn-unmatched-high\n"));
00425   fprintf (stream, _("\
00426   -Wnuh                   synonym for -no-warn-unmatched-high\n"));
00427 
00428   fprintf (stream, _("\
00429   -KPIC                   generate PIC\n"));
00430 }
00431 
00432 /* Set by md_assemble for use by m32r_fill_insn.  */
00433 static subsegT prev_subseg;
00434 static segT prev_seg;
00435 
00436 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
00437 symbolS * GOT_symbol;
00438 
00439 static inline int
00440 m32r_PIC_related_p (symbolS *sym)
00441 {
00442   expressionS *exp;
00443 
00444   if (! sym)
00445     return 0;
00446 
00447   if (sym == GOT_symbol)
00448     return 1;
00449 
00450   exp = symbol_get_value_expression (sym);
00451 
00452   return (exp->X_op == O_PIC_reloc
00453           || exp->X_md == BFD_RELOC_M32R_26_PLTREL
00454           || m32r_PIC_related_p (exp->X_add_symbol)
00455           || m32r_PIC_related_p (exp->X_op_symbol));
00456 }
00457 
00458 static inline int
00459 m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
00460 {
00461   expressionS *exp = main_exp;
00462 
00463   if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
00464     return 1;
00465 
00466   if (exp->X_op == O_symbol && exp->X_add_symbol)
00467     {
00468       if (exp->X_add_symbol == GOT_symbol)
00469         {
00470           *r_type_p = BFD_RELOC_M32R_GOTPC24;
00471           return 0;
00472         }
00473     }
00474   else if (exp->X_op == O_add)
00475     {
00476       exp = symbol_get_value_expression (exp->X_add_symbol);
00477       if (! exp)
00478         return 0;
00479     }
00480 
00481   if (exp->X_op == O_PIC_reloc)
00482     {
00483       *r_type_p = exp->X_md;
00484       if (exp == main_exp)
00485         exp->X_op = O_symbol;
00486       else
00487        {
00488           main_exp->X_add_symbol = exp->X_add_symbol;
00489           main_exp->X_add_number += exp->X_add_number;
00490        }
00491     }
00492   else
00493     return (m32r_PIC_related_p (exp->X_add_symbol)
00494             || m32r_PIC_related_p (exp->X_op_symbol));
00495 
00496   return 0;
00497 }
00498 
00499 /* FIXME: Should be machine generated.  */
00500 #define NOP_INSN     0x7000
00501 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot.  */
00502 
00503 /* This is called from HANDLE_ALIGN in write.c.  Fill in the contents
00504    of an rs_align_code fragment.  */
00505 
00506 void
00507 m32r_handle_align (fragS *fragp)
00508 {
00509   static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
00510   static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
00511 
00512   int bytes, fix;
00513   char *p;
00514 
00515   if (fragp->fr_type != rs_align_code)
00516     return;
00517 
00518   bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
00519   p = fragp->fr_literal + fragp->fr_fix;
00520   fix = 0;
00521 
00522   if (bytes & 1)
00523     {
00524       fix = 1;
00525       *p++ = 0;
00526       bytes--;
00527     }
00528 
00529   if (bytes & 2)
00530     {
00531       memcpy (p, nop_pattern, 2);
00532       p += 2;
00533       bytes -= 2;
00534       fix += 2;
00535     }
00536 
00537   memcpy (p, multi_nop_pattern, 4);
00538 
00539   fragp->fr_fix += fix;
00540   fragp->fr_var = 4;
00541 }
00542 
00543 /* If the last instruction was the first of 2 16 bit insns,
00544    output a nop to move the PC to a 32 bit boundary.
00545 
00546    This is done via an alignment specification since branch relaxing
00547    may make it unnecessary.
00548 
00549    Internally, we need to output one of these each time a 32 bit insn is
00550    seen after an insn that is relaxable.  */
00551 
00552 static void
00553 fill_insn (int ignore ATTRIBUTE_UNUSED)
00554 {
00555   frag_align_code (2, 0);
00556   prev_insn.insn = NULL;
00557   seen_relaxable_p = 0;
00558 }
00559 
00560 /* Record the symbol so that when we output the insn, we can create
00561    a symbol that is at the start of the instruction.  This is used
00562    to emit the label for the start of a breakpoint without causing
00563    the assembler to emit a NOP if the previous instruction was a
00564    16 bit instruction.  */
00565 
00566 static void
00567 debug_sym (int ignore ATTRIBUTE_UNUSED)
00568 {
00569   char *name;
00570   char delim;
00571   char *end_name;
00572   symbolS *symbolP;
00573   sym_linkS *link;
00574 
00575   name = input_line_pointer;
00576   delim = get_symbol_end ();
00577   end_name = input_line_pointer;
00578 
00579   if ((symbolP = symbol_find (name)) == NULL
00580       && (symbolP = md_undefined_symbol (name)) == NULL)
00581     symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
00582 
00583   symbol_table_insert (symbolP);
00584   if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
00585                                  || S_IS_EXTERNAL (symbolP)
00586                                  || S_IS_WEAK (symbolP)))
00587     /* xgettext:c-format */
00588     as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
00589 
00590   else
00591     {
00592       link = (sym_linkS *) xmalloc (sizeof (sym_linkS));
00593       link->symbol = symbolP;
00594       link->next = debug_sym_link;
00595       debug_sym_link = link;
00596       symbol_get_obj (symbolP)->local = 1;
00597     }
00598 
00599   *end_name = delim;
00600   demand_empty_rest_of_line ();
00601 }
00602 
00603 /* Second pass to expanding the debug symbols, go through linked
00604    list of symbols and reassign the address.  */
00605 
00606 static void
00607 expand_debug_syms (sym_linkS *syms, int align)
00608 {
00609   char *save_input_line = input_line_pointer;
00610   sym_linkS *next_syms;
00611 
00612   if (!syms)
00613     return;
00614 
00615   (void) frag_align_code (align, 0);
00616   for (; syms != (sym_linkS *) 0; syms = next_syms)
00617     {
00618       symbolS *symbolP = syms->symbol;
00619       next_syms = syms->next;
00620       input_line_pointer = ".\n";
00621       pseudo_set (symbolP);
00622       free ((char *) syms);
00623     }
00624 
00625   input_line_pointer = save_input_line;
00626 }
00627 
00628 void
00629 m32r_flush_pending_output (void)
00630 {
00631   if (debug_sym_link)
00632     {
00633       expand_debug_syms (debug_sym_link, 1);
00634       debug_sym_link = (sym_linkS *) 0;
00635     }
00636 }
00637 
00638 /* Cover function to fill_insn called after a label and at end of assembly.
00639    The result is always 1: we're called in a conditional to see if the
00640    current line is a label.  */
00641 
00642 int
00643 m32r_fill_insn (int done)
00644 {
00645   if (prev_seg != NULL)
00646     {
00647       segT seg = now_seg;
00648       subsegT subseg = now_subseg;
00649 
00650       subseg_set (prev_seg, prev_subseg);
00651 
00652       fill_insn (0);
00653 
00654       subseg_set (seg, subseg);
00655     }
00656 
00657   if (done && debug_sym_link)
00658     {
00659       expand_debug_syms (debug_sym_link, 1);
00660       debug_sym_link = (sym_linkS *) 0;
00661     }
00662 
00663   return 1;
00664 }
00665 
00666 /* The default target format to use.  */
00667 
00668 const char *
00669 m32r_target_format (void)
00670 {
00671 #ifdef TE_LINUX
00672   if (target_big_endian)
00673     return "elf32-m32r-linux";
00674   else
00675     return "elf32-m32rle-linux";
00676 #else
00677   if (target_big_endian)
00678     return "elf32-m32r";
00679   else
00680     return "elf32-m32rle";
00681 #endif
00682 }
00683 
00684 void
00685 md_begin (void)
00686 {
00687   flagword applicable;
00688   segT seg;
00689   subsegT subseg;
00690 
00691   /* Initialize the `cgen' interface.  */
00692 
00693   /* Set the machine number and endian.  */
00694   gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
00695                                      CGEN_CPU_OPEN_ENDIAN,
00696                                      (target_big_endian ?
00697                                       CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE),
00698                                      CGEN_CPU_OPEN_END);
00699   m32r_cgen_init_asm (gas_cgen_cpu_desc);
00700 
00701   /* The operand instance table is used during optimization to determine
00702      which insns can be executed in parallel.  It is also used to give
00703      warnings regarding operand interference in parallel insns.  */
00704   m32r_cgen_init_opinst_table (gas_cgen_cpu_desc);
00705 
00706   /* This is a callback from cgen to gas to parse operands.  */
00707   cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
00708 
00709   /* Save the current subseg so we can restore it [it's the default one and
00710      we don't want the initial section to be .sbss].  */
00711   seg    = now_seg;
00712   subseg = now_subseg;
00713 
00714   /* The sbss section is for local .scomm symbols.  */
00715   sbss_section = subseg_new (".sbss", 0);
00716 
00717   /* This is copied from perform_an_assembly_pass.  */
00718   applicable = bfd_applicable_section_flags (stdoutput);
00719   bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
00720 
00721   subseg_set (seg, subseg);
00722 
00723   /* We must construct a fake section similar to bfd_com_section
00724      but with the name .scommon.  */
00725   scom_section                = bfd_com_section;
00726   scom_section.name           = ".scommon";
00727   scom_section.output_section = & scom_section;
00728   scom_section.symbol         = & scom_symbol;
00729   scom_section.symbol_ptr_ptr = & scom_section.symbol;
00730   scom_symbol                 = * bfd_com_section.symbol;
00731   scom_symbol.name            = ".scommon";
00732   scom_symbol.section         = & scom_section;
00733 
00734   allow_m32rx (enable_m32rx);
00735 
00736   gas_cgen_initialize_saved_fixups_array ();
00737 }
00738 
00739 #define OPERAND_IS_COND_BIT(operand, indices, index) \
00740   ((operand)->hw_type == HW_H_COND               \
00741    || ((operand)->hw_type == HW_H_PSW)                  \
00742    || ((operand)->hw_type == HW_H_CR                    \
00743        && (indices [index] == 0 || indices [index] == 1)))
00744 
00745 /* Returns true if an output of instruction 'a' is referenced by an operand
00746    of instruction 'b'.  If 'check_outputs' is true then b's outputs are
00747    checked, otherwise its inputs are examined.  */
00748 
00749 static int
00750 first_writes_to_seconds_operands (m32r_insn *a,
00751                               m32r_insn *b,
00752                               const int check_outputs)
00753 {
00754   const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
00755   const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
00756   int a_index;
00757 
00758   if (ignore_parallel_conflicts)
00759     return 0;
00760 
00761   /* If at least one of the instructions takes no operands, then there is
00762      nothing to check.  There really are instructions without operands,
00763      eg 'nop'.  */
00764   if (a_operands == NULL || b_ops == NULL)
00765     return 0;
00766 
00767   /* Scan the operand list of 'a' looking for an output operand.  */
00768   for (a_index = 0;
00769        a_operands->type != CGEN_OPINST_END;
00770        a_index ++, a_operands ++)
00771     {
00772       if (a_operands->type == CGEN_OPINST_OUTPUT)
00773        {
00774          int b_index;
00775          const CGEN_OPINST *b_operands = b_ops;
00776 
00777          /* Special Case:
00778             The Condition bit 'C' is a shadow of the CBR register (control
00779             register 1) and also a shadow of bit 31 of the program status
00780             word (control register 0).  For now this is handled here, rather
00781             than by cgen....  */
00782 
00783          if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
00784            {
00785              /* Scan operand list of 'b' looking for another reference to the
00786                condition bit, which goes in the right direction.  */
00787              for (b_index = 0;
00788                  b_operands->type != CGEN_OPINST_END;
00789                  b_index++, b_operands++)
00790               {
00791                 if ((b_operands->type
00792                      == (check_outputs
00793                         ? CGEN_OPINST_OUTPUT
00794                         : CGEN_OPINST_INPUT))
00795                     && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
00796                   return 1;
00797               }
00798            }
00799          else
00800            {
00801              /* Scan operand list of 'b' looking for an operand that
00802                references the same hardware element, and which goes in the
00803                right direction.  */
00804              for (b_index = 0;
00805                  b_operands->type != CGEN_OPINST_END;
00806                  b_index++, b_operands++)
00807               {
00808                 if ((b_operands->type
00809                      == (check_outputs
00810                         ? CGEN_OPINST_OUTPUT
00811                         : CGEN_OPINST_INPUT))
00812                     && (b_operands->hw_type == a_operands->hw_type)
00813                     && (a->indices[a_index] == b->indices[b_index]))
00814                   return 1;
00815               }
00816            }
00817        }
00818     }
00819 
00820   return 0;
00821 }
00822 
00823 /* Returns true if the insn can (potentially) alter the program counter.  */
00824 
00825 static int
00826 writes_to_pc (m32r_insn *a)
00827 {
00828   if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
00829       || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
00830     return 1;
00831   return 0;
00832 }
00833 
00834 /* Return NULL if the two 16 bit insns can be executed in parallel.
00835    Otherwise return a pointer to an error message explaining why not.  */
00836 
00837 static const char *
00838 can_make_parallel (m32r_insn *a, m32r_insn *b)
00839 {
00840   PIPE_ATTR a_pipe;
00841   PIPE_ATTR b_pipe;
00842 
00843   /* Make sure the instructions are the right length.  */
00844   if (CGEN_FIELDS_BITSIZE (&a->fields) != 16
00845       || CGEN_FIELDS_BITSIZE (&b->fields) != 16)
00846     abort ();
00847 
00848   if (first_writes_to_seconds_operands (a, b, TRUE))
00849     return _("instructions write to the same destination register.");
00850 
00851   a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
00852   b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
00853 
00854   /* Make sure that the instructions use the correct execution pipelines.  */
00855   if (a_pipe == PIPE_NONE
00856       || b_pipe == PIPE_NONE)
00857     return _("Instructions do not use parallel execution pipelines.");
00858 
00859   /* Leave this test for last, since it is the only test that can
00860      go away if the instructions are swapped, and we want to make
00861      sure that any other errors are detected before this happens.  */
00862   if (a_pipe == PIPE_S
00863       || b_pipe == PIPE_O
00864       || (b_pipe == PIPE_O_OS && (enable_m32rx != 2)))
00865     return _("Instructions share the same execution pipeline");
00866 
00867   return NULL;
00868 }
00869 
00870 /* Force the top bit of the second 16-bit insn to be set.  */
00871 
00872 static void
00873 make_parallel (CGEN_INSN_BYTES_PTR buffer)
00874 {
00875 #if CGEN_INT_INSN_P
00876   *buffer |= 0x8000;
00877 #else
00878   buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
00879     |= 0x80;
00880 #endif
00881 }
00882 
00883 /* Same as make_parallel except buffer contains the bytes in target order.  */
00884 
00885 static void
00886 target_make_parallel (char *buffer)
00887 {
00888   buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
00889     |= 0x80;
00890 }
00891 
00892 /* Assemble two instructions with an explicit parallel operation (||) or
00893    sequential operation (->).  */
00894 
00895 static void
00896 assemble_two_insns (char *str1, char *str2, int parallel_p)
00897 {
00898   char *str3;
00899   m32r_insn first;
00900   m32r_insn second;
00901   char *errmsg;
00902   char save_str2 = *str2;
00903 
00904   /* Separate the two instructions.  */
00905   *str2 = 0;
00906 
00907   /* Make sure the two insns begin on a 32 bit boundary.
00908      This is also done for the serial case (foo -> bar), relaxing doesn't
00909      affect insns written like this.
00910      Note that we must always do this as we can't assume anything about
00911      whether we're currently on a 32 bit boundary or not.  Relaxing may
00912      change this.  */
00913   fill_insn (0);
00914 
00915   first.debug_sym_link = debug_sym_link;
00916   debug_sym_link = (sym_linkS *) 0;
00917 
00918   /* Parse the first instruction.  */
00919   if (! (first.insn = m32r_cgen_assemble_insn
00920         (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
00921     {
00922       as_bad (errmsg);
00923       return;
00924     }
00925 
00926   /* Check it.  */
00927   if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
00928     {
00929       /* xgettext:c-format  */
00930       as_bad (_("not a 16 bit instruction '%s'"), str1);
00931       return;
00932     }
00933 #ifdef E_M32R2_ARCH
00934   else if ((enable_m32rx == 1)
00935            /* FIXME: Need standard macro to perform this test.  */
00936            && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
00937                 & (1 << MACH_M32R2))
00938                && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
00939                     & (1 << MACH_M32RX)))))
00940     {
00941       /* xgettext:c-format  */
00942       as_bad (_("instruction '%s' is for the M32R2 only"), str1);
00943       return;
00944     }
00945   else if ((! enable_special
00946             && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
00947            || (! enable_special_m32r
00948                && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)))
00949 #else
00950   else if (! enable_special
00951       && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
00952 #endif
00953     {
00954       /* xgettext:c-format  */
00955       as_bad (_("unknown instruction '%s'"), str1);
00956       return;
00957     }
00958   else if (! enable_m32rx
00959           /* FIXME: Need standard macro to perform this test.  */
00960           && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
00961               == (1 << MACH_M32RX)))
00962     {
00963       /* xgettext:c-format  */
00964       as_bad (_("instruction '%s' is for the M32RX only"), str1);
00965       return;
00966     }
00967 
00968   /* Check to see if this is an allowable parallel insn.  */
00969   if (parallel_p
00970       && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
00971     {
00972       /* xgettext:c-format  */
00973       as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
00974       return;
00975     }
00976 
00977   /* Restore the original assembly text, just in case it is needed.  */
00978   *str2 = save_str2;
00979 
00980   /* Save the original string pointer.  */
00981   str3 = str1;
00982 
00983   /* Advanced past the parsed string.  */
00984   str1 = str2 + 2;
00985 
00986   /* Remember the entire string in case it is needed for error
00987      messages.  */
00988   str2 = str3;
00989 
00990   /* Convert the opcode to lower case.  */
00991   {
00992     char *s2 = str1;
00993 
00994     while (ISSPACE (*s2++))
00995       continue;
00996 
00997     --s2;
00998 
00999     while (ISALNUM (*s2))
01000       {
01001        *s2 = TOLOWER (*s2);
01002        s2++;
01003       }
01004   }
01005 
01006   /* Preserve any fixups that have been generated and reset the list
01007      to empty.  */
01008   gas_cgen_save_fixups (0);
01009 
01010   /* Get the indices of the operands of the instruction.  */
01011   /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
01012      doesn't seem right.  Perhaps allow passing fields like we do insn.  */
01013   /* FIXME: ALIAS insns do not have operands, so we use this function
01014      to find the equivalent insn and overwrite the value stored in our
01015      structure.  We still need the original insn, however, since this
01016      may have certain attributes that are not present in the unaliased
01017      version (eg relaxability).  When aliases behave differently this
01018      may have to change.  */
01019   first.orig_insn = first.insn;
01020   {
01021     CGEN_FIELDS tmp_fields;
01022     first.insn = cgen_lookup_get_insn_operands
01023       (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
01024        first.indices, &tmp_fields);
01025   }
01026 
01027   if (first.insn == NULL)
01028     as_fatal (_("internal error: lookup/get operands failed"));
01029 
01030   second.debug_sym_link = NULL;
01031 
01032   /* Parse the second instruction.  */
01033   if (! (second.insn = m32r_cgen_assemble_insn
01034         (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
01035     {
01036       as_bad (errmsg);
01037       return;
01038     }
01039 
01040   /* Check it.  */
01041   if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
01042     {
01043       /* xgettext:c-format  */
01044       as_bad (_("not a 16 bit instruction '%s'"), str1);
01045       return;
01046     }
01047 #ifdef E_M32R2_ARCH
01048   else if ((enable_m32rx == 1)
01049            /* FIXME: Need standard macro to perform this test.  */
01050            && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
01051                 & (1 << MACH_M32R2))
01052                && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH)
01053                     & (1 << MACH_M32RX)))))
01054     {
01055       /* xgettext:c-format  */
01056       as_bad (_("instruction '%s' is for the M32R2 only"), str1);
01057       return;
01058     }
01059   else if ((! enable_special
01060             && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
01061            || (! enable_special_m32r
01062                && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)))
01063 #else
01064   else if (! enable_special
01065       && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
01066 #endif
01067     {
01068       /* xgettext:c-format  */
01069       as_bad (_("unknown instruction '%s'"), str1);
01070       return;
01071     }
01072   else if (! enable_m32rx
01073       && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
01074     {
01075       /* xgettext:c-format  */
01076       as_bad (_("instruction '%s' is for the M32RX only"), str1);
01077       return;
01078     }
01079 
01080   /* Check to see if this is an allowable parallel insn.  */
01081   if (parallel_p
01082       && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
01083     {
01084       /* xgettext:c-format  */
01085       as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
01086       return;
01087     }
01088 
01089   if (parallel_p && ! enable_m32rx)
01090     {
01091       if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
01092          && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
01093        {
01094          /* xgettext:c-format  */
01095          as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
01096          return;
01097        }
01098     }
01099 
01100   /* Get the indices of the operands of the instruction.  */
01101   second.orig_insn = second.insn;
01102   {
01103     CGEN_FIELDS tmp_fields;
01104     second.insn = cgen_lookup_get_insn_operands
01105       (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
01106        second.indices, &tmp_fields);
01107   }
01108 
01109   if (second.insn == NULL)
01110     as_fatal (_("internal error: lookup/get operands failed"));
01111 
01112   /* We assume that if the first instruction writes to a register that is
01113      read by the second instruction it is because the programmer intended
01114      this to happen, (after all they have explicitly requested that these
01115      two instructions be executed in parallel).  Although if the global
01116      variable warn_explicit_parallel_conflicts is true then we do generate
01117      a warning message.  Similarly we assume that parallel branch and jump
01118      instructions are deliberate and should not produce errors.  */
01119 
01120   if (parallel_p && warn_explicit_parallel_conflicts)
01121     {
01122       if (first_writes_to_seconds_operands (&first, &second, FALSE))
01123        /* xgettext:c-format  */
01124        as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
01125 
01126       if (first_writes_to_seconds_operands (&second, &first, FALSE))
01127        /* xgettext:c-format  */
01128        as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
01129     }
01130 
01131   if (!parallel_p
01132       || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL)
01133     {
01134       /* Get the fixups for the first instruction.  */
01135       gas_cgen_swap_fixups (0);
01136 
01137       /* Write it out.  */
01138       expand_debug_syms (first.debug_sym_link, 1);
01139       gas_cgen_finish_insn (first.orig_insn, first.buffer,
01140                          CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
01141 
01142       /* Force the top bit of the second insn to be set.  */
01143       if (parallel_p)
01144        make_parallel (second.buffer);
01145 
01146       /* Get its fixups.  */
01147       gas_cgen_restore_fixups (0);
01148 
01149       /* Write it out.  */
01150       expand_debug_syms (second.debug_sym_link, 1);
01151       gas_cgen_finish_insn (second.orig_insn, second.buffer,
01152                          CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
01153     }
01154   /* Try swapping the instructions to see if they work that way.  */
01155   else if (can_make_parallel (&second, &first) == NULL)
01156     {
01157       /* Write out the second instruction first.  */
01158       expand_debug_syms (second.debug_sym_link, 1);
01159       gas_cgen_finish_insn (second.orig_insn, second.buffer,
01160                          CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL);
01161 
01162       /* Force the top bit of the first instruction to be set.  */
01163       make_parallel (first.buffer);
01164 
01165       /* Get the fixups for the first instruction.  */
01166       gas_cgen_restore_fixups (0);
01167 
01168       /* Write out the first instruction.  */
01169       expand_debug_syms (first.debug_sym_link, 1);
01170       gas_cgen_finish_insn (first.orig_insn, first.buffer,
01171                          CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL);
01172     }
01173   else
01174     {
01175       as_bad ("'%s': %s", str2, errmsg);
01176       return;
01177     }
01178 
01179   if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)
01180       || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
01181     m32r_flags |= E_M32R_HAS_HIDDEN_INST;
01182   if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R)
01183       || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))
01184     m32r_flags |= E_M32R_HAS_BIT_INST;
01185   if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT)
01186       || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT))
01187     m32r_flags |= E_M32R_HAS_FLOAT_INST;
01188 
01189   /* Set these so m32r_fill_insn can use them.  */
01190   prev_seg    = now_seg;
01191   prev_subseg = now_subseg;
01192 }
01193 
01194 void
01195 md_assemble (char *str)
01196 {
01197   m32r_insn insn;
01198   char *errmsg;
01199   char *str2 = NULL;
01200 
01201   /* Initialize GAS's cgen interface for a new instruction.  */
01202   gas_cgen_init_parse ();
01203 
01204   /* Look for a parallel instruction separator.  */
01205   if ((str2 = strstr (str, "||")) != NULL)
01206     {
01207       assemble_two_insns (str, str2, 1);
01208       m32r_flags |= E_M32R_HAS_PARALLEL;
01209       return;
01210     }
01211 
01212   /* Also look for a sequential instruction separator.  */
01213   if ((str2 = strstr (str, "->")) != NULL)
01214     {
01215       assemble_two_insns (str, str2, 0);
01216       return;
01217     }
01218 
01219   insn.debug_sym_link = debug_sym_link;
01220   debug_sym_link = (sym_linkS *) 0;
01221 
01222   insn.insn = m32r_cgen_assemble_insn
01223     (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg);
01224 
01225   if (!insn.insn)
01226     {
01227       as_bad (errmsg);
01228       return;
01229     }
01230 
01231 #ifdef E_M32R2_ARCH
01232   if ((enable_m32rx == 1)
01233        /* FIXME: Need standard macro to perform this test.  */
01234       && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
01235            & (1 << MACH_M32R2))
01236           && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH)
01237                & (1 << MACH_M32RX)))))
01238     {
01239       /* xgettext:c-format  */
01240       as_bad (_("instruction '%s' is for the M32R2 only"), str);
01241       return;
01242     }
01243   else if ((! enable_special
01244        && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
01245       || (! enable_special_m32r
01246           && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)))
01247 #else
01248   if (! enable_special
01249       && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
01250 #endif
01251     {
01252       /* xgettext:c-format  */
01253       as_bad (_("unknown instruction '%s'"), str);
01254       return;
01255     }
01256   else if (! enable_m32rx
01257           && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
01258     {
01259       /* xgettext:c-format  */
01260       as_bad (_("instruction '%s' is for the M32RX only"), str);
01261       return;
01262     }
01263 
01264   if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
01265     m32r_flags |= E_M32R_HAS_HIDDEN_INST;
01266   if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))
01267     m32r_flags |= E_M32R_HAS_BIT_INST;
01268   if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT))
01269     m32r_flags |= E_M32R_HAS_FLOAT_INST;
01270 
01271   if (CGEN_INSN_BITSIZE (insn.insn) == 32)
01272     {
01273       /* 32 bit insns must live on 32 bit boundaries.  */
01274       if (prev_insn.insn || seen_relaxable_p)
01275        {
01276          /* ??? If calling fill_insn too many times turns us into a memory
01277             pig, can we call a fn to assemble a nop instead of
01278             !seen_relaxable_p?  */
01279          fill_insn (0);
01280        }
01281 
01282       expand_debug_syms (insn.debug_sym_link, 2);
01283 
01284       /* Doesn't really matter what we pass for RELAX_P here.  */
01285       gas_cgen_finish_insn (insn.insn, insn.buffer,
01286                          CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL);
01287     }
01288   else
01289     {
01290       int on_32bit_boundary_p;
01291       int swap = FALSE;
01292 
01293       if (CGEN_INSN_BITSIZE (insn.insn) != 16)
01294        abort ();
01295 
01296       insn.orig_insn = insn.insn;
01297 
01298       /* If the previous insn was relaxable, then it may be expanded
01299         to fill the current 16 bit slot.  Emit a NOP here to occupy
01300         this slot, so that we can start at optimizing at a 32 bit
01301         boundary.  */
01302       if (prev_insn.insn && seen_relaxable_p && optimize)
01303        fill_insn (0);
01304 
01305       if (enable_m32rx)
01306        {
01307          /* Get the indices of the operands of the instruction.
01308             FIXME: See assemble_parallel for notes on orig_insn.  */
01309          {
01310            CGEN_FIELDS tmp_fields;
01311            insn.insn = cgen_lookup_get_insn_operands
01312              (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
01313               16, insn.indices, &tmp_fields);
01314          }
01315 
01316          if (insn.insn == NULL)
01317            as_fatal (_("internal error: lookup/get operands failed"));
01318        }
01319 
01320       /* Compute whether we're on a 32 bit boundary or not.
01321         prev_insn.insn is NULL when we're on a 32 bit boundary.  */
01322       on_32bit_boundary_p = prev_insn.insn == NULL;
01323 
01324       /* Change a frag to, if each insn to swap is in a different frag.
01325          It must keep only one instruction in a frag.  */
01326       if (parallel() && on_32bit_boundary_p)
01327         {
01328           frag_wane (frag_now);
01329           frag_new (0);
01330         }
01331 
01332       /* Look to see if this instruction can be combined with the
01333         previous instruction to make one, parallel, 32 bit instruction.
01334         If the previous instruction (potentially) changed the flow of
01335         program control, then it cannot be combined with the current
01336         instruction.  If the current instruction is relaxable, then it
01337         might be replaced with a longer version, so we cannot combine it.
01338         Also if the output of the previous instruction is used as an
01339         input to the current instruction then it cannot be combined.
01340         Otherwise call can_make_parallel() with both orderings of the
01341         instructions to see if they can be combined.  */
01342       if (! on_32bit_boundary_p
01343          && parallel ()
01344          && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
01345          && ! writes_to_pc (&prev_insn)
01346          && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE))
01347        {
01348          if (can_make_parallel (&prev_insn, &insn) == NULL)
01349            make_parallel (insn.buffer);
01350          else if (can_make_parallel (&insn, &prev_insn) == NULL)
01351            swap = TRUE;
01352        }
01353 
01354       expand_debug_syms (insn.debug_sym_link, 1);
01355 
01356       {
01357        int i;
01358        finished_insnS fi;
01359 
01360        /* Ensure each pair of 16 bit insns is in the same frag.  */
01361        frag_grow (4);
01362 
01363        gas_cgen_finish_insn (insn.orig_insn, insn.buffer,
01364                            CGEN_FIELDS_BITSIZE (&insn.fields),
01365                            1 /* relax_p  */, &fi);
01366        insn.addr = fi.addr;
01367        insn.frag = fi.frag;
01368        insn.num_fixups = fi.num_fixups;
01369        for (i = 0; i < fi.num_fixups; ++i)
01370          insn.fixups[i] = fi.fixups[i];
01371       }
01372 
01373       if (swap)
01374        {
01375          int i, tmp;
01376 
01377 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
01378 
01379          /* Swap the two insns */
01380          SWAP_BYTES (prev_insn.addr[0], insn.addr[0]);
01381          SWAP_BYTES (prev_insn.addr[1], insn.addr[1]);
01382 
01383          target_make_parallel (insn.addr);
01384 
01385          /* Swap any relaxable frags recorded for the two insns.  */
01386          /* FIXME: Clarify.  relaxation precludes parallel insns */
01387          if (prev_insn.frag->fr_opcode == prev_insn.addr)
01388            prev_insn.frag->fr_opcode = insn.addr;
01389          else if (insn.frag->fr_opcode == insn.addr)
01390            insn.frag->fr_opcode = prev_insn.addr;
01391 
01392           /* Change a frag to, if each insn is in a different frag.
01393             It must keep only one instruction in a frag.  */
01394           if (prev_insn.frag != insn.frag)
01395             {
01396               for (i = 0; i < prev_insn.num_fixups; ++i)
01397                 prev_insn.fixups[i]->fx_frag = insn.frag;
01398               for (i = 0; i < insn.num_fixups; ++i)
01399                 insn.fixups[i]->fx_frag = prev_insn.frag;
01400             }
01401           else
01402            {
01403              /* Update the addresses in any fixups.
01404                Note that we don't have to handle the case where each insn is in
01405                a different frag as we ensure they're in the same frag above.  */
01406              for (i = 0; i < prev_insn.num_fixups; ++i)
01407               prev_insn.fixups[i]->fx_where += 2;
01408              for (i = 0; i < insn.num_fixups; ++i)
01409               insn.fixups[i]->fx_where -= 2;
01410            }
01411        }
01412 
01413       /* Keep track of whether we've seen a pair of 16 bit insns.
01414         prev_insn.insn is NULL when we're on a 32 bit boundary.  */
01415       if (on_32bit_boundary_p)
01416        prev_insn = insn;
01417       else
01418        prev_insn.insn = NULL;
01419 
01420       /* If the insn needs the following one to be on a 32 bit boundary
01421         (e.g. subroutine calls), fill this insn's slot.  */
01422       if (on_32bit_boundary_p
01423          && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0)
01424        fill_insn (0);
01425 
01426       /* If this is a relaxable insn (can be replaced with a larger version)
01427         mark the fact so that we can emit an alignment directive for a
01428         following 32 bit insn if we see one.   */
01429       if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0)
01430        seen_relaxable_p = 1;
01431     }
01432 
01433   /* Set these so m32r_fill_insn can use them.  */
01434   prev_seg    = now_seg;
01435   prev_subseg = now_subseg;
01436 }
01437 
01438 /* The syntax in the manual says constants begin with '#'.
01439    We just ignore it.  */
01440 
01441 void
01442 md_operand (expressionS *expressionP)
01443 {
01444   if (*input_line_pointer == '#')
01445     {
01446       input_line_pointer++;
01447       expression (expressionP);
01448     }
01449 }
01450 
01451 valueT
01452 md_section_align (segT segment, valueT size)
01453 {
01454   int align = bfd_get_section_alignment (stdoutput, segment);
01455 
01456   return ((size + (1 << align) - 1) & (-1 << align));
01457 }
01458 
01459 symbolS *
01460 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
01461 {
01462   return 0;
01463 }
01464 
01465 /* .scomm pseudo-op handler.
01466 
01467    This is a new pseudo-op to handle putting objects in .scommon.
01468    By doing this the linker won't need to do any work,
01469    and more importantly it removes the implicit -G arg necessary to
01470    correctly link the object file.  */
01471 
01472 static void
01473 m32r_scomm (int ignore ATTRIBUTE_UNUSED)
01474 {
01475   char *name;
01476   char c;
01477   char *p;
01478   offsetT size;
01479   symbolS *symbolP;
01480   offsetT align;
01481   int align2;
01482 
01483   name = input_line_pointer;
01484   c = get_symbol_end ();
01485 
01486   /* Just after name is now '\0'.  */
01487   p = input_line_pointer;
01488   *p = c;
01489   SKIP_WHITESPACE ();
01490   if (*input_line_pointer != ',')
01491     {
01492       as_bad (_("Expected comma after symbol-name: rest of line ignored."));
01493       ignore_rest_of_line ();
01494       return;
01495     }
01496 
01497   /* Skip ','.  */
01498   input_line_pointer++;
01499   if ((size = get_absolute_expression ()) < 0)
01500     {
01501       /* xgettext:c-format  */
01502       as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size);
01503       ignore_rest_of_line ();
01504       return;
01505     }
01506 
01507   /* The third argument to .scomm is the alignment.  */
01508   if (*input_line_pointer != ',')
01509     align = 8;
01510   else
01511     {
01512       ++input_line_pointer;
01513       align = get_absolute_expression ();
01514       if (align <= 0)
01515        {
01516          as_warn (_("ignoring bad alignment"));
01517          align = 8;
01518        }
01519     }
01520 
01521   /* Convert to a power of 2 alignment.  */
01522   if (align)
01523     {
01524       for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
01525        continue;
01526       if (align != 1)
01527        {
01528          as_bad (_("Common alignment not a power of 2"));
01529          ignore_rest_of_line ();
01530          return;
01531        }
01532     }
01533   else
01534     align2 = 0;
01535 
01536   *p = 0;
01537   symbolP = symbol_find_or_make (name);
01538   *p = c;
01539 
01540   if (S_IS_DEFINED (symbolP))
01541     {
01542       /* xgettext:c-format  */
01543       as_bad (_("Ignoring attempt to re-define symbol `%s'."),
01544              S_GET_NAME (symbolP));
01545       ignore_rest_of_line ();
01546       return;
01547     }
01548 
01549   if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size)
01550     {
01551       /* xgettext:c-format  */
01552       as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
01553              S_GET_NAME (symbolP),
01554              (long) S_GET_VALUE (symbolP),
01555              (long) size);
01556 
01557       ignore_rest_of_line ();
01558       return;
01559     }
01560 
01561   if (symbol_get_obj (symbolP)->local)
01562     {
01563       segT old_sec = now_seg;
01564       int old_subsec = now_subseg;
01565       char *pfrag;
01566 
01567       record_alignment (sbss_section, align2);
01568       subseg_set (sbss_section, 0);
01569 
01570       if (align2)
01571        frag_align (align2, 0, 0);
01572 
01573       if (S_GET_SEGMENT (symbolP) == sbss_section)
01574        symbol_get_frag (symbolP)->fr_symbol = 0;
01575 
01576       symbol_set_frag (symbolP, frag_now);
01577 
01578       pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size,
01579                      (char *) 0);
01580       *pfrag = 0;
01581       S_SET_SIZE (symbolP, size);
01582       S_SET_SEGMENT (symbolP, sbss_section);
01583       S_CLEAR_EXTERNAL (symbolP);
01584       subseg_set (old_sec, old_subsec);
01585     }
01586   else
01587     {
01588       S_SET_VALUE (symbolP, (valueT) size);
01589       S_SET_ALIGN (symbolP, align2);
01590       S_SET_EXTERNAL (symbolP);
01591       S_SET_SEGMENT (symbolP, &scom_section);
01592     }
01593 
01594   demand_empty_rest_of_line ();
01595 }
01596 
01597 /* The target specific pseudo-ops which we support.  */
01598 const pseudo_typeS md_pseudo_table[] =
01599 {
01600   { "word",   cons,         4 },
01601   { "fillinsn", fill_insn,  0 },
01602   { "scomm",  m32r_scomm,   0 },
01603   { "debugsym",      debug_sym,    0 },
01604   { "m32r",   allow_m32rx,  0 },
01605   { "m32rx",  allow_m32rx,  1 },
01606   { "m32r2",  allow_m32rx,  2 },
01607   { "little",   little,         1 },
01608   { "big",      little,         0 },
01609   { NULL, NULL, 0 }
01610 };
01611 
01612 /* Interface to relax_segment.  */
01613 
01614 /* FIXME: Build table by hand, get it working, then machine generate.  */
01615 
01616 const relax_typeS md_relax_table[] =
01617 {
01618 /* The fields are:
01619    1) most positive reach of this state,
01620    2) most negative reach of this state,
01621    3) how many bytes this mode will add to the size of the current frag
01622    4) which index into the table to try if we can't fit into this one.  */
01623 
01624   /* The first entry must be unused because an `rlx_more' value of zero ends
01625      each list.  */
01626   {1, 1, 0, 0},
01627 
01628   /* The displacement used by GAS is from the end of the 2 byte insn,
01629      so we subtract 2 from the following.  */
01630   /* 16 bit insn, 8 bit disp -> 10 bit range.
01631      This doesn't handle a branch in the right slot at the border:
01632      the "& -4" isn't taken into account.  It's not important enough to
01633      complicate things over it, so we subtract an extra 2 (or + 2 in -ve
01634      case).  */
01635   {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
01636   /* 32 bit insn, 24 bit disp -> 26 bit range.  */
01637   {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
01638   /* Same thing, but with leading nop for alignment.  */
01639   {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
01640 };
01641 
01642 long
01643 m32r_relax_frag (segT segment, fragS *fragP, long stretch)
01644 {
01645   /* Address of branch insn.  */
01646   long address = fragP->fr_address + fragP->fr_fix - 2;
01647   long growth = 0;
01648 
01649   /* Keep 32 bit insns aligned on 32 bit boundaries.  */
01650   if (fragP->fr_subtype == 2)
01651     {
01652       if ((address & 3) != 0)
01653        {
01654          fragP->fr_subtype = 3;
01655          growth = 2;
01656        }
01657     }
01658   else if (fragP->fr_subtype == 3)
01659     {
01660       if ((address & 3) == 0)
01661        {
01662          fragP->fr_subtype = 2;
01663          growth = -2;
01664        }
01665     }
01666   else
01667     {
01668       growth = relax_frag (segment, fragP, stretch);
01669 
01670       /* Long jump on odd halfword boundary?  */
01671       if (fragP->fr_subtype == 2 && (address & 3) != 0)
01672        {
01673          fragP->fr_subtype = 3;
01674          growth += 2;
01675        }
01676     }
01677 
01678   return growth;
01679 }
01680 
01681 /* Return an initial guess of the length by which a fragment must grow to
01682    hold a branch to reach its destination.
01683    Also updates fr_type/fr_subtype as necessary.
01684 
01685    Called just before doing relaxation.
01686    Any symbol that is now undefined will not become defined.
01687    The guess for fr_var is ACTUALLY the growth beyond fr_fix.
01688    Whatever we do to grow fr_fix or fr_var contributes to our returned value.
01689    Although it may not be explicit in the frag, pretend fr_var starts
01690    with a 0 value.  */
01691 
01692 int
01693 md_estimate_size_before_relax (fragS *fragP, segT segment)
01694 {
01695   /* The only thing we have to handle here are symbols outside of the
01696      current segment.  They may be undefined or in a different segment in
01697      which case linker scripts may place them anywhere.
01698      However, we can't finish the fragment here and emit the reloc as insn
01699      alignment requirements may move the insn about.  */
01700   if (S_GET_SEGMENT (fragP->fr_symbol) != segment
01701       || S_IS_EXTERNAL (fragP->fr_symbol)
01702       || S_IS_WEAK (fragP->fr_symbol))
01703     {
01704       /* The symbol is undefined in this segment.
01705         Change the relaxation subtype to the max allowable and leave
01706         all further handling to md_convert_frag.  */
01707       fragP->fr_subtype = 2;
01708 
01709       {
01710        const CGEN_INSN *insn;
01711        int i;
01712 
01713        /* Update the recorded insn.
01714           Fortunately we don't have to look very far.
01715           FIXME: Change this to record in the instruction the next higher
01716           relaxable insn to use.  */
01717        for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
01718          {
01719            if ((strcmp (CGEN_INSN_MNEMONIC (insn),
01720                       CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
01721                == 0)
01722               && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
01723              break;
01724          }
01725        if (i == 4)
01726          abort ();
01727 
01728        fragP->fr_cgen.insn = insn;
01729        return 2;
01730       }
01731     }
01732 
01733   return md_relax_table[fragP->fr_subtype].rlx_length;
01734 }
01735 
01736 /* *FRAGP has been relaxed to its final size, and now needs to have
01737    the bytes inside it modified to conform to the new size.
01738 
01739    Called after relaxation is finished.
01740    fragP->fr_type == rs_machine_dependent.
01741    fragP->fr_subtype is the subtype of what the address relaxed to.  */
01742 
01743 void
01744 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
01745                segT sec,
01746                fragS *fragP)
01747 {
01748   char *opcode;
01749   char *displacement;
01750   int target_address;
01751   int opcode_address;
01752   int extension;
01753   int addend;
01754 
01755   opcode = fragP->fr_opcode;
01756 
01757   /* Address opcode resides at in file space.  */
01758   opcode_address = fragP->fr_address + fragP->fr_fix - 2;
01759 
01760   switch (fragP->fr_subtype)
01761     {
01762     case 1:
01763       extension = 0;
01764       displacement = &opcode[1];
01765       break;
01766     case 2:
01767       opcode[0] |= 0x80;
01768       extension = 2;
01769       displacement = &opcode[1];
01770       break;
01771     case 3:
01772       opcode[2] = opcode[0] | 0x80;
01773       md_number_to_chars (opcode, PAR_NOP_INSN, 2);
01774       opcode_address += 2;
01775       extension = 4;
01776       displacement = &opcode[3];
01777       break;
01778     default:
01779       abort ();
01780     }
01781 
01782   if (S_GET_SEGMENT (fragP->fr_symbol) != sec
01783       || S_IS_EXTERNAL (fragP->fr_symbol)
01784       || S_IS_WEAK (fragP->fr_symbol))
01785     {
01786       /* Symbol must be resolved by linker.  */
01787       if (fragP->fr_offset & 3)
01788        as_warn (_("Addend to unresolved symbol not on word boundary."));
01789 #ifdef USE_M32R_OLD_RELOC
01790       addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
01791 #else
01792       addend = 0;
01793 #endif
01794     }
01795   else
01796     {
01797       /* Address we want to reach in file space.  */
01798       target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
01799       addend = (target_address - (opcode_address & -4)) >> 2;
01800     }
01801 
01802   /* Create a relocation for symbols that must be resolved by the linker.
01803      Otherwise output the completed insn.  */
01804 
01805   if (S_GET_SEGMENT (fragP->fr_symbol) != sec
01806       || S_IS_EXTERNAL (fragP->fr_symbol)
01807       || S_IS_WEAK (fragP->fr_symbol))
01808     {
01809       fixS *fixP;
01810 
01811       assert (fragP->fr_subtype != 1);
01812       assert (fragP->fr_cgen.insn != 0);
01813 
01814       fixP = gas_cgen_record_fixup (fragP,
01815                                 /* Offset of branch insn in frag.  */
01816                                 fragP->fr_fix + extension - 4,
01817                                 fragP->fr_cgen.insn,
01818                                 4 /* Length.  */,
01819                                 /* FIXME: quick hack.  */
01820                                 cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
01821                                                         M32R_OPERAND_DISP24),
01822                                 fragP->fr_cgen.opinfo,
01823                                 fragP->fr_symbol, fragP->fr_offset);
01824       if (fragP->fr_cgen.opinfo)
01825         fixP->fx_r_type = fragP->fr_cgen.opinfo;
01826     }
01827 
01828 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
01829 
01830   md_number_to_chars (displacement, (valueT) addend,
01831                     SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
01832 
01833   fragP->fr_fix += extension;
01834 }
01835 
01836 /* Functions concerning relocs.  */
01837 
01838 /* The location from which a PC relative jump should be calculated,
01839    given a PC relative reloc.  */
01840 
01841 long
01842 md_pcrel_from_section (fixS *fixP, segT sec)
01843 {
01844   if (fixP->fx_addsy != (symbolS *) NULL
01845       && (! S_IS_DEFINED (fixP->fx_addsy)
01846          || S_GET_SEGMENT (fixP->fx_addsy) != sec
01847           || S_IS_EXTERNAL (fixP->fx_addsy)
01848           || S_IS_WEAK (fixP->fx_addsy)))
01849     {
01850       if (S_GET_SEGMENT (fixP->fx_addsy) != sec
01851           && S_IS_DEFINED (fixP->fx_addsy)
01852           && ! S_IS_EXTERNAL (fixP->fx_addsy)
01853           && ! S_IS_WEAK (fixP->fx_addsy))
01854         return fixP->fx_offset;
01855 
01856       /* The symbol is undefined (or is defined but not in this section).
01857         Let the linker figure it out.  */
01858       return 0;
01859     }
01860 
01861   return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L;
01862 }
01863 
01864 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
01865    Returns BFD_RELOC_NONE if no reloc type can be found.
01866    *FIXP may be modified if desired.  */
01867 
01868 bfd_reloc_code_real_type
01869 md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
01870                     const CGEN_OPERAND *operand,
01871                     fixS *fixP)
01872 {
01873   switch (operand->type)
01874     {
01875     case M32R_OPERAND_DISP8:  return BFD_RELOC_M32R_10_PCREL;
01876     case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL;
01877     case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL;
01878     case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24;
01879     case M32R_OPERAND_HI16:
01880     case M32R_OPERAND_SLO16:
01881     case M32R_OPERAND_ULO16:
01882       /* If low/high/shigh/sda was used, it is recorded in `opinfo'.  */
01883       if (fixP->fx_cgen.opinfo != 0)
01884        return fixP->fx_cgen.opinfo;
01885       break;
01886     default:
01887       /* Avoid -Wall warning.  */
01888       break;
01889     }
01890   return BFD_RELOC_NONE;
01891 }
01892 
01893 /* Record a HI16 reloc for later matching with its LO16 cousin.  */
01894 
01895 static void
01896 m32r_record_hi16 (int reloc_type,
01897                 fixS *fixP,
01898                 segT seg ATTRIBUTE_UNUSED)
01899 {
01900   struct m32r_hi_fixup *hi_fixup;
01901 
01902   assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
01903          || reloc_type == BFD_RELOC_M32R_HI16_ULO);
01904 
01905   hi_fixup = xmalloc (sizeof (* hi_fixup));
01906   hi_fixup->fixp = fixP;
01907   hi_fixup->seg  = now_seg;
01908   hi_fixup->next = m32r_hi_fixup_list;
01909 
01910   m32r_hi_fixup_list = hi_fixup;
01911 }
01912 
01913 /* Called while parsing an instruction to create a fixup.
01914    We need to check for HI16 relocs and queue them up for later sorting.  */
01915 
01916 fixS *
01917 m32r_cgen_record_fixup_exp (fragS *frag,
01918                          int where,
01919                          const CGEN_INSN *insn,
01920                          int length,
01921                          const CGEN_OPERAND *operand,
01922                          int opinfo,
01923                          expressionS *exp)
01924 {
01925   fixS *fixP;
01926   bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
01927 
01928   if (m32r_check_fixup (exp, &r_type))
01929     as_bad (_("Invalid PIC expression."));
01930 
01931   fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
01932                                 operand, opinfo, exp);
01933 
01934   switch (operand->type)
01935     {
01936     case M32R_OPERAND_HI16:
01937       /* If low/high/shigh/sda was used, it is recorded in `opinfo'.  */
01938       if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO
01939          || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
01940        m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
01941       break;
01942 
01943     default:
01944       /* Avoid -Wall warning.  */
01945       break;
01946     }
01947 
01948   switch (r_type)
01949     {
01950     case BFD_RELOC_UNUSED:
01951     default:
01952       return fixP;
01953 
01954     case BFD_RELOC_M32R_GOTPC24:
01955       if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
01956         r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
01957       else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
01958         r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
01959       else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
01960         r_type = BFD_RELOC_M32R_GOTPC_LO;
01961       break;
01962 
01963     case BFD_RELOC_M32R_GOT24:
01964       if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
01965         r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
01966       else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
01967         r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
01968       else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
01969         r_type = BFD_RELOC_M32R_GOT16_LO;
01970       break;
01971 
01972     case BFD_RELOC_M32R_GOTOFF:
01973       if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
01974         r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
01975       else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
01976         r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
01977       else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
01978         r_type = BFD_RELOC_M32R_GOTOFF_LO;
01979       break;
01980 
01981     case BFD_RELOC_M32R_26_PLTREL:
01982       as_bad (_("Invalid PIC expression."));
01983       break;
01984     }
01985 
01986   fixP->fx_r_type = r_type;
01987 
01988   return fixP;
01989 }
01990 
01991 /* Return BFD reloc type from opinfo field in a fixS.
01992    It's tricky using fx_r_type in m32r_frob_file because the values
01993    are BFD_RELOC_UNUSED + operand number.  */
01994 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
01995 
01996 /* Sort any unmatched HI16 relocs so that they immediately precede
01997    the corresponding LO16 reloc.  This is called before md_apply_fix and
01998    tc_gen_reloc.  */
01999 
02000 void
02001 m32r_frob_file (void)
02002 {
02003   struct m32r_hi_fixup *l;
02004 
02005   for (l = m32r_hi_fixup_list; l != NULL; l = l->next)
02006     {
02007       segment_info_type *seginfo;
02008       int pass;
02009 
02010       assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO
02011              || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO);
02012 
02013       /* Check quickly whether the next fixup happens to be a matching low.  */
02014       if (l->fixp->fx_next != NULL
02015          && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16
02016          && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
02017          && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
02018        continue;
02019 
02020       /* Look through the fixups for this segment for a matching `low'.
02021          When we find one, move the high/shigh just in front of it.  We do
02022          this in two passes.  In the first pass, we try to find a
02023          unique `low'.  In the second pass, we permit multiple high's
02024          relocs for a single `low'.  */
02025       seginfo = seg_info (l->seg);
02026       for (pass = 0; pass < 2; pass++)
02027        {
02028          fixS *f;
02029          fixS *prev;
02030 
02031          prev = NULL;
02032          for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
02033            {
02034              /* Check whether this is a `low' fixup which matches l->fixp.  */
02035              if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16
02036                 && f->fx_addsy == l->fixp->fx_addsy
02037                 && f->fx_offset == l->fixp->fx_offset
02038                 && (pass == 1
02039                     || prev == NULL
02040                     || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO
02041                        && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO)
02042                     || prev->fx_addsy != f->fx_addsy
02043                     || prev->fx_offset != f->fx_offset))
02044               {
02045                 fixS **pf;
02046 
02047                 /* Move l->fixp before f.  */
02048                 for (pf = &seginfo->fix_root;
02049                      *pf != l->fixp;
02050                      pf = & (*pf)->fx_next)
02051                   assert (*pf != NULL);
02052 
02053                 *pf = l->fixp->fx_next;
02054 
02055                 l->fixp->fx_next = f;
02056                 if (prev == NULL)
02057                   seginfo->fix_root = l->fixp;
02058                 else
02059                   prev->fx_next = l->fixp;
02060 
02061                 break;
02062               }
02063 
02064              prev = f;
02065            }
02066 
02067          if (f != NULL)
02068            break;
02069 
02070          if (pass == 1
02071              && warn_unmatched_high)
02072            as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
02073                         _("Unmatched high/shigh reloc"));
02074        }
02075     }
02076 }
02077 
02078 /* See whether we need to force a relocation into the output file.
02079    This is used to force out switch and PC relative relocations when
02080    relaxing.  */
02081 
02082 int
02083 m32r_force_relocation (fixS *fix)
02084 {
02085   if (generic_force_reloc (fix))
02086     return 1;
02087 
02088   if (! m32r_relax)
02089     return 0;
02090 
02091   return fix->fx_pcrel;
02092 }
02093 
02094 /* Write a value out to the object file, using the appropriate endianness.  */
02095 
02096 void
02097 md_number_to_chars (char *buf, valueT val, int n)
02098 {
02099   if (target_big_endian)
02100     number_to_chars_bigendian (buf, val, n);
02101   else
02102     number_to_chars_littleendian (buf, val, n);
02103 }
02104 
02105 /* Turn a string in input_line_pointer into a floating point constant
02106    of type TYPE, and store the appropriate bytes in *LITP.  The number
02107    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
02108    returned, or NULL on OK.  */
02109 
02110 /* Equal to MAX_PRECISION in atof-ieee.c.  */
02111 #define MAX_LITTLENUMS 6
02112 
02113 char *
02114 md_atof (int type, char *litP, int *sizeP)
02115 {
02116   int i;
02117   int prec;
02118   LITTLENUM_TYPE words[MAX_LITTLENUMS];
02119   char *t;
02120 
02121   switch (type)
02122     {
02123     case 'f':
02124     case 'F':
02125     case 's':
02126     case 'S':
02127       prec = 2;
02128       break;
02129 
02130     case 'd':
02131     case 'D':
02132     case 'r':
02133     case 'R':
02134       prec = 4;
02135       break;
02136 
02137       /* FIXME: Some targets allow other format chars for bigger sizes
02138          here.  */
02139 
02140     default:
02141       *sizeP = 0;
02142       return _("Bad call to md_atof()");
02143     }
02144 
02145   t = atof_ieee (input_line_pointer, type, words);
02146   if (t)
02147     input_line_pointer = t;
02148   *sizeP = prec * sizeof (LITTLENUM_TYPE);
02149 
02150   if (target_big_endian)
02151     {
02152       for (i = 0; i < prec; i++)
02153        {
02154          md_number_to_chars (litP, (valueT) words[i],
02155                            sizeof (LITTLENUM_TYPE));
02156          litP += sizeof (LITTLENUM_TYPE);
02157        }
02158     }
02159   else
02160     {
02161       for (i = prec - 1; i >= 0; i--)
02162        {
02163          md_number_to_chars (litP, (valueT) words[i],
02164                            sizeof (LITTLENUM_TYPE));
02165          litP += sizeof (LITTLENUM_TYPE);
02166        }
02167     }
02168 
02169   return 0;
02170 }
02171 
02172 void
02173 m32r_elf_section_change_hook (void)
02174 {
02175   /* If we have reached the end of a section and we have just emitted a
02176      16 bit insn, then emit a nop to make sure that the section ends on
02177      a 32 bit boundary.  */
02178 
02179   if (prev_insn.insn || seen_relaxable_p)
02180     (void) m32r_fill_insn (0);
02181 }
02182 
02183 /* Return true if can adjust the reloc to be relative to its section
02184    (such as .data) instead of relative to some symbol.  */
02185 
02186 bfd_boolean
02187 m32r_fix_adjustable (fixS *fixP)
02188 {
02189   bfd_reloc_code_real_type reloc_type;
02190 
02191   if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
02192     {
02193       const CGEN_INSN *insn = NULL;
02194       int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
02195       const CGEN_OPERAND *operand =
02196        cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
02197 
02198       reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
02199     }
02200   else
02201     reloc_type = fixP->fx_r_type;
02202 
02203   if (fixP->fx_addsy == NULL)
02204     return 1;
02205 
02206   /* Prevent all adjustments to global symbols.  */
02207   if (S_IS_EXTERNAL (fixP->fx_addsy))
02208     return 0;
02209   if (S_IS_WEAK (fixP->fx_addsy))
02210     return 0;
02211 
02212   if (pic_code
02213       && (reloc_type == BFD_RELOC_M32R_24
02214           || reloc_type == BFD_RELOC_M32R_26_PCREL
02215           || reloc_type == BFD_RELOC_M32R_HI16_SLO
02216           || reloc_type == BFD_RELOC_M32R_HI16_ULO
02217           || reloc_type == BFD_RELOC_M32R_LO16))
02218     return 0;
02219 
02220   if (reloc_type == BFD_RELOC_M32R_GOT24
02221       || reloc_type == BFD_RELOC_M32R_26_PLTREL
02222       || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
02223       || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
02224       || reloc_type == BFD_RELOC_M32R_GOTPC_LO
02225       || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
02226       || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
02227       || reloc_type == BFD_RELOC_M32R_GOT16_LO)
02228     return 0;
02229 
02230   /* We need the symbol name for the VTABLE entries.  */
02231   if (reloc_type == BFD_RELOC_VTABLE_INHERIT
02232       || reloc_type == BFD_RELOC_VTABLE_ENTRY)
02233     return 0;
02234 
02235   return 1;
02236 }
02237 
02238 void
02239 m32r_elf_final_processing (void)
02240 {
02241   if (use_parallel)
02242     m32r_flags |= E_M32R_HAS_PARALLEL;
02243   elf_elfheader (stdoutput)->e_flags |= m32r_flags;
02244 }
02245 
02246 /* Translate internal representation of relocation info to BFD target
02247    format. */
02248 
02249 arelent *
02250 tc_gen_reloc (asection * section, fixS * fixP)
02251 {
02252   arelent * reloc;
02253   bfd_reloc_code_real_type code;
02254  
02255   reloc = xmalloc (sizeof (* reloc));
02256  
02257   reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
02258   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
02259   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
02260 
02261   if (fixP->fx_pcrel)
02262     {
02263       if (fixP->fx_r_type == BFD_RELOC_32)
02264         fixP->fx_r_type = BFD_RELOC_32_PCREL;
02265       else if (fixP->fx_r_type == BFD_RELOC_16)
02266        {
02267           fixP->fx_r_type = BFD_RELOC_16_PCREL;
02268           bfd_set_error (bfd_error_bad_value);
02269        }
02270     }
02271  
02272   code = fixP->fx_r_type;
02273   if (pic_code)
02274     {
02275 #ifdef DEBUG_PIC
02276 printf("%s",bfd_get_reloc_code_name(code));
02277 #endif
02278       switch (code)
02279         {
02280         case BFD_RELOC_M32R_26_PCREL:
02281             code = BFD_RELOC_M32R_26_PLTREL;
02282           break;
02283 
02284         case BFD_RELOC_M32R_24:
02285           if (fixP->fx_addsy != NULL
02286               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
02287             code = BFD_RELOC_M32R_GOTPC24;
02288           else
02289             code = BFD_RELOC_M32R_GOT24;
02290           break;
02291 
02292         case BFD_RELOC_M32R_HI16_ULO:
02293           if (fixP->fx_addsy != NULL
02294               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
02295             code = BFD_RELOC_M32R_GOTPC_HI_ULO;
02296           else
02297             code = BFD_RELOC_M32R_GOT16_HI_ULO;
02298           break;
02299 
02300         case BFD_RELOC_M32R_HI16_SLO:
02301           if (fixP->fx_addsy != NULL
02302               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
02303             code = BFD_RELOC_M32R_GOTPC_HI_SLO;
02304           else
02305             code = BFD_RELOC_M32R_GOT16_HI_SLO;
02306           break;
02307 
02308         case BFD_RELOC_M32R_LO16:
02309           if (fixP->fx_addsy != NULL
02310               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
02311             code = BFD_RELOC_M32R_GOTPC_LO;
02312           else
02313             code = BFD_RELOC_M32R_GOT16_LO;
02314           break;
02315 
02316         default:
02317           break;
02318         }
02319 #ifdef DEBUG_PIC
02320 printf(" => %s",bfd_get_reloc_code_name(code));
02321 #endif
02322     }
02323  
02324   reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
02325 
02326 #ifdef DEBUG_PIC
02327 printf(" => %s\n",reloc->howto->name);
02328 #endif
02329 
02330  if (reloc->howto == (reloc_howto_type *) NULL)
02331     {
02332       as_bad_where (fixP->fx_file, fixP->fx_line,
02333             _("internal error: can't export reloc type %d (`%s')"),
02334             fixP->fx_r_type, bfd_get_reloc_code_name (code));
02335       return NULL;
02336     }
02337  
02338   /* Use fx_offset for these cases.  */
02339   if (   fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
02340       || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
02341       || fixP->fx_r_type == BFD_RELOC_32_PCREL)
02342     reloc->addend  = fixP->fx_offset;
02343   else if ((!pic_code
02344             && code != BFD_RELOC_M32R_26_PLTREL)
02345            && fixP->fx_pcrel
02346            && fixP->fx_addsy != NULL
02347            && (S_GET_SEGMENT(fixP->fx_addsy) != section)
02348            && S_IS_DEFINED (fixP->fx_addsy)
02349            && ! S_IS_EXTERNAL(fixP->fx_addsy)
02350            && ! S_IS_WEAK(fixP->fx_addsy))
02351     /* Already used fx_offset in the opcode field itseld.  */
02352     reloc->addend  = fixP->fx_offset;
02353   else
02354     reloc->addend  = fixP->fx_addnumber;
02355  
02356   return reloc;
02357 }
02358 
02359 inline static char *
02360 m32r_end_of_match (char *cont, char *what)
02361 {
02362   int len = strlen (what);
02363 
02364   if (strncasecmp (cont, what, strlen (what)) == 0
02365       && ! is_part_of_name (cont[len]))
02366     return cont + len;
02367 
02368   return NULL;
02369 }
02370 
02371 int
02372 m32r_parse_name (char const *name,
02373                expressionS *exprP,
02374                enum expr_mode mode,
02375                char *nextcharP)
02376 {
02377   char *next = input_line_pointer;
02378   char *next_end;
02379   int reloc_type;
02380   operatorT op_type;
02381   segT segment;
02382 
02383   exprP->X_op_symbol = NULL;
02384   exprP->X_md = BFD_RELOC_UNUSED;
02385 
02386   if (strcmp (name, GOT_NAME) == 0)
02387     {
02388       if (! GOT_symbol)
02389        GOT_symbol = symbol_find_or_make (name);
02390 
02391       exprP->X_add_symbol = GOT_symbol;
02392     no_suffix:
02393       /* If we have an absolute symbol or a
02394         reg, then we know its value now.  */
02395       segment = S_GET_SEGMENT (exprP->X_add_symbol);
02396       if (mode != expr_defer && segment == absolute_section)
02397        {
02398          exprP->X_op = O_constant;
02399          exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
02400          exprP->X_add_symbol = NULL;
02401        }
02402       else if (mode != expr_defer && segment == reg_section)
02403        {
02404          exprP->X_op = O_register;
02405          exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
02406          exprP->X_add_symbol = NULL;
02407        }
02408       else
02409        {
02410          exprP->X_op = O_symbol;
02411          exprP->X_add_number = 0;
02412        }
02413 
02414       return 1;
02415     }
02416 
02417   exprP->X_add_symbol = symbol_find_or_make (name);
02418 
02419   if (*nextcharP != '@')
02420     goto no_suffix;
02421   else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
02422     {
02423       reloc_type = BFD_RELOC_M32R_GOTOFF;
02424       op_type = O_PIC_reloc;
02425     }
02426   else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
02427     {
02428       reloc_type = BFD_RELOC_M32R_GOT24;
02429       op_type = O_PIC_reloc;
02430     }
02431   else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
02432     {
02433       reloc_type = BFD_RELOC_M32R_26_PLTREL;
02434       op_type = O_PIC_reloc;
02435     }
02436   else
02437     goto no_suffix;
02438 
02439   *input_line_pointer = *nextcharP;
02440   input_line_pointer = next_end;
02441   *nextcharP = *input_line_pointer;
02442   *input_line_pointer = '\0';
02443 
02444   exprP->X_op = op_type;
02445   exprP->X_add_number = 0;
02446   exprP->X_md = reloc_type;
02447 
02448   return 1;
02449 }
02450 
02451 int
02452 m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
02453 {
02454   if (exp->X_op == O_PIC_reloc
02455       && exp->X_md == BFD_RELOC_M32R_26_PLTREL)
02456     {
02457       exp->X_op = O_symbol;
02458       opinfo = exp->X_md;
02459     }
02460 
02461   return opinfo;
02462 }