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cell-binutils  2.17cvs20070401
tc-i960.c
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00001 /* tc-i960.c - All the i80960-specific stuff
00002    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
00003    1999, 2000, 2001, 2002, 2003, 2005, 2006
00004    Free Software Foundation, Inc.
00005 
00006    This file is part of GAS.
00007 
00008    GAS is free software; you can redistribute it and/or modify
00009    it under the terms of the GNU General Public License as published by
00010    the Free Software Foundation; either version 2, or (at your option)
00011    any later version.
00012 
00013    GAS is distributed in the hope that it will be useful,
00014    but WITHOUT ANY WARRANTY; without even the implied warranty of
00015    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016    GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with GAS; see the file COPYING.  If not, write to the Free
00020    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00021    02110-1301, USA.  */
00022 
00023 /* See comment on md_parse_option for 80960-specific invocation options.  */
00024 
00025 /* There are 4 different lengths of (potentially) symbol-based displacements
00026    in the 80960 instruction set, each of which could require address fix-ups
00027    and (in the case of external symbols) emission of relocation directives:
00028 
00029    32-bit (MEMB)
00030         This is a standard length for the base assembler and requires no
00031         special action.
00032 
00033    13-bit (COBR)
00034         This is a non-standard length, but the base assembler has a
00035         hook for bit field address fixups: the fixS structure can
00036         point to a descriptor of the field, in which case our
00037         md_number_to_field() routine gets called to process it.
00038 
00039         I made the hook a little cleaner by having fix_new() (in the base
00040         assembler) return a pointer to the fixS in question.  And I made it a
00041         little simpler by storing the field size (in this case 13) instead of
00042         of a pointer to another structure:  80960 displacements are ALWAYS
00043         stored in the low-order bits of a 4-byte word.
00044 
00045         Since the target of a COBR cannot be external, no relocation
00046         directives for this size displacement have to be generated.
00047         But the base assembler had to be modified to issue error
00048         messages if the symbol did turn out to be external.
00049 
00050    24-bit (CTRL)
00051         Fixups are handled as for the 13-bit case (except that 24 is stored
00052         in the fixS).
00053 
00054         The relocation directive generated is the same as that for the 32-bit
00055         displacement, except that it's PC-relative (the 32-bit displacement
00056         never is).   The i80960 version of the linker needs a mod to
00057         distinguish and handle the 24-bit case.
00058 
00059    12-bit (MEMA)
00060         MEMA formats are always promoted to MEMB (32-bit) if the displacement
00061         is based on a symbol, because it could be relocated at link time.
00062         The only time we use the 12-bit format is if an absolute value of
00063         less than 4096 is specified, in which case we need neither a fixup nor
00064         a relocation directive.  */
00065 
00066 #include "as.h"
00067 
00068 #include "safe-ctype.h"
00069 #include "obstack.h"
00070 
00071 #include "opcode/i960.h"
00072 
00073 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
00074 
00075 #define TC_S_IS_SYSPROC(s)  ((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
00076 #define TC_S_IS_BALNAME(s)  (S_GET_OTHER (s) == N_BALNAME)
00077 #define TC_S_IS_CALLNAME(s) (S_GET_OTHER (s) == N_CALLNAME)
00078 #define TC_S_IS_BADPROC(s)  ((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
00079 
00080 #define TC_S_SET_SYSPROC(s, p)     (S_SET_OTHER ((s), (p) + 1))
00081 #define TC_S_GET_SYSPROC(s) (S_GET_OTHER (s) - 1)
00082 
00083 #define TC_S_FORCE_TO_BALNAME(s)   (S_SET_OTHER ((s), N_BALNAME))
00084 #define TC_S_FORCE_TO_CALLNAME(s)  (S_SET_OTHER ((s), N_CALLNAME))
00085 #define TC_S_FORCE_TO_SYSPROC(s)   {;}
00086 
00087 #else /* ! OBJ_A/BOUT */
00088 #ifdef OBJ_COFF
00089 
00090 #define TC_S_IS_SYSPROC(s)  (S_GET_STORAGE_CLASS (s) == C_SCALL)
00091 #define TC_S_IS_BALNAME(s)  (SF_GET_BALNAME (s))
00092 #define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME (s))
00093 #define TC_S_IS_BADPROC(s)  (TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
00094 
00095 #define TC_S_SET_SYSPROC(s, p)     ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
00096 #define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
00097 
00098 #define TC_S_FORCE_TO_BALNAME(s)   (SF_SET_BALNAME (s))
00099 #define TC_S_FORCE_TO_CALLNAME(s)  (SF_SET_CALLNAME (s))
00100 #define TC_S_FORCE_TO_SYSPROC(s)   (S_SET_STORAGE_CLASS ((s), C_SCALL))
00101 
00102 #else /* ! OBJ_COFF */
00103 #ifdef OBJ_ELF
00104 #define TC_S_IS_SYSPROC(s)  0
00105 
00106 #define TC_S_IS_BALNAME(s)  0
00107 #define TC_S_IS_CALLNAME(s) 0
00108 #define TC_S_IS_BADPROC(s)  0
00109 
00110 #define TC_S_SET_SYSPROC(s, p)
00111 #define TC_S_GET_SYSPROC(s)     0
00112 
00113 #define TC_S_FORCE_TO_BALNAME(s)
00114 #define TC_S_FORCE_TO_CALLNAME(s)
00115 #define TC_S_FORCE_TO_SYSPROC(s)
00116 #else
00117  #error COFF, a.out, b.out, and ELF are the only supported formats.
00118 #endif /* ! OBJ_ELF */
00119 #endif /* ! OBJ_COFF */
00120 #endif /* ! OBJ_A/BOUT */
00121 
00122 extern char *input_line_pointer;
00123 
00124 /* Local i80960 routines.  */
00125 struct memS;
00126 struct regop;
00127 
00128 /* See md_parse_option() for meanings of these options.  */
00129 static char norelax;               /* True if -norelax switch seen.  */
00130 static char instrument_branches;   /* True if -b switch seen.  */
00131 
00132 /* Characters that always start a comment.
00133    If the pre-processor is disabled, these aren't very useful.  */
00134 const char comment_chars[] = "#";
00135 
00136 /* Characters that only start a comment at the beginning of
00137    a line.  If the line seems to have the form '# 123 filename'
00138    .line and .file directives will appear in the pre-processed output.
00139 
00140    Note that input_file.c hand checks for '#' at the beginning of the
00141    first line of the input file.  This is because the compiler outputs
00142    #NO_APP at the beginning of its output.  */
00143 
00144 /* Also note that comments started like this one will always work.  */
00145 
00146 const char line_comment_chars[]   = "#";
00147 const char line_separator_chars[] = ";";
00148 
00149 /* Chars that can be used to separate mant from exp in floating point nums.  */
00150 const char EXP_CHARS[] = "eE";
00151 
00152 /* Chars that mean this number is a floating point constant,
00153    as in 0f12.456 or 0d1.2345e12.  */
00154 const char FLT_CHARS[] = "fFdDtT";
00155 
00156 /* Table used by base assembler to relax addresses based on varying length
00157    instructions.  The fields are:
00158      1) most positive reach of this state,
00159      2) most negative reach of this state,
00160      3) how many bytes this mode will add to the size of the current frag
00161      4) which index into the table to try if we can't fit into this one.
00162 
00163    For i80960, the only application is the (de-)optimization of cobr
00164    instructions into separate compare and branch instructions when a 13-bit
00165    displacement won't hack it.  */
00166 const relax_typeS md_relax_table[] =
00167 {
00168   {0, 0, 0, 0},                           /* State 0 => no more relaxation possible.  */
00169   {4088, -4096, 0, 2},                    /* State 1: conditional branch (cobr).  */
00170   {0x800000 - 8, -0x800000, 4, 0}, /* State 2: compare (reg) & branch (ctrl).  */
00171 };
00172 
00173 /* These are the machine dependent pseudo-ops.
00174 
00175    This table describes all the machine specific pseudo-ops the assembler
00176    has to support.  The fields are:
00177         pseudo-op name without dot
00178         function to call to execute this pseudo-op
00179         integer arg to pass to the function.  */
00180 #define S_LEAFPROC   1
00181 #define S_SYSPROC    2
00182 
00183 /* Macros to extract info from an 'expressionS' structure 'e'.  */
00184 #define adds(e)      e.X_add_symbol
00185 #define offs(e)      e.X_add_number
00186 
00187 /* Branch-prediction bits for CTRL/COBR format opcodes.  */
00188 #define BP_MASK             0x00000002    /* Mask for branch-prediction bit.  */
00189 #define BP_TAKEN     0x00000000    /* Value to OR in to predict branch.  */
00190 #define BP_NOT_TAKEN 0x00000002    /* Value to OR in to predict no branch.  */
00191 
00192 /* Some instruction opcodes that we need explicitly.  */
00193 #define BE    0x12000000
00194 #define BG    0x11000000
00195 #define BGE   0x13000000
00196 #define BL    0x14000000
00197 #define BLE   0x16000000
00198 #define BNE   0x15000000
00199 #define BNO   0x10000000
00200 #define BO    0x17000000
00201 #define CHKBIT       0x5a002700
00202 #define CMPI  0x5a002080
00203 #define CMPO  0x5a002000
00204 
00205 #define B     0x08000000
00206 #define BAL   0x0b000000
00207 #define CALL  0x09000000
00208 #define CALLS 0x66003800
00209 #define RET   0x0a000000
00210 
00211 /* These masks are used to build up a set of MEMB mode bits.  */
00212 #define       A_BIT         0x0400
00213 #define       I_BIT         0x0800
00214 #define MEMB_BIT     0x1000
00215 #define       D_BIT         0x2000
00216 
00217 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
00218    used).  */
00219 #define MEMA_ABASE   0x2000
00220 
00221 /* Info from which a MEMA or MEMB format instruction can be generated.  */
00222 typedef struct memS
00223   {
00224     /* (First) 32 bits of instruction.  */
00225     long opcode;
00226     /* 0-(none), 12- or, 32-bit displacement needed.  */
00227     int disp;
00228     /* The expression in the source instruction from which the
00229        displacement should be determined.  */
00230     char *e;
00231   }
00232 memS;
00233 
00234 /* The two pieces of info we need to generate a register operand.  */
00235 struct regop
00236   {
00237     int mode;               /* 0 =>local/global/spec reg; 1=> literal or fp reg.  */
00238     int special;            /* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0).  */
00239     int n;                  /* Register number or literal value.  */
00240   };
00241 
00242 /* Number and assembler mnemonic for all registers that can appear in
00243    operands.  */
00244 static const struct
00245   {
00246     char *reg_name;
00247     int reg_num;
00248   }
00249 regnames[] =
00250 {
00251   { "pfp", 0 },
00252   { "sp", 1 },
00253   { "rip", 2 },
00254   { "r3", 3 },
00255   { "r4", 4 },
00256   { "r5", 5 },
00257   { "r6", 6 },
00258   { "r7", 7 },
00259   { "r8", 8 },
00260   { "r9", 9 },
00261   { "r10", 10 },
00262   { "r11", 11 },
00263   { "r12", 12 },
00264   { "r13", 13 },
00265   { "r14", 14 },
00266   { "r15", 15 },
00267   { "g0", 16 },
00268   { "g1", 17 },
00269   { "g2", 18 },
00270   { "g3", 19 },
00271   { "g4", 20 },
00272   { "g5", 21 },
00273   { "g6", 22 },
00274   { "g7", 23 },
00275   { "g8", 24 },
00276   { "g9", 25 },
00277   { "g10", 26 },
00278   { "g11", 27 },
00279   { "g12", 28 },
00280   { "g13", 29 },
00281   { "g14", 30 },
00282   { "fp", 31 },
00283 
00284   /* Numbers for special-function registers are for assembler internal
00285      use only: they are scaled back to range [0-31] for binary output.  */
00286 #define SF0   32
00287 
00288   { "sf0", 32 },
00289   { "sf1", 33 },
00290   { "sf2", 34 },
00291   { "sf3", 35 },
00292   { "sf4", 36 },
00293   { "sf5", 37 },
00294   { "sf6", 38 },
00295   { "sf7", 39 },
00296   { "sf8", 40 },
00297   { "sf9", 41 },
00298   { "sf10", 42 },
00299   { "sf11", 43 },
00300   { "sf12", 44 },
00301   { "sf13", 45 },
00302   { "sf14", 46 },
00303   { "sf15", 47 },
00304   { "sf16", 48 },
00305   { "sf17", 49 },
00306   { "sf18", 50 },
00307   { "sf19", 51 },
00308   { "sf20", 52 },
00309   { "sf21", 53 },
00310   { "sf22", 54 },
00311   { "sf23", 55 },
00312   { "sf24", 56 },
00313   { "sf25", 57 },
00314   { "sf26", 58 },
00315   { "sf27", 59 },
00316   { "sf28", 60 },
00317   { "sf29", 61 },
00318   { "sf30", 62 },
00319   { "sf31", 63 },
00320 
00321   /* Numbers for floating point registers are for assembler internal
00322      use only: they are scaled back to [0-3] for binary output.  */
00323 #define FP0   64
00324 
00325   { "fp0", 64 },
00326   { "fp1", 65 },
00327   { "fp2", 66 },
00328   { "fp3", 67 },
00329 
00330   { NULL, 0 },                            /* END OF LIST */
00331 };
00332 
00333 #define       IS_RG_REG(n)  ((0 <= (n)) && ((n) < SF0))
00334 #define       IS_SF_REG(n)  ((SF0 <= (n)) && ((n) < FP0))
00335 #define       IS_FP_REG(n)  ((n) >= FP0)
00336 
00337 /* Number and assembler mnemonic for all registers that can appear as
00338    'abase' (indirect addressing) registers.  */
00339 static const struct
00340 {
00341   char *areg_name;
00342   int areg_num;
00343 }
00344 aregs[] =
00345 {
00346   { "(pfp)", 0 },
00347   { "(sp)", 1 },
00348   { "(rip)", 2 },
00349   { "(r3)", 3 },
00350   { "(r4)", 4 },
00351   { "(r5)", 5 },
00352   { "(r6)", 6 },
00353   { "(r7)", 7 },
00354   { "(r8)", 8 },
00355   { "(r9)", 9 },
00356   { "(r10)", 10 },
00357   { "(r11)", 11 },
00358   { "(r12)", 12 },
00359   { "(r13)", 13 },
00360   { "(r14)", 14 },
00361   { "(r15)", 15 },
00362   { "(g0)", 16 },
00363   { "(g1)", 17 },
00364   { "(g2)", 18 },
00365   { "(g3)", 19 },
00366   { "(g4)", 20 },
00367   { "(g5)", 21 },
00368   { "(g6)", 22 },
00369   { "(g7)", 23 },
00370   { "(g8)", 24 },
00371   { "(g9)", 25 },
00372   { "(g10)", 26 },
00373   { "(g11)", 27 },
00374   { "(g12)", 28 },
00375   { "(g13)", 29 },
00376   { "(g14)", 30 },
00377   { "(fp)", 31 },
00378 
00379 #define IPREL 32
00380   /* For assembler internal use only: this number never appears in binary
00381      output.  */
00382   { "(ip)", IPREL },
00383 
00384   { NULL, 0 },                            /* END OF LIST */
00385 };
00386 
00387 /* Hash tables.  */
00388 static struct hash_control *op_hash;      /* Opcode mnemonics.  */
00389 static struct hash_control *reg_hash;     /* Register name hash table.  */
00390 static struct hash_control *areg_hash;    /* Abase register hash table.  */
00391 
00392 /* Architecture for which we are assembling.  */
00393 #define ARCH_ANY     0      /* Default: no architecture checking done.  */
00394 #define ARCH_KA             1
00395 #define ARCH_KB             2
00396 #define ARCH_MC             3
00397 #define ARCH_CA             4
00398 #define ARCH_JX             5
00399 #define ARCH_HX             6
00400 int architecture = ARCH_ANY;       /* Architecture requested on invocation line.  */
00401 int iclasses_seen;          /* OR of instruction classes (I_* constants)
00402                                   for which we've actually assembled
00403                                     instructions.  */
00404 
00405 /* BRANCH-PREDICTION INSTRUMENTATION
00406 
00407         The following supports generation of branch-prediction instrumentation
00408         (turned on by -b switch).  The instrumentation collects counts
00409         of branches taken/not-taken for later input to a utility that will
00410         set the branch prediction bits of the instructions in accordance with
00411         the behavior observed.  (Note that the KX series does not have
00412         brach-prediction.)
00413 
00414         The instrumentation consists of:
00415 
00416         (1) before and after each conditional branch, a call to an external
00417             routine that increments and steps over an inline counter.  The
00418             counter itself, initialized to 0, immediately follows the call
00419             instruction.  For each branch, the counter following the branch
00420             is the number of times the branch was not taken, and the difference
00421             between the counters is the number of times it was taken.  An
00422             example of an instrumented conditional branch:
00423 
00424                                 call    BR_CNT_FUNC
00425                                 .word   0
00426                 LBRANCH23:      be      label
00427                                 call    BR_CNT_FUNC
00428                                 .word   0
00429 
00430         (2) a table of pointers to the instrumented branches, so that an
00431             external postprocessing routine can locate all of the counters.
00432             the table begins with a 2-word header: a pointer to the next in
00433             a linked list of such tables (initialized to 0);  and a count
00434             of the number of entries in the table (exclusive of the header.
00435 
00436             Note that input source code is expected to already contain calls
00437             an external routine that will link the branch local table into a
00438             list of such tables.  */
00439 
00440 /* Number of branches instrumented so far.  Also used to generate
00441    unique local labels for each instrumented branch.  */
00442 static int br_cnt;
00443 
00444 #define BR_LABEL_BASE       "LBRANCH"
00445 /* Basename of local labels on instrumented branches, to avoid
00446    conflict with compiler- generated local labels.  */
00447 
00448 #define BR_CNT_FUNC  "__inc_branch"
00449 /* Name of the external routine that will increment (and step over) an
00450    inline counter.  */
00451 
00452 #define BR_TAB_NAME  "__BRANCH_TABLE__"
00453 /* Name of the table of pointers to branches.  A local (i.e.,
00454    non-external) symbol.  */
00455 
00456 static void ctrl_fmt (char *, long, int);
00457 
00458 
00459 void
00460 md_begin (void)
00461 {
00462   int i;                    /* Loop counter.  */
00463   const struct i960_opcode *oP;    /* Pointer into opcode table.  */
00464   const char *retval;              /* Value returned by hash functions.  */
00465 
00466   op_hash = hash_new ();
00467   reg_hash = hash_new ();
00468   areg_hash = hash_new ();
00469 
00470   /* For some reason, the base assembler uses an empty string for "no
00471      error message", instead of a NULL pointer.  */
00472   retval = 0;
00473 
00474   for (oP = i960_opcodes; oP->name && !retval; oP++)
00475     retval = hash_insert (op_hash, oP->name, (void *) oP);
00476 
00477   for (i = 0; regnames[i].reg_name && !retval; i++)
00478     retval = hash_insert (reg_hash, regnames[i].reg_name,
00479                        (char *) &regnames[i].reg_num);
00480 
00481   for (i = 0; aregs[i].areg_name && !retval; i++)
00482     retval = hash_insert (areg_hash, aregs[i].areg_name,
00483                        (char *) &aregs[i].areg_num);
00484 
00485   if (retval)
00486     as_fatal (_("Hashing returned \"%s\"."), retval);
00487 }
00488 
00489 /* parse_expr:              parse an expression
00490 
00491    Use base assembler's expression parser to parse an expression.
00492    It, unfortunately, runs off a global which we have to save/restore
00493    in order to make it work for us.
00494 
00495    An empty expression string is treated as an absolute 0.
00496 
00497    Sets O_illegal regardless of expression evaluation if entire input
00498    string is not consumed in the evaluation -- tolerate no dangling junk!  */
00499 
00500 static void
00501 parse_expr (char *textP,           /* Text of expression to be parsed.  */
00502            expressionS *expP)             /* Where to put the results of parsing.  */
00503 {
00504   char *save_in;            /* Save global here.  */
00505   symbolS *symP;
00506 
00507   know (textP);
00508 
00509   if (*textP == '\0')
00510     {
00511       /* Treat empty string as absolute 0.  */
00512       expP->X_add_symbol = expP->X_op_symbol = NULL;
00513       expP->X_add_number = 0;
00514       expP->X_op = O_constant;
00515     }
00516   else
00517     {
00518       save_in = input_line_pointer;       /* Save global.  */
00519       input_line_pointer = textP;  /* Make parser work for us.  */
00520 
00521       (void) expression (expP);
00522       if ((size_t) (input_line_pointer - textP) != strlen (textP))
00523        /* Did not consume all of the input.  */
00524        expP->X_op = O_illegal;
00525 
00526       symP = expP->X_add_symbol;
00527       if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
00528        /* Register name in an expression.  */
00529        /* FIXME: this isn't much of a check any more.  */
00530        expP->X_op = O_illegal;
00531 
00532       input_line_pointer = save_in;       /* Restore global.  */
00533     }
00534 }
00535 
00536 /* emit:      output instruction binary
00537 
00538    Output instruction binary, in target byte order, 4 bytes at a time.
00539    Return pointer to where it was placed.  */
00540 
00541 static char *
00542 emit (long instr)           /* Word to be output, host byte order.  */
00543 {
00544   char *toP;                /* Where to output it.  */
00545 
00546   toP = frag_more (4);             /* Allocate storage.  */
00547   md_number_to_chars (toP, instr, 4);     /* Convert to target byte order.  */
00548   return toP;
00549 }
00550 
00551 /* get_cdisp: handle displacement for a COBR or CTRL instruction.
00552 
00553    Parse displacement for a COBR or CTRL instruction.
00554 
00555    If successful, output the instruction opcode and set up for it,
00556    depending on the arg 'var_frag', either:
00557            o an address fixup to be done when all symbol values are known, or
00558            o a varying length code fragment, with address fixup info.  This
00559               will be done for cobr instructions that may have to be relaxed
00560               in to compare/branch instructions (8 bytes) if the final
00561               address displacement is greater than 13 bits.  */
00562 
00563 static void
00564 get_cdisp (char *dispP, /* Displacement as specified in source instruction.  */
00565           char *ifmtP, /* "COBR" or "CTRL" (for use in error message).  */
00566           long instr,  /* Instruction needing the displacement.  */
00567           int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL).  */
00568           int var_frag,/* 1 if varying length code fragment should be emitted;
00569                         0 if an address fix should be emitted.  */
00570           int callj) /* 1 if callj relocation should be done; else 0.  */       
00571 {
00572   expressionS e;            /* Parsed expression.  */
00573   fixS *fixP;               /* Structure describing needed address fix.  */
00574   char *outP;               /* Where instruction binary is output to.  */
00575 
00576   fixP = NULL;
00577 
00578   parse_expr (dispP, &e);
00579   switch (e.X_op)
00580     {
00581     case O_illegal:
00582       as_bad (_("expression syntax error"));
00583 
00584     case O_symbol:
00585       if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
00586          || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
00587        {
00588          if (var_frag)
00589            {
00590              outP = frag_more (8); /* Allocate worst-case storage.  */
00591              md_number_to_chars (outP, instr, 4);
00592              frag_variant (rs_machine_dependent, 4, 4, 1,
00593                          adds (e), offs (e), outP);
00594            }
00595          else
00596            {
00597              /* Set up a new fix structure, so address can be updated
00598                 when all symbol values are known.  */
00599              outP = emit (instr);
00600              fixP = fix_new (frag_now,
00601                            outP - frag_now->fr_literal,
00602                            4,
00603                            adds (e),
00604                            offs (e),
00605                            1,
00606                            NO_RELOC);
00607 
00608              fixP->fx_tcbit = callj;
00609 
00610              /* We want to modify a bit field when the address is
00611                 known.  But we don't need all the garbage in the
00612                 bit_fix structure.  So we're going to lie and store
00613                 the number of bits affected instead of a pointer.  */
00614              fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
00615            }
00616        }
00617       else
00618        as_bad (_("attempt to branch into different segment"));
00619       break;
00620 
00621     default:
00622       as_bad (_("target of %s instruction must be a label"), ifmtP);
00623       break;
00624     }
00625 }
00626 
00627 static int
00628 md_chars_to_number (char * val,           /* Value in target byte order.  */
00629                   int n)           /* Number of bytes in the input.  */
00630 {
00631   int retval;
00632 
00633   for (retval = 0; n--;)
00634     {
00635       retval <<= 8;
00636       retval |= (unsigned char) val[n];
00637     }
00638   return retval;
00639 }
00640 
00641 /* mema_to_memb:     convert a MEMA-format opcode to a MEMB-format opcode.
00642 
00643    There are 2 possible MEMA formats:
00644        - displacement only
00645        - displacement + abase
00646 
00647    They are distinguished by the setting of the MEMA_ABASE bit.  */
00648 
00649 static void
00650 mema_to_memb (char * opcodeP)      /* Where to find the opcode, in target byte order.  */
00651 {
00652   long opcode;                     /* Opcode in host byte order.  */
00653   long mode;                /* Mode bits for MEMB instruction.  */
00654 
00655   opcode = md_chars_to_number (opcodeP, 4);
00656   know (!(opcode & MEMB_BIT));
00657 
00658   mode = MEMB_BIT | D_BIT;
00659   if (opcode & MEMA_ABASE)
00660     mode |= A_BIT;
00661 
00662   opcode &= 0xffffc000;            /* Clear MEMA offset and mode bits.  */
00663   opcode |= mode;           /* Set MEMB mode bits.  */
00664 
00665   md_number_to_chars (opcodeP, opcode, 4);
00666 }
00667 
00668 /* targ_has_sfr:
00669 
00670    Return TRUE iff the target architecture supports the specified
00671    special-function register (sfr).  */
00672 
00673 static int
00674 targ_has_sfr (int n)        /* Number (0-31) of sfr.  */
00675 {
00676   switch (architecture)
00677     {
00678     case ARCH_KA:
00679     case ARCH_KB:
00680     case ARCH_MC:
00681     case ARCH_JX:
00682       return 0;
00683     case ARCH_HX:
00684       return ((0 <= n) && (n <= 4));
00685     case ARCH_CA:
00686     default:
00687       return ((0 <= n) && (n <= 2));
00688     }
00689 }
00690 
00691 /* Look up a (suspected) register name in the register table and return the
00692    associated register number (or -1 if not found).  */
00693 
00694 static int
00695 get_regnum (char *regname)  /* Suspected register name.  */
00696 {
00697   int *rP;
00698 
00699   rP = (int *) hash_find (reg_hash, regname);
00700   return (rP == NULL) ? -1 : *rP;
00701 }
00702 
00703 /* syntax: Issue a syntax error.  */
00704 
00705 static void
00706 syntax (void)
00707 {
00708   as_bad (_("syntax error"));
00709 }
00710 
00711 /* parse_regop: parse a register operand.
00712 
00713    In case of illegal operand, issue a message and return some valid
00714    information so instruction processing can continue.  */
00715 
00716 static void
00717 parse_regop (struct regop *regopP, /* Where to put description of register operand.  */
00718             char *optext,          /* Text of operand.  */
00719             char opdesc)                  /* Descriptor byte:  what's legal for this operand.  */
00720 {
00721   int n;                    /* Register number.  */
00722   expressionS e;            /* Parsed expression.  */
00723 
00724   /* See if operand is a register.  */
00725   n = get_regnum (optext);
00726   if (n >= 0)
00727     {
00728       if (IS_RG_REG (n))
00729        {
00730          /* Global or local register.  */
00731          if (!REG_ALIGN (opdesc, n))
00732            as_bad (_("unaligned register"));
00733 
00734          regopP->n = n;
00735          regopP->mode = 0;
00736          regopP->special = 0;
00737          return;
00738        }
00739       else if (IS_FP_REG (n) && FP_OK (opdesc))
00740        {
00741          /* Floating point register, and it's allowed.  */
00742          regopP->n = n - FP0;
00743          regopP->mode = 1;
00744          regopP->special = 0;
00745          return;
00746        }
00747       else if (IS_SF_REG (n) && SFR_OK (opdesc))
00748        {
00749          /* Special-function register, and it's allowed.  */
00750          regopP->n = n - SF0;
00751          regopP->mode = 0;
00752          regopP->special = 1;
00753          if (!targ_has_sfr (regopP->n))
00754            as_bad (_("no such sfr in this architecture"));
00755 
00756          return;
00757        }
00758     }
00759   else if (LIT_OK (opdesc))
00760     {
00761       /* How about a literal?  */
00762       regopP->mode = 1;
00763       regopP->special = 0;
00764       if (FP_OK (opdesc))
00765        {
00766          /* Floating point literal acceptable.  */
00767          /* Skip over 0f, 0d, or 0e prefix.  */
00768          if ((optext[0] == '0')
00769              && (optext[1] >= 'd')
00770              && (optext[1] <= 'f'))
00771            optext += 2;
00772 
00773          if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
00774            {
00775              regopP->n = 0x10;
00776              return;
00777            }
00778 
00779          if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
00780            {
00781              regopP->n = 0x16;
00782              return;
00783            }
00784        }
00785       else
00786        {
00787          /* Fixed point literal acceptable.  */
00788          parse_expr (optext, &e);
00789          if (e.X_op != O_constant
00790              || (offs (e) < 0) || (offs (e) > 31))
00791            {
00792              as_bad (_("illegal literal"));
00793              offs (e) = 0;
00794            }
00795          regopP->n = offs (e);
00796          return;
00797        }
00798     }
00799 
00800   /* Nothing worked.  */
00801   syntax ();
00802   regopP->mode = 0;         /* Register r0 is always a good one.  */
00803   regopP->n = 0;
00804   regopP->special = 0;
00805 }
00806 
00807 /* get_ispec: parse a memory operand for an index specification
00808    
00809    Here, an "index specification" is taken to be anything surrounded
00810    by square brackets and NOT followed by anything else.
00811 
00812    If it's found, detach it from the input string, remove the surrounding
00813    square brackets, and return a pointer to it.  Otherwise, return NULL.  */
00814 
00815 static char *
00816 get_ispec (char *textP)  /* Pointer to memory operand from source instruction, no white space.  */
00817           
00818 {
00819   /* Points to start of index specification.  */
00820   char *start;
00821   /* Points to end of index specification.  */
00822   char *end;
00823 
00824   /* Find opening square bracket, if any.  */
00825   start = strchr (textP, '[');
00826 
00827   if (start != NULL)
00828     {
00829       /* Eliminate '[', detach from rest of operand.  */
00830       *start++ = '\0';
00831 
00832       end = strchr (start, ']');
00833 
00834       if (end == NULL)
00835        as_bad (_("unmatched '['"));
00836       else
00837        {
00838          /* Eliminate ']' and make sure it was the last thing
00839             in the string.  */
00840          *end = '\0';
00841          if (*(end + 1) != '\0')
00842            as_bad (_("garbage after index spec ignored"));
00843        }
00844     }
00845   return start;
00846 }
00847 
00848 /* parse_memop:      parse a memory operand
00849 
00850        This routine is based on the observation that the 4 mode bits of the
00851        MEMB format, taken individually, have fairly consistent meaning:
00852 
00853                M3 (bit 13): 1 if displacement is present (D_BIT)
00854                M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
00855                M1 (bit 11): 1 if index is present (I_BIT)
00856                M0 (bit 10): 1 if abase is present (A_BIT)
00857 
00858        So we parse the memory operand and set bits in the mode as we find
00859        things.  Then at the end, if we go to MEMB format, we need only set
00860        the MEMB bit (M2) and our mode is built for us.
00861 
00862        Unfortunately, I said "fairly consistent".  The exceptions:
00863 
00864                DBIA
00865                0100  Would seem illegal, but means "abase-only".
00866 
00867                0101  Would seem to mean "abase-only" -- it means IP-relative.
00868                      Must be converted to 0100.
00869 
00870                0110  Would seem to mean "index-only", but is reserved.
00871                      We turn on the D bit and provide a 0 displacement.
00872 
00873        The other thing to observe is that we parse from the right, peeling
00874        things * off as we go:  first any index spec, then any abase, then
00875        the displacement.  */
00876 
00877 static void
00878 parse_memop (memS *memP,    /* Where to put the results.  */
00879             char *argP,     /* Text of the operand to be parsed.  */
00880             int optype)     /* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16.  */
00881 {
00882   char *indexP;                    /* Pointer to index specification with "[]" removed.  */
00883   char *p;                  /* Temp char pointer.  */
00884   char iprel_flag;          /* True if this is an IP-relative operand.  */
00885   int regnum;               /* Register number.  */
00886   /* Scale factor: 1,2,4,8, or 16.  Later converted to internal format
00887      (0,1,2,3,4 respectively).  */
00888   int scale;
00889   int mode;                 /* MEMB mode bits.  */
00890   int *intP;                /* Pointer to register number.  */
00891 
00892   /* The following table contains the default scale factors for each
00893      type of memory instruction.  It is accessed using (optype-MEM1)
00894      as an index -- thus it assumes the 'optype' constants are
00895      assigned consecutive values, in the order they appear in this
00896      table.  */
00897   static const int def_scale[] =
00898   {
00899     1,                      /* MEM1 */
00900     2,                      /* MEM2 */
00901     4,                      /* MEM4 */
00902     8,                      /* MEM8 */
00903     -1,                            /* MEM12 -- no valid default */
00904     16                      /* MEM16 */
00905   };
00906 
00907   iprel_flag = mode = 0;
00908 
00909   /* Any index present? */
00910   indexP = get_ispec (argP);
00911   if (indexP)
00912     {
00913       p = strchr (indexP, '*');
00914       if (p == NULL)
00915        {
00916          /* No explicit scale -- use default for this instruction
00917             type and assembler mode.  */
00918          if (flag_mri)
00919            scale = 1;
00920          else
00921            /* GNU960 compatibility */
00922            scale = def_scale[optype - MEM1];
00923        }
00924       else
00925        {
00926          *p++ = '\0';              /* Eliminate '*' */
00927 
00928          /* Now indexP->a '\0'-terminated register name,
00929             and p->a scale factor.  */
00930 
00931          if (!strcmp (p, "16"))
00932            scale = 16;
00933          else if (strchr ("1248", *p) && (p[1] == '\0'))
00934            scale = *p - '0';
00935          else
00936            scale = -1;
00937        }
00938 
00939       regnum = get_regnum (indexP);       /* Get index reg. # */
00940       if (!IS_RG_REG (regnum))
00941        {
00942          as_bad (_("invalid index register"));
00943          return;
00944        }
00945 
00946       /* Convert scale to its binary encoding.  */
00947       switch (scale)
00948        {
00949        case 1:
00950          scale = 0 << 7;
00951          break;
00952        case 2:
00953          scale = 1 << 7;
00954          break;
00955        case 4:
00956          scale = 2 << 7;
00957          break;
00958        case 8:
00959          scale = 3 << 7;
00960          break;
00961        case 16:
00962          scale = 4 << 7;
00963          break;
00964        default:
00965          as_bad (_("invalid scale factor"));
00966          return;
00967        };
00968 
00969       memP->opcode |= scale | regnum;     /* Set index bits in opcode.  */
00970       mode |= I_BIT;               /* Found a valid index spec.  */
00971     }
00972 
00973   /* Any abase (Register Indirect) specification present?  */
00974   if ((p = strrchr (argP, '(')) != NULL)
00975     {
00976       /* "(" is there -- does it start a legal abase spec?  If not, it
00977          could be part of a displacement expression.  */
00978       intP = (int *) hash_find (areg_hash, p);
00979       if (intP != NULL)
00980        {
00981          /* Got an abase here.  */
00982          regnum = *intP;
00983          *p = '\0';         /* Discard register spec.  */
00984          if (regnum == IPREL)
00985            /* We have to specialcase ip-rel mode.  */
00986            iprel_flag = 1;
00987          else
00988            {
00989              memP->opcode |= regnum << 14;
00990              mode |= A_BIT;
00991            }
00992        }
00993     }
00994 
00995   /* Any expression present?  */
00996   memP->e = argP;
00997   if (*argP != '\0')
00998     mode |= D_BIT;
00999 
01000   /* Special-case ip-relative addressing.  */
01001   if (iprel_flag)
01002     {
01003       if (mode & I_BIT)
01004        syntax ();
01005       else
01006        {
01007          memP->opcode |= 5 << 10;  /* IP-relative mode.  */
01008          memP->disp = 32;
01009        }
01010       return;
01011     }
01012 
01013   /* Handle all other modes.  */
01014   switch (mode)
01015     {
01016     case D_BIT | A_BIT:
01017       /* Go with MEMA instruction format for now (grow to MEMB later
01018          if 12 bits is not enough for the displacement).  MEMA format
01019          has a single mode bit: set it to indicate that abase is
01020          present.  */
01021       memP->opcode |= MEMA_ABASE;
01022       memP->disp = 12;
01023       break;
01024 
01025     case D_BIT:
01026       /* Go with MEMA instruction format for now (grow to MEMB later
01027          if 12 bits is not enough for the displacement).  */
01028       memP->disp = 12;
01029       break;
01030 
01031     case A_BIT:
01032       /* For some reason, the bit string for this mode is not
01033          consistent: it should be 0 (exclusive of the MEMB bit), so we
01034          set it "by hand" here.  */
01035       memP->opcode |= MEMB_BIT;
01036       break;
01037 
01038     case A_BIT | I_BIT:
01039       /* set MEMB bit in mode, and OR in mode bits.  */
01040       memP->opcode |= mode | MEMB_BIT;
01041       break;
01042 
01043     case I_BIT:
01044       /* Treat missing displacement as displacement of 0.  */
01045       mode |= D_BIT;
01046       /* Fall into next case.  */
01047     case D_BIT | A_BIT | I_BIT:
01048     case D_BIT | I_BIT:
01049       /* Set MEMB bit in mode, and OR in mode bits.  */
01050       memP->opcode |= mode | MEMB_BIT;
01051       memP->disp = 32;
01052       break;
01053 
01054     default:
01055       syntax ();
01056       break;
01057     }
01058 }
01059 
01060 /* Generate a MEMA- or MEMB-format instruction.  */
01061 
01062 static void
01063 mem_fmt (char *args[],             /* args[0]->opcode mnemonic, args[1-3]->operands.  */
01064         struct i960_opcode *oP,/* Pointer to description of instruction.  */
01065         int callx)          /* Is this a callx opcode.  */
01066 {
01067   int i;                    /* Loop counter.  */
01068   struct regop regop;              /* Description of register operand.  */
01069   char opdesc;                     /* Operand descriptor byte.  */
01070   memS instr;               /* Description of binary to be output.  */
01071   char *outP;               /* Where the binary was output to.  */
01072   expressionS expr;         /* Parsed expression.  */
01073   /* ->description of deferred address fixup.  */
01074   fixS *fixP;
01075 
01076 #ifdef OBJ_COFF
01077   /* COFF support isn't in place yet for callx relaxing.  */
01078   callx = 0;
01079 #endif
01080 
01081   memset (&instr, '\0', sizeof (memS));
01082   instr.opcode = oP->opcode;
01083 
01084   /* Process operands.  */
01085   for (i = 1; i <= oP->num_ops; i++)
01086     {
01087       opdesc = oP->operand[i - 1];
01088 
01089       if (MEMOP (opdesc))
01090        parse_memop (&instr, args[i], oP->format);
01091       else
01092        {
01093          parse_regop (&regop, args[i], opdesc);
01094          instr.opcode |= regop.n << 19;
01095        }
01096     }
01097 
01098   /* Parse the displacement; this must be done before emitting the
01099      opcode, in case it is an expression using `.'.  */
01100   parse_expr (instr.e, &expr);
01101 
01102   /* Output opcode.  */
01103   outP = emit (instr.opcode);
01104 
01105   if (instr.disp == 0)
01106     return;
01107 
01108   /* Process the displacement.  */
01109   switch (expr.X_op)
01110     {
01111     case O_illegal:
01112       as_bad (_("expression syntax error"));
01113       break;
01114 
01115     case O_constant:
01116       if (instr.disp == 32)
01117        (void) emit (offs (expr));  /* Output displacement.  */
01118       else
01119        {
01120          /* 12-bit displacement.  */
01121          if (offs (expr) & ~0xfff)
01122            {
01123              /* Won't fit in 12 bits: convert already-output
01124                 instruction to MEMB format, output
01125                 displacement.  */
01126              mema_to_memb (outP);
01127              (void) emit (offs (expr));
01128            }
01129          else
01130            {
01131              /* WILL fit in 12 bits:  OR into opcode and
01132                 overwrite the binary we already put out.  */
01133              instr.opcode |= offs (expr);
01134              md_number_to_chars (outP, instr.opcode, 4);
01135            }
01136        }
01137       break;
01138 
01139     default:
01140       if (instr.disp == 12)
01141        /* Displacement is dependent on a symbol, whose value
01142           may change at link time.  We HAVE to reserve 32 bits.
01143           Convert already-output opcode to MEMB format.  */
01144        mema_to_memb (outP);
01145 
01146       /* Output 0 displacement and set up address fixup for when
01147          this symbol's value becomes known.  */
01148       outP = emit ((long) 0);
01149       fixP = fix_new_exp (frag_now,
01150                        outP - frag_now->fr_literal,
01151                        4, & expr, 0, NO_RELOC);
01152       /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
01153          being in the instruction stream, specifically as part of a callx
01154          instruction.  */
01155       fixP->fx_bsr = callx;
01156       break;
01157     }
01158 }
01159 
01160 /* targ_has_iclass:
01161 
01162    Return TRUE iff the target architecture supports the indicated
01163    class of instructions.  */
01164 
01165 static int
01166 targ_has_iclass (int ic) /* Instruction class;  one of:
01167                          I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2.  */
01168 {
01169   iclasses_seen |= ic;
01170 
01171   switch (architecture)
01172     {
01173     case ARCH_KA:
01174       return ic & (I_BASE | I_KX);
01175     case ARCH_KB:
01176       return ic & (I_BASE | I_KX | I_FP | I_DEC);
01177     case ARCH_MC:
01178       return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
01179     case ARCH_CA:
01180       return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
01181     case ARCH_JX:
01182       return ic & (I_BASE | I_CX2 | I_JX);
01183     case ARCH_HX:
01184       return ic & (I_BASE | I_CX2 | I_JX | I_HX);
01185     default:
01186       if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
01187          && (iclasses_seen & (I_CX | I_CX2)))
01188        {
01189          as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
01190          iclasses_seen &= ~ic;
01191        }
01192       return 1;
01193     }
01194 }
01195 
01196 /* shift_ok:
01197    Determine if a "shlo" instruction can be used to implement a "ldconst".
01198    This means that some number X < 32 can be shifted left to produce the
01199    constant of interest.
01200 
01201    Return the shift count, or 0 if we can't do it.
01202    Caller calculates X by shifting original constant right 'shift' places.  */
01203 
01204 static int
01205 shift_ok (int n)            /* The constant of interest.  */
01206 {
01207   int shift;                /* The shift count.  */
01208 
01209   if (n <= 0)
01210     /* Can't do it for negative numbers.  */
01211     return 0;
01212 
01213   /* Shift 'n' right until a 1 is about to be lost.  */
01214   for (shift = 0; (n & 1) == 0; shift++)
01215     n >>= 1;
01216 
01217   if (n >= 32)
01218     return 0;
01219 
01220   return shift;
01221 }
01222 
01223 /* parse_ldcont:
01224    Parse and replace a 'ldconst' pseudo-instruction with an appropriate
01225    i80960 instruction.
01226 
01227    Assumes the input consists of:
01228               arg[0] opcode mnemonic ('ldconst')
01229               arg[1]  first operand (constant)
01230               arg[2] name of register to be loaded
01231 
01232    Replaces opcode and/or operands as appropriate.
01233 
01234    Returns the new number of arguments, or -1 on failure.  */
01235 
01236 static int
01237 parse_ldconst (char *arg[]) /* See above.  */
01238 {
01239   int n;                    /* Constant to be loaded.  */
01240   int shift;                /* Shift count for "shlo" instruction.  */
01241   static char buf[5];              /* Literal for first operand.  */
01242   static char buf2[5];             /* Literal for second operand.  */
01243   expressionS e;            /* Parsed expression.  */
01244 
01245   arg[3] = NULL;            /* So we can tell at the end if it got used or not.  */
01246 
01247   parse_expr (arg[1], &e);
01248   switch (e.X_op)
01249     {
01250     default:
01251       /* We're dependent on one or more symbols -- use "lda".  */
01252       arg[0] = "lda";
01253       break;
01254 
01255     case O_constant:
01256       /* Try the following mappings:
01257               ldconst   0,<reg>  -> mov  0,<reg>
01258               ldconst  31,<reg>  -> mov  31,<reg>
01259               ldconst  32,<reg>  -> addo 1,31,<reg>
01260               ldconst  62,<reg>  -> addo 31,31,<reg>
01261               ldconst  64,<reg>  -> shlo 8,3,<reg>
01262               ldconst  -1,<reg>  -> subo 1,0,<reg>
01263               ldconst -31,<reg>  -> subo 31,0,<reg>
01264         
01265          Anything else becomes:
01266                 lda xxx,<reg>.  */
01267       n = offs (e);
01268       if ((0 <= n) && (n <= 31))
01269        arg[0] = "mov";
01270       else if ((-31 <= n) && (n <= -1))
01271        {
01272          arg[0] = "subo";
01273          arg[3] = arg[2];
01274          sprintf (buf, "%d", -n);
01275          arg[1] = buf;
01276          arg[2] = "0";
01277        }
01278       else if ((32 <= n) && (n <= 62))
01279        {
01280          arg[0] = "addo";
01281          arg[3] = arg[2];
01282          arg[1] = "31";
01283          sprintf (buf, "%d", n - 31);
01284          arg[2] = buf;
01285        }
01286       else if ((shift = shift_ok (n)) != 0)
01287        {
01288          arg[0] = "shlo";
01289          arg[3] = arg[2];
01290          sprintf (buf, "%d", shift);
01291          arg[1] = buf;
01292          sprintf (buf2, "%d", n >> shift);
01293          arg[2] = buf2;
01294        }
01295       else
01296        arg[0] = "lda";
01297       break;
01298 
01299     case O_illegal:
01300       as_bad (_("invalid constant"));
01301       return -1;
01302       break;
01303     }
01304   return (arg[3] == 0) ? 2 : 3;
01305 }
01306 
01307 /* reg_fmt:   generate a REG-format instruction.  */
01308 
01309 static void
01310 reg_fmt (char *args[],             /* args[0]->opcode mnemonic, args[1-3]->operands.  */
01311         struct i960_opcode *oP)/* Pointer to description of instruction.  */
01312 {
01313   long instr;               /* Binary to be output.  */
01314   struct regop regop;              /* Description of register operand.  */
01315   int n_ops;                /* Number of operands.  */
01316 
01317   instr = oP->opcode;
01318   n_ops = oP->num_ops;
01319 
01320   if (n_ops >= 1)
01321     {
01322       parse_regop (&regop, args[1], oP->operand[0]);
01323 
01324       if ((n_ops == 1) && !(instr & M3))
01325        {
01326          /* 1-operand instruction in which the dst field should
01327             be used (instead of src1).  */
01328          regop.n <<= 19;
01329          if (regop.special)
01330            regop.mode = regop.special;
01331          regop.mode <<= 13;
01332          regop.special = 0;
01333        }
01334       else
01335        {
01336          /* regop.n goes in bit 0, needs no shifting.  */
01337          regop.mode <<= 11;
01338          regop.special <<= 5;
01339        }
01340       instr |= regop.n | regop.mode | regop.special;
01341     }
01342 
01343   if (n_ops >= 2)
01344     {
01345       parse_regop (&regop, args[2], oP->operand[1]);
01346 
01347       if ((n_ops == 2) && !(instr & M3))
01348        {
01349          /* 2-operand instruction in which the dst field should
01350             be used instead of src2).  */
01351          regop.n <<= 19;
01352          if (regop.special)
01353            regop.mode = regop.special;
01354          regop.mode <<= 13;
01355          regop.special = 0;
01356        }
01357       else
01358        {
01359          regop.n <<= 14;
01360          regop.mode <<= 12;
01361          regop.special <<= 6;
01362        }
01363       instr |= regop.n | regop.mode | regop.special;
01364     }
01365   if (n_ops == 3)
01366     {
01367       parse_regop (&regop, args[3], oP->operand[2]);
01368       if (regop.special)
01369        regop.mode = regop.special;
01370       instr |= (regop.n <<= 19) | (regop.mode <<= 13);
01371     }
01372   emit (instr);
01373 }
01374 
01375 /* get_args:  break individual arguments out of comma-separated list
01376 
01377    Input assumptions:
01378        - all comments and labels have been removed
01379        - all strings of whitespace have been collapsed to a single blank.
01380        - all character constants ('x') have been replaced with decimal
01381 
01382    Output:
01383        args[0] is untouched. args[1] points to first operand, etc. All args:
01384        - are NULL-terminated
01385        - contain no whitespace
01386 
01387    Return value:
01388    Number of operands (0,1,2, or 3) or -1 on error.  */
01389 
01390 static int
01391 get_args (char *p,   /* Pointer to comma-separated operands; Mucked by us.  */
01392          char *args[]) /* Output arg: pointers to operands placed in args[1-3].
01393                         Must accommodate 4 entries (args[0-3]).  */
01394 
01395 {
01396   int n;             /* Number of operands.  */
01397   char *to;
01398 
01399   /* Skip lead white space.  */
01400   while (*p == ' ')
01401     p++;
01402 
01403   if (*p == '\0')
01404     return 0;
01405 
01406   n = 1;
01407   args[1] = p;
01408 
01409   /* Squeze blanks out by moving non-blanks toward start of string.
01410      Isolate operands, whenever comma is found.  */
01411   to = p;
01412   while (*p != '\0')
01413     {
01414       if (*p == ' '
01415          && (! ISALNUM (p[1])
01416              || ! ISALNUM (p[-1])))
01417        p++;
01418       else if (*p == ',')
01419        {
01420          /* Start of operand.  */
01421          if (n == 3)
01422            {
01423              as_bad (_("too many operands"));
01424              return -1;
01425            }
01426          *to++ = '\0';             /* Terminate argument.  */
01427          args[++n] = to;    /* Start next argument.  */
01428          p++;
01429        }
01430       else
01431        *to++ = *p++;
01432     }
01433   *to = '\0';
01434   return n;
01435 }
01436 
01437 /* i_scan:    perform lexical scan of ascii assembler instruction.
01438 
01439    Input assumptions:
01440        - input string is an i80960 instruction (not a pseudo-op)
01441        - all comments and labels have been removed
01442        - all strings of whitespace have been collapsed to a single blank.
01443 
01444    Output:
01445        args[0] points to opcode, other entries point to operands. All strings:
01446        - are NULL-terminated
01447        - contain no whitespace
01448        - have character constants ('x') replaced with a decimal number
01449 
01450    Return value:
01451      Number of operands (0,1,2, or 3) or -1 on error.  */
01452 
01453 static int
01454 i_scan (char *iP,     /* Pointer to ascii instruction;  Mucked by us.  */
01455        char *args[]) /* Output arg: pointers to opcode and operands placed here.
01456                       Must accommodate 4 entries.  */
01457 {
01458   /* Isolate opcode.  */
01459   if (*(iP) == ' ')
01460     iP++;
01461 
01462   args[0] = iP;
01463   for (; *iP != ' '; iP++)
01464     {
01465       if (*iP == '\0')
01466        {
01467          /* There are no operands.  */
01468          if (args[0] == iP)
01469            {
01470              /* We never moved: there was no opcode either!  */
01471              as_bad (_("missing opcode"));
01472              return -1;
01473            }
01474          return 0;
01475        }
01476     }
01477   *iP++ = '\0';
01478   return (get_args (iP, args));
01479 }
01480 
01481 static void
01482 brcnt_emit (void)
01483 {
01484   /* Emit call to "increment" routine.  */
01485   ctrl_fmt (BR_CNT_FUNC, CALL, 1);
01486   /* Emit inline counter to be incremented.  */
01487   emit (0);
01488 }
01489 
01490 static char *
01491 brlab_next (void)
01492 {
01493   static char buf[20];
01494 
01495   sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
01496   return buf;
01497 }
01498 
01499 static void
01500 ctrl_fmt (char *targP,             /* Pointer to text of lone operand (if any).  */
01501          long opcode,              /* Template of instruction.  */
01502          int num_ops)              /* Number of operands.  */
01503 {
01504   int instrument;           /* TRUE iff we should add instrumentation to track
01505                                how often the branch is taken.  */
01506 
01507   if (num_ops == 0)
01508     emit (opcode);          /* Output opcode.  */
01509   else
01510     {
01511       instrument = instrument_branches && (opcode != CALL)
01512        && (opcode != B) && (opcode != RET) && (opcode != BAL);
01513 
01514       if (instrument)
01515        {
01516          brcnt_emit ();
01517          colon (brlab_next ());
01518        }
01519 
01520       /* The operand MUST be an ip-relative displacement. Parse it
01521          and set up address fix for the instruction we just output.  */
01522       get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
01523 
01524       if (instrument)
01525        brcnt_emit ();
01526     }
01527 }
01528 
01529 static void
01530 cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
01531          char *arg[],
01532          /* Opcode, with branch-prediction bits already set if necessary.  */
01533          long opcode,
01534          /* Pointer to description of instruction.  */
01535          struct i960_opcode *oP)
01536 {
01537   long instr;               /* 32-bit instruction.  */
01538   struct regop regop;              /* Description of register operand.  */
01539   int n;                    /* Number of operands.  */
01540   int var_frag;                    /* 1 if varying length code fragment should
01541                                  be emitted;  0 if an address fix
01542                                     should be emitted.  */
01543 
01544   instr = opcode;
01545   n = oP->num_ops;
01546 
01547   if (n >= 1)
01548     {
01549       /* First operand (if any) of a COBR is always a register
01550         operand.  Parse it.  */
01551       parse_regop (&regop, arg[1], oP->operand[0]);
01552       instr |= (regop.n << 19) | (regop.mode << 13);
01553     }
01554 
01555   if (n >= 2)
01556     {
01557       /* Second operand (if any) of a COBR is always a register
01558         operand.  Parse it.  */
01559       parse_regop (&regop, arg[2], oP->operand[1]);
01560       instr |= (regop.n << 14) | regop.special;
01561     }
01562 
01563   if (n < 3)
01564     emit (instr);
01565   else
01566     {
01567       if (instrument_branches)
01568        {
01569          brcnt_emit ();
01570          colon (brlab_next ());
01571        }
01572 
01573       /* A third operand to a COBR is always a displacement.  Parse
01574          it; if it's relaxable (a cobr "j" directive, or any cobr
01575          other than bbs/bbc when the "-norelax" option is not in use)
01576          set up a variable code fragment; otherwise set up an address
01577          fix.  */
01578       var_frag = !norelax || (oP->format == COJ);       /* TRUE or FALSE */
01579       get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
01580 
01581       if (instrument_branches)
01582        brcnt_emit ();
01583     }
01584 }
01585 
01586 /* Assumptions about the passed-in text:
01587        - all comments, labels removed
01588        - text is an instruction
01589        - all white space compressed to single blanks
01590        - all character constants have been replaced with decimal.  */
01591 
01592 void
01593 md_assemble (char *textP)
01594 {
01595   /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
01596      mnemonic arg[1-3]->operands, with char constants replaced by
01597      decimal numbers.  */
01598   char *args[4];
01599   /* Number of instruction operands.  */
01600   int n_ops;
01601   /* Pointer to instruction description.  */
01602   struct i960_opcode *oP;
01603   /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
01604      or ".t").  */
01605   int branch_predict;
01606   /* Setting of branch-prediction bit(s) to be OR'd into instruction
01607      opcode of CTRL/COBR format instructions.  */
01608   long bp_bits;
01609   /* Offset of last character in opcode mnemonic.  */
01610   int n;
01611   const char *bp_error_msg = _("branch prediction invalid on this opcode");
01612 
01613   /* Parse instruction into opcode and operands.  */
01614   memset (args, '\0', sizeof (args));
01615 
01616   n_ops = i_scan (textP, args);
01617 
01618   if (n_ops == -1)
01619     return;                 /* Error message already issued.  */
01620 
01621   /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction.  */
01622   if (!strcmp (args[0], "ldconst"))
01623     {
01624       n_ops = parse_ldconst (args);
01625       if (n_ops == -1)
01626        return;
01627     }
01628 
01629   /* Check for branch-prediction suffix on opcode mnemonic, strip it off.  */
01630   n = strlen (args[0]) - 1;
01631   branch_predict = 0;
01632   bp_bits = 0;
01633 
01634   if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
01635     {
01636       /* We could check here to see if the target architecture
01637         supports branch prediction, but why bother?  The bit will
01638         just be ignored by processors that don't use it.  */
01639       branch_predict = 1;
01640       bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
01641       args[0][n - 1] = '\0';       /* Strip suffix from opcode mnemonic */
01642     }
01643 
01644   /* Look up opcode mnemonic in table and check number of operands.
01645      Check that opcode is legal for the target architecture.  If all
01646      looks good, assemble instruction.  */
01647   oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
01648   if (!oP || !targ_has_iclass (oP->iclass))
01649     as_bad (_("invalid opcode, \"%s\"."), args[0]);
01650   else if (n_ops != oP->num_ops)
01651     as_bad (_("improper number of operands.  expecting %d, got %d"),
01652            oP->num_ops, n_ops);
01653   else
01654     {
01655       switch (oP->format)
01656        {
01657        case FBRA:
01658        case CTRL:
01659          ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
01660          if (oP->format == FBRA)
01661            /* Now generate a 'bno' to same arg */
01662            ctrl_fmt (args[1], BNO | bp_bits, 1);
01663          break;
01664        case COBR:
01665        case COJ:
01666          cobr_fmt (args, oP->opcode | bp_bits, oP);
01667          break;
01668        case REG:
01669          if (branch_predict)
01670            as_warn (bp_error_msg);
01671          reg_fmt (args, oP);
01672          break;
01673        case MEM1:
01674          if (args[0][0] == 'c' && args[0][1] == 'a')
01675            {
01676              if (branch_predict)
01677               as_warn (bp_error_msg);
01678              mem_fmt (args, oP, 1);
01679              break;
01680            }
01681        case MEM2:
01682        case MEM4:
01683        case MEM8:
01684        case MEM12:
01685        case MEM16:
01686          if (branch_predict)
01687            as_warn (bp_error_msg);
01688          mem_fmt (args, oP, 0);
01689          break;
01690        case CALLJ:
01691          if (branch_predict)
01692            as_warn (bp_error_msg);
01693          /* Output opcode & set up "fixup" (relocation); flag
01694             relocation as 'callj' type.  */
01695          know (oP->num_ops == 1);
01696          get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
01697          break;
01698        default:
01699          BAD_CASE (oP->format);
01700          break;
01701        }
01702     }
01703 }
01704 
01705 void
01706 md_number_to_chars (char *buf,
01707                   valueT value,
01708                   int n)
01709 {
01710   number_to_chars_littleendian (buf, value, n);
01711 }
01712 
01713 #define MAX_LITTLENUMS      6
01714 #define LNUM_SIZE    sizeof (LITTLENUM_TYPE)
01715 
01716 /* md_atof:   convert ascii to floating point
01717 
01718    Turn a string at input_line_pointer into a floating point constant of type
01719    'type', and store the appropriate bytes at *litP.  The number of LITTLENUMS
01720    emitted is returned at 'sizeP'.  An error message is returned, or a pointer
01721    to an empty message if OK.
01722 
01723    Note we call the i386 floating point routine, rather than complicating
01724    things with more files or symbolic links.  */
01725 
01726 char *
01727 md_atof (int type, char *litP, int *sizeP)
01728 {
01729   LITTLENUM_TYPE words[MAX_LITTLENUMS];
01730   LITTLENUM_TYPE *wordP;
01731   int prec;
01732   char *t;
01733 
01734   switch (type)
01735     {
01736     case 'f':
01737     case 'F':
01738       prec = 2;
01739       break;
01740 
01741     case 'd':
01742     case 'D':
01743       prec = 4;
01744       break;
01745 
01746     case 't':
01747     case 'T':
01748       prec = 5;
01749       type = 'x';           /* That's what atof_ieee() understands.  */
01750       break;
01751 
01752     default:
01753       *sizeP = 0;
01754       return _("Bad call to md_atof()");
01755     }
01756 
01757   t = atof_ieee (input_line_pointer, type, words);
01758   if (t)
01759     input_line_pointer = t;
01760 
01761   *sizeP = prec * LNUM_SIZE;
01762 
01763   /* Output the LITTLENUMs in REVERSE order in accord with i80960
01764      word-order.  (Dunno why atof_ieee doesn't do it in the right
01765      order in the first place -- probably because it's a hack of
01766      atof_m68k.)  */
01767   for (wordP = words + prec - 1; prec--;)
01768     {
01769       md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
01770       litP += sizeof (LITTLENUM_TYPE);
01771     }
01772 
01773   return 0;
01774 }
01775 
01776 static void
01777 md_number_to_imm (char *buf, long val, int n)
01778 {
01779   md_number_to_chars (buf, val, n);
01780 }
01781 
01782 static void
01783 md_number_to_field (char *instrP,         /* Pointer to instruction to be fixed.  */
01784                   long val,               /* Address fixup value.  */
01785                   bit_fixS *bfixP)        /* Description of bit field to be fixed up.  */
01786 {
01787   int numbits;                     /* Length of bit field to be fixed.  */
01788   long instr;               /* 32-bit instruction to be fixed-up.  */
01789   long sign;                /* 0 or -1, according to sign bit of 'val'.  */
01790 
01791   /* Convert instruction back to host byte order.  */
01792   instr = md_chars_to_number (instrP, 4);
01793 
01794   /* Surprise! -- we stored the number of bits to be modified rather
01795      than a pointer to a structure.  */
01796   numbits = (int) (size_t) bfixP;
01797   if (numbits == 1)
01798     /* This is a no-op, stuck here by reloc_callj().  */
01799     return;
01800 
01801   know ((numbits == 13) || (numbits == 24));
01802 
01803   /* Propagate sign bit of 'val' for the given number of bits.  Result
01804      should be all 0 or all 1.  */
01805   sign = val >> ((int) numbits - 1);
01806   if (((val < 0) && (sign != -1))
01807       || ((val > 0) && (sign != 0)))
01808     as_bad (_("Fixup of %ld too large for field width of %d"),
01809            val, numbits);
01810   else
01811     {
01812       /* Put bit field into instruction and write back in target
01813          * byte order.  */
01814       val &= ~(-1 << (int) numbits);      /* Clear unused sign bits.  */
01815       instr |= val;
01816       md_number_to_chars (instrP, instr, 4);
01817     }
01818 }
01819 
01820 
01821 /* md_parse_option
01822        Invocation line includes a switch not recognized by the base assembler.
01823        See if it's a processor-specific option.  For the 960, these are:
01824 
01825        -norelax:
01826               Conditional branch instructions that require displacements
01827               greater than 13 bits (or that have external targets) should
01828               generate errors.  The default is to replace each such
01829               instruction with the corresponding compare (or chkbit) and
01830               branch instructions.  Note that the Intel "j" cobr directives
01831               are ALWAYS "de-optimized" in this way when necessary,
01832               regardless of the setting of this option.
01833 
01834        -b:
01835               Add code to collect information about branches taken, for
01836               later optimization of branch prediction bits by a separate
01837               tool.  COBR and CNTL format instructions have branch
01838               prediction bits (in the CX architecture);  if "BR" represents
01839               an instruction in one of these classes, the following rep-
01840               resents the code generated by the assembler:
01841 
01842                      call   <increment routine>
01843                      .word  0      # pre-counter
01844               Label:  BR
01845                      call   <increment routine>
01846                      .word  0      # post-counter
01847 
01848               A table of all such "Labels" is also generated.
01849 
01850        -AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
01851               Select the 80960 architecture.  Instructions or features not
01852               supported by the selected architecture cause fatal errors.
01853               The default is to generate code for any instruction or feature
01854               that is supported by SOME version of the 960 (even if this
01855               means mixing architectures!).  */
01856 
01857 const char *md_shortopts = "A:b";
01858 struct option md_longopts[] =
01859 {
01860 #define OPTION_LINKRELAX (OPTION_MD_BASE)
01861   {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
01862   {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
01863 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
01864   {"norelax", no_argument, NULL, OPTION_NORELAX},
01865   {"no-relax", no_argument, NULL, OPTION_NORELAX},
01866   {NULL, no_argument, NULL, 0}
01867 };
01868 size_t md_longopts_size = sizeof (md_longopts);
01869 
01870 struct tabentry
01871 {
01872   char *flag;
01873   int arch;
01874 };
01875 static const struct tabentry arch_tab[] =
01876 {
01877   {"KA", ARCH_KA},
01878   {"KB", ARCH_KB},
01879   {"SA", ARCH_KA},          /* Synonym for KA.  */
01880   {"SB", ARCH_KB},          /* Synonym for KB.  */
01881   {"KC", ARCH_MC},          /* Synonym for MC.  */
01882   {"MC", ARCH_MC},
01883   {"CA", ARCH_CA},
01884   {"JX", ARCH_JX},
01885   {"HX", ARCH_HX},
01886   {NULL, 0}
01887 };
01888 
01889 int
01890 md_parse_option (int c, char *arg)
01891 {
01892   switch (c)
01893     {
01894     case OPTION_LINKRELAX:
01895       linkrelax = 1;
01896       flag_keep_locals = 1;
01897       break;
01898 
01899     case OPTION_NORELAX:
01900       norelax = 1;
01901       break;
01902 
01903     case 'b':
01904       instrument_branches = 1;
01905       break;
01906 
01907     case 'A':
01908       {
01909        const struct tabentry *tp;
01910        char *p = arg;
01911 
01912        for (tp = arch_tab; tp->flag != NULL; tp++)
01913          if (!strcmp (p, tp->flag))
01914            break;
01915 
01916        if (tp->flag == NULL)
01917          {
01918            as_bad (_("invalid architecture %s"), p);
01919            return 0;
01920          }
01921        else
01922          architecture = tp->arch;
01923       }
01924       break;
01925 
01926     default:
01927       return 0;
01928     }
01929 
01930   return 1;
01931 }
01932 
01933 void
01934 md_show_usage (FILE *stream)
01935 {
01936   int i;
01937 
01938   fprintf (stream, _("I960 options:\n"));
01939   for (i = 0; arch_tab[i].flag; i++)
01940     fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
01941   fprintf (stream, _("\n\
01942                      specify variant of 960 architecture\n\
01943 -b                   add code to collect statistics about branches taken\n\
01944 -link-relax          preserve individual alignment directives so linker\n\
01945                      can do relaxing (b.out format only)\n\
01946 -no-relax            don't alter compare-and-branch instructions for\n\
01947                      long displacements\n"));
01948 }
01949 
01950 /* relax_cobr:
01951    Replace cobr instruction in a code fragment with equivalent branch and
01952    compare instructions, so it can reach beyond a 13-bit displacement.
01953    Set up an address fix/relocation for the new branch instruction.  */
01954 
01955 /* This "conditional jump" table maps cobr instructions into
01956    equivalent compare and branch opcodes.  */
01957 
01958 static const
01959 struct
01960 {
01961   long compare;
01962   long branch;
01963 }
01964 
01965 coj[] =
01966 {                           /* COBR OPCODE: */
01967   { CHKBIT, BNO },          /*      0x30 - bbc */
01968   { CMPO, BG },                    /*      0x31 - cmpobg */
01969   { CMPO, BE },                    /*      0x32 - cmpobe */
01970   { CMPO, BGE },            /*      0x33 - cmpobge */
01971   { CMPO, BL },                    /*      0x34 - cmpobl */
01972   { CMPO, BNE },            /*      0x35 - cmpobne */
01973   { CMPO, BLE },            /*      0x36 - cmpoble */
01974   { CHKBIT, BO },           /*      0x37 - bbs */
01975   { CMPI, BNO },            /*      0x38 - cmpibno */
01976   { CMPI, BG },                    /*      0x39 - cmpibg */
01977   { CMPI, BE },                    /*      0x3a - cmpibe */
01978   { CMPI, BGE },            /*      0x3b - cmpibge */
01979   { CMPI, BL },                    /*      0x3c - cmpibl */
01980   { CMPI, BNE },            /*      0x3d - cmpibne */
01981   { CMPI, BLE },            /*      0x3e - cmpible */
01982   { CMPI, BO },                    /*      0x3f - cmpibo */
01983 };
01984 
01985 static void
01986 relax_cobr (fragS *fragP)   /* fragP->fr_opcode is assumed to point to
01987                                the cobr instruction, which comes at the
01988                                end of the code fragment.  */
01989 {
01990   int opcode, src1, src2, m1, s2;
01991   /* Bit fields from cobr instruction.  */
01992   long bp_bits;                    /* Branch prediction bits from cobr instruction.  */
01993   long instr;               /* A single i960 instruction.  */
01994   /* ->instruction to be replaced.  */
01995   char *iP;
01996   fixS *fixP;               /* Relocation that can be done at assembly time.  */
01997 
01998   /* Pick up & parse cobr instruction.  */
01999   iP = fragP->fr_opcode;
02000   instr = md_chars_to_number (iP, 4);
02001   opcode = ((instr >> 24) & 0xff) - 0x30; /* "-0x30" for table index.  */
02002   src1 = (instr >> 19) & 0x1f;
02003   m1 = (instr >> 13) & 1;
02004   s2 = instr & 1;
02005   src2 = (instr >> 14) & 0x1f;
02006   bp_bits = instr & BP_MASK;
02007 
02008   /* Generate and output compare instruction.  */
02009   instr = coj[opcode].compare
02010     | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
02011   md_number_to_chars (iP, instr, 4);
02012 
02013   /* Output branch instruction.  */
02014   md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
02015 
02016   /* Set up address fixup/relocation.  */
02017   fixP = fix_new (fragP,
02018                 iP + 4 - fragP->fr_literal,
02019                 4,
02020                 fragP->fr_symbol,
02021                 fragP->fr_offset,
02022                 1,
02023                 NO_RELOC);
02024 
02025   fixP->fx_bit_fixP = (bit_fixS *) 24;    /* Store size of bit field.  */
02026 
02027   fragP->fr_fix += 4;
02028   frag_wane (fragP);
02029 }
02030 
02031 /* md_convert_frag:
02032 
02033    Called by base assembler after address relaxation is finished:  modify
02034    variable fragments according to how much relaxation was done.
02035 
02036    If the fragment substate is still 1, a 13-bit displacement was enough
02037    to reach the symbol in question.  Set up an address fixup, but otherwise
02038    leave the cobr instruction alone.
02039 
02040    If the fragment substate is 2, a 13-bit displacement was not enough.
02041    Replace the cobr with a two instructions (a compare and a branch).  */
02042 
02043 void
02044 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
02045                segT sec ATTRIBUTE_UNUSED,
02046                fragS *fragP)
02047 {
02048   /* Structure describing needed address fix.  */
02049   fixS *fixP;
02050 
02051   switch (fragP->fr_subtype)
02052     {
02053     case 1:
02054       /* Leave single cobr instruction.  */
02055       fixP = fix_new (fragP,
02056                     fragP->fr_opcode - fragP->fr_literal,
02057                     4,
02058                     fragP->fr_symbol,
02059                     fragP->fr_offset,
02060                     1,
02061                     NO_RELOC);
02062 
02063       fixP->fx_bit_fixP = (bit_fixS *) 13;       /* Size of bit field.  */
02064       break;
02065     case 2:
02066       /* Replace cobr with compare/branch instructions.  */
02067       relax_cobr (fragP);
02068       break;
02069     default:
02070       BAD_CASE (fragP->fr_subtype);
02071       break;
02072     }
02073 }
02074 
02075 /* md_estimate_size_before_relax:  How much does it look like *fragP will grow?
02076 
02077    Called by base assembler just before address relaxation.
02078    Return the amount by which the fragment will grow.
02079 
02080    Any symbol that is now undefined will not become defined; cobr's
02081    based on undefined symbols will have to be replaced with a compare
02082    instruction and a branch instruction, and the code fragment will grow
02083    by 4 bytes.  */
02084 
02085 int
02086 md_estimate_size_before_relax (fragS *fragP, segT segment_type)
02087 {
02088   /* If symbol is undefined in this segment, go to "relaxed" state
02089      (compare and branch instructions instead of cobr) right now.  */
02090   if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
02091     {
02092       relax_cobr (fragP);
02093       return 4;
02094     }
02095 
02096   return md_relax_table[fragP->fr_subtype].rlx_length;
02097 }
02098 
02099 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
02100 
02101 /* md_ri_to_chars:
02102    This routine exists in order to overcome machine byte-order problems
02103    when dealing with bit-field entries in the relocation_info struct.
02104 
02105    But relocation info will be used on the host machine only (only
02106    executable code is actually downloaded to the i80960).  Therefore,
02107    we leave it in host byte order.  */
02108 
02109 static void
02110 md_ri_to_chars (char *where, struct relocation_info *ri)
02111 {
02112   host_number_to_chars (where, ri->r_address, 4);
02113   host_number_to_chars (where + 4, ri->r_index, 3);
02114 #if WORDS_BIGENDIAN
02115   where[7] = (ri->r_pcrel << 7
02116              | ri->r_length << 5
02117              | ri->r_extern << 4
02118              | ri->r_bsr << 3
02119              | ri->r_disp << 2
02120              | ri->r_callj << 1
02121              | ri->nuthin << 0);
02122 #else
02123   where[7] = (ri->r_pcrel << 0
02124              | ri->r_length << 1
02125              | ri->r_extern << 3
02126              | ri->r_bsr << 4
02127              | ri->r_disp << 5
02128              | ri->r_callj << 6
02129              | ri->nuthin << 7);
02130 #endif
02131 }
02132 
02133 #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
02134 
02135 
02136 /* brtab_emit:       generate the fetch-prediction branch table.
02137 
02138    See the comments above the declaration of 'br_cnt' for details on
02139    branch-prediction instrumentation.
02140 
02141    The code emitted here would be functionally equivalent to the following
02142    example assembler source.
02143 
02144                      .data
02145                      .align 2
02146           BR_TAB_NAME:
02147                      .word  0             # link to next table
02148                      .word  3             # length of table
02149                      .word  LBRANCH0      # 1st entry in table proper
02150                      .word  LBRANCH1
02151                      .word  LBRANCH2  */
02152 
02153 void
02154 brtab_emit (void)
02155 {
02156   int i;
02157   char buf[20];
02158   /* Where the binary was output to.  */
02159   char *p;
02160   /* Pointer to description of deferred address fixup.  */
02161   fixS *fixP;
02162 
02163   if (!instrument_branches)
02164     return;
02165 
02166   subseg_set (data_section, 0);    /*      .data */
02167   frag_align (2, 0, 0);            /*      .align 2 */
02168   record_alignment (now_seg, 2);
02169   colon (BR_TAB_NAME);             /* BR_TAB_NAME: */
02170   emit (0);                 /*      .word 0 #link to next table */
02171   emit (br_cnt);            /*      .word n #length of table */
02172 
02173   for (i = 0; i < br_cnt; i++)
02174     {
02175       sprintf (buf, "%s%d", BR_LABEL_BASE, i);
02176       p = emit (0);
02177       fixP = fix_new (frag_now,
02178                     p - frag_now->fr_literal,
02179                     4, symbol_find (buf), 0, 0, NO_RELOC);
02180     }
02181 }
02182 
02183 /* s_leafproc:       process .leafproc pseudo-op
02184 
02185        .leafproc takes two arguments, the second one is optional:
02186               arg[1]: name of 'call' entry point to leaf procedure
02187               arg[2]: name of 'bal' entry point to leaf procedure
02188 
02189        If the two arguments are identical, or if the second one is missing,
02190        the first argument is taken to be the 'bal' entry point.
02191 
02192        If there are 2 distinct arguments, we must make sure that the 'bal'
02193        entry point immediately follows the 'call' entry point in the linked
02194        list of symbols.  */
02195 
02196 static void
02197 s_leafproc (int n_ops,             /* Number of operands.  */
02198            char *args[])    /* args[1]->1st operand, args[2]->2nd operand.  */
02199 {
02200   symbolS *callP;           /* Pointer to leafproc 'call' entry point symbol.  */
02201   symbolS *balP;            /* Pointer to leafproc 'bal' entry point symbol.  */
02202 
02203   if ((n_ops != 1) && (n_ops != 2))
02204     {
02205       as_bad (_("should have 1 or 2 operands"));
02206       return;
02207     }
02208 
02209   /* Find or create symbol for 'call' entry point.  */
02210   callP = symbol_find_or_make (args[1]);
02211 
02212   if (TC_S_IS_CALLNAME (callP))
02213     as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
02214 
02215   /* If that was the only argument, use it as the 'bal' entry point.
02216      Otherwise, mark it as the 'call' entry point and find or create
02217      another symbol for the 'bal' entry point.  */
02218   if ((n_ops == 1) || !strcmp (args[1], args[2]))
02219     {
02220       TC_S_FORCE_TO_BALNAME (callP);
02221     }
02222   else
02223     {
02224       TC_S_FORCE_TO_CALLNAME (callP);
02225 
02226       balP = symbol_find_or_make (args[2]);
02227       if (TC_S_IS_CALLNAME (balP))
02228        as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
02229 
02230       TC_S_FORCE_TO_BALNAME (balP);
02231 
02232 #ifndef OBJ_ELF
02233       tc_set_bal_of_call (callP, balP);
02234 #endif
02235     }
02236 }
02237 
02238 /* s_sysproc: process .sysproc pseudo-op
02239 
02240    .sysproc takes two arguments:
02241      arg[1]: name of entry point to system procedure
02242      arg[2]: 'entry_num' (index) of system procedure in the range
02243      [0,31] inclusive.
02244 
02245    For [ab].out, we store the 'entrynum' in the 'n_other' field of
02246    the symbol.  Since that entry is normally 0, we bias 'entrynum'
02247    by adding 1 to it.  It must be unbiased before it is used.  */
02248 
02249 static void
02250 s_sysproc (int n_ops,              /* Number of operands.  */
02251           char *args[])     /* args[1]->1st operand, args[2]->2nd operand.  */
02252 {
02253   expressionS exp;
02254   symbolS *symP;
02255 
02256   if (n_ops != 2)
02257     {
02258       as_bad (_("should have two operands"));
02259       return;
02260     }
02261 
02262   /* Parse "entry_num" argument and check it for validity.  */
02263   parse_expr (args[2], &exp);
02264   if (exp.X_op != O_constant
02265       || (offs (exp) < 0)
02266       || (offs (exp) > 31))
02267     {
02268       as_bad (_("'entry_num' must be absolute number in [0,31]"));
02269       return;
02270     }
02271 
02272   /* Find/make symbol and stick entry number (biased by +1) into it.  */
02273   symP = symbol_find_or_make (args[1]);
02274 
02275   if (TC_S_IS_SYSPROC (symP))
02276     as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
02277 
02278   TC_S_SET_SYSPROC (symP, offs (exp));    /* Encode entry number.  */
02279   TC_S_FORCE_TO_SYSPROC (symP);
02280 }
02281 
02282 /* parse_po:  parse machine-dependent pseudo-op
02283 
02284    This is a top-level routine for machine-dependent pseudo-ops.  It slurps
02285    up the rest of the input line, breaks out the individual arguments,
02286    and dispatches them to the correct handler.  */
02287 
02288 static void
02289 parse_po (int po_num)       /* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC.  */
02290 {
02291   /* Pointers operands, with no embedded whitespace.
02292      arg[0] unused, arg[1-3]->operands.  */
02293   char *args[4];
02294   int n_ops;                /* Number of operands.  */
02295   char *p;                  /* Pointer to beginning of unparsed argument string.  */
02296   char eol;                 /* Character that indicated end of line.  */
02297 
02298   extern char is_end_of_line[];
02299 
02300   /* Advance input pointer to end of line.  */
02301   p = input_line_pointer;
02302   while (!is_end_of_line[(unsigned char) *input_line_pointer])
02303     input_line_pointer++;
02304 
02305   eol = *input_line_pointer;       /* Save end-of-line char.  */
02306   *input_line_pointer = '\0';      /* Terminate argument list.  */
02307 
02308   /* Parse out operands.  */
02309   n_ops = get_args (p, args);
02310   if (n_ops == -1)
02311     return;
02312 
02313   /* Dispatch to correct handler.  */
02314   switch (po_num)
02315     {
02316     case S_SYSPROC:
02317       s_sysproc (n_ops, args);
02318       break;
02319     case S_LEAFPROC:
02320       s_leafproc (n_ops, args);
02321       break;
02322     default:
02323       BAD_CASE (po_num);
02324       break;
02325     }
02326 
02327   /* Restore eol, so line numbers get updated correctly.  Base
02328      assembler assumes we leave input pointer pointing at char
02329      following the eol.  */
02330   *input_line_pointer++ = eol;
02331 }
02332 
02333 /* reloc_callj:      Relocate a 'callj' instruction
02334 
02335        This is a "non-(GNU)-standard" machine-dependent hook.  The base
02336        assembler calls it when it decides it can relocate an address at
02337        assembly time instead of emitting a relocation directive.
02338 
02339        Check to see if the relocation involves a 'callj' instruction to a:
02340            sysproc:  Replace the default 'call' instruction with a 'calls'
02341            leafproc: Replace the default 'call' instruction with a 'bal'.
02342            other proc:      Do nothing.
02343 
02344        See b.out.h for details on the 'n_other' field in a symbol structure.
02345 
02346    IMPORTANT!:
02347        Assumes the caller has already figured out, in the case of a leafproc,
02348        to use the 'bal' entry point, and has substituted that symbol into the
02349        passed fixup structure.  */
02350 
02351 int
02352 reloc_callj (fixS *fixP)  /* Relocation that can be done at assembly time.  */    
02353 {
02354   /* Points to the binary for the instruction being relocated.  */
02355   char *where;
02356 
02357   if (!fixP->fx_tcbit)
02358     /* This wasn't a callj instruction in the first place.  */
02359     return 0;
02360 
02361   where = fixP->fx_frag->fr_literal + fixP->fx_where;
02362 
02363   if (TC_S_IS_SYSPROC (fixP->fx_addsy))
02364     {
02365       /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
02366          procedure number is (other-1).  */
02367       md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
02368 
02369       /* Nothing else needs to be done for this instruction.  Make
02370          sure 'md_number_to_field()' will perform a no-op.  */
02371       fixP->fx_bit_fixP = (bit_fixS *) 1;
02372     }
02373   else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
02374     {
02375       /* Should not happen: see block comment above.  */
02376       as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
02377     }
02378   else if (TC_S_IS_BALNAME (fixP->fx_addsy))
02379     {
02380       /* Replace 'call' with 'bal'; both instructions have the same
02381          format, so calling code should complete relocation as if
02382          nothing happened here.  */
02383       md_number_to_chars (where, BAL, 4);
02384     }
02385   else if (TC_S_IS_BADPROC (fixP->fx_addsy))
02386     as_bad (_("Looks like a proc, but can't tell what kind.\n"));
02387 
02388   /* Otherwise Symbol is neither a sysproc nor a leafproc.  */
02389   return 0;
02390 }
02391 
02392 /* Handle the MRI .endian pseudo-op.  */
02393 
02394 static void
02395 s_endian (int ignore ATTRIBUTE_UNUSED)
02396 {
02397   char *name;
02398   char c;
02399 
02400   name = input_line_pointer;
02401   c = get_symbol_end ();
02402   if (strcasecmp (name, "little") == 0)
02403     ;
02404   else if (strcasecmp (name, "big") == 0)
02405     as_bad (_("big endian mode is not supported"));
02406   else
02407     as_warn (_("ignoring unrecognized .endian type `%s'"), name);
02408 
02409   *input_line_pointer = c;
02410 
02411   demand_empty_rest_of_line ();
02412 }
02413 
02414 /* We have no need to default values of symbols.  */
02415 
02416 symbolS *
02417 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
02418 {
02419   return 0;
02420 }
02421 
02422 /* Exactly what point is a PC-relative offset relative TO?
02423    On the i960, they're relative to the address of the instruction,
02424    which we have set up as the address of the fixup too.  */
02425 long
02426 md_pcrel_from (fixS *fixP)
02427 {
02428   return fixP->fx_where + fixP->fx_frag->fr_address;
02429 }
02430 
02431 void
02432 md_apply_fix (fixS *fixP,
02433               valueT *valP,
02434               segT seg ATTRIBUTE_UNUSED)
02435 {
02436   long val = *valP;
02437   char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
02438 
02439   if (!fixP->fx_bit_fixP)
02440     {
02441       md_number_to_imm (place, val, fixP->fx_size);
02442     }
02443   else if ((int) (size_t) fixP->fx_bit_fixP == 13
02444           && fixP->fx_addsy != NULL
02445           && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
02446     {
02447       /* This is a COBR instruction.  They have only a
02448         13-bit displacement and are only to be used
02449         for local branches: flag as error, don't generate
02450         relocation.  */
02451       as_bad_where (fixP->fx_file, fixP->fx_line,
02452                   _("can't use COBR format with external label"));
02453       fixP->fx_addsy = NULL;
02454     }
02455   else
02456     md_number_to_field (place, val, fixP->fx_bit_fixP);
02457 
02458   if (fixP->fx_addsy == NULL)
02459     fixP->fx_done = 1;
02460 }
02461 
02462 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
02463 void
02464 tc_bout_fix_to_chars (char *where,
02465                     fixS *fixP,
02466                     relax_addressT segment_address_in_file)
02467 {
02468   static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
02469   struct relocation_info ri;
02470   symbolS *symbolP;
02471 
02472   memset ((char *) &ri, '\0', sizeof (ri));
02473   symbolP = fixP->fx_addsy;
02474   know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
02475   ri.r_bsr = fixP->fx_bsr;  /*SAC LD RELAX HACK */
02476   /* These two 'cuz of NS32K */
02477   ri.r_callj = fixP->fx_tcbit;
02478   if (fixP->fx_bit_fixP)
02479     ri.r_length = 2;
02480   else
02481     ri.r_length = nbytes_r_length[fixP->fx_size];
02482   ri.r_pcrel = fixP->fx_pcrel;
02483   ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
02484 
02485   if (fixP->fx_r_type != NO_RELOC)
02486     {
02487       switch (fixP->fx_r_type)
02488        {
02489        case rs_align:
02490          ri.r_index = -2;
02491          ri.r_pcrel = 1;
02492          ri.r_length = fixP->fx_size - 1;
02493          break;
02494        case rs_org:
02495          ri.r_index = -2;
02496          ri.r_pcrel = 0;
02497          break;
02498        case rs_fill:
02499          ri.r_index = -1;
02500          break;
02501        default:
02502          abort ();
02503        }
02504       ri.r_extern = 0;
02505     }
02506   else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
02507     {
02508       ri.r_extern = 1;
02509       ri.r_index = symbolP->sy_number;
02510     }
02511   else
02512     {
02513       ri.r_extern = 0;
02514       ri.r_index = S_GET_TYPE (symbolP);
02515     }
02516 
02517   /* Output the relocation information in machine-dependent form.  */
02518   md_ri_to_chars (where, &ri);
02519 }
02520 
02521 #endif /* OBJ_AOUT or OBJ_BOUT */
02522 
02523 /* Align an address by rounding it up to the specified boundary.  */
02524 
02525 valueT
02526 md_section_align (segT seg,
02527                 valueT addr)              /* Address to be rounded up.  */
02528 {
02529   int align;
02530 
02531   align = bfd_get_section_alignment (stdoutput, seg);
02532   return (addr + (1 << align) - 1) & (-1 << align);
02533 }
02534 
02535 extern int coff_flags;
02536 
02537 /* For aout or bout, the bal immediately follows the call.
02538 
02539    For coff, we cheat and store a pointer to the bal symbol in the
02540    second aux entry of the call.  */
02541 
02542 #undef OBJ_ABOUT
02543 #ifdef OBJ_AOUT
02544 #define OBJ_ABOUT
02545 #endif
02546 #ifdef OBJ_BOUT
02547 #define OBJ_ABOUT
02548 #endif
02549 
02550 void
02551 tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
02552                   symbolS *balP ATTRIBUTE_UNUSED)
02553 {
02554   know (TC_S_IS_CALLNAME (callP));
02555   know (TC_S_IS_BALNAME (balP));
02556 
02557 #ifdef OBJ_COFF
02558 
02559   callP->sy_tc = balP;
02560   S_SET_NUMBER_AUXILIARY (callP, 2);
02561 
02562 #else /* ! OBJ_COFF */
02563 #ifdef OBJ_ABOUT
02564 
02565   /* If the 'bal' entry doesn't immediately follow the 'call'
02566      symbol, unlink it from the symbol list and re-insert it.  */
02567   if (symbol_next (callP) != balP)
02568     {
02569       symbol_remove (balP, &symbol_rootP, &symbol_lastP);
02570       symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
02571     }                       /* if not in order */
02572 
02573 #else /* ! OBJ_ABOUT */
02574   as_fatal ("Only supported for a.out, b.out, or COFF");
02575 #endif /* ! OBJ_ABOUT */
02576 #endif /* ! OBJ_COFF */
02577 }
02578 
02579 symbolS *
02580 tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
02581 {
02582   symbolS *retval;
02583 
02584   know (TC_S_IS_CALLNAME (callP));
02585 
02586 #ifdef OBJ_COFF
02587   retval = callP->sy_tc;
02588 #else
02589 #ifdef OBJ_ABOUT
02590   retval = symbol_next (callP);
02591 #else
02592   as_fatal ("Only supported for a.out, b.out, or COFF");
02593 #endif /* ! OBJ_ABOUT */
02594 #endif /* ! OBJ_COFF */
02595 
02596   know (TC_S_IS_BALNAME (retval));
02597   return retval;
02598 }
02599 
02600 #ifdef OBJ_COFF
02601 void
02602 tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
02603 {
02604   if (TC_S_IS_CALLNAME (symbolP))
02605     {
02606       symbolS *balP = tc_get_bal_of_call (symbolP);
02607 
02608       symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
02609       if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
02610        S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
02611       else
02612        S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
02613       S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
02614       /* Fix up the bal symbol.  */
02615       S_SET_STORAGE_CLASS (balP, C_LABEL);
02616     }
02617 }
02618 #endif /* OBJ_COFF */
02619 
02620 void
02621 i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
02622 {
02623   if (!linkrelax)
02624     return;
02625 
02626 #ifndef OBJ_BOUT
02627   as_bad (_("option --link-relax is only supported in b.out format"));
02628   linkrelax = 0;
02629   return;
02630 #else
02631 
02632   /* The text section "ends" with another alignment reloc, to which we
02633      aren't adding padding.  */
02634   if (fragp->fr_next == text_last_frag
02635       || fragp->fr_next == data_last_frag)
02636     return;
02637 
02638   /* alignment directive */
02639   fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
02640           (int) fragp->fr_type);
02641 #endif /* OBJ_BOUT */
02642 }
02643 
02644 int
02645 i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
02646 {
02647   if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
02648     {
02649       /* Relocation should be done via the associated 'bal'
02650          entry point symbol.  */
02651       if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
02652        {
02653          as_bad_where (fixP->fx_file, fixP->fx_line,
02654                      _("No 'bal' entry point for leafproc %s"),
02655                      S_GET_NAME (fixP->fx_addsy));
02656          return 0;
02657        }
02658       fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
02659     }
02660 
02661   return 1;
02662 }
02663 
02664 /* From cgen.c:  */
02665 
02666 static short
02667 tc_bfd_fix2rtype (fixS *fixP)
02668 {
02669   if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
02670     return BFD_RELOC_32;
02671 
02672   if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
02673     return BFD_RELOC_24_PCREL;
02674 
02675   abort ();
02676   return 0;
02677 }
02678 
02679 /* Translate internal representation of relocation info to BFD target
02680    format.
02681 
02682    FIXME: To what extent can we get all relevant targets to use this?  */
02683 
02684 arelent *
02685 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
02686 {
02687   arelent * reloc;
02688 
02689   reloc = xmalloc (sizeof (arelent));
02690 
02691   /* HACK: Is this right?  */
02692   fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
02693 
02694   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
02695   if (reloc->howto == NULL)
02696     {
02697       as_bad_where (fixP->fx_file, fixP->fx_line,
02698                   "internal error: can't export reloc type %d (`%s')",
02699                   fixP->fx_r_type,
02700                   bfd_get_reloc_code_name (fixP->fx_r_type));
02701       return NULL;
02702     }
02703 
02704   assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
02705 
02706   reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
02707   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
02708   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
02709   reloc->addend = fixP->fx_addnumber;
02710 
02711   return reloc;
02712 }
02713 
02714 /* end from cgen.c */
02715 
02716 const pseudo_typeS md_pseudo_table[] =
02717 {
02718   {"bss", s_lcomm, 1},
02719   {"endian", s_endian, 0},
02720   {"extended", float_cons, 't'},
02721   {"leafproc", parse_po, S_LEAFPROC},
02722   {"sysproc", parse_po, S_SYSPROC},
02723 
02724   {"word", cons, 4},
02725   {"quad", cons, 16},
02726 
02727   {0, 0, 0}
02728 };