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cell-binutils  2.17cvs20070401
tc-i386.c
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00001 /* tc-i386.c -- Assemble code for the Intel 80386
00002    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
00003    2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
00004    Free Software Foundation, Inc.
00005 
00006    This file is part of GAS, the GNU Assembler.
00007 
00008    GAS is free software; you can redistribute it and/or modify
00009    it under the terms of the GNU General Public License as published by
00010    the Free Software Foundation; either version 2, or (at your option)
00011    any later version.
00012 
00013    GAS is distributed in the hope that it will be useful,
00014    but WITHOUT ANY WARRANTY; without even the implied warranty of
00015    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016    GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with GAS; see the file COPYING.  If not, write to the Free
00020    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00021    02110-1301, USA.  */
00022 
00023 /* Intel 80386 machine specific gas.
00024    Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
00025    x86_64 support by Jan Hubicka (jh@suse.cz)
00026    VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
00027    Bugs & suggestions are completely welcome.  This is free software.
00028    Please help us make it better.  */
00029 
00030 #include "as.h"
00031 #include "safe-ctype.h"
00032 #include "subsegs.h"
00033 #include "dwarf2dbg.h"
00034 #include "dw2gencfi.h"
00035 #include "elf/x86-64.h"
00036 
00037 #ifndef REGISTER_WARNINGS
00038 #define REGISTER_WARNINGS 1
00039 #endif
00040 
00041 #ifndef INFER_ADDR_PREFIX
00042 #define INFER_ADDR_PREFIX 1
00043 #endif
00044 
00045 #ifndef SCALE1_WHEN_NO_INDEX
00046 /* Specifying a scale factor besides 1 when there is no index is
00047    futile.  eg. `mov (%ebx,2),%al' does exactly the same as
00048    `mov (%ebx),%al'.  To slavishly follow what the programmer
00049    specified, set SCALE1_WHEN_NO_INDEX to 0.  */
00050 #define SCALE1_WHEN_NO_INDEX 1
00051 #endif
00052 
00053 #ifndef DEFAULT_ARCH
00054 #define DEFAULT_ARCH "i386"
00055 #endif
00056 
00057 #ifndef INLINE
00058 #if __GNUC__ >= 2
00059 #define INLINE __inline__
00060 #else
00061 #define INLINE
00062 #endif
00063 #endif
00064 
00065 static void set_code_flag (int);
00066 static void set_16bit_gcc_code_flag (int);
00067 static void set_intel_syntax (int);
00068 static void set_cpu_arch (int);
00069 #ifdef TE_PE
00070 static void pe_directive_secrel (int);
00071 #endif
00072 static void signed_cons (int);
00073 static char *output_invalid (int c);
00074 static int i386_operand (char *);
00075 static int i386_intel_operand (char *, int);
00076 static const reg_entry *parse_register (char *, char **);
00077 static char *parse_insn (char *, char *);
00078 static char *parse_operands (char *, const char *);
00079 static void swap_operands (void);
00080 static void swap_2_operands (int, int);
00081 static void optimize_imm (void);
00082 static void optimize_disp (void);
00083 static int match_template (void);
00084 static int check_string (void);
00085 static int process_suffix (void);
00086 static int check_byte_reg (void);
00087 static int check_long_reg (void);
00088 static int check_qword_reg (void);
00089 static int check_word_reg (void);
00090 static int finalize_imm (void);
00091 static int process_operands (void);
00092 static const seg_entry *build_modrm_byte (void);
00093 static void output_insn (void);
00094 static void output_imm (fragS *, offsetT);
00095 static void output_disp (fragS *, offsetT);
00096 #ifndef I386COFF
00097 static void s_bss (int);
00098 #endif
00099 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
00100 static void handle_large_common (int small ATTRIBUTE_UNUSED);
00101 #endif
00102 
00103 static const char *default_arch = DEFAULT_ARCH;
00104 
00105 /* 'md_assemble ()' gathers together information and puts it into a
00106    i386_insn.  */
00107 
00108 union i386_op
00109   {
00110     expressionS *disps;
00111     expressionS *imms;
00112     const reg_entry *regs;
00113   };
00114 
00115 struct _i386_insn
00116   {
00117     /* TM holds the template for the insn were currently assembling.  */
00118     template tm;
00119 
00120     /* SUFFIX holds the instruction mnemonic suffix if given.
00121        (e.g. 'l' for 'movl')  */
00122     char suffix;
00123 
00124     /* OPERANDS gives the number of given operands.  */
00125     unsigned int operands;
00126 
00127     /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
00128        of given register, displacement, memory operands and immediate
00129        operands.  */
00130     unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
00131 
00132     /* TYPES [i] is the type (see above #defines) which tells us how to
00133        use OP[i] for the corresponding operand.  */
00134     unsigned int types[MAX_OPERANDS];
00135 
00136     /* Displacement expression, immediate expression, or register for each
00137        operand.  */
00138     union i386_op op[MAX_OPERANDS];
00139 
00140     /* Flags for operands.  */
00141     unsigned int flags[MAX_OPERANDS];
00142 #define Operand_PCrel 1
00143 
00144     /* Relocation type for operand */
00145     enum bfd_reloc_code_real reloc[MAX_OPERANDS];
00146 
00147     /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
00148        the base index byte below.  */
00149     const reg_entry *base_reg;
00150     const reg_entry *index_reg;
00151     unsigned int log2_scale_factor;
00152 
00153     /* SEG gives the seg_entries of this insn.  They are zero unless
00154        explicit segment overrides are given.  */
00155     const seg_entry *seg[2];
00156 
00157     /* PREFIX holds all the given prefix opcodes (usually null).
00158        PREFIXES is the number of prefix opcodes.  */
00159     unsigned int prefixes;
00160     unsigned char prefix[MAX_PREFIXES];
00161 
00162     /* RM and SIB are the modrm byte and the sib byte where the
00163        addressing modes of this insn are encoded.  */
00164 
00165     modrm_byte rm;
00166     rex_byte rex;
00167     sib_byte sib;
00168   };
00169 
00170 typedef struct _i386_insn i386_insn;
00171 
00172 /* List of chars besides those in app.c:symbol_chars that can start an
00173    operand.  Used to prevent the scrubber eating vital white-space.  */
00174 const char extra_symbol_chars[] = "*%-(["
00175 #ifdef LEX_AT
00176        "@"
00177 #endif
00178 #ifdef LEX_QM
00179        "?"
00180 #endif
00181        ;
00182 
00183 #if (defined (TE_I386AIX)                        \
00184      || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
00185         && !defined (TE_GNU)                            \
00186         && !defined (TE_LINUX)                          \
00187         && !defined (TE_NETWARE)                 \
00188         && !defined (TE_FreeBSD)                 \
00189         && !defined (TE_NetBSD)))
00190 /* This array holds the chars that always start a comment.  If the
00191    pre-processor is disabled, these aren't very useful.  The option
00192    --divide will remove '/' from this list.  */
00193 const char *i386_comment_chars = "#/";
00194 #define SVR4_COMMENT_CHARS 1
00195 #define PREFIX_SEPARATOR '\\'
00196 
00197 #else
00198 const char *i386_comment_chars = "#";
00199 #define PREFIX_SEPARATOR '/'
00200 #endif
00201 
00202 /* This array holds the chars that only start a comment at the beginning of
00203    a line.  If the line seems to have the form '# 123 filename'
00204    .line and .file directives will appear in the pre-processed output.
00205    Note that input_file.c hand checks for '#' at the beginning of the
00206    first line of the input file.  This is because the compiler outputs
00207    #NO_APP at the beginning of its output.
00208    Also note that comments started like this one will always work if
00209    '/' isn't otherwise defined.  */
00210 const char line_comment_chars[] = "#/";
00211 
00212 const char line_separator_chars[] = ";";
00213 
00214 /* Chars that can be used to separate mant from exp in floating point
00215    nums.  */
00216 const char EXP_CHARS[] = "eE";
00217 
00218 /* Chars that mean this number is a floating point constant
00219    As in 0f12.456
00220    or    0d1.2345e12.  */
00221 const char FLT_CHARS[] = "fFdDxX";
00222 
00223 /* Tables for lexical analysis.  */
00224 static char mnemonic_chars[256];
00225 static char register_chars[256];
00226 static char operand_chars[256];
00227 static char identifier_chars[256];
00228 static char digit_chars[256];
00229 
00230 /* Lexical macros.  */
00231 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
00232 #define is_operand_char(x) (operand_chars[(unsigned char) x])
00233 #define is_register_char(x) (register_chars[(unsigned char) x])
00234 #define is_space_char(x) ((x) == ' ')
00235 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
00236 #define is_digit_char(x) (digit_chars[(unsigned char) x])
00237 
00238 /* All non-digit non-letter characters that may occur in an operand.  */
00239 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
00240 
00241 /* md_assemble() always leaves the strings it's passed unaltered.  To
00242    effect this we maintain a stack of saved characters that we've smashed
00243    with '\0's (indicating end of strings for various sub-fields of the
00244    assembler instruction).  */
00245 static char save_stack[32];
00246 static char *save_stack_p;
00247 #define END_STRING_AND_SAVE(s) \
00248        do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
00249 #define RESTORE_END_STRING(s) \
00250        do { *(s) = *--save_stack_p; } while (0)
00251 
00252 /* The instruction we're assembling.  */
00253 static i386_insn i;
00254 
00255 /* Possible templates for current insn.  */
00256 static const templates *current_templates;
00257 
00258 /* Per instruction expressionS buffers: max displacements & immediates.  */
00259 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
00260 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
00261 
00262 /* Current operand we are working on.  */
00263 static int this_operand;
00264 
00265 /* We support four different modes.  FLAG_CODE variable is used to distinguish
00266    these.  */
00267 
00268 enum flag_code {
00269        CODE_32BIT,
00270        CODE_16BIT,
00271        CODE_64BIT };
00272 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
00273 
00274 static enum flag_code flag_code;
00275 static unsigned int object_64bit;
00276 static int use_rela_relocations = 0;
00277 
00278 /* The names used to print error messages.  */
00279 static const char *flag_code_names[] =
00280   {
00281     "32",
00282     "16",
00283     "64"
00284   };
00285 
00286 /* 1 for intel syntax,
00287    0 if att syntax.  */
00288 static int intel_syntax = 0;
00289 
00290 /* 1 if register prefix % not required.  */
00291 static int allow_naked_reg = 0;
00292 
00293 /* Register prefix used for error message.  */
00294 static const char *register_prefix = "%";
00295 
00296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
00297    leave, push, and pop instructions so that gcc has the same stack
00298    frame as in 32 bit mode.  */
00299 static char stackop_size = '\0';
00300 
00301 /* Non-zero to optimize code alignment.  */
00302 int optimize_align_code = 1;
00303 
00304 /* Non-zero to quieten some warnings.  */
00305 static int quiet_warnings = 0;
00306 
00307 /* CPU name.  */
00308 static const char *cpu_arch_name = NULL;
00309 static const char *cpu_sub_arch_name = NULL;
00310 
00311 /* CPU feature flags.  */
00312 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
00313 
00314 /* If we have selected a cpu we are generating instructions for.  */
00315 static int cpu_arch_tune_set = 0;
00316 
00317 /* Cpu we are generating instructions for.  */
00318 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
00319 
00320 /* CPU feature flags of cpu we are generating instructions for.  */
00321 static unsigned int cpu_arch_tune_flags = 0;
00322 
00323 /* CPU instruction set architecture used.  */
00324 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
00325 
00326 /* CPU feature flags of instruction set architecture used.  */
00327 static unsigned int cpu_arch_isa_flags = 0;
00328 
00329 /* If set, conditional jumps are not automatically promoted to handle
00330    larger than a byte offset.  */
00331 static unsigned int no_cond_jump_promotion = 0;
00332 
00333 /* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
00334 static symbolS *GOT_symbol;
00335 
00336 /* The dwarf2 return column, adjusted for 32 or 64 bit.  */
00337 unsigned int x86_dwarf2_return_column;
00338 
00339 /* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
00340 int x86_cie_data_alignment;
00341 
00342 /* Interface to relax_segment.
00343    There are 3 major relax states for 386 jump insns because the
00344    different types of jumps add different sizes to frags when we're
00345    figuring out what sort of jump to choose to reach a given label.  */
00346 
00347 /* Types.  */
00348 #define UNCOND_JUMP 0
00349 #define COND_JUMP 1
00350 #define COND_JUMP86 2
00351 
00352 /* Sizes.  */
00353 #define CODE16       1
00354 #define SMALL 0
00355 #define SMALL16 (SMALL | CODE16)
00356 #define BIG   2
00357 #define BIG16 (BIG | CODE16)
00358 
00359 #ifndef INLINE
00360 #ifdef __GNUC__
00361 #define INLINE __inline__
00362 #else
00363 #define INLINE
00364 #endif
00365 #endif
00366 
00367 #define ENCODE_RELAX_STATE(type, size) \
00368   ((relax_substateT) (((type) << 2) | (size)))
00369 #define TYPE_FROM_RELAX_STATE(s) \
00370   ((s) >> 2)
00371 #define DISP_SIZE_FROM_RELAX_STATE(s) \
00372     ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
00373 
00374 /* This table is used by relax_frag to promote short jumps to long
00375    ones where necessary.  SMALL (short) jumps may be promoted to BIG
00376    (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We
00377    don't allow a short jump in a 32 bit code segment to be promoted to
00378    a 16 bit offset jump because it's slower (requires data size
00379    prefix), and doesn't work, unless the destination is in the bottom
00380    64k of the code segment (The top 16 bits of eip are zeroed).  */
00381 
00382 const relax_typeS md_relax_table[] =
00383 {
00384   /* The fields are:
00385      1) most positive reach of this state,
00386      2) most negative reach of this state,
00387      3) how many bytes this mode will have in the variable part of the frag
00388      4) which index into the table to try if we can't fit into this one.  */
00389 
00390   /* UNCOND_JUMP states.  */
00391   {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
00392   {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
00393   /* dword jmp adds 4 bytes to frag:
00394      0 extra opcode bytes, 4 displacement bytes.  */
00395   {0, 0, 4, 0},
00396   /* word jmp adds 2 byte2 to frag:
00397      0 extra opcode bytes, 2 displacement bytes.  */
00398   {0, 0, 2, 0},
00399 
00400   /* COND_JUMP states.  */
00401   {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
00402   {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
00403   /* dword conditionals adds 5 bytes to frag:
00404      1 extra opcode byte, 4 displacement bytes.  */
00405   {0, 0, 5, 0},
00406   /* word conditionals add 3 bytes to frag:
00407      1 extra opcode byte, 2 displacement bytes.  */
00408   {0, 0, 3, 0},
00409 
00410   /* COND_JUMP86 states.  */
00411   {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
00412   {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
00413   /* dword conditionals adds 5 bytes to frag:
00414      1 extra opcode byte, 4 displacement bytes.  */
00415   {0, 0, 5, 0},
00416   /* word conditionals add 4 bytes to frag:
00417      1 displacement byte and a 3 byte long branch insn.  */
00418   {0, 0, 4, 0}
00419 };
00420 
00421 static const arch_entry cpu_arch[] =
00422 {
00423   {"generic32", PROCESSOR_GENERIC32,
00424    Cpu186|Cpu286|Cpu386},
00425   {"generic64", PROCESSOR_GENERIC64,
00426    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00427    |CpuMMX2|CpuSSE|CpuSSE2},
00428   {"i8086", PROCESSOR_UNKNOWN,
00429    0},
00430   {"i186", PROCESSOR_UNKNOWN,
00431    Cpu186},
00432   {"i286", PROCESSOR_UNKNOWN,
00433    Cpu186|Cpu286},
00434   {"i386", PROCESSOR_GENERIC32,
00435    Cpu186|Cpu286|Cpu386},
00436   {"i486", PROCESSOR_I486,
00437    Cpu186|Cpu286|Cpu386|Cpu486},
00438   {"i586", PROCESSOR_PENTIUM,
00439    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
00440   {"i686", PROCESSOR_PENTIUMPRO,
00441    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
00442   {"pentium", PROCESSOR_PENTIUM,
00443    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
00444   {"pentiumpro",PROCESSOR_PENTIUMPRO,
00445    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
00446   {"pentiumii",      PROCESSOR_PENTIUMPRO,
00447    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
00448   {"pentiumiii",PROCESSOR_PENTIUMPRO,
00449    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
00450   {"pentium4", PROCESSOR_PENTIUM4,
00451    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00452    |CpuMMX2|CpuSSE|CpuSSE2},
00453   {"prescott", PROCESSOR_NOCONA,
00454    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00455    |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
00456   {"nocona", PROCESSOR_NOCONA,
00457    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00458    |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
00459   {"yonah", PROCESSOR_CORE,
00460    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00461    |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
00462   {"core", PROCESSOR_CORE,
00463    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00464    |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
00465   {"merom", PROCESSOR_CORE2,
00466    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00467    |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
00468   {"core2", PROCESSOR_CORE2,
00469    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
00470    |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
00471   {"k6", PROCESSOR_K6,
00472    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
00473   {"k6_2", PROCESSOR_K6,
00474    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
00475   {"athlon", PROCESSOR_ATHLON,
00476    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
00477    |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
00478   {"sledgehammer", PROCESSOR_K8,
00479    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
00480    |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
00481   {"opteron", PROCESSOR_K8,
00482    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
00483    |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
00484   {"k8", PROCESSOR_K8,
00485    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
00486    |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
00487   {"amdfam10", PROCESSOR_AMDFAM10,
00488    Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
00489    |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
00490    |CpuABM},
00491   {".mmx", PROCESSOR_UNKNOWN,
00492    CpuMMX},
00493   {".sse", PROCESSOR_UNKNOWN,
00494    CpuMMX|CpuMMX2|CpuSSE},
00495   {".sse2", PROCESSOR_UNKNOWN,
00496    CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
00497   {".sse3", PROCESSOR_UNKNOWN,
00498    CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
00499   {".ssse3", PROCESSOR_UNKNOWN,
00500    CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
00501   {".3dnow", PROCESSOR_UNKNOWN,
00502    CpuMMX|Cpu3dnow},
00503   {".3dnowa", PROCESSOR_UNKNOWN,
00504    CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
00505   {".padlock", PROCESSOR_UNKNOWN,
00506    CpuPadLock},
00507   {".pacifica", PROCESSOR_UNKNOWN,
00508    CpuSVME},
00509   {".svme", PROCESSOR_UNKNOWN,
00510    CpuSVME},
00511   {".sse4a", PROCESSOR_UNKNOWN,
00512    CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
00513   {".abm", PROCESSOR_UNKNOWN,
00514    CpuABM}
00515 };
00516 
00517 const pseudo_typeS md_pseudo_table[] =
00518 {
00519 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
00520   {"align", s_align_bytes, 0},
00521 #else
00522   {"align", s_align_ptwo, 0},
00523 #endif
00524   {"arch", set_cpu_arch, 0},
00525 #ifndef I386COFF
00526   {"bss", s_bss, 0},
00527 #endif
00528   {"ffloat", float_cons, 'f'},
00529   {"dfloat", float_cons, 'd'},
00530   {"tfloat", float_cons, 'x'},
00531   {"value", cons, 2},
00532   {"slong", signed_cons, 4},
00533   {"noopt", s_ignore, 0},
00534   {"optim", s_ignore, 0},
00535   {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
00536   {"code16", set_code_flag, CODE_16BIT},
00537   {"code32", set_code_flag, CODE_32BIT},
00538   {"code64", set_code_flag, CODE_64BIT},
00539   {"intel_syntax", set_intel_syntax, 1},
00540   {"att_syntax", set_intel_syntax, 0},
00541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
00542   {"largecomm", handle_large_common, 0},
00543 #else
00544   {"file", (void (*) (int)) dwarf2_directive_file, 0},
00545   {"loc", dwarf2_directive_loc, 0},
00546   {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
00547 #endif
00548 #ifdef TE_PE
00549   {"secrel32", pe_directive_secrel, 0},
00550 #endif
00551   {0, 0, 0}
00552 };
00553 
00554 /* For interface with expression ().  */
00555 extern char *input_line_pointer;
00556 
00557 /* Hash table for instruction mnemonic lookup.  */
00558 static struct hash_control *op_hash;
00559 
00560 /* Hash table for register lookup.  */
00561 static struct hash_control *reg_hash;
00562 
00563 void
00564 i386_align_code (fragS *fragP, int count)
00565 {
00566   /* Various efficient no-op patterns for aligning code labels.
00567      Note: Don't try to assemble the instructions in the comments.
00568      0L and 0w are not legal.  */
00569   static const char f32_1[] =
00570     {0x90};                               /* nop               */
00571   static const char f32_2[] =
00572     {0x66,0x90};                          /* xchg %ax,%ax */
00573   static const char f32_3[] =
00574     {0x8d,0x76,0x00};                            /* leal 0(%esi),%esi */
00575   static const char f32_4[] =
00576     {0x8d,0x74,0x26,0x00};                /* leal 0(%esi,1),%esi      */
00577   static const char f32_5[] =
00578     {0x90,                                /* nop               */
00579      0x8d,0x74,0x26,0x00};                /* leal 0(%esi,1),%esi      */
00580   static const char f32_6[] =
00581     {0x8d,0xb6,0x00,0x00,0x00,0x00};             /* leal 0L(%esi),%esi       */
00582   static const char f32_7[] =
00583     {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
00584   static const char f32_8[] =
00585     {0x90,                                /* nop               */
00586      0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
00587   static const char f32_9[] =
00588     {0x89,0xf6,                                  /* movl %esi,%esi    */
00589      0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
00590   static const char f32_10[] =
00591     {0x8d,0x76,0x00,                      /* leal 0(%esi),%esi */
00592      0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
00593   static const char f32_11[] =
00594     {0x8d,0x74,0x26,0x00,                 /* leal 0(%esi,1),%esi      */
00595      0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
00596   static const char f32_12[] =
00597     {0x8d,0xb6,0x00,0x00,0x00,0x00,              /* leal 0L(%esi),%esi       */
00598      0x8d,0xbf,0x00,0x00,0x00,0x00};             /* leal 0L(%edi),%edi       */
00599   static const char f32_13[] =
00600     {0x8d,0xb6,0x00,0x00,0x00,0x00,              /* leal 0L(%esi),%esi       */
00601      0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
00602   static const char f32_14[] =
00603     {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,  /* leal 0L(%esi,1),%esi */
00604      0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
00605   static const char f32_15[] =
00606     {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90,  /* jmp .+15; lotsa nops     */
00607      0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
00608   static const char f16_3[] =
00609     {0x8d,0x74,0x00};                            /* lea 0(%esi),%esi  */
00610   static const char f16_4[] =
00611     {0x8d,0xb4,0x00,0x00};                /* lea 0w(%si),%si   */
00612   static const char f16_5[] =
00613     {0x90,                                /* nop               */
00614      0x8d,0xb4,0x00,0x00};                /* lea 0w(%si),%si   */
00615   static const char f16_6[] =
00616     {0x89,0xf6,                                  /* mov %si,%si              */
00617      0x8d,0xbd,0x00,0x00};                /* lea 0w(%di),%di   */
00618   static const char f16_7[] =
00619     {0x8d,0x74,0x00,                      /* lea 0(%si),%si    */
00620      0x8d,0xbd,0x00,0x00};                /* lea 0w(%di),%di   */
00621   static const char f16_8[] =
00622     {0x8d,0xb4,0x00,0x00,                 /* lea 0w(%si),%si   */
00623      0x8d,0xbd,0x00,0x00};                /* lea 0w(%di),%di   */
00624   static const char *const f32_patt[] = {
00625     f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
00626     f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
00627   };
00628   static const char *const f16_patt[] = {
00629     f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
00630     f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
00631   };
00632   /* nopl (%[re]ax) */
00633   static const char alt_3[] =
00634     {0x0f,0x1f,0x00};
00635   /* nopl 0(%[re]ax) */
00636   static const char alt_4[] =
00637     {0x0f,0x1f,0x40,0x00};
00638   /* nopl 0(%[re]ax,%[re]ax,1) */
00639   static const char alt_5[] =
00640     {0x0f,0x1f,0x44,0x00,0x00};
00641   /* nopw 0(%[re]ax,%[re]ax,1) */
00642   static const char alt_6[] =
00643     {0x66,0x0f,0x1f,0x44,0x00,0x00};
00644   /* nopl 0L(%[re]ax) */
00645   static const char alt_7[] =
00646     {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
00647   /* nopl 0L(%[re]ax,%[re]ax,1) */
00648   static const char alt_8[] =
00649     {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00650   /* nopw 0L(%[re]ax,%[re]ax,1) */
00651   static const char alt_9[] =
00652     {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00653   /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
00654   static const char alt_10[] =
00655     {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00656   /* data16
00657      nopw %cs:0L(%[re]ax,%[re]ax,1) */
00658   static const char alt_long_11[] =
00659     {0x66,
00660      0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00661   /* data16
00662      data16
00663      nopw %cs:0L(%[re]ax,%[re]ax,1) */
00664   static const char alt_long_12[] =
00665     {0x66,
00666      0x66,
00667      0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00668   /* data16
00669      data16
00670      data16
00671      nopw %cs:0L(%[re]ax,%[re]ax,1) */
00672   static const char alt_long_13[] =
00673     {0x66,
00674      0x66,
00675      0x66,
00676      0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00677   /* data16
00678      data16
00679      data16
00680      data16
00681      nopw %cs:0L(%[re]ax,%[re]ax,1) */
00682   static const char alt_long_14[] =
00683     {0x66,
00684      0x66,
00685      0x66,
00686      0x66,
00687      0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00688   /* data16
00689      data16
00690      data16
00691      data16
00692      data16
00693      nopw %cs:0L(%[re]ax,%[re]ax,1) */
00694   static const char alt_long_15[] =
00695     {0x66,
00696      0x66,
00697      0x66,
00698      0x66,
00699      0x66,
00700      0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00701   /* nopl 0(%[re]ax,%[re]ax,1)
00702      nopw 0(%[re]ax,%[re]ax,1) */
00703   static const char alt_short_11[] =
00704     {0x0f,0x1f,0x44,0x00,0x00,
00705      0x66,0x0f,0x1f,0x44,0x00,0x00};
00706   /* nopw 0(%[re]ax,%[re]ax,1)
00707      nopw 0(%[re]ax,%[re]ax,1) */
00708   static const char alt_short_12[] =
00709     {0x66,0x0f,0x1f,0x44,0x00,0x00,
00710      0x66,0x0f,0x1f,0x44,0x00,0x00};
00711   /* nopw 0(%[re]ax,%[re]ax,1)
00712      nopl 0L(%[re]ax) */
00713   static const char alt_short_13[] =
00714     {0x66,0x0f,0x1f,0x44,0x00,0x00,
00715      0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
00716   /* nopl 0L(%[re]ax)
00717      nopl 0L(%[re]ax) */
00718   static const char alt_short_14[] =
00719     {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
00720      0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
00721   /* nopl 0L(%[re]ax)
00722      nopl 0L(%[re]ax,%[re]ax,1) */
00723   static const char alt_short_15[] =
00724     {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
00725      0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
00726   static const char *const alt_short_patt[] = {
00727     f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
00728     alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
00729     alt_short_14, alt_short_15
00730   };
00731   static const char *const alt_long_patt[] = {
00732     f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
00733     alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
00734     alt_long_14, alt_long_15
00735   };
00736 
00737   if (count <= 0 || count > 15)
00738     return;
00739 
00740   /* We need to decide which NOP sequence to use for 32bit and
00741      64bit. When -mtune= is used:
00742 
00743      1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
00744      f32_patt will be used.
00745      2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
00746      0x66 prefix will be used.
00747      3. For PROCESSOR_CORE2, alt_long_patt will be used.
00748      4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
00749      PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
00750      and PROCESSOR_GENERIC64, alt_short_patt will be used.
00751 
00752      When -mtune= isn't used, alt_short_patt will be used if
00753      cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
00754 
00755      When -march= or .arch is used, we can't use anything beyond
00756      cpu_arch_isa_flags.   */
00757 
00758   if (flag_code == CODE_16BIT)
00759     {
00760       memcpy (fragP->fr_literal + fragP->fr_fix,
00761              f16_patt[count - 1], count);
00762       if (count > 8)
00763        /* Adjust jump offset.  */
00764        fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
00765     }
00766   else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
00767     {
00768       int i;
00769       int nnops = (count + 3) / 4;
00770       int len = count / nnops;
00771       int remains = count - nnops * len;
00772       int pos = 0;
00773 
00774       /* The recommended way to pad 64bit code is to use NOPs preceded
00775         by maximally four 0x66 prefixes.  Balance the size of nops.  */
00776       for (i = 0; i < remains; i++)
00777        {
00778          memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
00779          fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
00780          pos += len + 1;
00781        }
00782       for (; i < nnops; i++)
00783        {
00784          memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
00785          fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
00786          pos += len;
00787        }
00788     }
00789   else
00790     {
00791       const char *const *patt = NULL;
00792 
00793       if (cpu_arch_isa == PROCESSOR_UNKNOWN)
00794        {
00795          /* PROCESSOR_UNKNOWN means that all ISAs may be used.  */
00796          switch (cpu_arch_tune)
00797            {
00798            case PROCESSOR_UNKNOWN:
00799              /* We use cpu_arch_isa_flags to check if we SHOULD
00800                optimize for Cpu686.  */
00801              if ((cpu_arch_isa_flags & Cpu686) != 0)
00802               patt = alt_short_patt;
00803              else
00804               patt = f32_patt;
00805              break;
00806            case PROCESSOR_CORE2:
00807              patt = alt_long_patt;
00808              break;
00809            case PROCESSOR_PENTIUMPRO:
00810            case PROCESSOR_PENTIUM4:
00811            case PROCESSOR_NOCONA:
00812            case PROCESSOR_CORE:
00813            case PROCESSOR_K6:
00814            case PROCESSOR_ATHLON:
00815            case PROCESSOR_K8:
00816            case PROCESSOR_GENERIC64:
00817            case PROCESSOR_AMDFAM10:
00818              patt = alt_short_patt;
00819              break;
00820            case PROCESSOR_I486:
00821            case PROCESSOR_PENTIUM:
00822            case PROCESSOR_GENERIC32:
00823              patt = f32_patt;
00824              break;
00825            }
00826        }
00827       else
00828        {
00829          switch (cpu_arch_tune)
00830            {
00831            case PROCESSOR_UNKNOWN:
00832              /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
00833                PROCESSOR_UNKNOWN.  */
00834              abort ();
00835              break;
00836 
00837            case PROCESSOR_I486:
00838            case PROCESSOR_PENTIUM:
00839            case PROCESSOR_PENTIUMPRO:
00840            case PROCESSOR_PENTIUM4:
00841            case PROCESSOR_NOCONA:
00842            case PROCESSOR_CORE:
00843            case PROCESSOR_K6:
00844            case PROCESSOR_ATHLON:
00845            case PROCESSOR_K8:
00846            case PROCESSOR_AMDFAM10:
00847            case PROCESSOR_GENERIC32:
00848              /* We use cpu_arch_isa_flags to check if we CAN optimize
00849                for Cpu686.  */
00850              if ((cpu_arch_isa_flags & Cpu686) != 0)
00851               patt = alt_short_patt;
00852              else
00853               patt = f32_patt;
00854              break;
00855            case PROCESSOR_CORE2:
00856              if ((cpu_arch_isa_flags & Cpu686) != 0)
00857               patt = alt_long_patt;
00858              else
00859               patt = f32_patt;
00860              break;
00861            case PROCESSOR_GENERIC64:
00862              patt = alt_short_patt;
00863              break;
00864            }
00865        }
00866 
00867       memcpy (fragP->fr_literal + fragP->fr_fix,
00868              patt[count - 1], count);
00869     }
00870   fragP->fr_var = count;
00871 }
00872 
00873 static INLINE unsigned int
00874 mode_from_disp_size (unsigned int t)
00875 {
00876   return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
00877 }
00878 
00879 static INLINE int
00880 fits_in_signed_byte (offsetT num)
00881 {
00882   return (num >= -128) && (num <= 127);
00883 }
00884 
00885 static INLINE int
00886 fits_in_unsigned_byte (offsetT num)
00887 {
00888   return (num & 0xff) == num;
00889 }
00890 
00891 static INLINE int
00892 fits_in_unsigned_word (offsetT num)
00893 {
00894   return (num & 0xffff) == num;
00895 }
00896 
00897 static INLINE int
00898 fits_in_signed_word (offsetT num)
00899 {
00900   return (-32768 <= num) && (num <= 32767);
00901 }
00902 
00903 static INLINE int
00904 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
00905 {
00906 #ifndef BFD64
00907   return 1;
00908 #else
00909   return (!(((offsetT) -1 << 31) & num)
00910          || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
00911 #endif
00912 }                           /* fits_in_signed_long() */
00913 
00914 static INLINE int
00915 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
00916 {
00917 #ifndef BFD64
00918   return 1;
00919 #else
00920   return (num & (((offsetT) 2 << 31) - 1)) == num;
00921 #endif
00922 }                           /* fits_in_unsigned_long() */
00923 
00924 static unsigned int
00925 smallest_imm_type (offsetT num)
00926 {
00927   if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
00928     {
00929       /* This code is disabled on the 486 because all the Imm1 forms
00930         in the opcode table are slower on the i486.  They're the
00931         versions with the implicitly specified single-position
00932         displacement, which has another syntax if you really want to
00933         use that form.  */
00934       if (num == 1)
00935        return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
00936     }
00937   return (fits_in_signed_byte (num)
00938          ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
00939          : fits_in_unsigned_byte (num)
00940          ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
00941          : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
00942          ? (Imm16 | Imm32 | Imm32S | Imm64)
00943          : fits_in_signed_long (num)
00944          ? (Imm32 | Imm32S | Imm64)
00945          : fits_in_unsigned_long (num)
00946          ? (Imm32 | Imm64)
00947          : Imm64);
00948 }
00949 
00950 static offsetT
00951 offset_in_range (offsetT val, int size)
00952 {
00953   addressT mask;
00954 
00955   switch (size)
00956     {
00957     case 1: mask = ((addressT) 1 <<  8) - 1; break;
00958     case 2: mask = ((addressT) 1 << 16) - 1; break;
00959     case 4: mask = ((addressT) 2 << 31) - 1; break;
00960 #ifdef BFD64
00961     case 8: mask = ((addressT) 2 << 63) - 1; break;
00962 #endif
00963     default: abort ();
00964     }
00965 
00966   /* If BFD64, sign extend val.  */
00967   if (!use_rela_relocations)
00968     if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
00969       val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
00970 
00971   if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
00972     {
00973       char buf1[40], buf2[40];
00974 
00975       sprint_value (buf1, val);
00976       sprint_value (buf2, val & mask);
00977       as_warn (_("%s shortened to %s"), buf1, buf2);
00978     }
00979   return val & mask;
00980 }
00981 
00982 /* Returns 0 if attempting to add a prefix where one from the same
00983    class already exists, 1 if non rep/repne added, 2 if rep/repne
00984    added.  */
00985 static int
00986 add_prefix (unsigned int prefix)
00987 {
00988   int ret = 1;
00989   unsigned int q;
00990 
00991   if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
00992       && flag_code == CODE_64BIT)
00993     {
00994       if ((i.prefix[REX_PREFIX] & prefix & REX_W)
00995          || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
00996              && (prefix & (REX_R | REX_X | REX_B))))
00997        ret = 0;
00998       q = REX_PREFIX;
00999     }
01000   else
01001     {
01002       switch (prefix)
01003        {
01004        default:
01005          abort ();
01006 
01007        case CS_PREFIX_OPCODE:
01008        case DS_PREFIX_OPCODE:
01009        case ES_PREFIX_OPCODE:
01010        case FS_PREFIX_OPCODE:
01011        case GS_PREFIX_OPCODE:
01012        case SS_PREFIX_OPCODE:
01013          q = SEG_PREFIX;
01014          break;
01015 
01016        case REPNE_PREFIX_OPCODE:
01017        case REPE_PREFIX_OPCODE:
01018          ret = 2;
01019          /* fall thru */
01020        case LOCK_PREFIX_OPCODE:
01021          q = LOCKREP_PREFIX;
01022          break;
01023 
01024        case FWAIT_OPCODE:
01025          q = WAIT_PREFIX;
01026          break;
01027 
01028        case ADDR_PREFIX_OPCODE:
01029          q = ADDR_PREFIX;
01030          break;
01031 
01032        case DATA_PREFIX_OPCODE:
01033          q = DATA_PREFIX;
01034          break;
01035        }
01036       if (i.prefix[q] != 0)
01037        ret = 0;
01038     }
01039 
01040   if (ret)
01041     {
01042       if (!i.prefix[q])
01043        ++i.prefixes;
01044       i.prefix[q] |= prefix;
01045     }
01046   else
01047     as_bad (_("same type of prefix used twice"));
01048 
01049   return ret;
01050 }
01051 
01052 static void
01053 set_code_flag (int value)
01054 {
01055   flag_code = value;
01056   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
01057   cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
01058   if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
01059     {
01060       as_bad (_("64bit mode not supported on this CPU."));
01061     }
01062   if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
01063     {
01064       as_bad (_("32bit mode not supported on this CPU."));
01065     }
01066   stackop_size = '\0';
01067 }
01068 
01069 static void
01070 set_16bit_gcc_code_flag (int new_code_flag)
01071 {
01072   flag_code = new_code_flag;
01073   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
01074   cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
01075   stackop_size = LONG_MNEM_SUFFIX;
01076 }
01077 
01078 static void
01079 set_intel_syntax (int syntax_flag)
01080 {
01081   /* Find out if register prefixing is specified.  */
01082   int ask_naked_reg = 0;
01083 
01084   SKIP_WHITESPACE ();
01085   if (!is_end_of_line[(unsigned char) *input_line_pointer])
01086     {
01087       char *string = input_line_pointer;
01088       int e = get_symbol_end ();
01089 
01090       if (strcmp (string, "prefix") == 0)
01091        ask_naked_reg = 1;
01092       else if (strcmp (string, "noprefix") == 0)
01093        ask_naked_reg = -1;
01094       else
01095        as_bad (_("bad argument to syntax directive."));
01096       *input_line_pointer = e;
01097     }
01098   demand_empty_rest_of_line ();
01099 
01100   intel_syntax = syntax_flag;
01101 
01102   if (ask_naked_reg == 0)
01103     allow_naked_reg = (intel_syntax
01104                      && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
01105   else
01106     allow_naked_reg = (ask_naked_reg < 0);
01107 
01108   identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
01109   identifier_chars['$'] = intel_syntax ? '$' : 0;
01110   register_prefix = allow_naked_reg ? "" : "%";
01111 }
01112 
01113 static void
01114 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
01115 {
01116   SKIP_WHITESPACE ();
01117 
01118   if (!is_end_of_line[(unsigned char) *input_line_pointer])
01119     {
01120       char *string = input_line_pointer;
01121       int e = get_symbol_end ();
01122       unsigned int i;
01123 
01124       for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
01125        {
01126          if (strcmp (string, cpu_arch[i].name) == 0)
01127            {
01128              if (*string != '.')
01129               {
01130                 cpu_arch_name = cpu_arch[i].name;
01131                 cpu_sub_arch_name = NULL;
01132                 cpu_arch_flags = (cpu_arch[i].flags
01133                                 | (flag_code == CODE_64BIT
01134                                    ? Cpu64 : CpuNo64));
01135                 cpu_arch_isa = cpu_arch[i].type;
01136                 cpu_arch_isa_flags = cpu_arch[i].flags;
01137                 if (!cpu_arch_tune_set)
01138                   {
01139                     cpu_arch_tune = cpu_arch_isa;
01140                     cpu_arch_tune_flags = cpu_arch_isa_flags;
01141                   }
01142                 break;
01143               }
01144              if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
01145               {
01146                 cpu_sub_arch_name = cpu_arch[i].name;
01147                 cpu_arch_flags |= cpu_arch[i].flags;
01148               }
01149              *input_line_pointer = e;
01150              demand_empty_rest_of_line ();
01151              return;
01152            }
01153        }
01154       if (i >= ARRAY_SIZE (cpu_arch))
01155        as_bad (_("no such architecture: `%s'"), string);
01156 
01157       *input_line_pointer = e;
01158     }
01159   else
01160     as_bad (_("missing cpu architecture"));
01161 
01162   no_cond_jump_promotion = 0;
01163   if (*input_line_pointer == ','
01164       && !is_end_of_line[(unsigned char) input_line_pointer[1]])
01165     {
01166       char *string = ++input_line_pointer;
01167       int e = get_symbol_end ();
01168 
01169       if (strcmp (string, "nojumps") == 0)
01170        no_cond_jump_promotion = 1;
01171       else if (strcmp (string, "jumps") == 0)
01172        ;
01173       else
01174        as_bad (_("no such architecture modifier: `%s'"), string);
01175 
01176       *input_line_pointer = e;
01177     }
01178 
01179   demand_empty_rest_of_line ();
01180 }
01181 
01182 unsigned long
01183 i386_mach ()
01184 {
01185   if (!strcmp (default_arch, "x86_64"))
01186     return bfd_mach_x86_64;
01187   else if (!strcmp (default_arch, "i386"))
01188     return bfd_mach_i386_i386;
01189   else
01190     as_fatal (_("Unknown architecture"));
01191 }
01192 
01193 void
01194 md_begin ()
01195 {
01196   const char *hash_err;
01197 
01198   /* Initialize op_hash hash table.  */
01199   op_hash = hash_new ();
01200 
01201   {
01202     const template *optab;
01203     templates *core_optab;
01204 
01205     /* Setup for loop.  */
01206     optab = i386_optab;
01207     core_optab = (templates *) xmalloc (sizeof (templates));
01208     core_optab->start = optab;
01209 
01210     while (1)
01211       {
01212        ++optab;
01213        if (optab->name == NULL
01214            || strcmp (optab->name, (optab - 1)->name) != 0)
01215          {
01216            /* different name --> ship out current template list;
01217               add to hash table; & begin anew.  */
01218            core_optab->end = optab;
01219            hash_err = hash_insert (op_hash,
01220                                 (optab - 1)->name,
01221                                 (PTR) core_optab);
01222            if (hash_err)
01223              {
01224               as_fatal (_("Internal Error:  Can't hash %s: %s"),
01225                        (optab - 1)->name,
01226                        hash_err);
01227              }
01228            if (optab->name == NULL)
01229              break;
01230            core_optab = (templates *) xmalloc (sizeof (templates));
01231            core_optab->start = optab;
01232          }
01233       }
01234   }
01235 
01236   /* Initialize reg_hash hash table.  */
01237   reg_hash = hash_new ();
01238   {
01239     const reg_entry *regtab;
01240     unsigned int regtab_size = i386_regtab_size;
01241 
01242     for (regtab = i386_regtab; regtab_size--; regtab++)
01243       {
01244        hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
01245        if (hash_err)
01246          as_fatal (_("Internal Error:  Can't hash %s: %s"),
01247                   regtab->reg_name,
01248                   hash_err);
01249       }
01250   }
01251 
01252   /* Fill in lexical tables:  mnemonic_chars, operand_chars.  */
01253   {
01254     int c;
01255     char *p;
01256 
01257     for (c = 0; c < 256; c++)
01258       {
01259        if (ISDIGIT (c))
01260          {
01261            digit_chars[c] = c;
01262            mnemonic_chars[c] = c;
01263            register_chars[c] = c;
01264            operand_chars[c] = c;
01265          }
01266        else if (ISLOWER (c))
01267          {
01268            mnemonic_chars[c] = c;
01269            register_chars[c] = c;
01270            operand_chars[c] = c;
01271          }
01272        else if (ISUPPER (c))
01273          {
01274            mnemonic_chars[c] = TOLOWER (c);
01275            register_chars[c] = mnemonic_chars[c];
01276            operand_chars[c] = c;
01277          }
01278 
01279        if (ISALPHA (c) || ISDIGIT (c))
01280          identifier_chars[c] = c;
01281        else if (c >= 128)
01282          {
01283            identifier_chars[c] = c;
01284            operand_chars[c] = c;
01285          }
01286       }
01287 
01288 #ifdef LEX_AT
01289     identifier_chars['@'] = '@';
01290 #endif
01291 #ifdef LEX_QM
01292     identifier_chars['?'] = '?';
01293     operand_chars['?'] = '?';
01294 #endif
01295     digit_chars['-'] = '-';
01296     mnemonic_chars['-'] = '-';
01297     mnemonic_chars['.'] = '.';
01298     identifier_chars['_'] = '_';
01299     identifier_chars['.'] = '.';
01300 
01301     for (p = operand_special_chars; *p != '\0'; p++)
01302       operand_chars[(unsigned char) *p] = *p;
01303   }
01304 
01305 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
01306   if (IS_ELF)
01307     {
01308       record_alignment (text_section, 2);
01309       record_alignment (data_section, 2);
01310       record_alignment (bss_section, 2);
01311     }
01312 #endif
01313 
01314   if (flag_code == CODE_64BIT)
01315     {
01316       x86_dwarf2_return_column = 16;
01317       x86_cie_data_alignment = -8;
01318     }
01319   else
01320     {
01321       x86_dwarf2_return_column = 8;
01322       x86_cie_data_alignment = -4;
01323     }
01324 }
01325 
01326 void
01327 i386_print_statistics (FILE *file)
01328 {
01329   hash_print_statistics (file, "i386 opcode", op_hash);
01330   hash_print_statistics (file, "i386 register", reg_hash);
01331 }
01332 
01333 #ifdef DEBUG386
01334 
01335 /* Debugging routines for md_assemble.  */
01336 static void pte (template *);
01337 static void pt (unsigned int);
01338 static void pe (expressionS *);
01339 static void ps (symbolS *);
01340 
01341 static void
01342 pi (char *line, i386_insn *x)
01343 {
01344   unsigned int i;
01345 
01346   fprintf (stdout, "%s: template ", line);
01347   pte (&x->tm);
01348   fprintf (stdout, "  address: base %s  index %s  scale %x\n",
01349           x->base_reg ? x->base_reg->reg_name : "none",
01350           x->index_reg ? x->index_reg->reg_name : "none",
01351           x->log2_scale_factor);
01352   fprintf (stdout, "  modrm:  mode %x  reg %x  reg/mem %x\n",
01353           x->rm.mode, x->rm.reg, x->rm.regmem);
01354   fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
01355           x->sib.base, x->sib.index, x->sib.scale);
01356   fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
01357           (x->rex & REX_W) != 0,
01358           (x->rex & REX_R) != 0,
01359           (x->rex & REX_X) != 0,
01360           (x->rex & REX_B) != 0);
01361   for (i = 0; i < x->operands; i++)
01362     {
01363       fprintf (stdout, "    #%d:  ", i + 1);
01364       pt (x->types[i]);
01365       fprintf (stdout, "\n");
01366       if (x->types[i]
01367          & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
01368        fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
01369       if (x->types[i] & Imm)
01370        pe (x->op[i].imms);
01371       if (x->types[i] & Disp)
01372        pe (x->op[i].disps);
01373     }
01374 }
01375 
01376 static void
01377 pte (template *t)
01378 {
01379   unsigned int i;
01380   fprintf (stdout, " %d operands ", t->operands);
01381   fprintf (stdout, "opcode %x ", t->base_opcode);
01382   if (t->extension_opcode != None)
01383     fprintf (stdout, "ext %x ", t->extension_opcode);
01384   if (t->opcode_modifier & D)
01385     fprintf (stdout, "D");
01386   if (t->opcode_modifier & W)
01387     fprintf (stdout, "W");
01388   fprintf (stdout, "\n");
01389   for (i = 0; i < t->operands; i++)
01390     {
01391       fprintf (stdout, "    #%d type ", i + 1);
01392       pt (t->operand_types[i]);
01393       fprintf (stdout, "\n");
01394     }
01395 }
01396 
01397 static void
01398 pe (expressionS *e)
01399 {
01400   fprintf (stdout, "    operation     %d\n", e->X_op);
01401   fprintf (stdout, "    add_number    %ld (%lx)\n",
01402           (long) e->X_add_number, (long) e->X_add_number);
01403   if (e->X_add_symbol)
01404     {
01405       fprintf (stdout, "    add_symbol    ");
01406       ps (e->X_add_symbol);
01407       fprintf (stdout, "\n");
01408     }
01409   if (e->X_op_symbol)
01410     {
01411       fprintf (stdout, "    op_symbol    ");
01412       ps (e->X_op_symbol);
01413       fprintf (stdout, "\n");
01414     }
01415 }
01416 
01417 static void
01418 ps (symbolS *s)
01419 {
01420   fprintf (stdout, "%s type %s%s",
01421           S_GET_NAME (s),
01422           S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
01423           segment_name (S_GET_SEGMENT (s)));
01424 }
01425 
01426 static struct type_name
01427   {
01428     unsigned int mask;
01429     char *tname;
01430   }
01431 const type_names[] =
01432 {
01433   { Reg8, "r8" },
01434   { Reg16, "r16" },
01435   { Reg32, "r32" },
01436   { Reg64, "r64" },
01437   { Imm8, "i8" },
01438   { Imm8S, "i8s" },
01439   { Imm16, "i16" },
01440   { Imm32, "i32" },
01441   { Imm32S, "i32s" },
01442   { Imm64, "i64" },
01443   { Imm1, "i1" },
01444   { BaseIndex, "BaseIndex" },
01445   { Disp8, "d8" },
01446   { Disp16, "d16" },
01447   { Disp32, "d32" },
01448   { Disp32S, "d32s" },
01449   { Disp64, "d64" },
01450   { InOutPortReg, "InOutPortReg" },
01451   { ShiftCount, "ShiftCount" },
01452   { Control, "control reg" },
01453   { Test, "test reg" },
01454   { Debug, "debug reg" },
01455   { FloatReg, "FReg" },
01456   { FloatAcc, "FAcc" },
01457   { SReg2, "SReg2" },
01458   { SReg3, "SReg3" },
01459   { Acc, "Acc" },
01460   { JumpAbsolute, "Jump Absolute" },
01461   { RegMMX, "rMMX" },
01462   { RegXMM, "rXMM" },
01463   { EsSeg, "es" },
01464   { 0, "" }
01465 };
01466 
01467 static void
01468 pt (t)
01469      unsigned int t;
01470 {
01471   const struct type_name *ty;
01472 
01473   for (ty = type_names; ty->mask; ty++)
01474     if (t & ty->mask)
01475       fprintf (stdout, "%s, ", ty->tname);
01476   fflush (stdout);
01477 }
01478 
01479 #endif /* DEBUG386 */
01480 
01481 static bfd_reloc_code_real_type
01482 reloc (unsigned int size,
01483        int pcrel,
01484        int sign,
01485        bfd_reloc_code_real_type other)
01486 {
01487   if (other != NO_RELOC)
01488     {
01489       reloc_howto_type *reloc;
01490 
01491       if (size == 8)
01492        switch (other)
01493          {
01494          case BFD_RELOC_X86_64_GOT32:
01495            return BFD_RELOC_X86_64_GOT64;
01496            break;
01497          case BFD_RELOC_X86_64_PLTOFF64:
01498            return BFD_RELOC_X86_64_PLTOFF64;
01499            break;
01500          case BFD_RELOC_X86_64_GOTPC32:
01501            other = BFD_RELOC_X86_64_GOTPC64;
01502            break;
01503          case BFD_RELOC_X86_64_GOTPCREL:
01504            other = BFD_RELOC_X86_64_GOTPCREL64;
01505            break;
01506          case BFD_RELOC_X86_64_TPOFF32:
01507            other = BFD_RELOC_X86_64_TPOFF64;
01508            break;
01509          case BFD_RELOC_X86_64_DTPOFF32:
01510            other = BFD_RELOC_X86_64_DTPOFF64;
01511            break;
01512          default:
01513            break;
01514          }
01515 
01516       /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
01517       if (size == 4 && flag_code != CODE_64BIT)
01518        sign = -1;
01519 
01520       reloc = bfd_reloc_type_lookup (stdoutput, other);
01521       if (!reloc)
01522        as_bad (_("unknown relocation (%u)"), other);
01523       else if (size != bfd_get_reloc_size (reloc))
01524        as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
01525               bfd_get_reloc_size (reloc),
01526               size);
01527       else if (pcrel && !reloc->pc_relative)
01528        as_bad (_("non-pc-relative relocation for pc-relative field"));
01529       else if ((reloc->complain_on_overflow == complain_overflow_signed
01530               && !sign)
01531               || (reloc->complain_on_overflow == complain_overflow_unsigned
01532                  && sign > 0))
01533        as_bad (_("relocated field and relocation type differ in signedness"));
01534       else
01535        return other;
01536       return NO_RELOC;
01537     }
01538 
01539   if (pcrel)
01540     {
01541       if (!sign)
01542        as_bad (_("there are no unsigned pc-relative relocations"));
01543       switch (size)
01544        {
01545        case 1: return BFD_RELOC_8_PCREL;
01546        case 2: return BFD_RELOC_16_PCREL;
01547        case 4: return BFD_RELOC_32_PCREL;
01548        case 8: return BFD_RELOC_64_PCREL;
01549        }
01550       as_bad (_("cannot do %u byte pc-relative relocation"), size);
01551     }
01552   else
01553     {
01554       if (sign > 0)
01555        switch (size)
01556          {
01557          case 4: return BFD_RELOC_X86_64_32S;
01558          }
01559       else
01560        switch (size)
01561          {
01562          case 1: return BFD_RELOC_8;
01563          case 2: return BFD_RELOC_16;
01564          case 4: return BFD_RELOC_32;
01565          case 8: return BFD_RELOC_64;
01566          }
01567       as_bad (_("cannot do %s %u byte relocation"),
01568              sign > 0 ? "signed" : "unsigned", size);
01569     }
01570 
01571   abort ();
01572   return BFD_RELOC_NONE;
01573 }
01574 
01575 /* Here we decide which fixups can be adjusted to make them relative to
01576    the beginning of the section instead of the symbol.  Basically we need
01577    to make sure that the dynamic relocations are done correctly, so in
01578    some cases we force the original symbol to be used.  */
01579 
01580 int
01581 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
01582 {
01583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
01584   if (!IS_ELF)
01585     return 1;
01586 
01587   /* Don't adjust pc-relative references to merge sections in 64-bit
01588      mode.  */
01589   if (use_rela_relocations
01590       && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
01591       && fixP->fx_pcrel)
01592     return 0;
01593 
01594   /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
01595      and changed later by validate_fix.  */
01596   if (GOT_symbol && fixP->fx_subsy == GOT_symbol
01597       && fixP->fx_r_type == BFD_RELOC_32_PCREL)
01598     return 0;
01599 
01600   /* adjust_reloc_syms doesn't know about the GOT.  */
01601   if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
01602       || fixP->fx_r_type == BFD_RELOC_386_PLT32
01603       || fixP->fx_r_type == BFD_RELOC_386_GOT32
01604       || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
01605       || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
01606       || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
01607       || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
01608       || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
01609       || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
01610       || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
01611       || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
01612       || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
01613       || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
01614       || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
01615       || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
01616       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
01617       || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
01618       || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
01619       || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
01620       || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
01621       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
01622       || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
01623       || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
01624       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
01625       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
01626       || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
01627       || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
01628       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
01629     return 0;
01630 #endif
01631   return 1;
01632 }
01633 
01634 static int
01635 intel_float_operand (const char *mnemonic)
01636 {
01637   /* Note that the value returned is meaningful only for opcodes with (memory)
01638      operands, hence the code here is free to improperly handle opcodes that
01639      have no operands (for better performance and smaller code). */
01640 
01641   if (mnemonic[0] != 'f')
01642     return 0; /* non-math */
01643 
01644   switch (mnemonic[1])
01645     {
01646     /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
01647        the fs segment override prefix not currently handled because no
01648        call path can make opcodes without operands get here */
01649     case 'i':
01650       return 2 /* integer op */;
01651     case 'l':
01652       if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
01653        return 3; /* fldcw/fldenv */
01654       break;
01655     case 'n':
01656       if (mnemonic[2] != 'o' /* fnop */)
01657        return 3; /* non-waiting control op */
01658       break;
01659     case 'r':
01660       if (mnemonic[2] == 's')
01661        return 3; /* frstor/frstpm */
01662       break;
01663     case 's':
01664       if (mnemonic[2] == 'a')
01665        return 3; /* fsave */
01666       if (mnemonic[2] == 't')
01667        {
01668          switch (mnemonic[3])
01669            {
01670            case 'c': /* fstcw */
01671            case 'd': /* fstdw */
01672            case 'e': /* fstenv */
01673            case 's': /* fsts[gw] */
01674              return 3;
01675            }
01676        }
01677       break;
01678     case 'x':
01679       if (mnemonic[2] == 'r' || mnemonic[2] == 's')
01680        return 0; /* fxsave/fxrstor are not really math ops */
01681       break;
01682     }
01683 
01684   return 1;
01685 }
01686 
01687 /* This is the guts of the machine-dependent assembler.  LINE points to a
01688    machine dependent instruction.  This function is supposed to emit
01689    the frags/bytes it assembles to.  */
01690 
01691 void
01692 md_assemble (line)
01693      char *line;
01694 {
01695   int j;
01696   char mnemonic[MAX_MNEM_SIZE];
01697 
01698   /* Initialize globals.  */
01699   memset (&i, '\0', sizeof (i));
01700   for (j = 0; j < MAX_OPERANDS; j++)
01701     i.reloc[j] = NO_RELOC;
01702   memset (disp_expressions, '\0', sizeof (disp_expressions));
01703   memset (im_expressions, '\0', sizeof (im_expressions));
01704   save_stack_p = save_stack;
01705 
01706   /* First parse an instruction mnemonic & call i386_operand for the operands.
01707      We assume that the scrubber has arranged it so that line[0] is the valid
01708      start of a (possibly prefixed) mnemonic.  */
01709 
01710   line = parse_insn (line, mnemonic);
01711   if (line == NULL)
01712     return;
01713 
01714   line = parse_operands (line, mnemonic);
01715   if (line == NULL)
01716     return;
01717 
01718   /* The order of the immediates should be reversed
01719      for 2 immediates extrq and insertq instructions */
01720   if ((i.imm_operands == 2)
01721       && ((strcmp (mnemonic, "extrq") == 0)
01722          || (strcmp (mnemonic, "insertq") == 0)))
01723     {
01724       swap_2_operands (0, 1);
01725       /* "extrq" and insertq" are the only two instructions whose operands
01726         have to be reversed even though they have two immediate operands.
01727       */
01728       if (intel_syntax)
01729        swap_operands ();
01730     }
01731 
01732   /* Now we've parsed the mnemonic into a set of templates, and have the
01733      operands at hand.  */
01734 
01735   /* All intel opcodes have reversed operands except for "bound" and
01736      "enter".  We also don't reverse intersegment "jmp" and "call"
01737      instructions with 2 immediate operands so that the immediate segment
01738      precedes the offset, as it does when in AT&T mode. */
01739   if (intel_syntax
01740       && i.operands > 1
01741       && (strcmp (mnemonic, "bound") != 0)
01742       && (strcmp (mnemonic, "invlpga") != 0)
01743       && !((i.types[0] & Imm) && (i.types[1] & Imm)))
01744     swap_operands ();
01745 
01746   if (i.imm_operands)
01747     optimize_imm ();
01748 
01749   /* Don't optimize displacement for movabs since it only takes 64bit
01750      displacement.  */
01751   if (i.disp_operands
01752       && (flag_code != CODE_64BIT
01753          || strcmp (mnemonic, "movabs") != 0))
01754     optimize_disp ();
01755 
01756   /* Next, we find a template that matches the given insn,
01757      making sure the overlap of the given operands types is consistent
01758      with the template operand types.  */
01759 
01760   if (!match_template ())
01761     return;
01762 
01763   if (intel_syntax)
01764     {
01765       /* Undo SYSV386_COMPAT brokenness when in Intel mode.  See i386.h  */
01766       if (SYSV386_COMPAT
01767          && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
01768        i.tm.base_opcode ^= Opcode_FloatR;
01769 
01770       /* Zap movzx and movsx suffix.  The suffix may have been set from
01771         "word ptr" or "byte ptr" on the source operand, but we'll use
01772         the suffix later to choose the destination register.  */
01773       if ((i.tm.base_opcode & ~9) == 0x0fb6)
01774        {
01775          if (i.reg_operands < 2
01776              && !i.suffix
01777              && (~i.tm.opcode_modifier
01778                 & (No_bSuf
01779                    | No_wSuf
01780                    | No_lSuf
01781                    | No_sSuf
01782                    | No_xSuf
01783                    | No_qSuf)))
01784            as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
01785 
01786          i.suffix = 0;
01787        }
01788     }
01789 
01790   if (i.tm.opcode_modifier & FWait)
01791     if (!add_prefix (FWAIT_OPCODE))
01792       return;
01793 
01794   /* Check string instruction segment overrides.  */
01795   if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
01796     {
01797       if (!check_string ())
01798        return;
01799     }
01800 
01801   if (!process_suffix ())
01802     return;
01803 
01804   /* Make still unresolved immediate matches conform to size of immediate
01805      given in i.suffix.  */
01806   if (!finalize_imm ())
01807     return;
01808 
01809   if (i.types[0] & Imm1)
01810     i.imm_operands = 0;     /* kludge for shift insns.  */
01811   if (i.types[0] & ImplicitRegister)
01812     i.reg_operands--;
01813   if (i.types[1] & ImplicitRegister)
01814     i.reg_operands--;
01815   if (i.types[2] & ImplicitRegister)
01816     i.reg_operands--;
01817 
01818   if (i.tm.opcode_modifier & ImmExt)
01819     {
01820       expressionS *exp;
01821 
01822       if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
01823        {
01824          /* Streaming SIMD extensions 3 Instructions have the fixed
01825             operands with an opcode suffix which is coded in the same
01826             place as an 8-bit immediate field would be. Here we check
01827             those operands and remove them afterwards.  */
01828          unsigned int x;
01829 
01830          for (x = 0; x < i.operands; x++)
01831            if (i.op[x].regs->reg_num != x)
01832              as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
01833                     i.op[x].regs->reg_name, x + 1, i.tm.name);
01834          i.operands = 0;
01835        }
01836 
01837       /* These AMD 3DNow! and Intel Katmai New Instructions have an
01838         opcode suffix which is coded in the same place as an 8-bit
01839         immediate field would be.  Here we fake an 8-bit immediate
01840         operand from the opcode suffix stored in tm.extension_opcode.  */
01841 
01842       assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
01843 
01844       exp = &im_expressions[i.imm_operands++];
01845       i.op[i.operands].imms = exp;
01846       i.types[i.operands++] = Imm8;
01847       exp->X_op = O_constant;
01848       exp->X_add_number = i.tm.extension_opcode;
01849       i.tm.extension_opcode = None;
01850     }
01851 
01852   /* For insns with operands there are more diddles to do to the opcode.  */
01853   if (i.operands)
01854     {
01855       if (!process_operands ())
01856        return;
01857     }
01858   else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
01859     {
01860       /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
01861       as_warn (_("translating to `%sp'"), i.tm.name);
01862     }
01863 
01864   /* Handle conversion of 'int $3' --> special int3 insn.  */
01865   if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
01866     {
01867       i.tm.base_opcode = INT3_OPCODE;
01868       i.imm_operands = 0;
01869     }
01870 
01871   if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
01872       && i.op[0].disps->X_op == O_constant)
01873     {
01874       /* Convert "jmp constant" (and "call constant") to a jump (call) to
01875         the absolute address given by the constant.  Since ix86 jumps and
01876         calls are pc relative, we need to generate a reloc.  */
01877       i.op[0].disps->X_add_symbol = &abs_symbol;
01878       i.op[0].disps->X_op = O_symbol;
01879     }
01880 
01881   if ((i.tm.opcode_modifier & Rex64) != 0)
01882     i.rex |= REX_W;
01883 
01884   /* For 8 bit registers we need an empty rex prefix.  Also if the
01885      instruction already has a prefix, we need to convert old
01886      registers to new ones.  */
01887 
01888   if (((i.types[0] & Reg8) != 0
01889        && (i.op[0].regs->reg_flags & RegRex64) != 0)
01890       || ((i.types[1] & Reg8) != 0
01891          && (i.op[1].regs->reg_flags & RegRex64) != 0)
01892       || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
01893          && i.rex != 0))
01894     {
01895       int x;
01896 
01897       i.rex |= REX_OPCODE;
01898       for (x = 0; x < 2; x++)
01899        {
01900          /* Look for 8 bit operand that uses old registers.  */
01901          if ((i.types[x] & Reg8) != 0
01902              && (i.op[x].regs->reg_flags & RegRex64) == 0)
01903            {
01904              /* In case it is "hi" register, give up.  */
01905              if (i.op[x].regs->reg_num > 3)
01906               as_bad (_("can't encode register '%%%s' in an "
01907                        "instruction requiring REX prefix."),
01908                      i.op[x].regs->reg_name);
01909 
01910              /* Otherwise it is equivalent to the extended register.
01911                Since the encoding doesn't change this is merely
01912                cosmetic cleanup for debug output.  */
01913 
01914              i.op[x].regs = i.op[x].regs + 8;
01915            }
01916        }
01917     }
01918 
01919   if (i.rex != 0)
01920     add_prefix (REX_OPCODE | i.rex);
01921 
01922   /* We are ready to output the insn.  */
01923   output_insn ();
01924 }
01925 
01926 static char *
01927 parse_insn (char *line, char *mnemonic)
01928 {
01929   char *l = line;
01930   char *token_start = l;
01931   char *mnem_p;
01932   int supported;
01933   const template *t;
01934 
01935   /* Non-zero if we found a prefix only acceptable with string insns.  */
01936   const char *expecting_string_instruction = NULL;
01937 
01938   while (1)
01939     {
01940       mnem_p = mnemonic;
01941       while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
01942        {
01943          mnem_p++;
01944          if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
01945            {
01946              as_bad (_("no such instruction: `%s'"), token_start);
01947              return NULL;
01948            }
01949          l++;
01950        }
01951       if (!is_space_char (*l)
01952          && *l != END_OF_INSN
01953          && (intel_syntax
01954              || (*l != PREFIX_SEPARATOR
01955                 && *l != ',')))
01956        {
01957          as_bad (_("invalid character %s in mnemonic"),
01958                 output_invalid (*l));
01959          return NULL;
01960        }
01961       if (token_start == l)
01962        {
01963          if (!intel_syntax && *l == PREFIX_SEPARATOR)
01964            as_bad (_("expecting prefix; got nothing"));
01965          else
01966            as_bad (_("expecting mnemonic; got nothing"));
01967          return NULL;
01968        }
01969 
01970       /* Look up instruction (or prefix) via hash table.  */
01971       current_templates = hash_find (op_hash, mnemonic);
01972 
01973       if (*l != END_OF_INSN
01974          && (!is_space_char (*l) || l[1] != END_OF_INSN)
01975          && current_templates
01976          && (current_templates->start->opcode_modifier & IsPrefix))
01977        {
01978          if (current_templates->start->cpu_flags
01979              & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
01980            {
01981              as_bad ((flag_code != CODE_64BIT
01982                      ? _("`%s' is only supported in 64-bit mode")
01983                      : _("`%s' is not supported in 64-bit mode")),
01984                     current_templates->start->name);
01985              return NULL;
01986            }
01987          /* If we are in 16-bit mode, do not allow addr16 or data16.
01988             Similarly, in 32-bit mode, do not allow addr32 or data32.  */
01989          if ((current_templates->start->opcode_modifier & (Size16 | Size32))
01990              && flag_code != CODE_64BIT
01991              && (((current_templates->start->opcode_modifier & Size32) != 0)
01992                 ^ (flag_code == CODE_16BIT)))
01993            {
01994              as_bad (_("redundant %s prefix"),
01995                     current_templates->start->name);
01996              return NULL;
01997            }
01998          /* Add prefix, checking for repeated prefixes.  */
01999          switch (add_prefix (current_templates->start->base_opcode))
02000            {
02001            case 0:
02002              return NULL;
02003            case 2:
02004              expecting_string_instruction = current_templates->start->name;
02005              break;
02006            }
02007          /* Skip past PREFIX_SEPARATOR and reset token_start.  */
02008          token_start = ++l;
02009        }
02010       else
02011        break;
02012     }
02013 
02014   if (!current_templates)
02015     {
02016       /* See if we can get a match by trimming off a suffix.  */
02017       switch (mnem_p[-1])
02018        {
02019        case WORD_MNEM_SUFFIX:
02020          if (intel_syntax && (intel_float_operand (mnemonic) & 2))
02021            i.suffix = SHORT_MNEM_SUFFIX;
02022          else
02023        case BYTE_MNEM_SUFFIX:
02024        case QWORD_MNEM_SUFFIX:
02025          i.suffix = mnem_p[-1];
02026          mnem_p[-1] = '\0';
02027          current_templates = hash_find (op_hash, mnemonic);
02028          break;
02029        case SHORT_MNEM_SUFFIX:
02030        case LONG_MNEM_SUFFIX:
02031          if (!intel_syntax)
02032            {
02033              i.suffix = mnem_p[-1];
02034              mnem_p[-1] = '\0';
02035              current_templates = hash_find (op_hash, mnemonic);
02036            }
02037          break;
02038 
02039          /* Intel Syntax.  */
02040        case 'd':
02041          if (intel_syntax)
02042            {
02043              if (intel_float_operand (mnemonic) == 1)
02044               i.suffix = SHORT_MNEM_SUFFIX;
02045              else
02046               i.suffix = LONG_MNEM_SUFFIX;
02047              mnem_p[-1] = '\0';
02048              current_templates = hash_find (op_hash, mnemonic);
02049            }
02050          break;
02051        }
02052       if (!current_templates)
02053        {
02054          as_bad (_("no such instruction: `%s'"), token_start);
02055          return NULL;
02056        }
02057     }
02058 
02059   if (current_templates->start->opcode_modifier & (Jump | JumpByte))
02060     {
02061       /* Check for a branch hint.  We allow ",pt" and ",pn" for
02062         predict taken and predict not taken respectively.
02063         I'm not sure that branch hints actually do anything on loop
02064         and jcxz insns (JumpByte) for current Pentium4 chips.  They
02065         may work in the future and it doesn't hurt to accept them
02066         now.  */
02067       if (l[0] == ',' && l[1] == 'p')
02068        {
02069          if (l[2] == 't')
02070            {
02071              if (!add_prefix (DS_PREFIX_OPCODE))
02072               return NULL;
02073              l += 3;
02074            }
02075          else if (l[2] == 'n')
02076            {
02077              if (!add_prefix (CS_PREFIX_OPCODE))
02078               return NULL;
02079              l += 3;
02080            }
02081        }
02082     }
02083   /* Any other comma loses.  */
02084   if (*l == ',')
02085     {
02086       as_bad (_("invalid character %s in mnemonic"),
02087              output_invalid (*l));
02088       return NULL;
02089     }
02090 
02091   /* Check if instruction is supported on specified architecture.  */
02092   supported = 0;
02093   for (t = current_templates->start; t < current_templates->end; ++t)
02094     {
02095       if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
02096            & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
02097        supported |= 1;
02098       if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
02099        supported |= 2;
02100     }
02101   if (!(supported & 2))
02102     {
02103       as_bad (flag_code == CODE_64BIT
02104              ? _("`%s' is not supported in 64-bit mode")
02105              : _("`%s' is only supported in 64-bit mode"),
02106              current_templates->start->name);
02107       return NULL;
02108     }
02109   if (!(supported & 1))
02110     {
02111       as_warn (_("`%s' is not supported on `%s%s'"),
02112               current_templates->start->name,
02113               cpu_arch_name,
02114               cpu_sub_arch_name ? cpu_sub_arch_name : "");
02115     }
02116   else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
02117     {
02118       as_warn (_("use .code16 to ensure correct addressing mode"));
02119     }
02120 
02121   /* Check for rep/repne without a string instruction.  */
02122   if (expecting_string_instruction)
02123     {
02124       static templates override;
02125 
02126       for (t = current_templates->start; t < current_templates->end; ++t)
02127        if (t->opcode_modifier & IsString)
02128          break;
02129       if (t >= current_templates->end)
02130        {
02131          as_bad (_("expecting string instruction after `%s'"),
02132                 expecting_string_instruction);
02133          return NULL;
02134        }
02135       for (override.start = t; t < current_templates->end; ++t)
02136        if (!(t->opcode_modifier & IsString))
02137          break;
02138       override.end = t;
02139       current_templates = &override;
02140     }
02141 
02142   return l;
02143 }
02144 
02145 static char *
02146 parse_operands (char *l, const char *mnemonic)
02147 {
02148   char *token_start;
02149 
02150   /* 1 if operand is pending after ','.  */
02151   unsigned int expecting_operand = 0;
02152 
02153   /* Non-zero if operand parens not balanced.  */
02154   unsigned int paren_not_balanced;
02155 
02156   while (*l != END_OF_INSN)
02157     {
02158       /* Skip optional white space before operand.  */
02159       if (is_space_char (*l))
02160        ++l;
02161       if (!is_operand_char (*l) && *l != END_OF_INSN)
02162        {
02163          as_bad (_("invalid character %s before operand %d"),
02164                 output_invalid (*l),
02165                 i.operands + 1);
02166          return NULL;
02167        }
02168       token_start = l;      /* after white space */
02169       paren_not_balanced = 0;
02170       while (paren_not_balanced || *l != ',')
02171        {
02172          if (*l == END_OF_INSN)
02173            {
02174              if (paren_not_balanced)
02175               {
02176                 if (!intel_syntax)
02177                   as_bad (_("unbalanced parenthesis in operand %d."),
02178                          i.operands + 1);
02179                 else
02180                   as_bad (_("unbalanced brackets in operand %d."),
02181                          i.operands + 1);
02182                 return NULL;
02183               }
02184              else
02185               break; /* we are done */
02186            }
02187          else if (!is_operand_char (*l) && !is_space_char (*l))
02188            {
02189              as_bad (_("invalid character %s in operand %d"),
02190                     output_invalid (*l),
02191                     i.operands + 1);
02192              return NULL;
02193            }
02194          if (!intel_syntax)
02195            {
02196              if (*l == '(')
02197               ++paren_not_balanced;
02198              if (*l == ')')
02199               --paren_not_balanced;
02200            }
02201          else
02202            {
02203              if (*l == '[')
02204               ++paren_not_balanced;
02205              if (*l == ']')
02206               --paren_not_balanced;
02207            }
02208          l++;
02209        }
02210       if (l != token_start)
02211        {                    /* Yes, we've read in another operand.  */
02212          unsigned int operand_ok;
02213          this_operand = i.operands++;
02214          if (i.operands > MAX_OPERANDS)
02215            {
02216              as_bad (_("spurious operands; (%d operands/instruction max)"),
02217                     MAX_OPERANDS);
02218              return NULL;
02219            }
02220          /* Now parse operand adding info to 'i' as we go along.  */
02221          END_STRING_AND_SAVE (l);
02222 
02223          if (intel_syntax)
02224            operand_ok =
02225              i386_intel_operand (token_start,
02226                               intel_float_operand (mnemonic));
02227          else
02228            operand_ok = i386_operand (token_start);
02229 
02230          RESTORE_END_STRING (l);
02231          if (!operand_ok)
02232            return NULL;
02233        }
02234       else
02235        {
02236          if (expecting_operand)
02237            {
02238            expecting_operand_after_comma:
02239              as_bad (_("expecting operand after ','; got nothing"));
02240              return NULL;
02241            }
02242          if (*l == ',')
02243            {
02244              as_bad (_("expecting operand before ','; got nothing"));
02245              return NULL;
02246            }
02247        }
02248 
02249       /* Now *l must be either ',' or END_OF_INSN.  */
02250       if (*l == ',')
02251        {
02252          if (*++l == END_OF_INSN)
02253            {
02254              /* Just skip it, if it's \n complain.  */
02255              goto expecting_operand_after_comma;
02256            }
02257          expecting_operand = 1;
02258        }
02259     }
02260   return l;
02261 }
02262 
02263 static void
02264 swap_2_operands (int xchg1, int xchg2)
02265 {
02266   union i386_op temp_op;
02267   unsigned int temp_type;
02268   enum bfd_reloc_code_real temp_reloc;
02269 
02270   temp_type = i.types[xchg2];
02271   i.types[xchg2] = i.types[xchg1];
02272   i.types[xchg1] = temp_type;
02273   temp_op = i.op[xchg2];
02274   i.op[xchg2] = i.op[xchg1];
02275   i.op[xchg1] = temp_op;
02276   temp_reloc = i.reloc[xchg2];
02277   i.reloc[xchg2] = i.reloc[xchg1];
02278   i.reloc[xchg1] = temp_reloc;
02279 }
02280 
02281 static void
02282 swap_operands (void)
02283 {
02284   switch (i.operands)
02285     {
02286     case 4:
02287       swap_2_operands (1, i.operands - 2);
02288     case 3:
02289     case 2:
02290       swap_2_operands (0, i.operands - 1);
02291       break;
02292     default:
02293       abort ();
02294     }
02295 
02296   if (i.mem_operands == 2)
02297     {
02298       const seg_entry *temp_seg;
02299       temp_seg = i.seg[0];
02300       i.seg[0] = i.seg[1];
02301       i.seg[1] = temp_seg;
02302     }
02303 }
02304 
02305 /* Try to ensure constant immediates are represented in the smallest
02306    opcode possible.  */
02307 static void
02308 optimize_imm (void)
02309 {
02310   char guess_suffix = 0;
02311   int op;
02312 
02313   if (i.suffix)
02314     guess_suffix = i.suffix;
02315   else if (i.reg_operands)
02316     {
02317       /* Figure out a suffix from the last register operand specified.
02318         We can't do this properly yet, ie. excluding InOutPortReg,
02319         but the following works for instructions with immediates.
02320         In any case, we can't set i.suffix yet.  */
02321       for (op = i.operands; --op >= 0;)
02322        if (i.types[op] & Reg)
02323          {
02324            if (i.types[op] & Reg8)
02325              guess_suffix = BYTE_MNEM_SUFFIX;
02326            else if (i.types[op] & Reg16)
02327              guess_suffix = WORD_MNEM_SUFFIX;
02328            else if (i.types[op] & Reg32)
02329              guess_suffix = LONG_MNEM_SUFFIX;
02330            else if (i.types[op] & Reg64)
02331              guess_suffix = QWORD_MNEM_SUFFIX;
02332            break;
02333          }
02334     }
02335   else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
02336     guess_suffix = WORD_MNEM_SUFFIX;
02337 
02338   for (op = i.operands; --op >= 0;)
02339     if (i.types[op] & Imm)
02340       {
02341        switch (i.op[op].imms->X_op)
02342          {
02343          case O_constant:
02344            /* If a suffix is given, this operand may be shortened.  */
02345            switch (guess_suffix)
02346              {
02347              case LONG_MNEM_SUFFIX:
02348               i.types[op] |= Imm32 | Imm64;
02349               break;
02350              case WORD_MNEM_SUFFIX:
02351               i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
02352               break;
02353              case BYTE_MNEM_SUFFIX:
02354               i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
02355               break;
02356              }
02357 
02358            /* If this operand is at most 16 bits, convert it
02359               to a signed 16 bit number before trying to see
02360               whether it will fit in an even smaller size.
02361               This allows a 16-bit operand such as $0xffe0 to
02362               be recognised as within Imm8S range.  */
02363            if ((i.types[op] & Imm16)
02364               && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
02365              {
02366               i.op[op].imms->X_add_number =
02367                 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
02368              }
02369            if ((i.types[op] & Imm32)
02370               && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
02371                   == 0))
02372              {
02373               i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
02374                                           ^ ((offsetT) 1 << 31))
02375                                           - ((offsetT) 1 << 31));
02376              }
02377            i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
02378 
02379            /* We must avoid matching of Imm32 templates when 64bit
02380               only immediate is available.  */
02381            if (guess_suffix == QWORD_MNEM_SUFFIX)
02382              i.types[op] &= ~Imm32;
02383            break;
02384 
02385          case O_absent:
02386          case O_register:
02387            abort ();
02388 
02389            /* Symbols and expressions.  */
02390          default:
02391            /* Convert symbolic operand to proper sizes for matching, but don't
02392               prevent matching a set of insns that only supports sizes other
02393               than those matching the insn suffix.  */
02394            {
02395              unsigned int mask, allowed = 0;
02396              const template *t;
02397 
02398              for (t = current_templates->start;
02399                  t < current_templates->end;
02400                  ++t)
02401               allowed |= t->operand_types[op];
02402              switch (guess_suffix)
02403               {
02404               case QWORD_MNEM_SUFFIX:
02405                 mask = Imm64 | Imm32S;
02406                 break;
02407               case LONG_MNEM_SUFFIX:
02408                 mask = Imm32;
02409                 break;
02410               case WORD_MNEM_SUFFIX:
02411                 mask = Imm16;
02412                 break;
02413               case BYTE_MNEM_SUFFIX:
02414                 mask = Imm8;
02415                 break;
02416               default:
02417                 mask = 0;
02418                 break;
02419               }
02420              if (mask & allowed)
02421               i.types[op] &= mask;
02422            }
02423            break;
02424          }
02425       }
02426 }
02427 
02428 /* Try to use the smallest displacement type too.  */
02429 static void
02430 optimize_disp (void)
02431 {
02432   int op;
02433 
02434   for (op = i.operands; --op >= 0;)
02435     if (i.types[op] & Disp)
02436       {
02437        if (i.op[op].disps->X_op == O_constant)
02438          {
02439            offsetT disp = i.op[op].disps->X_add_number;
02440 
02441            if ((i.types[op] & Disp16)
02442               && (disp & ~(offsetT) 0xffff) == 0)
02443              {
02444               /* If this operand is at most 16 bits, convert
02445                  to a signed 16 bit number and don't use 64bit
02446                  displacement.  */
02447               disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
02448               i.types[op] &= ~Disp64;
02449              }
02450            if ((i.types[op] & Disp32)
02451               && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
02452              {
02453               /* If this operand is at most 32 bits, convert
02454                  to a signed 32 bit number and don't use 64bit
02455                  displacement.  */
02456               disp &= (((offsetT) 2 << 31) - 1);
02457               disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
02458               i.types[op] &= ~Disp64;
02459              }
02460            if (!disp && (i.types[op] & BaseIndex))
02461              {
02462               i.types[op] &= ~Disp;
02463               i.op[op].disps = 0;
02464               i.disp_operands--;
02465              }
02466            else if (flag_code == CODE_64BIT)
02467              {
02468               if (fits_in_signed_long (disp))
02469                 {
02470                   i.types[op] &= ~Disp64;
02471                   i.types[op] |= Disp32S;
02472                 }
02473               if (fits_in_unsigned_long (disp))
02474                 i.types[op] |= Disp32;
02475              }
02476            if ((i.types[op] & (Disp32 | Disp32S | Disp16))
02477               && fits_in_signed_byte (disp))
02478              i.types[op] |= Disp8;
02479          }
02480        else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
02481                || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
02482          {
02483            fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
02484                       i.op[op].disps, 0, i.reloc[op]);
02485            i.types[op] &= ~Disp;
02486          }
02487        else
02488          /* We only support 64bit displacement on constants.  */
02489          i.types[op] &= ~Disp64;
02490       }
02491 }
02492 
02493 static int
02494 match_template (void)
02495 {
02496   /* Points to template once we've found it.  */
02497   const template *t;
02498   unsigned int overlap0, overlap1, overlap2, overlap3;
02499   unsigned int found_reverse_match;
02500   int suffix_check;
02501   unsigned int operand_types [MAX_OPERANDS];
02502   int addr_prefix_disp;
02503   unsigned int j;
02504 
02505 #if MAX_OPERANDS != 4
02506 # error "MAX_OPERANDS must be 4."
02507 #endif
02508 
02509 #define MATCH(overlap, given, template)                        \
02510   ((overlap & ~JumpAbsolute)                                   \
02511    && (((given) & (BaseIndex | JumpAbsolute))                  \
02512        == ((overlap) & (BaseIndex | JumpAbsolute))))
02513 
02514   /* If given types r0 and r1 are registers they must be of the same type
02515      unless the expected operand type register overlap is null.
02516      Note that Acc in a template matches every size of reg.  */
02517 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1)      \
02518   (((g0) & Reg) == 0 || ((g1) & Reg) == 0               \
02519    || ((g0) & Reg) == ((g1) & Reg)                      \
02520    || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
02521 
02522   overlap0 = 0;
02523   overlap1 = 0;
02524   overlap2 = 0;
02525   overlap3 = 0;
02526   found_reverse_match = 0;
02527   for (j = 0; j < MAX_OPERANDS; j++)
02528     operand_types [j] = 0;
02529   addr_prefix_disp = -1;
02530   suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
02531                 ? No_bSuf
02532                 : (i.suffix == WORD_MNEM_SUFFIX
02533                    ? No_wSuf
02534                    : (i.suffix == SHORT_MNEM_SUFFIX
02535                      ? No_sSuf
02536                      : (i.suffix == LONG_MNEM_SUFFIX
02537                         ? No_lSuf
02538                         : (i.suffix == QWORD_MNEM_SUFFIX
02539                            ? No_qSuf
02540                            : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
02541                              ? No_xSuf : 0))))));
02542 
02543   for (t = current_templates->start; t < current_templates->end; t++)
02544     {
02545       addr_prefix_disp = -1;
02546 
02547       /* Must have right number of operands.  */
02548       if (i.operands != t->operands)
02549        continue;
02550 
02551       /* Check the suffix, except for some instructions in intel mode.  */
02552       if ((t->opcode_modifier & suffix_check)
02553          && !(intel_syntax
02554               && (t->opcode_modifier & IgnoreSize)))
02555        continue;
02556 
02557       for (j = 0; j < MAX_OPERANDS; j++)
02558        operand_types [j] = t->operand_types [j];
02559 
02560       /* In general, don't allow 64-bit operands in 32-bit mode.  */
02561       if (i.suffix == QWORD_MNEM_SUFFIX
02562          && flag_code != CODE_64BIT
02563          && (intel_syntax
02564              ? (!(t->opcode_modifier & IgnoreSize)
02565                && !intel_float_operand (t->name))
02566              : intel_float_operand (t->name) != 2)
02567          && (!(operand_types[0] & (RegMMX | RegXMM))
02568              || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
02569          && (t->base_opcode != 0x0fc7
02570              || t->extension_opcode != 1 /* cmpxchg8b */))
02571        continue;
02572 
02573       /* Do not verify operands when there are none.  */
02574       else if (!t->operands)
02575        {
02576          if (t->cpu_flags & ~cpu_arch_flags)
02577            continue;
02578          /* We've found a match; break out of loop.  */
02579          break;
02580        }
02581 
02582       /* Address size prefix will turn Disp64/Disp32/Disp16 operand
02583         into Disp32/Disp16/Disp32 operand.  */
02584       if (i.prefix[ADDR_PREFIX] != 0)
02585          {
02586            unsigned int DispOn = 0, DispOff = 0;
02587 
02588            switch (flag_code)
02589            {
02590            case CODE_16BIT:
02591              DispOn = Disp32;
02592              DispOff = Disp16;
02593              break;
02594            case CODE_32BIT:
02595              DispOn = Disp16;
02596              DispOff = Disp32;
02597              break;
02598            case CODE_64BIT:
02599              DispOn = Disp32;
02600              DispOff = Disp64;
02601              break;
02602            }
02603 
02604            for (j = 0; j < MAX_OPERANDS; j++)
02605              {
02606               /* There should be only one Disp operand.  */
02607               if ((operand_types[j] & DispOff))
02608                 {
02609                   addr_prefix_disp = j;
02610                   operand_types[j] |= DispOn;
02611                   operand_types[j] &= ~DispOff;
02612                   break;
02613                 }
02614              }
02615          }
02616 
02617       overlap0 = i.types[0] & operand_types[0];
02618       switch (t->operands)
02619        {
02620        case 1:
02621          if (!MATCH (overlap0, i.types[0], operand_types[0]))
02622            continue;
02623          break;
02624        case 2:
02625          /* xchg %eax, %eax is a special case. It is an aliase for nop
02626             only in 32bit mode and we can use opcode 0x90.  In 64bit
02627             mode, we can't use 0x90 for xchg %eax, %eax since it should
02628             zero-extend %eax to %rax.  */
02629          if (flag_code == CODE_64BIT
02630              && t->base_opcode == 0x90
02631              && i.types [0] == (Acc | Reg32)
02632              && i.types [1] == (Acc | Reg32))
02633            continue;
02634        case 3:
02635        case 4:
02636          overlap1 = i.types[1] & operand_types[1];
02637          if (!MATCH (overlap0, i.types[0], operand_types[0])
02638              || !MATCH (overlap1, i.types[1], operand_types[1])
02639              /* monitor in SSE3 is a very special case.  The first
02640                register and the second register may have different
02641                sizes.  */
02642              || !((t->base_opcode == 0x0f01
02643                   && t->extension_opcode == 0xc8)
02644                  || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
02645                                            operand_types[0],
02646                                            overlap1, i.types[1],
02647                                            operand_types[1])))
02648            {
02649              /* Check if other direction is valid ...  */
02650              if ((t->opcode_modifier & (D | FloatD)) == 0)
02651               continue;
02652 
02653              /* Try reversing direction of operands.  */
02654              overlap0 = i.types[0] & operand_types[1];
02655              overlap1 = i.types[1] & operand_types[0];
02656              if (!MATCH (overlap0, i.types[0], operand_types[1])
02657                 || !MATCH (overlap1, i.types[1], operand_types[0])
02658                 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
02659                                            operand_types[1],
02660                                            overlap1, i.types[1],
02661                                            operand_types[0]))
02662               {
02663                 /* Does not match either direction.  */
02664                 continue;
02665               }
02666              /* found_reverse_match holds which of D or FloatDR
02667                we've found.  */
02668              if ((t->opcode_modifier & D))
02669               found_reverse_match = Opcode_D;
02670              else if ((t->opcode_modifier & FloatD))
02671               found_reverse_match = Opcode_FloatD;
02672              else
02673               found_reverse_match = 0;
02674              if ((t->opcode_modifier & FloatR))
02675               found_reverse_match |= Opcode_FloatR;
02676            }
02677          else
02678            {
02679              /* Found a forward 2 operand match here.  */
02680              switch (t->operands)
02681               {
02682               case 4:
02683                 overlap3 = i.types[3] & operand_types[3];
02684               case 3:
02685                 overlap2 = i.types[2] & operand_types[2];
02686                 break;
02687               }
02688 
02689              switch (t->operands)
02690               {
02691               case 4:
02692                 if (!MATCH (overlap3, i.types[3], operand_types[3])
02693                     || !CONSISTENT_REGISTER_MATCH (overlap2,
02694                                                i.types[2],
02695                                                operand_types[2],
02696                                                overlap3,
02697                                                i.types[3],
02698                                                operand_types[3]))
02699                   continue;
02700               case 3:
02701                 /* Here we make use of the fact that there are no
02702                    reverse match 3 operand instructions, and all 3
02703                    operand instructions only need to be checked for
02704                    register consistency between operands 2 and 3.  */
02705                 if (!MATCH (overlap2, i.types[2], operand_types[2])
02706                     || !CONSISTENT_REGISTER_MATCH (overlap1,
02707                                                i.types[1],
02708                                                operand_types[1],
02709                                                overlap2,
02710                                                i.types[2],
02711                                                operand_types[2]))
02712                   continue;
02713                 break;
02714               }
02715            }
02716          /* Found either forward/reverse 2, 3 or 4 operand match here:
02717             slip through to break.  */
02718        }
02719       if (t->cpu_flags & ~cpu_arch_flags)
02720        {
02721          found_reverse_match = 0;
02722          continue;
02723        }
02724       /* We've found a match; break out of loop.  */
02725       break;
02726     }
02727 
02728   if (t == current_templates->end)
02729     {
02730       /* We found no match.  */
02731       as_bad (_("suffix or operands invalid for `%s'"),
02732              current_templates->start->name);
02733       return 0;
02734     }
02735 
02736   if (!quiet_warnings)
02737     {
02738       if (!intel_syntax
02739          && ((i.types[0] & JumpAbsolute)
02740              != (operand_types[0] & JumpAbsolute)))
02741        {
02742          as_warn (_("indirect %s without `*'"), t->name);
02743        }
02744 
02745       if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
02746          == (IsPrefix | IgnoreSize))
02747        {
02748          /* Warn them that a data or address size prefix doesn't
02749             affect assembly of the next line of code.  */
02750          as_warn (_("stand-alone `%s' prefix"), t->name);
02751        }
02752     }
02753 
02754   /* Copy the template we found.  */
02755   i.tm = *t;
02756 
02757   if (addr_prefix_disp != -1)
02758     i.tm.operand_types[addr_prefix_disp]
02759       = operand_types[addr_prefix_disp];
02760 
02761   if (found_reverse_match)
02762     {
02763       /* If we found a reverse match we must alter the opcode
02764         direction bit.  found_reverse_match holds bits to change
02765         (different for int & float insns).  */
02766 
02767       i.tm.base_opcode ^= found_reverse_match;
02768 
02769       i.tm.operand_types[0] = operand_types[1];
02770       i.tm.operand_types[1] = operand_types[0];
02771     }
02772 
02773   return 1;
02774 }
02775 
02776 static int
02777 check_string (void)
02778 {
02779   int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
02780   if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
02781     {
02782       if (i.seg[0] != NULL && i.seg[0] != &es)
02783        {
02784          as_bad (_("`%s' operand %d must use `%%es' segment"),
02785                 i.tm.name,
02786                 mem_op + 1);
02787          return 0;
02788        }
02789       /* There's only ever one segment override allowed per instruction.
02790         This instruction possibly has a legal segment override on the
02791         second operand, so copy the segment to where non-string
02792         instructions store it, allowing common code.  */
02793       i.seg[0] = i.seg[1];
02794     }
02795   else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
02796     {
02797       if (i.seg[1] != NULL && i.seg[1] != &es)
02798        {
02799          as_bad (_("`%s' operand %d must use `%%es' segment"),
02800                 i.tm.name,
02801                 mem_op + 2);
02802          return 0;
02803        }
02804     }
02805   return 1;
02806 }
02807 
02808 static int
02809 process_suffix (void)
02810 {
02811   /* If matched instruction specifies an explicit instruction mnemonic
02812      suffix, use it.  */
02813   if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
02814     {
02815       if (i.tm.opcode_modifier & Size16)
02816        i.suffix = WORD_MNEM_SUFFIX;
02817       else if (i.tm.opcode_modifier & Size64)
02818        i.suffix = QWORD_MNEM_SUFFIX;
02819       else
02820        i.suffix = LONG_MNEM_SUFFIX;
02821     }
02822   else if (i.reg_operands)
02823     {
02824       /* If there's no instruction mnemonic suffix we try to invent one
02825         based on register operands.  */
02826       if (!i.suffix)
02827        {
02828          /* We take i.suffix from the last register operand specified,
02829             Destination register type is more significant than source
02830             register type.  */
02831          int op;
02832 
02833          for (op = i.operands; --op >= 0;)
02834            if ((i.types[op] & Reg)
02835               && !(i.tm.operand_types[op] & InOutPortReg))
02836              {
02837               i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
02838                          (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
02839                          (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
02840                          LONG_MNEM_SUFFIX);
02841               break;
02842              }
02843        }
02844       else if (i.suffix == BYTE_MNEM_SUFFIX)
02845        {
02846          if (!check_byte_reg ())
02847            return 0;
02848        }
02849       else if (i.suffix == LONG_MNEM_SUFFIX)
02850        {
02851          if (!check_long_reg ())
02852            return 0;
02853        }
02854       else if (i.suffix == QWORD_MNEM_SUFFIX)
02855        {
02856          if (!check_qword_reg ())
02857            return 0;
02858        }
02859       else if (i.suffix == WORD_MNEM_SUFFIX)
02860        {
02861          if (!check_word_reg ())
02862            return 0;
02863        }
02864       else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
02865        /* Do nothing if the instruction is going to ignore the prefix.  */
02866        ;
02867       else
02868        abort ();
02869     }
02870   else if ((i.tm.opcode_modifier & DefaultSize)
02871           && !i.suffix
02872           /* exclude fldenv/frstor/fsave/fstenv */
02873           && (i.tm.opcode_modifier & No_sSuf))
02874     {
02875       i.suffix = stackop_size;
02876     }
02877   else if (intel_syntax
02878           && !i.suffix
02879           && ((i.tm.operand_types[0] & JumpAbsolute)
02880               || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
02881               || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
02882                  && i.tm.extension_opcode <= 3)))
02883     {
02884       switch (flag_code)
02885        {
02886        case CODE_64BIT:
02887          if (!(i.tm.opcode_modifier & No_qSuf))
02888            {
02889              i.suffix = QWORD_MNEM_SUFFIX;
02890              break;
02891            }
02892        case CODE_32BIT:
02893          if (!(i.tm.opcode_modifier & No_lSuf))
02894            i.suffix = LONG_MNEM_SUFFIX;
02895          break;
02896        case CODE_16BIT:
02897          if (!(i.tm.opcode_modifier & No_wSuf))
02898            i.suffix = WORD_MNEM_SUFFIX;
02899          break;
02900        }
02901     }
02902 
02903   if (!i.suffix)
02904     {
02905       if (!intel_syntax)
02906        {
02907          if (i.tm.opcode_modifier & W)
02908            {
02909              as_bad (_("no instruction mnemonic suffix given and "
02910                      "no register operands; can't size instruction"));
02911              return 0;
02912            }
02913        }
02914       else
02915        {
02916          unsigned int suffixes = (~i.tm.opcode_modifier
02917                                & (No_bSuf
02918                                   | No_wSuf
02919                                   | No_lSuf
02920                                   | No_sSuf
02921                                   | No_xSuf
02922                                   | No_qSuf));
02923 
02924          if ((i.tm.opcode_modifier & W)
02925              || ((suffixes & (suffixes - 1))
02926                 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
02927            {
02928              as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
02929              return 0;
02930            }
02931        }
02932     }
02933 
02934   /* Change the opcode based on the operand size given by i.suffix;
02935      We don't need to change things for byte insns.  */
02936 
02937   if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
02938     {
02939       /* It's not a byte, select word/dword operation.  */
02940       if (i.tm.opcode_modifier & W)
02941        {
02942          if (i.tm.opcode_modifier & ShortForm)
02943            i.tm.base_opcode |= 8;
02944          else
02945            i.tm.base_opcode |= 1;
02946        }
02947 
02948       /* Now select between word & dword operations via the operand
02949         size prefix, except for instructions that will ignore this
02950         prefix anyway.  */
02951       if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
02952        {
02953          /* monitor in SSE3 is a very special case. The default size
02954             of AX is the size of mode. The address size override
02955             prefix will change the size of AX.  */
02956          if (i.op->regs[0].reg_type &
02957              (flag_code == CODE_32BIT ? Reg16 : Reg32))
02958            if (!add_prefix (ADDR_PREFIX_OPCODE))
02959              return 0;
02960        }
02961       else if (i.suffix != QWORD_MNEM_SUFFIX
02962               && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
02963               && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
02964               && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
02965                  || (flag_code == CODE_64BIT
02966                      && (i.tm.opcode_modifier & JumpByte))))
02967        {
02968          unsigned int prefix = DATA_PREFIX_OPCODE;
02969 
02970          if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
02971            prefix = ADDR_PREFIX_OPCODE;
02972 
02973          if (!add_prefix (prefix))
02974            return 0;
02975        }
02976 
02977       /* Set mode64 for an operand.  */
02978       if (i.suffix == QWORD_MNEM_SUFFIX
02979          && flag_code == CODE_64BIT
02980          && (i.tm.opcode_modifier & NoRex64) == 0)
02981        {
02982          /* Special case for xchg %rax,%rax.  It is NOP and doesn't
02983             need rex64.  */
02984          if (i.operands != 2
02985              || i.types [0] != (Acc | Reg64)
02986              || i.types [1] != (Acc | Reg64)
02987              || i.tm.base_opcode != 0x90)
02988            i.rex |= REX_W;
02989        }
02990 
02991       /* Size floating point instruction.  */
02992       if (i.suffix == LONG_MNEM_SUFFIX)
02993        if (i.tm.opcode_modifier & FloatMF)
02994          i.tm.base_opcode ^= 4;
02995     }
02996 
02997   return 1;
02998 }
02999 
03000 static int
03001 check_byte_reg (void)
03002 {
03003   int op;
03004 
03005   for (op = i.operands; --op >= 0;)
03006     {
03007       /* If this is an eight bit register, it's OK.  If it's the 16 or
03008         32 bit version of an eight bit register, we will just use the
03009         low portion, and that's OK too.  */
03010       if (i.types[op] & Reg8)
03011        continue;
03012 
03013       /* movzx and movsx should not generate this warning.  */
03014       if (intel_syntax
03015          && (i.tm.base_opcode == 0xfb7
03016              || i.tm.base_opcode == 0xfb6
03017              || i.tm.base_opcode == 0x63
03018              || i.tm.base_opcode == 0xfbe
03019              || i.tm.base_opcode == 0xfbf))
03020        continue;
03021 
03022       if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
03023        {
03024          /* Prohibit these changes in the 64bit mode, since the
03025             lowering is more complicated.  */
03026          if (flag_code == CODE_64BIT
03027              && (i.tm.operand_types[op] & InOutPortReg) == 0)
03028            {
03029              as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
03030                     register_prefix, i.op[op].regs->reg_name,
03031                     i.suffix);
03032              return 0;
03033            }
03034 #if REGISTER_WARNINGS
03035          if (!quiet_warnings
03036              && (i.tm.operand_types[op] & InOutPortReg) == 0)
03037            as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
03038                    (i.op[op].regs + (i.types[op] & Reg16
03039                                    ? REGNAM_AL - REGNAM_AX
03040                                    : REGNAM_AL - REGNAM_EAX))->reg_name,
03041                    i.op[op].regs->reg_name,
03042                    i.suffix);
03043 #endif
03044          continue;
03045        }
03046       /* Any other register is bad.  */
03047       if (i.types[op] & (Reg | RegMMX | RegXMM
03048                       | SReg2 | SReg3
03049                       | Control | Debug | Test
03050                       | FloatReg | FloatAcc))
03051        {
03052          as_bad (_("`%%%s' not allowed with `%s%c'"),
03053                 i.op[op].regs->reg_name,
03054                 i.tm.name,
03055                 i.suffix);
03056          return 0;
03057        }
03058     }
03059   return 1;
03060 }
03061 
03062 static int
03063 check_long_reg (void)
03064 {
03065   int op;
03066 
03067   for (op = i.operands; --op >= 0;)
03068     /* Reject eight bit registers, except where the template requires
03069        them. (eg. movzb)  */
03070     if ((i.types[op] & Reg8) != 0
03071        && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
03072       {
03073        as_bad (_("`%%%s' not allowed with `%s%c'"),
03074               i.op[op].regs->reg_name,
03075               i.tm.name,
03076               i.suffix);
03077        return 0;
03078       }
03079   /* Warn if the e prefix on a general reg is missing.  */
03080     else if ((!quiet_warnings || flag_code == CODE_64BIT)
03081             && (i.types[op] & Reg16) != 0
03082             && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
03083       {
03084        /* Prohibit these changes in the 64bit mode, since the
03085           lowering is more complicated.  */
03086        if (flag_code == CODE_64BIT)
03087          {
03088            as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
03089                   register_prefix, i.op[op].regs->reg_name,
03090                   i.suffix);
03091            return 0;
03092          }
03093 #if REGISTER_WARNINGS
03094        else
03095          as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
03096                  (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
03097                  i.op[op].regs->reg_name,
03098                  i.suffix);
03099 #endif
03100       }
03101   /* Warn if the r prefix on a general reg is missing.  */
03102     else if ((i.types[op] & Reg64) != 0
03103             && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
03104       {
03105        as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
03106               register_prefix, i.op[op].regs->reg_name,
03107               i.suffix);
03108        return 0;
03109       }
03110   return 1;
03111 }
03112 
03113 static int
03114 check_qword_reg (void)
03115 {
03116   int op;
03117 
03118   for (op = i.operands; --op >= 0; )
03119     /* Reject eight bit registers, except where the template requires
03120        them. (eg. movzb)  */
03121     if ((i.types[op] & Reg8) != 0
03122        && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
03123       {
03124        as_bad (_("`%%%s' not allowed with `%s%c'"),
03125               i.op[op].regs->reg_name,
03126               i.tm.name,
03127               i.suffix);
03128        return 0;
03129       }
03130   /* Warn if the e prefix on a general reg is missing.  */
03131     else if (((i.types[op] & Reg16) != 0
03132              || (i.types[op] & Reg32) != 0)
03133             && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
03134       {
03135        /* Prohibit these changes in the 64bit mode, since the
03136           lowering is more complicated.  */
03137        as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
03138               register_prefix, i.op[op].regs->reg_name,
03139               i.suffix);
03140        return 0;
03141       }
03142   return 1;
03143 }
03144 
03145 static int
03146 check_word_reg (void)
03147 {
03148   int op;
03149   for (op = i.operands; --op >= 0;)
03150     /* Reject eight bit registers, except where the template requires
03151        them. (eg. movzb)  */
03152     if ((i.types[op] & Reg8) != 0
03153        && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
03154       {
03155        as_bad (_("`%%%s' not allowed with `%s%c'"),
03156               i.op[op].regs->reg_name,
03157               i.tm.name,
03158               i.suffix);
03159        return 0;
03160       }
03161   /* Warn if the e prefix on a general reg is present.  */
03162     else if ((!quiet_warnings || flag_code == CODE_64BIT)
03163             && (i.types[op] & Reg32) != 0
03164             && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
03165       {
03166        /* Prohibit these changes in the 64bit mode, since the
03167           lowering is more complicated.  */
03168        if (flag_code == CODE_64BIT)
03169          {
03170            as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
03171                   register_prefix, i.op[op].regs->reg_name,
03172                   i.suffix);
03173            return 0;
03174          }
03175        else
03176 #if REGISTER_WARNINGS
03177          as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
03178                  (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
03179                  i.op[op].regs->reg_name,
03180                  i.suffix);
03181 #endif
03182       }
03183   return 1;
03184 }
03185 
03186 static int
03187 finalize_imm (void)
03188 {
03189   unsigned int overlap0, overlap1, overlap2;
03190 
03191   overlap0 = i.types[0] & i.tm.operand_types[0];
03192   if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
03193       && overlap0 != Imm8 && overlap0 != Imm8S
03194       && overlap0 != Imm16 && overlap0 != Imm32S
03195       && overlap0 != Imm32 && overlap0 != Imm64)
03196     {
03197       if (i.suffix)
03198        {
03199          overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
03200                      ? Imm8 | Imm8S
03201                      : (i.suffix == WORD_MNEM_SUFFIX
03202                        ? Imm16
03203                        : (i.suffix == QWORD_MNEM_SUFFIX
03204                           ? Imm64 | Imm32S
03205                           : Imm32)));
03206        }
03207       else if (overlap0 == (Imm16 | Imm32S | Imm32)
03208               || overlap0 == (Imm16 | Imm32)
03209               || overlap0 == (Imm16 | Imm32S))
03210        {
03211          overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
03212                     ? Imm16 : Imm32S);
03213        }
03214       if (overlap0 != Imm8 && overlap0 != Imm8S
03215          && overlap0 != Imm16 && overlap0 != Imm32S
03216          && overlap0 != Imm32 && overlap0 != Imm64)
03217        {
03218          as_bad (_("no instruction mnemonic suffix given; "
03219                   "can't determine immediate size"));
03220          return 0;
03221        }
03222     }
03223   i.types[0] = overlap0;
03224 
03225   overlap1 = i.types[1] & i.tm.operand_types[1];
03226   if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
03227       && overlap1 != Imm8 && overlap1 != Imm8S
03228       && overlap1 != Imm16 && overlap1 != Imm32S
03229       && overlap1 != Imm32 && overlap1 != Imm64)
03230     {
03231       if (i.suffix)
03232        {
03233          overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
03234                      ? Imm8 | Imm8S
03235                      : (i.suffix == WORD_MNEM_SUFFIX
03236                        ? Imm16
03237                        : (i.suffix == QWORD_MNEM_SUFFIX
03238                           ? Imm64 | Imm32S
03239                           : Imm32)));
03240        }
03241       else if (overlap1 == (Imm16 | Imm32 | Imm32S)
03242               || overlap1 == (Imm16 | Imm32)
03243               || overlap1 == (Imm16 | Imm32S))
03244        {
03245          overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
03246                     ? Imm16 : Imm32S);
03247        }
03248       if (overlap1 != Imm8 && overlap1 != Imm8S
03249          && overlap1 != Imm16 && overlap1 != Imm32S
03250          && overlap1 != Imm32 && overlap1 != Imm64)
03251        {
03252          as_bad (_("no instruction mnemonic suffix given; "
03253                   "can't determine immediate size %x %c"),
03254                 overlap1, i.suffix);
03255          return 0;
03256        }
03257     }
03258   i.types[1] = overlap1;
03259 
03260   overlap2 = i.types[2] & i.tm.operand_types[2];
03261   assert ((overlap2 & Imm) == 0);
03262   i.types[2] = overlap2;
03263 
03264   return 1;
03265 }
03266 
03267 static int
03268 process_operands (void)
03269 {
03270   /* Default segment register this instruction will use for memory
03271      accesses.  0 means unknown.  This is only for optimizing out
03272      unnecessary segment overrides.  */
03273   const seg_entry *default_seg = 0;
03274 
03275   /* The imul $imm, %reg instruction is converted into
03276      imul $imm, %reg, %reg, and the clr %reg instruction
03277      is converted into xor %reg, %reg.  */
03278   if (i.tm.opcode_modifier & regKludge)
03279     {
03280       unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
03281       /* Pretend we saw the extra register operand.  */
03282       assert (i.reg_operands == 1
03283              && i.op[first_reg_op + 1].regs == 0);
03284       i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
03285       i.types[first_reg_op + 1] = i.types[first_reg_op];
03286       i.operands++;
03287       i.reg_operands++;
03288     }
03289 
03290   if (i.tm.opcode_modifier & ShortForm)
03291     {
03292       if (i.types[0] & (SReg2 | SReg3))
03293        {
03294          if (i.tm.base_opcode == POP_SEG_SHORT
03295              && i.op[0].regs->reg_num == 1)
03296            {
03297              as_bad (_("you can't `pop %%cs'"));
03298              return 0;
03299            }
03300          i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
03301          if ((i.op[0].regs->reg_flags & RegRex) != 0)
03302            i.rex |= REX_B;
03303        }
03304       else
03305        {
03306          /* The register or float register operand is in operand 0 or 1.  */
03307          unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
03308          /* Register goes in low 3 bits of opcode.  */
03309          i.tm.base_opcode |= i.op[op].regs->reg_num;
03310          if ((i.op[op].regs->reg_flags & RegRex) != 0)
03311            i.rex |= REX_B;
03312          if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
03313            {
03314              /* Warn about some common errors, but press on regardless.
03315                The first case can be generated by gcc (<= 2.8.1).  */
03316              if (i.operands == 2)
03317               {
03318                 /* Reversed arguments on faddp, fsubp, etc.  */
03319                 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
03320                         i.op[1].regs->reg_name,
03321                         i.op[0].regs->reg_name);
03322               }
03323              else
03324               {
03325                 /* Extraneous `l' suffix on fp insn.  */
03326                 as_warn (_("translating to `%s %%%s'"), i.tm.name,
03327                         i.op[0].regs->reg_name);
03328               }
03329            }
03330        }
03331     }
03332   else if (i.tm.opcode_modifier & Modrm)
03333     {
03334       /* The opcode is completed (modulo i.tm.extension_opcode which
03335         must be put into the modrm byte).  Now, we make the modrm and
03336         index base bytes based on all the info we've collected.  */
03337 
03338       default_seg = build_modrm_byte ();
03339     }
03340   else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
03341     {
03342       default_seg = &ds;
03343     }
03344   else if ((i.tm.opcode_modifier & IsString) != 0)
03345     {
03346       /* For the string instructions that allow a segment override
03347         on one of their operands, the default segment is ds.  */
03348       default_seg = &ds;
03349     }
03350 
03351   if ((i.tm.base_opcode == 0x8d /* lea */
03352        || (i.tm.cpu_flags & CpuSVME))
03353       && i.seg[0] && !quiet_warnings)
03354     as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
03355 
03356   /* If a segment was explicitly specified, and the specified segment
03357      is not the default, use an opcode prefix to select it.  If we
03358      never figured out what the default segment is, then default_seg
03359      will be zero at this point, and the specified segment prefix will
03360      always be used.  */
03361   if ((i.seg[0]) && (i.seg[0] != default_seg))
03362     {
03363       if (!add_prefix (i.seg[0]->seg_prefix))
03364        return 0;
03365     }
03366   return 1;
03367 }
03368 
03369 static const seg_entry *
03370 build_modrm_byte (void)
03371 {
03372   const seg_entry *default_seg = 0;
03373 
03374   /* i.reg_operands MUST be the number of real register operands;
03375      implicit registers do not count.  */
03376   if (i.reg_operands == 2)
03377     {
03378       unsigned int source, dest;
03379 
03380       switch (i.operands)
03381        {
03382        case 2:
03383          source = 0;
03384          break;
03385        case 3:
03386          /* When there are 3 operands, one of them may be immediate,
03387             which may be the first or the last operand.  Otherwise,
03388             the first operand must be shift count register (cl). */
03389          assert (i.imm_operands == 1
03390                 || (i.imm_operands == 0
03391                     && (i.types[0] & ShiftCount)));
03392          source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
03393          break;
03394        case 4:
03395          /* When there are 4 operands, the first two must be immediate
03396             operands. The source operand will be the 3rd one.  */
03397          assert (i.imm_operands == 2
03398                 && (i.types[0] & Imm)
03399                 && (i.types[1] & Imm));
03400          source = 2;
03401          break;
03402        default:
03403          abort ();
03404        }
03405 
03406       dest = source + 1;
03407 
03408       i.rm.mode = 3;
03409       /* One of the register operands will be encoded in the i.tm.reg
03410         field, the other in the combined i.tm.mode and i.tm.regmem
03411         fields.  If no form of this instruction supports a memory
03412         destination operand, then we assume the source operand may
03413         sometimes be a memory operand and so we need to store the
03414         destination in the i.rm.reg field.  */
03415       if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
03416        {
03417          i.rm.reg = i.op[dest].regs->reg_num;
03418          i.rm.regmem = i.op[source].regs->reg_num;
03419          if ((i.op[dest].regs->reg_flags & RegRex) != 0)
03420            i.rex |= REX_R;
03421          if ((i.op[source].regs->reg_flags & RegRex) != 0)
03422            i.rex |= REX_B;
03423        }
03424       else
03425        {
03426          i.rm.reg = i.op[source].regs->reg_num;
03427          i.rm.regmem = i.op[dest].regs->reg_num;
03428          if ((i.op[dest].regs->reg_flags & RegRex) != 0)
03429            i.rex |= REX_B;
03430          if ((i.op[source].regs->reg_flags & RegRex) != 0)
03431            i.rex |= REX_R;
03432        }
03433       if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
03434        {
03435          if (!((i.types[0] | i.types[1]) & Control))
03436            abort ();
03437          i.rex &= ~(REX_R | REX_B);
03438          add_prefix (LOCK_PREFIX_OPCODE);
03439        }
03440     }
03441   else
03442     {                /* If it's not 2 reg operands...  */
03443       if (i.mem_operands)
03444        {
03445          unsigned int fake_zero_displacement = 0;
03446          unsigned int op;
03447 
03448          for (op = 0; op < i.operands; op++)
03449            if ((i.types[op] & AnyMem))
03450              break;
03451          assert (op < i.operands);
03452 
03453          default_seg = &ds;
03454 
03455          if (i.base_reg == 0)
03456            {
03457              i.rm.mode = 0;
03458              if (!i.disp_operands)
03459               fake_zero_displacement = 1;
03460              if (i.index_reg == 0)
03461               {
03462                 /* Operand is just <disp>  */
03463                 if (flag_code == CODE_64BIT)
03464                   {
03465                     /* 64bit mode overwrites the 32bit absolute
03466                       addressing by RIP relative addressing and
03467                       absolute addressing is encoded by one of the
03468                       redundant SIB forms.  */
03469                     i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
03470                     i.sib.base = NO_BASE_REGISTER;
03471                     i.sib.index = NO_INDEX_REGISTER;
03472                     i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
03473                                  ? Disp32S : Disp32);
03474                   }
03475                 else if ((flag_code == CODE_16BIT)
03476                         ^ (i.prefix[ADDR_PREFIX] != 0))
03477                   {
03478                     i.rm.regmem = NO_BASE_REGISTER_16;
03479                     i.types[op] = Disp16;
03480                   }
03481                 else
03482                   {
03483                     i.rm.regmem = NO_BASE_REGISTER;
03484                     i.types[op] = Disp32;
03485                   }
03486               }
03487              else /* !i.base_reg && i.index_reg  */
03488               {
03489                 i.sib.index = i.index_reg->reg_num;
03490                 i.sib.base = NO_BASE_REGISTER;
03491                 i.sib.scale = i.log2_scale_factor;
03492                 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
03493                 i.types[op] &= ~Disp;
03494                 if (flag_code != CODE_64BIT)
03495                   i.types[op] |= Disp32;  /* Must be 32 bit */
03496                 else
03497                   i.types[op] |= Disp32S;
03498                 if ((i.index_reg->reg_flags & RegRex) != 0)
03499                   i.rex |= REX_X;
03500               }
03501            }
03502          /* RIP addressing for 64bit mode.  */
03503          else if (i.base_reg->reg_type == BaseIndex)
03504            {
03505              i.rm.regmem = NO_BASE_REGISTER;
03506              i.types[op] &= ~ Disp;
03507              i.types[op] |= Disp32S;
03508              i.flags[op] |= Operand_PCrel;
03509              if (! i.disp_operands)
03510               fake_zero_displacement = 1;
03511            }
03512          else if (i.base_reg->reg_type & Reg16)
03513            {
03514              switch (i.base_reg->reg_num)
03515               {
03516               case 3: /* (%bx)  */
03517                 if (i.index_reg == 0)
03518                   i.rm.regmem = 7;
03519                 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1  */
03520                   i.rm.regmem = i.index_reg->reg_num - 6;
03521                 break;
03522               case 5: /* (%bp)  */
03523                 default_seg = &ss;
03524                 if (i.index_reg == 0)
03525                   {
03526                     i.rm.regmem = 6;
03527                     if ((i.types[op] & Disp) == 0)
03528                      {
03529                        /* fake (%bp) into 0(%bp)  */
03530                        i.types[op] |= Disp8;
03531                        fake_zero_displacement = 1;
03532                      }
03533                   }
03534                 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3  */
03535                   i.rm.regmem = i.index_reg->reg_num - 6 + 2;
03536                 break;
03537               default: /* (%si) -> 4 or (%di) -> 5  */
03538                 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
03539               }
03540              i.rm.mode = mode_from_disp_size (i.types[op]);
03541            }
03542          else /* i.base_reg and 32/64 bit mode  */
03543            {
03544              if (flag_code == CODE_64BIT
03545                 && (i.types[op] & Disp))
03546               i.types[op] = ((i.types[op] & Disp8)
03547                             | (i.prefix[ADDR_PREFIX] == 0
03548                               ? Disp32S : Disp32));
03549 
03550              i.rm.regmem = i.base_reg->reg_num;
03551              if ((i.base_reg->reg_flags & RegRex) != 0)
03552               i.rex |= REX_B;
03553              i.sib.base = i.base_reg->reg_num;
03554              /* x86-64 ignores REX prefix bit here to avoid decoder
03555                complications.  */
03556              if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
03557               {
03558                 default_seg = &ss;
03559                 if (i.disp_operands == 0)
03560                   {
03561                     fake_zero_displacement = 1;
03562                     i.types[op] |= Disp8;
03563                   }
03564               }
03565              else if (i.base_reg->reg_num == ESP_REG_NUM)
03566               {
03567                 default_seg = &ss;
03568               }
03569              i.sib.scale = i.log2_scale_factor;
03570              if (i.index_reg == 0)
03571               {
03572                 /* <disp>(%esp) becomes two byte modrm with no index
03573                    register.  We've already stored the code for esp
03574                    in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
03575                    Any base register besides %esp will not use the
03576                    extra modrm byte.  */
03577                 i.sib.index = NO_INDEX_REGISTER;
03578 #if !SCALE1_WHEN_NO_INDEX
03579                 /* Another case where we force the second modrm byte.  */
03580                 if (i.log2_scale_factor)
03581                   i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
03582 #endif
03583               }
03584              else
03585               {
03586                 i.sib.index = i.index_reg->reg_num;
03587                 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
03588                 if ((i.index_reg->reg_flags & RegRex) != 0)
03589                   i.rex |= REX_X;
03590               }
03591 
03592              if (i.disp_operands
03593                 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
03594                     || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
03595               i.rm.mode = 0;
03596              else
03597               i.rm.mode = mode_from_disp_size (i.types[op]);
03598            }
03599 
03600          if (fake_zero_displacement)
03601            {
03602              /* Fakes a zero displacement assuming that i.types[op]
03603                holds the correct displacement size.  */
03604              expressionS *exp;
03605 
03606              assert (i.op[op].disps == 0);
03607              exp = &disp_expressions[i.disp_operands++];
03608              i.op[op].disps = exp;
03609              exp->X_op = O_constant;
03610              exp->X_add_number = 0;
03611              exp->X_add_symbol = (symbolS *) 0;
03612              exp->X_op_symbol = (symbolS *) 0;
03613            }
03614        }
03615 
03616       /* Fill in i.rm.reg or i.rm.regmem field with register operand
03617         (if any) based on i.tm.extension_opcode.  Again, we must be
03618         careful to make sure that segment/control/debug/test/MMX
03619         registers are coded into the i.rm.reg field.  */
03620       if (i.reg_operands)
03621        {
03622          unsigned int op;
03623 
03624          for (op = 0; op < i.operands; op++)
03625            if ((i.types[op] & (Reg | RegMMX | RegXMM
03626                             | SReg2 | SReg3
03627                             | Control | Debug | Test)))
03628              break;
03629          assert (op < i.operands);
03630 
03631          /* If there is an extension opcode to put here, the register
03632             number must be put into the regmem field.  */
03633          if (i.tm.extension_opcode != None)
03634            {
03635              i.rm.regmem = i.op[op].regs->reg_num;
03636              if ((i.op[op].regs->reg_flags & RegRex) != 0)
03637               i.rex |= REX_B;
03638            }
03639          else
03640            {
03641              i.rm.reg = i.op[op].regs->reg_num;
03642              if ((i.op[op].regs->reg_flags & RegRex) != 0)
03643               i.rex |= REX_R;
03644            }
03645 
03646          /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
03647             must set it to 3 to indicate this is a register operand
03648             in the regmem field.  */
03649          if (!i.mem_operands)
03650            i.rm.mode = 3;
03651        }
03652 
03653       /* Fill in i.rm.reg field with extension opcode (if any).  */
03654       if (i.tm.extension_opcode != None)
03655        i.rm.reg = i.tm.extension_opcode;
03656     }
03657   return default_seg;
03658 }
03659 
03660 static void
03661 output_branch (void)
03662 {
03663   char *p;
03664   int code16;
03665   int prefix;
03666   relax_substateT subtype;
03667   symbolS *sym;
03668   offsetT off;
03669 
03670   code16 = 0;
03671   if (flag_code == CODE_16BIT)
03672     code16 = CODE16;
03673 
03674   prefix = 0;
03675   if (i.prefix[DATA_PREFIX] != 0)
03676     {
03677       prefix = 1;
03678       i.prefixes -= 1;
03679       code16 ^= CODE16;
03680     }
03681   /* Pentium4 branch hints.  */
03682   if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
03683       || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
03684     {
03685       prefix++;
03686       i.prefixes--;
03687     }
03688   if (i.prefix[REX_PREFIX] != 0)
03689     {
03690       prefix++;
03691       i.prefixes--;
03692     }
03693 
03694   if (i.prefixes != 0 && !intel_syntax)
03695     as_warn (_("skipping prefixes on this instruction"));
03696 
03697   /* It's always a symbol;  End frag & setup for relax.
03698      Make sure there is enough room in this frag for the largest
03699      instruction we may generate in md_convert_frag.  This is 2
03700      bytes for the opcode and room for the prefix and largest
03701      displacement.  */
03702   frag_grow (prefix + 2 + 4);
03703   /* Prefix and 1 opcode byte go in fr_fix.  */
03704   p = frag_more (prefix + 1);
03705   if (i.prefix[DATA_PREFIX] != 0)
03706     *p++ = DATA_PREFIX_OPCODE;
03707   if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
03708       || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
03709     *p++ = i.prefix[SEG_PREFIX];
03710   if (i.prefix[REX_PREFIX] != 0)
03711     *p++ = i.prefix[REX_PREFIX];
03712   *p = i.tm.base_opcode;
03713 
03714   if ((unsigned char) *p == JUMP_PC_RELATIVE)
03715     subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
03716   else if ((cpu_arch_flags & Cpu386) != 0)
03717     subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
03718   else
03719     subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
03720   subtype |= code16;
03721 
03722   sym = i.op[0].disps->X_add_symbol;
03723   off = i.op[0].disps->X_add_number;
03724 
03725   if (i.op[0].disps->X_op != O_constant
03726       && i.op[0].disps->X_op != O_symbol)
03727     {
03728       /* Handle complex expressions.  */
03729       sym = make_expr_symbol (i.op[0].disps);
03730       off = 0;
03731     }
03732 
03733   /* 1 possible extra opcode + 4 byte displacement go in var part.
03734      Pass reloc in fr_var.  */
03735   frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
03736 }
03737 
03738 static void
03739 output_jump (void)
03740 {
03741   char *p;
03742   int size;
03743   fixS *fixP;
03744 
03745   if (i.tm.opcode_modifier & JumpByte)
03746     {
03747       /* This is a loop or jecxz type instruction.  */
03748       size = 1;
03749       if (i.prefix[ADDR_PREFIX] != 0)
03750        {
03751          FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
03752          i.prefixes -= 1;
03753        }
03754       /* Pentium4 branch hints.  */
03755       if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
03756          || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
03757        {
03758          FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
03759          i.prefixes--;
03760        }
03761     }
03762   else
03763     {
03764       int code16;
03765 
03766       code16 = 0;
03767       if (flag_code == CODE_16BIT)
03768        code16 = CODE16;
03769 
03770       if (i.prefix[DATA_PREFIX] != 0)
03771        {
03772          FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
03773          i.prefixes -= 1;
03774          code16 ^= CODE16;
03775        }
03776 
03777       size = 4;
03778       if (code16)
03779        size = 2;
03780     }
03781 
03782   if (i.prefix[REX_PREFIX] != 0)
03783     {
03784       FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
03785       i.prefixes -= 1;
03786     }
03787 
03788   if (i.prefixes != 0 && !intel_syntax)
03789     as_warn (_("skipping prefixes on this instruction"));
03790 
03791   p = frag_more (1 + size);
03792   *p++ = i.tm.base_opcode;
03793 
03794   fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
03795                     i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
03796 
03797   /* All jumps handled here are signed, but don't use a signed limit
03798      check for 32 and 16 bit jumps as we want to allow wrap around at
03799      4G and 64k respectively.  */
03800   if (size == 1)
03801     fixP->fx_signed = 1;
03802 }
03803 
03804 static void
03805 output_interseg_jump (void)
03806 {
03807   char *p;
03808   int size;
03809   int prefix;
03810   int code16;
03811 
03812   code16 = 0;
03813   if (flag_code == CODE_16BIT)
03814     code16 = CODE16;
03815 
03816   prefix = 0;
03817   if (i.prefix[DATA_PREFIX] != 0)
03818     {
03819       prefix = 1;
03820       i.prefixes -= 1;
03821       code16 ^= CODE16;
03822     }
03823   if (i.prefix[REX_PREFIX] != 0)
03824     {
03825       prefix++;
03826       i.prefixes -= 1;
03827     }
03828 
03829   size = 4;
03830   if (code16)
03831     size = 2;
03832 
03833   if (i.prefixes != 0 && !intel_syntax)
03834     as_warn (_("skipping prefixes on this instruction"));
03835 
03836   /* 1 opcode; 2 segment; offset  */
03837   p = frag_more (prefix + 1 + 2 + size);
03838 
03839   if (i.prefix[DATA_PREFIX] != 0)
03840     *p++ = DATA_PREFIX_OPCODE;
03841 
03842   if (i.prefix[REX_PREFIX] != 0)
03843     *p++ = i.prefix[REX_PREFIX];
03844 
03845   *p++ = i.tm.base_opcode;
03846   if (i.op[1].imms->X_op == O_constant)
03847     {
03848       offsetT n = i.op[1].imms->X_add_number;
03849 
03850       if (size == 2
03851          && !fits_in_unsigned_word (n)
03852          && !fits_in_signed_word (n))
03853        {
03854          as_bad (_("16-bit jump out of range"));
03855          return;
03856        }
03857       md_number_to_chars (p, n, size);
03858     }
03859   else
03860     fix_new_exp (frag_now, p - frag_now->fr_literal, size,
03861                i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
03862   if (i.op[0].imms->X_op != O_constant)
03863     as_bad (_("can't handle non absolute segment in `%s'"),
03864            i.tm.name);
03865   md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
03866 }
03867 
03868 static void
03869 output_insn (void)
03870 {
03871   fragS *insn_start_frag;
03872   offsetT insn_start_off;
03873 
03874   /* Tie dwarf2 debug info to the address at the start of the insn.
03875      We can't do this after the insn has been output as the current
03876      frag may have been closed off.  eg. by frag_var.  */
03877   dwarf2_emit_insn (0);
03878 
03879   insn_start_frag = frag_now;
03880   insn_start_off = frag_now_fix ();
03881 
03882   /* Output jumps.  */
03883   if (i.tm.opcode_modifier & Jump)
03884     output_branch ();
03885   else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
03886     output_jump ();
03887   else if (i.tm.opcode_modifier & JumpInterSegment)
03888     output_interseg_jump ();
03889   else
03890     {
03891       /* Output normal instructions here.  */
03892       char *p;
03893       unsigned char *q;
03894       unsigned int prefix;
03895 
03896       /* All opcodes on i386 have either 1 or 2 bytes.  Supplemental
03897         Streaming SIMD extensions 3 Instructions have 3 bytes.  We may
03898         use one more higher byte to specify a prefix the instruction
03899         requires.  */
03900       if ((i.tm.cpu_flags & CpuSSSE3) != 0)
03901        {
03902          if (i.tm.base_opcode & 0xff000000)
03903            {
03904              prefix = (i.tm.base_opcode >> 24) & 0xff;
03905              goto check_prefix;
03906            }
03907        }
03908       else if ((i.tm.base_opcode & 0xff0000) != 0)
03909        {
03910          prefix = (i.tm.base_opcode >> 16) & 0xff;
03911          if ((i.tm.cpu_flags & CpuPadLock) != 0)
03912            {
03913            check_prefix:
03914              if (prefix != REPE_PREFIX_OPCODE
03915                 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
03916               add_prefix (prefix);
03917            }
03918          else
03919            add_prefix (prefix);
03920        }
03921 
03922       /* The prefix bytes.  */
03923       for (q = i.prefix;
03924           q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
03925           q++)
03926        {
03927          if (*q)
03928            {
03929              p = frag_more (1);
03930              md_number_to_chars (p, (valueT) *q, 1);
03931            }
03932        }
03933 
03934       /* Now the opcode; be careful about word order here!  */
03935       if (fits_in_unsigned_byte (i.tm.base_opcode))
03936        {
03937          FRAG_APPEND_1_CHAR (i.tm.base_opcode);
03938        }
03939       else
03940        {
03941          if ((i.tm.cpu_flags & CpuSSSE3) != 0)
03942            {
03943              p = frag_more (3);
03944              *p++ = (i.tm.base_opcode >> 16) & 0xff;
03945            }
03946          else
03947            p = frag_more (2);
03948 
03949          /* Put out high byte first: can't use md_number_to_chars!  */
03950          *p++ = (i.tm.base_opcode >> 8) & 0xff;
03951          *p = i.tm.base_opcode & 0xff;
03952        }
03953 
03954       /* Now the modrm byte and sib byte (if present).  */
03955       if (i.tm.opcode_modifier & Modrm)
03956        {
03957          p = frag_more (1);
03958          md_number_to_chars (p,
03959                            (valueT) (i.rm.regmem << 0
03960                                    | i.rm.reg << 3
03961                                    | i.rm.mode << 6),
03962                            1);
03963          /* If i.rm.regmem == ESP (4)
03964             && i.rm.mode != (Register mode)
03965             && not 16 bit
03966             ==> need second modrm byte.  */
03967          if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
03968              && i.rm.mode != 3
03969              && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
03970            {
03971              p = frag_more (1);
03972              md_number_to_chars (p,
03973                               (valueT) (i.sib.base << 0
03974                                        | i.sib.index << 3
03975                                        | i.sib.scale << 6),
03976                               1);
03977            }
03978        }
03979 
03980       if (i.disp_operands)
03981        output_disp (insn_start_frag, insn_start_off);
03982 
03983       if (i.imm_operands)
03984        output_imm (insn_start_frag, insn_start_off);
03985     }
03986 
03987 #ifdef DEBUG386
03988   if (flag_debug)
03989     {
03990       pi ("" /*line*/, &i);
03991     }
03992 #endif /* DEBUG386  */
03993 }
03994 
03995 static void
03996 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
03997 {
03998   char *p;
03999   unsigned int n;
04000 
04001   for (n = 0; n < i.operands; n++)
04002     {
04003       if (i.types[n] & Disp)
04004        {
04005          if (i.op[n].disps->X_op == O_constant)
04006            {
04007              int size;
04008              offsetT val;
04009 
04010              size = 4;
04011              if (i.types[n] & (Disp8 | Disp16 | Disp64))
04012               {
04013                 size = 2;
04014                 if (i.types[n] & Disp8)
04015                   size = 1;
04016                 if (i.types[n] & Disp64)
04017                   size = 8;
04018               }
04019              val = offset_in_range (i.op[n].disps->X_add_number,
04020                                  size);
04021              p = frag_more (size);
04022              md_number_to_chars (p, val, size);
04023            }
04024          else
04025            {
04026              enum bfd_reloc_code_real reloc_type;
04027              int size = 4;
04028              int sign = 0;
04029              int pcrel = (i.flags[n] & Operand_PCrel) != 0;
04030 
04031              /* The PC relative address is computed relative
04032                to the instruction boundary, so in case immediate
04033                fields follows, we need to adjust the value.  */
04034              if (pcrel && i.imm_operands)
04035               {
04036                 int imm_size = 4;
04037                 unsigned int n1;
04038 
04039                 for (n1 = 0; n1 < i.operands; n1++)
04040                   if (i.types[n1] & Imm)
04041                     {
04042                      if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
04043                        {
04044                          imm_size = 2;
04045                          if (i.types[n1] & (Imm8 | Imm8S))
04046                            imm_size = 1;
04047                          if (i.types[n1] & Imm64)
04048                            imm_size = 8;
04049                        }
04050                      break;
04051                     }
04052                 /* We should find the immediate.  */
04053                 if (n1 == i.operands)
04054                   abort ();
04055                 i.op[n].disps->X_add_number -= imm_size;
04056               }
04057 
04058              if (i.types[n] & Disp32S)
04059               sign = 1;
04060 
04061              if (i.types[n] & (Disp16 | Disp64))
04062               {
04063                 size = 2;
04064                 if (i.types[n] & Disp64)
04065                   size = 8;
04066               }
04067 
04068              p = frag_more (size);
04069              reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
04070              if (GOT_symbol
04071                 && GOT_symbol == i.op[n].disps->X_add_symbol
04072                 && (((reloc_type == BFD_RELOC_32
04073                      || reloc_type == BFD_RELOC_X86_64_32S
04074                      || (reloc_type == BFD_RELOC_64
04075                          && object_64bit))
04076                      && (i.op[n].disps->X_op == O_symbol
04077                         || (i.op[n].disps->X_op == O_add
04078                             && ((symbol_get_value_expression
04079                                 (i.op[n].disps->X_op_symbol)->X_op)
04080                                == O_subtract))))
04081                     || reloc_type == BFD_RELOC_32_PCREL))
04082               {
04083                 offsetT add;
04084 
04085                 if (insn_start_frag == frag_now)
04086                   add = (p - frag_now->fr_literal) - insn_start_off;
04087                 else
04088                   {
04089                     fragS *fr;
04090 
04091                     add = insn_start_frag->fr_fix - insn_start_off;
04092                     for (fr = insn_start_frag->fr_next;
04093                         fr && fr != frag_now; fr = fr->fr_next)
04094                      add += fr->fr_fix;
04095                     add += p - frag_now->fr_literal;
04096                   }
04097 
04098                 if (!object_64bit)
04099                   {
04100                     reloc_type = BFD_RELOC_386_GOTPC;
04101                     i.op[n].imms->X_add_number += add;
04102                   }
04103                 else if (reloc_type == BFD_RELOC_64)
04104                   reloc_type = BFD_RELOC_X86_64_GOTPC64;
04105                 else
04106                   /* Don't do the adjustment for x86-64, as there
04107                      the pcrel addressing is relative to the _next_
04108                      insn, and that is taken care of in other code.  */
04109                   reloc_type = BFD_RELOC_X86_64_GOTPC32;
04110               }
04111              fix_new_exp (frag_now, p - frag_now->fr_literal, size,
04112                         i.op[n].disps, pcrel, reloc_type);
04113            }
04114        }
04115     }
04116 }
04117 
04118 static void
04119 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
04120 {
04121   char *p;
04122   unsigned int n;
04123 
04124   for (n = 0; n < i.operands; n++)
04125     {
04126       if (i.types[n] & Imm)
04127        {
04128          if (i.op[n].imms->X_op == O_constant)
04129            {
04130              int size;
04131              offsetT val;
04132 
04133              size = 4;
04134              if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
04135               {
04136                 size = 2;
04137                 if (i.types[n] & (Imm8 | Imm8S))
04138                   size = 1;
04139                 else if (i.types[n] & Imm64)
04140                   size = 8;
04141               }
04142              val = offset_in_range (i.op[n].imms->X_add_number,
04143                                  size);
04144              p = frag_more (size);
04145              md_number_to_chars (p, val, size);
04146            }
04147          else
04148            {
04149              /* Not absolute_section.
04150                Need a 32-bit fixup (don't support 8bit
04151                non-absolute imms).  Try to support other
04152                sizes ...  */
04153              enum bfd_reloc_code_real reloc_type;
04154              int size = 4;
04155              int sign = 0;
04156 
04157              if ((i.types[n] & (Imm32S))
04158                 && (i.suffix == QWORD_MNEM_SUFFIX
04159                     || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
04160               sign = 1;
04161              if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
04162               {
04163                 size = 2;
04164                 if (i.types[n] & (Imm8 | Imm8S))
04165                   size = 1;
04166                 if (i.types[n] & Imm64)
04167                   size = 8;
04168               }
04169 
04170              p = frag_more (size);
04171              reloc_type = reloc (size, 0, sign, i.reloc[n]);
04172 
04173              /*   This is tough to explain.  We end up with this one if we
04174               * have operands that look like
04175               * "_GLOBAL_OFFSET_TABLE_+[.-.L284]".  The goal here is to
04176               * obtain the absolute address of the GOT, and it is strongly
04177               * preferable from a performance point of view to avoid using
04178               * a runtime relocation for this.  The actual sequence of
04179               * instructions often look something like:
04180               *
04181               *      call   .L66
04182               * .L66:
04183               *      popl   %ebx
04184               *      addl   $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
04185               *
04186               *   The call and pop essentially return the absolute address
04187               * of the label .L66 and store it in %ebx.  The linker itself
04188               * will ultimately change the first operand of the addl so
04189               * that %ebx points to the GOT, but to keep things simple, the
04190               * .o file must have this operand set so that it generates not
04191               * the absolute address of .L66, but the absolute address of
04192               * itself.  This allows the linker itself simply treat a GOTPC
04193               * relocation as asking for a pcrel offset to the GOT to be
04194               * added in, and the addend of the relocation is stored in the
04195               * operand field for the instruction itself.
04196               *
04197               *   Our job here is to fix the operand so that it would add
04198               * the correct offset so that %ebx would point to itself.  The
04199               * thing that is tricky is that .-.L66 will point to the
04200               * beginning of the instruction, so we need to further modify
04201               * the operand so that it will point to itself.  There are
04202               * other cases where you have something like:
04203               *
04204               *      .long  $_GLOBAL_OFFSET_TABLE_+[.-.L66]
04205               *
04206               * and here no correction would be required.  Internally in
04207               * the assembler we treat operands of this form as not being
04208               * pcrel since the '.' is explicitly mentioned, and I wonder
04209               * whether it would simplify matters to do it this way.  Who
04210               * knows.  In earlier versions of the PIC patches, the
04211               * pcrel_adjust field was used to store the correction, but
04212               * since the expression is not pcrel, I felt it would be
04213               * confusing to do it this way.  */
04214 
04215              if ((reloc_type == BFD_RELOC_32
04216                  || reloc_type == BFD_RELOC_X86_64_32S
04217                  || reloc_type == BFD_RELOC_64)
04218                 && GOT_symbol
04219                 && GOT_symbol == i.op[n].imms->X_add_symbol
04220                 && (i.op[n].imms->X_op == O_symbol
04221                     || (i.op[n].imms->X_op == O_add
04222                        && ((symbol_get_value_expression
04223                             (i.op[n].imms->X_op_symbol)->X_op)
04224                            == O_subtract))))
04225               {
04226                 offsetT add;
04227 
04228                 if (insn_start_frag == frag_now)
04229                   add = (p - frag_now->fr_literal) - insn_start_off;
04230                 else
04231                   {
04232                     fragS *fr;
04233 
04234                     add = insn_start_frag->fr_fix - insn_start_off;
04235                     for (fr = insn_start_frag->fr_next;
04236                         fr && fr != frag_now; fr = fr->fr_next)
04237                      add += fr->fr_fix;
04238                     add += p - frag_now->fr_literal;
04239                   }
04240 
04241                 if (!object_64bit)
04242                   reloc_type = BFD_RELOC_386_GOTPC;
04243                 else if (size == 4)
04244                   reloc_type = BFD_RELOC_X86_64_GOTPC32;
04245                 else if (size == 8)
04246                   reloc_type = BFD_RELOC_X86_64_GOTPC64;
04247                 i.op[n].imms->X_add_number += add;
04248               }
04249              fix_new_exp (frag_now, p - frag_now->fr_literal, size,
04250                         i.op[n].imms, 0, reloc_type);
04251            }
04252        }
04253     }
04254 }
04255 
04256 /* x86_cons_fix_new is called via the expression parsing code when a
04257    reloc is needed.  We use this hook to get the correct .got reloc.  */
04258 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
04259 static int cons_sign = -1;
04260 
04261 void
04262 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
04263                 expressionS *exp)
04264 {
04265   enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
04266 
04267   got_reloc = NO_RELOC;
04268 
04269 #ifdef TE_PE
04270   if (exp->X_op == O_secrel)
04271     {
04272       exp->X_op = O_symbol;
04273       r = BFD_RELOC_32_SECREL;
04274     }
04275 #endif
04276 
04277   fix_new_exp (frag, off, len, exp, 0, r);
04278 }
04279 
04280 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
04281 # define lex_got(reloc, adjust, types) NULL
04282 #else
04283 /* Parse operands of the form
04284    <symbol>@GOTOFF+<nnn>
04285    and similar .plt or .got references.
04286 
04287    If we find one, set up the correct relocation in RELOC and copy the
04288    input string, minus the `@GOTOFF' into a malloc'd buffer for
04289    parsing by the calling routine.  Return this buffer, and if ADJUST
04290    is non-null set it to the length of the string we removed from the
04291    input line.  Otherwise return NULL.  */
04292 static char *
04293 lex_got (enum bfd_reloc_code_real *reloc,
04294         int *adjust,
04295         unsigned int *types)
04296 {
04297   /* Some of the relocations depend on the size of what field is to
04298      be relocated.  But in our callers i386_immediate and i386_displacement
04299      we don't yet know the operand size (this will be set by insn
04300      matching).  Hence we record the word32 relocation here,
04301      and adjust the reloc according to the real size in reloc().  */
04302   static const struct {
04303     const char *str;
04304     const enum bfd_reloc_code_real rel[2];
04305     const unsigned int types64;
04306   } gotrel[] = {
04307     { "PLTOFF",   { 0,
04308                   BFD_RELOC_X86_64_PLTOFF64 },
04309       Imm64 },
04310     { "PLT",      { BFD_RELOC_386_PLT32,
04311                   BFD_RELOC_X86_64_PLT32    },
04312       Imm32 | Imm32S | Disp32 },
04313     { "GOTPLT",   { 0,
04314                   BFD_RELOC_X86_64_GOTPLT64 },
04315       Imm64 | Disp64 },
04316     { "GOTOFF",   { BFD_RELOC_386_GOTOFF,
04317                   BFD_RELOC_X86_64_GOTOFF64 },
04318       Imm64 | Disp64 },
04319     { "GOTPCREL", { 0,
04320                   BFD_RELOC_X86_64_GOTPCREL },
04321       Imm32 | Imm32S | Disp32 },
04322     { "TLSGD",    { BFD_RELOC_386_TLS_GD,
04323                   BFD_RELOC_X86_64_TLSGD    },
04324       Imm32 | Imm32S | Disp32 },
04325     { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,
04326                   0                         },
04327       0 },
04328     { "TLSLD",    { 0,
04329                   BFD_RELOC_X86_64_TLSLD    },
04330       Imm32 | Imm32S | Disp32 },
04331     { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
04332                   BFD_RELOC_X86_64_GOTTPOFF },
04333       Imm32 | Imm32S | Disp32 },
04334     { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,
04335                   BFD_RELOC_X86_64_TPOFF32  },
04336       Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
04337     { "NTPOFF",   { BFD_RELOC_386_TLS_LE,
04338                   0                         },
04339       0 },
04340     { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32,
04341                   BFD_RELOC_X86_64_DTPOFF32 },
04342       Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
04343     { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
04344                   0                         },
04345       0 },
04346     { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
04347                   0                         },
04348       0 },
04349     { "GOT",      { BFD_RELOC_386_GOT32,
04350                   BFD_RELOC_X86_64_GOT32    },
04351       Imm32 | Imm32S | Disp32 | Imm64 },
04352     { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC,
04353                   BFD_RELOC_X86_64_GOTPC32_TLSDESC },
04354       Imm32 | Imm32S | Disp32 },
04355     { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL,
04356                   BFD_RELOC_X86_64_TLSDESC_CALL },
04357       Imm32 | Imm32S | Disp32 }
04358   };
04359   char *cp;
04360   unsigned int j;
04361 
04362   if (!IS_ELF)
04363     return NULL;
04364 
04365   for (cp = input_line_pointer; *cp != '@'; cp++)
04366     if (is_end_of_line[(unsigned char) *cp])
04367       return NULL;
04368 
04369   for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
04370     {
04371       int len;
04372 
04373       len = strlen (gotrel[j].str);
04374       if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
04375        {
04376          if (gotrel[j].rel[object_64bit] != 0)
04377            {
04378              int first, second;
04379              char *tmpbuf, *past_reloc;
04380 
04381              *reloc = gotrel[j].rel[object_64bit];
04382              if (adjust)
04383               *adjust = len;
04384 
04385              if (types)
04386               {
04387                 if (flag_code != CODE_64BIT)
04388                   *types = Imm32 | Disp32;
04389                 else
04390                   *types = gotrel[j].types64;
04391               }
04392 
04393              if (GOT_symbol == NULL)
04394               GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
04395 
04396              /* Replace the relocation token with ' ', so that
04397                errors like foo@GOTOFF1 will be detected.  */
04398 
04399              /* The length of the first part of our input line.  */
04400              first = cp - input_line_pointer;
04401 
04402              /* The second part goes from after the reloc token until
04403                (and including) an end_of_line char.  Don't use strlen
04404                here as the end_of_line char may not be a NUL.  */
04405              past_reloc = cp + 1 + len;
04406              for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
04407               ;
04408              second = cp - past_reloc;
04409 
04410              /* Allocate and copy string.  The trailing NUL shouldn't
04411                be necessary, but be safe.  */
04412              tmpbuf = xmalloc (first + second + 2);
04413              memcpy (tmpbuf, input_line_pointer, first);
04414              tmpbuf[first] = ' ';
04415              memcpy (tmpbuf + first + 1, past_reloc, second);
04416              tmpbuf[first + second + 1] = '\0';
04417              return tmpbuf;
04418            }
04419 
04420          as_bad (_("@%s reloc is not supported with %d-bit output format"),
04421                 gotrel[j].str, 1 << (5 + object_64bit));
04422          return NULL;
04423        }
04424     }
04425 
04426   /* Might be a symbol version string.  Don't as_bad here.  */
04427   return NULL;
04428 }
04429 
04430 void
04431 x86_cons (expressionS *exp, int size)
04432 {
04433   if (size == 4 || (object_64bit && size == 8))
04434     {
04435       /* Handle @GOTOFF and the like in an expression.  */
04436       char *save;
04437       char *gotfree_input_line;
04438       int adjust;
04439 
04440       save = input_line_pointer;
04441       gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
04442       if (gotfree_input_line)
04443        input_line_pointer = gotfree_input_line;
04444 
04445       expression (exp);
04446 
04447       if (gotfree_input_line)
04448        {
04449          /* expression () has merrily parsed up to the end of line,
04450             or a comma - in the wrong buffer.  Transfer how far
04451             input_line_pointer has moved to the right buffer.  */
04452          input_line_pointer = (save
04453                             + (input_line_pointer - gotfree_input_line)
04454                             + adjust);
04455          free (gotfree_input_line);
04456        }
04457     }
04458   else
04459     expression (exp);
04460 }
04461 #endif
04462 
04463 static void signed_cons (int size)
04464 {
04465   if (flag_code == CODE_64BIT)
04466     cons_sign = 1;
04467   cons (size);
04468   cons_sign = -1;
04469 }
04470 
04471 #ifdef TE_PE
04472 static void
04473 pe_directive_secrel (dummy)
04474      int dummy ATTRIBUTE_UNUSED;
04475 {
04476   expressionS exp;
04477 
04478   do
04479     {
04480       expression (&exp);
04481       if (exp.X_op == O_symbol)
04482        exp.X_op = O_secrel;
04483 
04484       emit_expr (&exp, 4);
04485     }
04486   while (*input_line_pointer++ == ',');
04487 
04488   input_line_pointer--;
04489   demand_empty_rest_of_line ();
04490 }
04491 #endif
04492 
04493 static int
04494 i386_immediate (char *imm_start)
04495 {
04496   char *save_input_line_pointer;
04497   char *gotfree_input_line;
04498   segT exp_seg = 0;
04499   expressionS *exp;
04500   unsigned int types = ~0U;
04501 
04502   if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
04503     {
04504       as_bad (_("at most %d immediate operands are allowed"),
04505              MAX_IMMEDIATE_OPERANDS);
04506       return 0;
04507     }
04508 
04509   exp = &im_expressions[i.imm_operands++];
04510   i.op[this_operand].imms = exp;
04511 
04512   if (is_space_char (*imm_start))
04513     ++imm_start;
04514 
04515   save_input_line_pointer = input_line_pointer;
04516   input_line_pointer = imm_start;
04517 
04518   gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
04519   if (gotfree_input_line)
04520     input_line_pointer = gotfree_input_line;
04521 
04522   exp_seg = expression (exp);
04523 
04524   SKIP_WHITESPACE ();
04525   if (*input_line_pointer)
04526     as_bad (_("junk `%s' after expression"), input_line_pointer);
04527 
04528   input_line_pointer = save_input_line_pointer;
04529   if (gotfree_input_line)
04530     free (gotfree_input_line);
04531 
04532   if (exp->X_op == O_absent || exp->X_op == O_big)
04533     {
04534       /* Missing or bad expr becomes absolute 0.  */
04535       as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
04536              imm_start);
04537       exp->X_op = O_constant;
04538       exp->X_add_number = 0;
04539       exp->X_add_symbol = (symbolS *) 0;
04540       exp->X_op_symbol = (symbolS *) 0;
04541     }
04542   else if (exp->X_op == O_constant)
04543     {
04544       /* Size it properly later.  */
04545       i.types[this_operand] |= Imm64;
04546       /* If BFD64, sign extend val.  */
04547       if (!use_rela_relocations
04548          && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
04549        exp->X_add_number
04550          = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
04551     }
04552 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
04553   else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
04554           && exp_seg != absolute_section
04555           && exp_seg != text_section
04556           && exp_seg != data_section
04557           && exp_seg != bss_section
04558           && exp_seg != undefined_section
04559           && !bfd_is_com_section (exp_seg))
04560     {
04561       as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
04562       return 0;
04563     }
04564 #endif
04565   else if (!intel_syntax && exp->X_op == O_register)
04566     {
04567       as_bad (_("illegal immediate register operand %s"), imm_start);
04568       return 0;
04569     }
04570   else
04571     {
04572       /* This is an address.  The size of the address will be
04573         determined later, depending on destination register,
04574         suffix, or the default for the section.  */
04575       i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
04576       i.types[this_operand] &= types;
04577     }
04578 
04579   return 1;
04580 }
04581 
04582 static char *
04583 i386_scale (char *scale)
04584 {
04585   offsetT val;
04586   char *save = input_line_pointer;
04587 
04588   input_line_pointer = scale;
04589   val = get_absolute_expression ();
04590 
04591   switch (val)
04592     {
04593     case 1:
04594       i.log2_scale_factor = 0;
04595       break;
04596     case 2:
04597       i.log2_scale_factor = 1;
04598       break;
04599     case 4:
04600       i.log2_scale_factor = 2;
04601       break;
04602     case 8:
04603       i.log2_scale_factor = 3;
04604       break;
04605     default:
04606       {
04607        char sep = *input_line_pointer;
04608 
04609        *input_line_pointer = '\0';
04610        as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
04611               scale);
04612        *input_line_pointer = sep;
04613        input_line_pointer = save;
04614        return NULL;
04615       }
04616     }
04617   if (i.log2_scale_factor != 0 && i.index_reg == 0)
04618     {
04619       as_warn (_("scale factor of %d without an index register"),
04620               1 << i.log2_scale_factor);
04621 #if SCALE1_WHEN_NO_INDEX
04622       i.log2_scale_factor = 0;
04623 #endif
04624     }
04625   scale = input_line_pointer;
04626   input_line_pointer = save;
04627   return scale;
04628 }
04629 
04630 static int
04631 i386_displacement (char *disp_start, char *disp_end)
04632 {
04633   expressionS *exp;
04634   segT exp_seg = 0;
04635   char *save_input_line_pointer;
04636   char *gotfree_input_line;
04637   int bigdisp, override;
04638   unsigned int types = Disp;
04639 
04640   if (i.disp_operands == MAX_MEMORY_OPERANDS)
04641     {
04642       as_bad (_("at most %d displacement operands are allowed"),
04643              MAX_MEMORY_OPERANDS);
04644       return 0;
04645     }
04646 
04647   if ((i.types[this_operand] & JumpAbsolute)
04648       || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
04649     {
04650       bigdisp = Disp32;
04651       override = (i.prefix[ADDR_PREFIX] != 0);
04652     }
04653   else
04654     {
04655       /* For PC-relative branches, the width of the displacement
04656         is dependent upon data size, not address size.  */
04657       bigdisp = 0;
04658       override = (i.prefix[DATA_PREFIX] != 0);
04659     }
04660   if (flag_code == CODE_64BIT)
04661     {
04662       if (!bigdisp)
04663        bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
04664                  ? Disp16
04665                  : Disp32S | Disp32);
04666       else if (!override)
04667        bigdisp = Disp64 | Disp32S | Disp32;
04668     }
04669   else
04670     {
04671       if (!bigdisp)
04672        {
04673          if (!override)
04674            override = (i.suffix == (flag_code != CODE_16BIT
04675                                  ? WORD_MNEM_SUFFIX
04676                                  : LONG_MNEM_SUFFIX));
04677          bigdisp = Disp32;
04678        }
04679       if ((flag_code == CODE_16BIT) ^ override)
04680        bigdisp = Disp16;
04681     }
04682   i.types[this_operand] |= bigdisp;
04683 
04684   exp = &disp_expressions[i.disp_operands];
04685   i.op[this_operand].disps = exp;
04686   i.disp_operands++;
04687   save_input_line_pointer = input_line_pointer;
04688   input_line_pointer = disp_start;
04689   END_STRING_AND_SAVE (disp_end);
04690 
04691 #ifndef GCC_ASM_O_HACK
04692 #define GCC_ASM_O_HACK 0
04693 #endif
04694 #if GCC_ASM_O_HACK
04695   END_STRING_AND_SAVE (disp_end + 1);
04696   if ((i.types[this_operand] & BaseIndex) != 0
04697       && displacement_string_end[-1] == '+')
04698     {
04699       /* This hack is to avoid a warning when using the "o"
04700         constraint within gcc asm statements.
04701         For instance:
04702 
04703         #define _set_tssldt_desc(n,addr,limit,type) \
04704         __asm__ __volatile__ ( \
04705         "movw %w2,%0\n\t" \
04706         "movw %w1,2+%0\n\t" \
04707         "rorl $16,%1\n\t" \
04708         "movb %b1,4+%0\n\t" \
04709         "movb %4,5+%0\n\t" \
04710         "movb $0,6+%0\n\t" \
04711         "movb %h1,7+%0\n\t" \
04712         "rorl $16,%1" \
04713         : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
04714 
04715         This works great except that the output assembler ends
04716         up looking a bit weird if it turns out that there is
04717         no offset.  You end up producing code that looks like:
04718 
04719         #APP
04720         movw $235,(%eax)
04721         movw %dx,2+(%eax)
04722         rorl $16,%edx
04723         movb %dl,4+(%eax)
04724         movb $137,5+(%eax)
04725         movb $0,6+(%eax)
04726         movb %dh,7+(%eax)
04727         rorl $16,%edx
04728         #NO_APP
04729 
04730         So here we provide the missing zero.  */
04731 
04732       *displacement_string_end = '0';
04733     }
04734 #endif
04735   gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
04736   if (gotfree_input_line)
04737     input_line_pointer = gotfree_input_line;
04738 
04739   exp_seg = expression (exp);
04740 
04741   SKIP_WHITESPACE ();
04742   if (*input_line_pointer)
04743     as_bad (_("junk `%s' after expression"), input_line_pointer);
04744 #if GCC_ASM_O_HACK
04745   RESTORE_END_STRING (disp_end + 1);
04746 #endif
04747   RESTORE_END_STRING (disp_end);
04748   input_line_pointer = save_input_line_pointer;
04749   if (gotfree_input_line)
04750     free (gotfree_input_line);
04751 
04752   /* We do this to make sure that the section symbol is in
04753      the symbol table.  We will ultimately change the relocation
04754      to be relative to the beginning of the section.  */
04755   if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
04756       || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
04757       || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
04758     {
04759       if (exp->X_op != O_symbol)
04760        {
04761          as_bad (_("bad expression used with @%s"),
04762                 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
04763                  ? "GOTPCREL"
04764                  : "GOTOFF"));
04765          return 0;
04766        }
04767 
04768       if (S_IS_LOCAL (exp->X_add_symbol)
04769          && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
04770        section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
04771       exp->X_op = O_subtract;
04772       exp->X_op_symbol = GOT_symbol;
04773       if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
04774        i.reloc[this_operand] = BFD_RELOC_32_PCREL;
04775       else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
04776        i.reloc[this_operand] = BFD_RELOC_64;
04777       else
04778        i.reloc[this_operand] = BFD_RELOC_32;
04779     }
04780 
04781   if (exp->X_op == O_absent || exp->X_op == O_big)
04782     {
04783       /* Missing or bad expr becomes absolute 0.  */
04784       as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
04785              disp_start);
04786       exp->X_op = O_constant;
04787       exp->X_add_number = 0;
04788       exp->X_add_symbol = (symbolS *) 0;
04789       exp->X_op_symbol = (symbolS *) 0;
04790     }
04791 
04792 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
04793   if (exp->X_op != O_constant
04794       && OUTPUT_FLAVOR == bfd_target_aout_flavour
04795       && exp_seg != absolute_section
04796       && exp_seg != text_section
04797       && exp_seg != data_section
04798       && exp_seg != bss_section
04799       && exp_seg != undefined_section
04800       && !bfd_is_com_section (exp_seg))
04801     {
04802       as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
04803       return 0;
04804     }
04805 #endif
04806 
04807   if (!(i.types[this_operand] & ~Disp))
04808     i.types[this_operand] &= types;
04809 
04810   return 1;
04811 }
04812 
04813 /* Make sure the memory operand we've been dealt is valid.
04814    Return 1 on success, 0 on a failure.  */
04815 
04816 static int
04817 i386_index_check (const char *operand_string)
04818 {
04819   int ok;
04820 #if INFER_ADDR_PREFIX
04821   int fudged = 0;
04822 
04823  tryprefix:
04824 #endif
04825   ok = 1;
04826   if ((current_templates->start->cpu_flags & CpuSVME)
04827       && current_templates->end[-1].operand_types[0] == AnyMem)
04828     {
04829       /* Memory operands of SVME insns are special in that they only allow
04830         rAX as their memory address and ignore any segment override.  */
04831       unsigned RegXX;
04832 
04833       /* SKINIT is even more restrictive: it always requires EAX.  */
04834       if (strcmp (current_templates->start->name, "skinit") == 0)
04835        RegXX = Reg32;
04836       else if (flag_code == CODE_64BIT)
04837        RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
04838       else
04839        RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
04840                ? Reg16
04841                : Reg32);
04842       if (!i.base_reg
04843          || !(i.base_reg->reg_type & Acc)
04844          || !(i.base_reg->reg_type & RegXX)
04845          || i.index_reg
04846          || (i.types[0] & Disp))
04847        ok = 0;
04848     }
04849   else if (flag_code == CODE_64BIT)
04850     {
04851       unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
04852 
04853       if ((i.base_reg
04854           && ((i.base_reg->reg_type & RegXX) == 0)
04855           && (i.base_reg->reg_type != BaseIndex
04856               || i.index_reg))
04857          || (i.index_reg
04858              && ((i.index_reg->reg_type & (RegXX | BaseIndex))
04859                 != (RegXX | BaseIndex))))
04860        ok = 0;
04861     }
04862   else
04863     {
04864       if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
04865        {
04866          /* 16bit checks.  */
04867          if ((i.base_reg
04868               && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
04869                  != (Reg16 | BaseIndex)))
04870              || (i.index_reg
04871                 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
04872                      != (Reg16 | BaseIndex))
04873                     || !(i.base_reg
04874                         && i.base_reg->reg_num < 6
04875                         && i.index_reg->reg_num >= 6
04876                         && i.log2_scale_factor == 0))))
04877            ok = 0;
04878        }
04879       else
04880        {
04881          /* 32bit checks.  */
04882          if ((i.base_reg
04883               && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
04884              || (i.index_reg
04885                 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
04886                     != (Reg32 | BaseIndex))))
04887            ok = 0;
04888        }
04889     }
04890   if (!ok)
04891     {
04892 #if INFER_ADDR_PREFIX
04893       if (i.prefix[ADDR_PREFIX] == 0)
04894        {
04895          i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
04896          i.prefixes += 1;
04897          /* Change the size of any displacement too.  At most one of
04898             Disp16 or Disp32 is set.
04899             FIXME.  There doesn't seem to be any real need for separate
04900             Disp16 and Disp32 flags.  The same goes for Imm16 and Imm32.
04901             Removing them would probably clean up the code quite a lot.  */
04902          if (flag_code != CODE_64BIT
04903              && (i.types[this_operand] & (Disp16 | Disp32)))
04904            i.types[this_operand] ^= (Disp16 | Disp32);
04905          fudged = 1;
04906          goto tryprefix;
04907        }
04908       if (fudged)
04909        as_bad (_("`%s' is not a valid base/index expression"),
04910               operand_string);
04911       else
04912 #endif
04913        as_bad (_("`%s' is not a valid %s bit base/index expression"),
04914               operand_string,
04915               flag_code_names[flag_code]);
04916     }
04917   return ok;
04918 }
04919 
04920 /* Parse OPERAND_STRING into the i386_insn structure I.  Returns non-zero
04921    on error.  */
04922 
04923 static int
04924 i386_operand (char *operand_string)
04925 {
04926   const reg_entry *r;
04927   char *end_op;
04928   char *op_string = operand_string;
04929 
04930   if (is_space_char (*op_string))
04931     ++op_string;
04932 
04933   /* We check for an absolute prefix (differentiating,
04934      for example, 'jmp pc_relative_label' from 'jmp *absolute_label'.  */
04935   if (*op_string == ABSOLUTE_PREFIX)
04936     {
04937       ++op_string;
04938       if (is_space_char (*op_string))
04939        ++op_string;
04940       i.types[this_operand] |= JumpAbsolute;
04941     }
04942 
04943   /* Check if operand is a register.  */
04944   if ((r = parse_register (op_string, &end_op)) != NULL)
04945     {
04946       /* Check for a segment override by searching for ':' after a
04947         segment register.  */
04948       op_string = end_op;
04949       if (is_space_char (*op_string))
04950        ++op_string;
04951       if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
04952        {
04953          switch (r->reg_num)
04954            {
04955            case 0:
04956              i.seg[i.mem_operands] = &es;
04957              break;
04958            case 1:
04959              i.seg[i.mem_operands] = &cs;
04960              break;
04961            case 2:
04962              i.seg[i.mem_operands] = &ss;
04963              break;
04964            case 3:
04965              i.seg[i.mem_operands] = &ds;
04966              break;
04967            case 4:
04968              i.seg[i.mem_operands] = &fs;
04969              break;
04970            case 5:
04971              i.seg[i.mem_operands] = &gs;
04972              break;
04973            }
04974 
04975          /* Skip the ':' and whitespace.  */
04976          ++op_string;
04977          if (is_space_char (*op_string))
04978            ++op_string;
04979 
04980          if (!is_digit_char (*op_string)
04981              && !is_identifier_char (*op_string)
04982              && *op_string != '('
04983              && *op_string != ABSOLUTE_PREFIX)
04984            {
04985              as_bad (_("bad memory operand `%s'"), op_string);
04986              return 0;
04987            }
04988          /* Handle case of %es:*foo.  */
04989          if (*op_string == ABSOLUTE_PREFIX)
04990            {
04991              ++op_string;
04992              if (is_space_char (*op_string))
04993               ++op_string;
04994              i.types[this_operand] |= JumpAbsolute;
04995            }
04996          goto do_memory_reference;
04997        }
04998       if (*op_string)
04999        {
05000          as_bad (_("junk `%s' after register"), op_string);
05001          return 0;
05002        }
05003       i.types[this_operand] |= r->reg_type & ~BaseIndex;
05004       i.op[this_operand].regs = r;
05005       i.reg_operands++;
05006     }
05007   else if (*op_string == REGISTER_PREFIX)
05008     {
05009       as_bad (_("bad register name `%s'"), op_string);
05010       return 0;
05011     }
05012   else if (*op_string == IMMEDIATE_PREFIX)
05013     {
05014       ++op_string;
05015       if (i.types[this_operand] & JumpAbsolute)
05016        {
05017          as_bad (_("immediate operand illegal with absolute jump"));
05018          return 0;
05019        }
05020       if (!i386_immediate (op_string))
05021        return 0;
05022     }
05023   else if (is_digit_char (*op_string)
05024           || is_identifier_char (*op_string)
05025           || *op_string == '(')
05026     {
05027       /* This is a memory reference of some sort.  */
05028       char *base_string;
05029 
05030       /* Start and end of displacement string expression (if found).  */
05031       char *displacement_string_start;
05032       char *displacement_string_end;
05033 
05034     do_memory_reference:
05035       if ((i.mem_operands == 1
05036           && (current_templates->start->opcode_modifier & IsString) == 0)
05037          || i.mem_operands == 2)
05038        {
05039          as_bad (_("too many memory references for `%s'"),
05040                 current_templates->start->name);
05041          return 0;
05042        }
05043 
05044       /* Check for base index form.  We detect the base index form by
05045         looking for an ')' at the end of the operand, searching
05046         for the '(' matching it, and finding a REGISTER_PREFIX or ','
05047         after the '('.  */
05048       base_string = op_string + strlen (op_string);
05049 
05050       --base_string;
05051       if (is_space_char (*base_string))
05052        --base_string;
05053 
05054       /* If we only have a displacement, set-up for it to be parsed later.  */
05055       displacement_string_start = op_string;
05056       displacement_string_end = base_string + 1;
05057 
05058       if (*base_string == ')')
05059        {
05060          char *temp_string;
05061          unsigned int parens_balanced = 1;
05062          /* We've already checked that the number of left & right ()'s are
05063             equal, so this loop will not be infinite.  */
05064          do
05065            {
05066              base_string--;
05067              if (*base_string == ')')
05068               parens_balanced++;
05069              if (*base_string == '(')
05070               parens_balanced--;
05071            }
05072          while (parens_balanced);
05073 
05074          temp_string = base_string;
05075 
05076          /* Skip past '(' and whitespace.  */
05077          ++base_string;
05078          if (is_space_char (*base_string))
05079            ++base_string;
05080 
05081          if (*base_string == ','
05082              || ((i.base_reg = parse_register (base_string, &end_op))
05083                 != NULL))
05084            {
05085              displacement_string_end = temp_string;
05086 
05087              i.types[this_operand] |= BaseIndex;
05088 
05089              if (i.base_reg)
05090               {
05091                 base_string = end_op;
05092                 if (is_space_char (*base_string))
05093                   ++base_string;
05094               }
05095 
05096              /* There may be an index reg or scale factor here.  */
05097              if (*base_string == ',')
05098               {
05099                 ++base_string;
05100                 if (is_space_char (*base_string))
05101                   ++base_string;
05102 
05103                 if ((i.index_reg = parse_register (base_string, &end_op))
05104                     != NULL)
05105                   {
05106                     base_string = end_op;
05107                     if (is_space_char (*base_string))
05108                      ++base_string;
05109                     if (*base_string == ',')
05110                      {
05111                        ++base_string;
05112                        if (is_space_char (*base_string))
05113                          ++base_string;
05114                      }
05115                     else if (*base_string != ')')
05116                      {
05117                        as_bad (_("expecting `,' or `)' "
05118                                 "after index register in `%s'"),
05119                               operand_string);
05120                        return 0;
05121                      }
05122                   }
05123                 else if (*base_string == REGISTER_PREFIX)
05124                   {
05125                     as_bad (_("bad register name `%s'"), base_string);
05126                     return 0;
05127                   }
05128 
05129                 /* Check for scale factor.  */
05130                 if (*base_string != ')')
05131                   {
05132                     char *end_scale = i386_scale (base_string);
05133 
05134                     if (!end_scale)
05135                      return 0;
05136 
05137                     base_string = end_scale;
05138                     if (is_space_char (*base_string))
05139                      ++base_string;
05140                     if (*base_string != ')')
05141                      {
05142                        as_bad (_("expecting `)' "
05143                                 "after scale factor in `%s'"),
05144                               operand_string);
05145                        return 0;
05146                      }
05147                   }
05148                 else if (!i.index_reg)
05149                   {
05150                     as_bad (_("expecting index register or scale factor "
05151                             "after `,'; got '%c'"),
05152                            *base_string);
05153                     return 0;
05154                   }
05155               }
05156              else if (*base_string != ')')
05157               {
05158                 as_bad (_("expecting `,' or `)' "
05159                          "after base register in `%s'"),
05160                        operand_string);
05161                 return 0;
05162               }
05163            }
05164          else if (*base_string == REGISTER_PREFIX)
05165            {
05166              as_bad (_("bad register name `%s'"), base_string);
05167              return 0;
05168            }
05169        }
05170 
05171       /* If there's an expression beginning the operand, parse it,
05172         assuming displacement_string_start and
05173         displacement_string_end are meaningful.  */
05174       if (displacement_string_start != displacement_string_end)
05175        {
05176          if (!i386_displacement (displacement_string_start,
05177                               displacement_string_end))
05178            return 0;
05179        }
05180 
05181       /* Special case for (%dx) while doing input/output op.  */
05182       if (i.base_reg
05183          && i.base_reg->reg_type == (Reg16 | InOutPortReg)
05184          && i.index_reg == 0
05185          && i.log2_scale_factor == 0
05186          && i.seg[i.mem_operands] == 0
05187          && (i.types[this_operand] & Disp) == 0)
05188        {
05189          i.types[this_operand] = InOutPortReg;
05190          return 1;
05191        }
05192 
05193       if (i386_index_check (operand_string) == 0)
05194        return 0;
05195       i.mem_operands++;
05196     }
05197   else
05198     {
05199       /* It's not a memory operand; argh!  */
05200       as_bad (_("invalid char %s beginning operand %d `%s'"),
05201              output_invalid (*op_string),
05202              this_operand + 1,
05203              op_string);
05204       return 0;
05205     }
05206   return 1;                 /* Normal return.  */
05207 }
05208 
05209 /* md_estimate_size_before_relax()
05210 
05211    Called just before relax() for rs_machine_dependent frags.  The x86
05212    assembler uses these frags to handle variable size jump
05213    instructions.
05214 
05215    Any symbol that is now undefined will not become defined.
05216    Return the correct fr_subtype in the frag.
05217    Return the initial "guess for variable size of frag" to caller.
05218    The guess is actually the growth beyond the fixed part.  Whatever
05219    we do to grow the fixed or variable part contributes to our
05220    returned value.  */
05221 
05222 int
05223 md_estimate_size_before_relax (fragP, segment)
05224      fragS *fragP;
05225      segT segment;
05226 {
05227   /* We've already got fragP->fr_subtype right;  all we have to do is
05228      check for un-relaxable symbols.  On an ELF system, we can't relax
05229      an externally visible symbol, because it may be overridden by a
05230      shared library.  */
05231   if (S_GET_SEGMENT (fragP->fr_symbol) != segment
05232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
05233       || (IS_ELF
05234          && (S_IS_EXTERNAL (fragP->fr_symbol)
05235              || S_IS_WEAK (fragP->fr_symbol)))
05236 #endif
05237       )
05238     {
05239       /* Symbol is undefined in this segment, or we need to keep a
05240         reloc so that weak symbols can be overridden.  */
05241       int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
05242       enum bfd_reloc_code_real reloc_type;
05243       unsigned char *opcode;
05244       int old_fr_fix;
05245 
05246       if (fragP->fr_var != NO_RELOC)
05247        reloc_type = fragP->fr_var;
05248       else if (size == 2)
05249        reloc_type = BFD_RELOC_16_PCREL;
05250       else
05251        reloc_type = BFD_RELOC_32_PCREL;
05252 
05253       old_fr_fix = fragP->fr_fix;
05254       opcode = (unsigned char *) fragP->fr_opcode;
05255 
05256       switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
05257        {
05258        case UNCOND_JUMP:
05259          /* Make jmp (0xeb) a (d)word displacement jump.  */
05260          opcode[0] = 0xe9;
05261          fragP->fr_fix += size;
05262          fix_new (fragP, old_fr_fix, size,
05263                  fragP->fr_symbol,
05264                  fragP->fr_offset, 1,
05265                  reloc_type);
05266          break;
05267 
05268        case COND_JUMP86:
05269          if (size == 2
05270              && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
05271            {
05272              /* Negate the condition, and branch past an
05273                unconditional jump.  */
05274              opcode[0] ^= 1;
05275              opcode[1] = 3;
05276              /* Insert an unconditional jump.  */
05277              opcode[2] = 0xe9;
05278              /* We added two extra opcode bytes, and have a two byte
05279                offset.  */
05280              fragP->fr_fix += 2 + 2;
05281              fix_new (fragP, old_fr_fix + 2, 2,
05282                      fragP->fr_symbol,
05283                      fragP->fr_offset, 1,
05284                      reloc_type);
05285              break;
05286            }
05287          /* Fall through.  */
05288 
05289        case COND_JUMP:
05290          if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
05291            {
05292              fixS *fixP;
05293 
05294              fragP->fr_fix += 1;
05295              fixP = fix_new (fragP, old_fr_fix, 1,
05296                            fragP->fr_symbol,
05297                            fragP->fr_offset, 1,
05298                            BFD_RELOC_8_PCREL);
05299              fixP->fx_signed = 1;
05300              break;
05301            }
05302 
05303          /* This changes the byte-displacement jump 0x7N
05304             to the (d)word-displacement jump 0x0f,0x8N.  */
05305          opcode[1] = opcode[0] + 0x10;
05306          opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
05307          /* We've added an opcode byte.  */
05308          fragP->fr_fix += 1 + size;
05309          fix_new (fragP, old_fr_fix + 1, size,
05310                  fragP->fr_symbol,
05311                  fragP->fr_offset, 1,
05312                  reloc_type);
05313          break;
05314 
05315        default:
05316          BAD_CASE (fragP->fr_subtype);
05317          break;
05318        }
05319       frag_wane (fragP);
05320       return fragP->fr_fix - old_fr_fix;
05321     }
05322 
05323   /* Guess size depending on current relax state.  Initially the relax
05324      state will correspond to a short jump and we return 1, because
05325      the variable part of the frag (the branch offset) is one byte
05326      long.  However, we can relax a section more than once and in that
05327      case we must either set fr_subtype back to the unrelaxed state,
05328      or return the value for the appropriate branch.  */
05329   return md_relax_table[fragP->fr_subtype].rlx_length;
05330 }
05331 
05332 /* Called after relax() is finished.
05333 
05334    In: Address of frag.
05335        fr_type == rs_machine_dependent.
05336        fr_subtype is what the address relaxed to.
05337 
05338    Out:       Any fixSs and constants are set up.
05339        Caller will turn frag into a ".space 0".  */
05340 
05341 void
05342 md_convert_frag (abfd, sec, fragP)
05343      bfd *abfd ATTRIBUTE_UNUSED;
05344      segT sec ATTRIBUTE_UNUSED;
05345      fragS *fragP;
05346 {
05347   unsigned char *opcode;
05348   unsigned char *where_to_put_displacement = NULL;
05349   offsetT target_address;
05350   offsetT opcode_address;
05351   unsigned int extension = 0;
05352   offsetT displacement_from_opcode_start;
05353 
05354   opcode = (unsigned char *) fragP->fr_opcode;
05355 
05356   /* Address we want to reach in file space.  */
05357   target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
05358 
05359   /* Address opcode resides at in file space.  */
05360   opcode_address = fragP->fr_address + fragP->fr_fix;
05361 
05362   /* Displacement from opcode start to fill into instruction.  */
05363   displacement_from_opcode_start = target_address - opcode_address;
05364 
05365   if ((fragP->fr_subtype & BIG) == 0)
05366     {
05367       /* Don't have to change opcode.  */
05368       extension = 1;        /* 1 opcode + 1 displacement  */
05369       where_to_put_displacement = &opcode[1];
05370     }
05371   else
05372     {
05373       if (no_cond_jump_promotion
05374          && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
05375        as_warn_where (fragP->fr_file, fragP->fr_line,
05376                      _("long jump required"));
05377 
05378       switch (fragP->fr_subtype)
05379        {
05380        case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
05381          extension = 4;            /* 1 opcode + 4 displacement  */
05382          opcode[0] = 0xe9;
05383          where_to_put_displacement = &opcode[1];
05384          break;
05385 
05386        case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
05387          extension = 2;            /* 1 opcode + 2 displacement  */
05388          opcode[0] = 0xe9;
05389          where_to_put_displacement = &opcode[1];
05390          break;
05391 
05392        case ENCODE_RELAX_STATE (COND_JUMP, BIG):
05393        case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
05394          extension = 5;            /* 2 opcode + 4 displacement  */
05395          opcode[1] = opcode[0] + 0x10;
05396          opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
05397          where_to_put_displacement = &opcode[2];
05398          break;
05399 
05400        case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
05401          extension = 3;            /* 2 opcode + 2 displacement  */
05402          opcode[1] = opcode[0] + 0x10;
05403          opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
05404          where_to_put_displacement = &opcode[2];
05405          break;
05406 
05407        case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
05408          extension = 4;
05409          opcode[0] ^= 1;
05410          opcode[1] = 3;
05411          opcode[2] = 0xe9;
05412          where_to_put_displacement = &opcode[3];
05413          break;
05414 
05415        default:
05416          BAD_CASE (fragP->fr_subtype);
05417          break;
05418        }
05419     }
05420 
05421   /* If size if less then four we are sure that the operand fits,
05422      but if it's 4, then it could be that the displacement is larger
05423      then -/+ 2GB.  */
05424   if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
05425       && object_64bit
05426       && ((addressT) (displacement_from_opcode_start - extension
05427                     + ((addressT) 1 << 31))
05428          > (((addressT) 2 << 31) - 1)))
05429     {
05430       as_bad_where (fragP->fr_file, fragP->fr_line,
05431                   _("jump target out of range"));
05432       /* Make us emit 0.  */
05433       displacement_from_opcode_start = extension;
05434     }
05435   /* Now put displacement after opcode.  */
05436   md_number_to_chars ((char *) where_to_put_displacement,
05437                     (valueT) (displacement_from_opcode_start - extension),
05438                     DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
05439   fragP->fr_fix += extension;
05440 }
05441 
05442 /* Size of byte displacement jmp.  */
05443 int md_short_jump_size = 2;
05444 
05445 /* Size of dword displacement jmp.  */
05446 int md_long_jump_size = 5;
05447 
05448 void
05449 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
05450      char *ptr;
05451      addressT from_addr, to_addr;
05452      fragS *frag ATTRIBUTE_UNUSED;
05453      symbolS *to_symbol ATTRIBUTE_UNUSED;
05454 {
05455   offsetT offset;
05456 
05457   offset = to_addr - (from_addr + 2);
05458   /* Opcode for byte-disp jump.  */
05459   md_number_to_chars (ptr, (valueT) 0xeb, 1);
05460   md_number_to_chars (ptr + 1, (valueT) offset, 1);
05461 }
05462 
05463 void
05464 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
05465      char *ptr;
05466      addressT from_addr, to_addr;
05467      fragS *frag ATTRIBUTE_UNUSED;
05468      symbolS *to_symbol ATTRIBUTE_UNUSED;
05469 {
05470   offsetT offset;
05471 
05472   offset = to_addr - (from_addr + 5);
05473   md_number_to_chars (ptr, (valueT) 0xe9, 1);
05474   md_number_to_chars (ptr + 1, (valueT) offset, 4);
05475 }
05476 
05477 /* Apply a fixup (fixS) to segment data, once it has been determined
05478    by our caller that we have all the info we need to fix it up.
05479 
05480    On the 386, immediates, displacements, and data pointers are all in
05481    the same (little-endian) format, so we don't need to care about which
05482    we are handling.  */
05483 
05484 void
05485 md_apply_fix (fixP, valP, seg)
05486      /* The fix we're to put in.  */
05487      fixS *fixP;
05488      /* Pointer to the value of the bits.  */
05489      valueT *valP;
05490      /* Segment fix is from.  */
05491      segT seg ATTRIBUTE_UNUSED;
05492 {
05493   char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
05494   valueT value = *valP;
05495 
05496 #if !defined (TE_Mach)
05497   if (fixP->fx_pcrel)
05498     {
05499       switch (fixP->fx_r_type)
05500        {
05501        default:
05502          break;
05503 
05504        case BFD_RELOC_64:
05505          fixP->fx_r_type = BFD_RELOC_64_PCREL;
05506          break;
05507        case BFD_RELOC_32:
05508        case BFD_RELOC_X86_64_32S:
05509          fixP->fx_r_type = BFD_RELOC_32_PCREL;
05510          break;
05511        case BFD_RELOC_16:
05512          fixP->fx_r_type = BFD_RELOC_16_PCREL;
05513          break;
05514        case BFD_RELOC_8:
05515          fixP->fx_r_type = BFD_RELOC_8_PCREL;
05516          break;
05517        }
05518     }
05519 
05520   if (fixP->fx_addsy != NULL
05521       && (fixP->fx_r_type == BFD_RELOC_32_PCREL
05522          || fixP->fx_r_type == BFD_RELOC_64_PCREL
05523          || fixP->fx_r_type == BFD_RELOC_16_PCREL
05524          || fixP->fx_r_type == BFD_RELOC_8_PCREL)
05525       && !use_rela_relocations)
05526     {
05527       /* This is a hack.  There should be a better way to handle this.
05528         This covers for the fact that bfd_install_relocation will
05529         subtract the current location (for partial_inplace, PC relative
05530         relocations); see more below.  */
05531 #ifndef OBJ_AOUT
05532       if (IS_ELF
05533 #ifdef TE_PE
05534          || OUTPUT_FLAVOR == bfd_target_coff_flavour
05535 #endif
05536          )
05537        value += fixP->fx_where + fixP->fx_frag->fr_address;
05538 #endif
05539 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
05540       if (IS_ELF)
05541        {
05542          segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
05543 
05544          if ((sym_seg == seg
05545               || (symbol_section_p (fixP->fx_addsy)
05546                  && sym_seg != absolute_section))
05547              && !generic_force_reloc (fixP))
05548            {
05549              /* Yes, we add the values in twice.  This is because
05550                bfd_install_relocation subtracts them out again.  I think
05551                bfd_install_relocation is broken, but I don't dare change
05552                it.  FIXME.  */
05553              value += fixP->fx_where + fixP->fx_frag->fr_address;
05554            }
05555        }
05556 #endif
05557 #if defined (OBJ_COFF) && defined (TE_PE)
05558       /* For some reason, the PE format does not store a
05559         section address offset for a PC relative symbol.  */
05560       if (S_GET_SEGMENT (fixP->fx_addsy) != seg
05561          || S_IS_WEAK (fixP->fx_addsy))
05562        value += md_pcrel_from (fixP);
05563 #endif
05564     }
05565 
05566   /* Fix a few things - the dynamic linker expects certain values here,
05567      and we must not disappoint it.  */
05568 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
05569   if (IS_ELF && fixP->fx_addsy)
05570     switch (fixP->fx_r_type)
05571       {
05572       case BFD_RELOC_386_PLT32:
05573       case BFD_RELOC_X86_64_PLT32:
05574        /* Make the jump instruction point to the address of the operand.  At
05575           runtime we merely add the offset to the actual PLT entry.  */
05576        value = -4;
05577        break;
05578 
05579       case BFD_RELOC_386_TLS_GD:
05580       case BFD_RELOC_386_TLS_LDM:
05581       case BFD_RELOC_386_TLS_IE_32:
05582       case BFD_RELOC_386_TLS_IE:
05583       case BFD_RELOC_386_TLS_GOTIE:
05584       case BFD_RELOC_386_TLS_GOTDESC:
05585       case BFD_RELOC_X86_64_TLSGD:
05586       case BFD_RELOC_X86_64_TLSLD:
05587       case BFD_RELOC_X86_64_GOTTPOFF:
05588       case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
05589        value = 0; /* Fully resolved at runtime.  No addend.  */
05590        /* Fallthrough */
05591       case BFD_RELOC_386_TLS_LE:
05592       case BFD_RELOC_386_TLS_LDO_32:
05593       case BFD_RELOC_386_TLS_LE_32:
05594       case BFD_RELOC_X86_64_DTPOFF32:
05595       case BFD_RELOC_X86_64_DTPOFF64:
05596       case BFD_RELOC_X86_64_TPOFF32:
05597       case BFD_RELOC_X86_64_TPOFF64:
05598        S_SET_THREAD_LOCAL (fixP->fx_addsy);
05599        break;
05600 
05601       case BFD_RELOC_386_TLS_DESC_CALL:
05602       case BFD_RELOC_X86_64_TLSDESC_CALL:
05603        value = 0; /* Fully resolved at runtime.  No addend.  */
05604        S_SET_THREAD_LOCAL (fixP->fx_addsy);
05605        fixP->fx_done = 0;
05606        return;
05607 
05608       case BFD_RELOC_386_GOT32:
05609       case BFD_RELOC_X86_64_GOT32:
05610        value = 0; /* Fully resolved at runtime.  No addend.  */
05611        break;
05612 
05613       case BFD_RELOC_VTABLE_INHERIT:
05614       case BFD_RELOC_VTABLE_ENTRY:
05615        fixP->fx_done = 0;
05616        return;
05617 
05618       default:
05619        break;
05620       }
05621 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)  */
05622   *valP = value;
05623 #endif /* !defined (TE_Mach)  */
05624 
05625   /* Are we finished with this relocation now?  */
05626   if (fixP->fx_addsy == NULL)
05627     fixP->fx_done = 1;
05628   else if (use_rela_relocations)
05629     {
05630       fixP->fx_no_overflow = 1;
05631       /* Remember value for tc_gen_reloc.  */
05632       fixP->fx_addnumber = value;
05633       value = 0;
05634     }
05635 
05636   md_number_to_chars (p, value, fixP->fx_size);
05637 }
05638 
05639 #define MAX_LITTLENUMS 6
05640 
05641 /* Turn the string pointed to by litP into a floating point constant
05642    of type TYPE, and emit the appropriate bytes.  The number of
05643    LITTLENUMS emitted is stored in *SIZEP.  An error message is
05644    returned, or NULL on OK.  */
05645 
05646 char *
05647 md_atof (type, litP, sizeP)
05648      int type;
05649      char *litP;
05650      int *sizeP;
05651 {
05652   int prec;
05653   LITTLENUM_TYPE words[MAX_LITTLENUMS];
05654   LITTLENUM_TYPE *wordP;
05655   char *t;
05656 
05657   switch (type)
05658     {
05659     case 'f':
05660     case 'F':
05661       prec = 2;
05662       break;
05663 
05664     case 'd':
05665     case 'D':
05666       prec = 4;
05667       break;
05668 
05669     case 'x':
05670     case 'X':
05671       prec = 5;
05672       break;
05673 
05674     default:
05675       *sizeP = 0;
05676       return _("Bad call to md_atof ()");
05677     }
05678   t = atof_ieee (input_line_pointer, type, words);
05679   if (t)
05680     input_line_pointer = t;
05681 
05682   *sizeP = prec * sizeof (LITTLENUM_TYPE);
05683   /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
05684      the bigendian 386.  */
05685   for (wordP = words + prec - 1; prec--;)
05686     {
05687       md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
05688       litP += sizeof (LITTLENUM_TYPE);
05689     }
05690   return 0;
05691 }
05692 
05693 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
05694 
05695 static char *
05696 output_invalid (int c)
05697 {
05698   if (ISPRINT (c))
05699     snprintf (output_invalid_buf, sizeof (output_invalid_buf),
05700              "'%c'", c);
05701   else
05702     snprintf (output_invalid_buf, sizeof (output_invalid_buf),
05703              "(0x%x)", (unsigned char) c);
05704   return output_invalid_buf;
05705 }
05706 
05707 /* REG_STRING starts *before* REGISTER_PREFIX.  */
05708 
05709 static const reg_entry *
05710 parse_real_register (char *reg_string, char **end_op)
05711 {
05712   char *s = reg_string;
05713   char *p;
05714   char reg_name_given[MAX_REG_NAME_SIZE + 1];
05715   const reg_entry *r;
05716 
05717   /* Skip possible REGISTER_PREFIX and possible whitespace.  */
05718   if (*s == REGISTER_PREFIX)
05719     ++s;
05720 
05721   if (is_space_char (*s))
05722     ++s;
05723 
05724   p = reg_name_given;
05725   while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
05726     {
05727       if (p >= reg_name_given + MAX_REG_NAME_SIZE)
05728        return (const reg_entry *) NULL;
05729       s++;
05730     }
05731 
05732   /* For naked regs, make sure that we are not dealing with an identifier.
05733      This prevents confusing an identifier like `eax_var' with register
05734      `eax'.  */
05735   if (allow_naked_reg && identifier_chars[(unsigned char) *s])
05736     return (const reg_entry *) NULL;
05737 
05738   *end_op = s;
05739 
05740   r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
05741 
05742   /* Handle floating point regs, allowing spaces in the (i) part.  */
05743   if (r == i386_regtab /* %st is first entry of table  */)
05744     {
05745       if (is_space_char (*s))
05746        ++s;
05747       if (*s == '(')
05748        {
05749          ++s;
05750          if (is_space_char (*s))
05751            ++s;
05752          if (*s >= '0' && *s <= '7')
05753            {
05754              r = &i386_float_regtab[*s - '0'];
05755              ++s;
05756              if (is_space_char (*s))
05757               ++s;
05758              if (*s == ')')
05759               {
05760                 *end_op = s + 1;
05761                 return r;
05762               }
05763            }
05764          /* We have "%st(" then garbage.  */
05765          return (const reg_entry *) NULL;
05766        }
05767     }
05768 
05769   if (r != NULL
05770       && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
05771       && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
05772       && flag_code != CODE_64BIT)
05773     return (const reg_entry *) NULL;
05774 
05775   return r;
05776 }
05777 
05778 /* REG_STRING starts *before* REGISTER_PREFIX.  */
05779 
05780 static const reg_entry *
05781 parse_register (char *reg_string, char **end_op)
05782 {
05783   const reg_entry *r;
05784 
05785   if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
05786     r = parse_real_register (reg_string, end_op);
05787   else
05788     r = NULL;
05789   if (!r)
05790     {
05791       char *save = input_line_pointer;
05792       char c;
05793       symbolS *symbolP;
05794 
05795       input_line_pointer = reg_string;
05796       c = get_symbol_end ();
05797       symbolP = symbol_find (reg_string);
05798       if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
05799        {
05800          const expressionS *e = symbol_get_value_expression (symbolP);
05801 
05802          know (e->X_op == O_register);
05803          know (e->X_add_number >= 0
05804               && (valueT) e->X_add_number < i386_regtab_size);
05805          r = i386_regtab + e->X_add_number;
05806          *end_op = input_line_pointer;
05807        }
05808       *input_line_pointer = c;
05809       input_line_pointer = save;
05810     }
05811   return r;
05812 }
05813 
05814 int
05815 i386_parse_name (char *name, expressionS *e, char *nextcharP)
05816 {
05817   const reg_entry *r;
05818   char *end = input_line_pointer;
05819 
05820   *end = *nextcharP;
05821   r = parse_register (name, &input_line_pointer);
05822   if (r && end <= input_line_pointer)
05823     {
05824       *nextcharP = *input_line_pointer;
05825       *input_line_pointer = 0;
05826       e->X_op = O_register;
05827       e->X_add_number = r - i386_regtab;
05828       return 1;
05829     }
05830   input_line_pointer = end;
05831   *end = 0;
05832   return 0;
05833 }
05834 
05835 void
05836 md_operand (expressionS *e)
05837 {
05838   if (*input_line_pointer == REGISTER_PREFIX)
05839     {
05840       char *end;
05841       const reg_entry *r = parse_real_register (input_line_pointer, &end);
05842 
05843       if (r)
05844        {
05845          e->X_op = O_register;
05846          e->X_add_number = r - i386_regtab;
05847          input_line_pointer = end;
05848        }
05849     }
05850 }
05851 
05852 
05853 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
05854 const char *md_shortopts = "kVQ:sqn";
05855 #else
05856 const char *md_shortopts = "qn";
05857 #endif
05858 
05859 #define OPTION_32 (OPTION_MD_BASE + 0)
05860 #define OPTION_64 (OPTION_MD_BASE + 1)
05861 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
05862 #define OPTION_MARCH (OPTION_MD_BASE + 3)
05863 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
05864 
05865 struct option md_longopts[] =
05866 {
05867   {"32", no_argument, NULL, OPTION_32},
05868 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
05869   {"64", no_argument, NULL, OPTION_64},
05870 #endif
05871   {"divide", no_argument, NULL, OPTION_DIVIDE},
05872   {"march", required_argument, NULL, OPTION_MARCH},
05873   {"mtune", required_argument, NULL, OPTION_MTUNE},
05874   {NULL, no_argument, NULL, 0}
05875 };
05876 size_t md_longopts_size = sizeof (md_longopts);
05877 
05878 int
05879 md_parse_option (int c, char *arg)
05880 {
05881   unsigned int i;
05882 
05883   switch (c)
05884     {
05885     case 'n':
05886       optimize_align_code = 0;
05887       break;
05888 
05889     case 'q':
05890       quiet_warnings = 1;
05891       break;
05892 
05893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
05894       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
05895         should be emitted or not.  FIXME: Not implemented.  */
05896     case 'Q':
05897       break;
05898 
05899       /* -V: SVR4 argument to print version ID.  */
05900     case 'V':
05901       print_version_id ();
05902       break;
05903 
05904       /* -k: Ignore for FreeBSD compatibility.  */
05905     case 'k':
05906       break;
05907 
05908     case 's':
05909       /* -s: On i386 Solaris, this tells the native assembler to use
05910         .stab instead of .stab.excl.  We always use .stab anyhow.  */
05911       break;
05912 #endif
05913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
05914     case OPTION_64:
05915       {
05916        const char **list, **l;
05917 
05918        list = bfd_target_list ();
05919        for (l = list; *l != NULL; l++)
05920          if (CONST_STRNEQ (*l, "elf64-x86-64")
05921              || strcmp (*l, "coff-x86-64") == 0
05922              || strcmp (*l, "pe-x86-64") == 0
05923              || strcmp (*l, "pei-x86-64") == 0)
05924            {
05925              default_arch = "x86_64";
05926              break;
05927            }
05928        if (*l == NULL)
05929          as_fatal (_("No compiled in support for x86_64"));
05930        free (list);
05931       }
05932       break;
05933 #endif
05934 
05935     case OPTION_32:
05936       default_arch = "i386";
05937       break;
05938 
05939     case OPTION_DIVIDE:
05940 #ifdef SVR4_COMMENT_CHARS
05941       {
05942        char *n, *t;
05943        const char *s;
05944 
05945        n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
05946        t = n;
05947        for (s = i386_comment_chars; *s != '\0'; s++)
05948          if (*s != '/')
05949            *t++ = *s;
05950        *t = '\0';
05951        i386_comment_chars = n;
05952       }
05953 #endif
05954       break;
05955 
05956     case OPTION_MARCH:
05957       if (*arg == '.')
05958        as_fatal (_("Invalid -march= option: `%s'"), arg);
05959       for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
05960        {
05961          if (strcmp (arg, cpu_arch [i].name) == 0)
05962            {
05963              cpu_arch_isa = cpu_arch[i].type;
05964              cpu_arch_isa_flags = cpu_arch[i].flags;
05965              if (!cpu_arch_tune_set)
05966               {
05967                 cpu_arch_tune = cpu_arch_isa;
05968                 cpu_arch_tune_flags = cpu_arch_isa_flags;
05969               }
05970              break;
05971            }
05972        }
05973       if (i >= ARRAY_SIZE (cpu_arch))
05974        as_fatal (_("Invalid -march= option: `%s'"), arg);
05975       break;
05976 
05977     case OPTION_MTUNE:
05978       if (*arg == '.')
05979        as_fatal (_("Invalid -mtune= option: `%s'"), arg);
05980       for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
05981        {
05982          if (strcmp (arg, cpu_arch [i].name) == 0)
05983            {
05984              cpu_arch_tune_set = 1;
05985              cpu_arch_tune = cpu_arch [i].type;
05986              cpu_arch_tune_flags = cpu_arch[i].flags;
05987              break;
05988            }
05989        }
05990       if (i >= ARRAY_SIZE (cpu_arch))
05991        as_fatal (_("Invalid -mtune= option: `%s'"), arg);
05992       break;
05993 
05994     default:
05995       return 0;
05996     }
05997   return 1;
05998 }
05999 
06000 void
06001 md_show_usage (stream)
06002      FILE *stream;
06003 {
06004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
06005   fprintf (stream, _("\
06006   -Q                      ignored\n\
06007   -V                      print assembler version number\n\
06008   -k                      ignored\n"));
06009 #endif
06010   fprintf (stream, _("\
06011   -n                      Do not optimize code alignment\n\
06012   -q                      quieten some warnings\n"));
06013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
06014   fprintf (stream, _("\
06015   -s                      ignored\n"));
06016 #endif
06017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
06018   fprintf (stream, _("\
06019   --32/--64               generate 32bit/64bit code\n"));
06020 #endif
06021 #ifdef SVR4_COMMENT_CHARS
06022   fprintf (stream, _("\
06023   --divide                do not treat `/' as a comment character\n"));
06024 #else
06025   fprintf (stream, _("\
06026   --divide                ignored\n"));
06027 #endif
06028   fprintf (stream, _("\
06029   -march=CPU/-mtune=CPU   generate code/optimize for CPU, where CPU is one of:\n\
06030                            i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
06031                            core, core2, k6, athlon, k8, generic32, generic64\n"));
06032 
06033 }
06034 
06035 #if defined(TE_PEP)
06036 const char *
06037 x86_64_target_format (void)
06038 {
06039   if (strcmp (default_arch, "x86_64") == 0)
06040     {
06041       set_code_flag (CODE_64BIT);
06042       return COFF_TARGET_FORMAT;
06043     }
06044   else if (strcmp (default_arch, "i386") == 0)
06045     {
06046       set_code_flag (CODE_32BIT);
06047       return "coff-i386";
06048     }
06049 
06050   as_fatal (_("Unknown architecture"));
06051   return NULL;
06052 }
06053 #endif
06054 
06055 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
06056      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
06057 
06058 /* Pick the target format to use.  */
06059 
06060 const char *
06061 i386_target_format (void)
06062 {
06063   if (!strcmp (default_arch, "x86_64"))
06064     {
06065       set_code_flag (CODE_64BIT);
06066       if (cpu_arch_isa_flags == 0)
06067        cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
06068                           |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
06069                           |CpuSSE|CpuSSE2;
06070       if (cpu_arch_tune_flags == 0)
06071        cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
06072                            |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
06073                            |CpuSSE|CpuSSE2;
06074     }
06075   else if (!strcmp (default_arch, "i386"))
06076     {
06077       set_code_flag (CODE_32BIT);
06078       if (cpu_arch_isa_flags == 0)
06079        cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
06080       if (cpu_arch_tune_flags == 0)
06081        cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
06082     }
06083   else
06084     as_fatal (_("Unknown architecture"));
06085   switch (OUTPUT_FLAVOR)
06086     {
06087 #ifdef OBJ_MAYBE_AOUT
06088     case bfd_target_aout_flavour:
06089       return AOUT_TARGET_FORMAT;
06090 #endif
06091 #ifdef OBJ_MAYBE_COFF
06092     case bfd_target_coff_flavour:
06093       return "coff-i386";
06094 #endif
06095 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
06096     case bfd_target_elf_flavour:
06097       {
06098        if (flag_code == CODE_64BIT)
06099          {
06100            object_64bit = 1;
06101            use_rela_relocations = 1;
06102          }
06103        return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
06104       }
06105 #endif
06106     default:
06107       abort ();
06108       return NULL;
06109     }
06110 }
06111 
06112 #endif /* OBJ_MAYBE_ more than one  */
06113 
06114 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
06115 void
06116 i386_elf_emit_arch_note (void)
06117 {
06118   if (IS_ELF && cpu_arch_name != NULL)
06119     {
06120       char *p;
06121       asection *seg = now_seg;
06122       subsegT subseg = now_subseg;
06123       Elf_Internal_Note i_note;
06124       Elf_External_Note e_note;
06125       asection *note_secp;
06126       int len;
06127 
06128       /* Create the .note section.  */
06129       note_secp = subseg_new (".note", 0);
06130       bfd_set_section_flags (stdoutput,
06131                           note_secp,
06132                           SEC_HAS_CONTENTS | SEC_READONLY);
06133 
06134       /* Process the arch string.  */
06135       len = strlen (cpu_arch_name);
06136 
06137       i_note.namesz = len + 1;
06138       i_note.descsz = 0;
06139       i_note.type = NT_ARCH;
06140       p = frag_more (sizeof (e_note.namesz));
06141       md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
06142       p = frag_more (sizeof (e_note.descsz));
06143       md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
06144       p = frag_more (sizeof (e_note.type));
06145       md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
06146       p = frag_more (len + 1);
06147       strcpy (p, cpu_arch_name);
06148 
06149       frag_align (2, 0, 0);
06150 
06151       subseg_set (seg, subseg);
06152     }
06153 }
06154 #endif
06155 
06156 symbolS *
06157 md_undefined_symbol (name)
06158      char *name;
06159 {
06160   if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
06161       && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
06162       && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
06163       && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
06164     {
06165       if (!GOT_symbol)
06166        {
06167          if (symbol_find (name))
06168            as_bad (_("GOT already in symbol table"));
06169          GOT_symbol = symbol_new (name, undefined_section,
06170                                (valueT) 0, &zero_address_frag);
06171        };
06172       return GOT_symbol;
06173     }
06174   return 0;
06175 }
06176 
06177 /* Round up a section size to the appropriate boundary.  */
06178 
06179 valueT
06180 md_section_align (segment, size)
06181      segT segment ATTRIBUTE_UNUSED;
06182      valueT size;
06183 {
06184 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
06185   if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
06186     {
06187       /* For a.out, force the section size to be aligned.  If we don't do
06188         this, BFD will align it for us, but it will not write out the
06189         final bytes of the section.  This may be a bug in BFD, but it is
06190         easier to fix it here since that is how the other a.out targets
06191         work.  */
06192       int align;
06193 
06194       align = bfd_get_section_alignment (stdoutput, segment);
06195       size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
06196     }
06197 #endif
06198 
06199   return size;
06200 }
06201 
06202 /* On the i386, PC-relative offsets are relative to the start of the
06203    next instruction.  That is, the address of the offset, plus its
06204    size, since the offset is always the last part of the insn.  */
06205 
06206 long
06207 md_pcrel_from (fixS *fixP)
06208 {
06209   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
06210 }
06211 
06212 #ifndef I386COFF
06213 
06214 static void
06215 s_bss (int ignore ATTRIBUTE_UNUSED)
06216 {
06217   int temp;
06218 
06219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
06220   if (IS_ELF)
06221     obj_elf_section_change_hook ();
06222 #endif
06223   temp = get_absolute_expression ();
06224   subseg_set (bss_section, (subsegT) temp);
06225   demand_empty_rest_of_line ();
06226 }
06227 
06228 #endif
06229 
06230 void
06231 i386_validate_fix (fixS *fixp)
06232 {
06233   if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
06234     {
06235       if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
06236        {
06237          if (!object_64bit)
06238            abort ();
06239          fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
06240        }
06241       else
06242        {
06243          if (!object_64bit)
06244            fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
06245          else
06246            fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
06247        }
06248       fixp->fx_subsy = 0;
06249     }
06250 }
06251 
06252 arelent *
06253 tc_gen_reloc (section, fixp)
06254      asection *section ATTRIBUTE_UNUSED;
06255      fixS *fixp;
06256 {
06257   arelent *rel;
06258   bfd_reloc_code_real_type code;
06259 
06260   switch (fixp->fx_r_type)
06261     {
06262     case BFD_RELOC_X86_64_PLT32:
06263     case BFD_RELOC_X86_64_GOT32:
06264     case BFD_RELOC_X86_64_GOTPCREL:
06265     case BFD_RELOC_386_PLT32:
06266     case BFD_RELOC_386_GOT32:
06267     case BFD_RELOC_386_GOTOFF:
06268     case BFD_RELOC_386_GOTPC:
06269     case BFD_RELOC_386_TLS_GD:
06270     case BFD_RELOC_386_TLS_LDM:
06271     case BFD_RELOC_386_TLS_LDO_32:
06272     case BFD_RELOC_386_TLS_IE_32:
06273     case BFD_RELOC_386_TLS_IE:
06274     case BFD_RELOC_386_TLS_GOTIE:
06275     case BFD_RELOC_386_TLS_LE_32:
06276     case BFD_RELOC_386_TLS_LE:
06277     case BFD_RELOC_386_TLS_GOTDESC:
06278     case BFD_RELOC_386_TLS_DESC_CALL:
06279     case BFD_RELOC_X86_64_TLSGD:
06280     case BFD_RELOC_X86_64_TLSLD:
06281     case BFD_RELOC_X86_64_DTPOFF32:
06282     case BFD_RELOC_X86_64_DTPOFF64:
06283     case BFD_RELOC_X86_64_GOTTPOFF:
06284     case BFD_RELOC_X86_64_TPOFF32:
06285     case BFD_RELOC_X86_64_TPOFF64:
06286     case BFD_RELOC_X86_64_GOTOFF64:
06287     case BFD_RELOC_X86_64_GOTPC32:
06288     case BFD_RELOC_X86_64_GOT64:
06289     case BFD_RELOC_X86_64_GOTPCREL64:
06290     case BFD_RELOC_X86_64_GOTPC64:
06291     case BFD_RELOC_X86_64_GOTPLT64:
06292     case BFD_RELOC_X86_64_PLTOFF64:
06293     case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
06294     case BFD_RELOC_X86_64_TLSDESC_CALL:
06295     case BFD_RELOC_RVA:
06296     case BFD_RELOC_VTABLE_ENTRY:
06297     case BFD_RELOC_VTABLE_INHERIT:
06298 #ifdef TE_PE
06299     case BFD_RELOC_32_SECREL:
06300 #endif
06301       code = fixp->fx_r_type;
06302       break;
06303     case BFD_RELOC_X86_64_32S:
06304       if (!fixp->fx_pcrel)
06305        {
06306          /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32.  */
06307          code = fixp->fx_r_type;
06308          break;
06309        }
06310     default:
06311       if (fixp->fx_pcrel)
06312        {
06313          switch (fixp->fx_size)
06314            {
06315            default:
06316              as_bad_where (fixp->fx_file, fixp->fx_line,
06317                          _("can not do %d byte pc-relative relocation"),
06318                          fixp->fx_size);
06319              code = BFD_RELOC_32_PCREL;
06320              break;
06321            case 1: code = BFD_RELOC_8_PCREL;  break;
06322            case 2: code = BFD_RELOC_16_PCREL; break;
06323            case 4: code = BFD_RELOC_32_PCREL; break;
06324 #ifdef BFD64
06325            case 8: code = BFD_RELOC_64_PCREL; break;
06326 #endif
06327            }
06328        }
06329       else
06330        {
06331          switch (fixp->fx_size)
06332            {
06333            default:
06334              as_bad_where (fixp->fx_file, fixp->fx_line,
06335                          _("can not do %d byte relocation"),
06336                          fixp->fx_size);
06337              code = BFD_RELOC_32;
06338              break;
06339            case 1: code = BFD_RELOC_8;  break;
06340            case 2: code = BFD_RELOC_16; break;
06341            case 4: code = BFD_RELOC_32; break;
06342 #ifdef BFD64
06343            case 8: code = BFD_RELOC_64; break;
06344 #endif
06345            }
06346        }
06347       break;
06348     }
06349 
06350   if ((code == BFD_RELOC_32
06351        || code == BFD_RELOC_32_PCREL
06352        || code == BFD_RELOC_X86_64_32S)
06353       && GOT_symbol
06354       && fixp->fx_addsy == GOT_symbol)
06355     {
06356       if (!object_64bit)
06357        code = BFD_RELOC_386_GOTPC;
06358       else
06359        code = BFD_RELOC_X86_64_GOTPC32;
06360     }
06361   if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
06362       && GOT_symbol
06363       && fixp->fx_addsy == GOT_symbol)
06364     {
06365       code = BFD_RELOC_X86_64_GOTPC64;
06366     }
06367 
06368   rel = (arelent *) xmalloc (sizeof (arelent));
06369   rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
06370   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
06371 
06372   rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
06373 
06374   if (!use_rela_relocations)
06375     {
06376       /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
06377         vtable entry to be used in the relocation's section offset.  */
06378       if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
06379        rel->address = fixp->fx_offset;
06380 
06381       rel->addend = 0;
06382     }
06383   /* Use the rela in 64bit mode.  */
06384   else
06385     {
06386       if (!fixp->fx_pcrel)
06387        rel->addend = fixp->fx_offset;
06388       else
06389        switch (code)
06390          {
06391          case BFD_RELOC_X86_64_PLT32:
06392          case BFD_RELOC_X86_64_GOT32:
06393          case BFD_RELOC_X86_64_GOTPCREL:
06394          case BFD_RELOC_X86_64_TLSGD:
06395          case BFD_RELOC_X86_64_TLSLD:
06396          case BFD_RELOC_X86_64_GOTTPOFF:
06397          case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
06398          case BFD_RELOC_X86_64_TLSDESC_CALL:
06399            rel->addend = fixp->fx_offset - fixp->fx_size;
06400            break;
06401          default:
06402            rel->addend = (section->vma
06403                         - fixp->fx_size
06404                         + fixp->fx_addnumber
06405                         + md_pcrel_from (fixp));
06406            break;
06407          }
06408     }
06409 
06410   rel->howto = bfd_reloc_type_lookup (stdoutput, code);
06411   if (rel->howto == NULL)
06412     {
06413       as_bad_where (fixp->fx_file, fixp->fx_line,
06414                   _("cannot represent relocation type %s"),
06415                   bfd_get_reloc_code_name (code));
06416       /* Set howto to a garbage value so that we can keep going.  */
06417       rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
06418       assert (rel->howto != NULL);
06419     }
06420 
06421   return rel;
06422 }
06423 
06424 
06425 /* Parse operands using Intel syntax. This implements a recursive descent
06426    parser based on the BNF grammar published in Appendix B of the MASM 6.1
06427    Programmer's Guide.
06428 
06429    FIXME: We do not recognize the full operand grammar defined in the MASM
06430          documentation.  In particular, all the structure/union and
06431          high-level macro operands are missing.
06432 
06433    Uppercase words are terminals, lower case words are non-terminals.
06434    Objects surrounded by double brackets '[[' ']]' are optional. Vertical
06435    bars '|' denote choices. Most grammar productions are implemented in
06436    functions called 'intel_<production>'.
06437 
06438    Initial production is 'expr'.
06439 
06440     addOp            + | -
06441 
06442     alpha            [a-zA-Z]
06443 
06444     binOp            & | AND | \| | OR | ^ | XOR
06445 
06446     byteRegister     AL | AH | BL | BH | CL | CH | DL | DH
06447 
06448     constant         digits [[ radixOverride ]]
06449 
06450     dataType         BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
06451 
06452     digits           decdigit
06453                      | digits decdigit
06454                      | digits hexdigit
06455 
06456     decdigit         [0-9]
06457 
06458     e04                     e04 addOp e05
06459                      | e05
06460 
06461     e05                     e05 binOp e06
06462                      | e06
06463 
06464     e06                     e06 mulOp e09
06465                      | e09
06466 
06467     e09                     OFFSET e10
06468                      | SHORT e10
06469                      | + e10
06470                      | - e10
06471                      | ~ e10
06472                      | NOT e10
06473                      | e09 PTR e10
06474                      | e09 : e10
06475                      | e10
06476 
06477     e10                     e10 [ expr ]
06478                      | e11
06479 
06480     e11                     ( expr )
06481                      | [ expr ]
06482                      | constant
06483                      | dataType
06484                      | id
06485                      | $
06486                      | register
06487 
06488  => expr             expr cmpOp e04
06489                      | e04
06490 
06491     gpRegister              AX | EAX | BX | EBX | CX | ECX | DX | EDX
06492                      | BP | EBP | SP | ESP | DI | EDI | SI | ESI
06493 
06494     hexdigit         a | b | c | d | e | f
06495                      | A | B | C | D | E | F
06496 
06497     id               alpha
06498                      | id alpha
06499                      | id decdigit
06500 
06501     mulOp            * | / | % | MOD | << | SHL | >> | SHR
06502 
06503     quote            " | '
06504 
06505     register         specialRegister
06506                      | gpRegister
06507                      | byteRegister
06508 
06509     segmentRegister  CS | DS | ES | FS | GS | SS
06510 
06511     specialRegister  CR0 | CR2 | CR3 | CR4
06512                      | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
06513                      | TR3 | TR4 | TR5 | TR6 | TR7
06514 
06515     We simplify the grammar in obvious places (e.g., register parsing is
06516     done by calling parse_register) and eliminate immediate left recursion
06517     to implement a recursive-descent parser.
06518 
06519     expr      e04 expr'
06520 
06521     expr'     cmpOp e04 expr'
06522               | Empty
06523 
06524     e04              e05 e04'
06525 
06526     e04'      addOp e05 e04'
06527               | Empty
06528 
06529     e05              e06 e05'
06530 
06531     e05'      binOp e06 e05'
06532               | Empty
06533 
06534     e06              e09 e06'
06535 
06536     e06'      mulOp e09 e06'
06537               | Empty
06538 
06539     e09              OFFSET e10 e09'
06540               | SHORT e10'
06541               | + e10'
06542               | - e10'
06543               | ~ e10'
06544               | NOT e10'
06545               | e10 e09'
06546 
06547     e09'      PTR e10 e09'
06548               | : e10 e09'
06549               | Empty
06550 
06551     e10              e11 e10'
06552 
06553     e10'      [ expr ] e10'
06554               | Empty
06555 
06556     e11              ( expr )
06557               | [ expr ]
06558               | BYTE
06559               | WORD
06560               | DWORD
06561               | FWORD
06562               | QWORD
06563               | TBYTE
06564               | OWORD
06565               | XMMWORD
06566               | .
06567               | $
06568               | register
06569               | id
06570               | constant  */
06571 
06572 /* Parsing structure for the intel syntax parser. Used to implement the
06573    semantic actions for the operand grammar.  */
06574 struct intel_parser_s
06575   {
06576     char *op_string;        /* The string being parsed.  */
06577     int got_a_float;        /* Whether the operand is a float.  */
06578     int op_modifier;        /* Operand modifier.  */
06579     int is_mem;                    /* 1 if operand is memory reference.  */
06580     int in_offset;          /* >=1 if parsing operand of offset.  */
06581     int in_bracket;         /* >=1 if parsing operand in brackets.  */
06582     const reg_entry *reg;   /* Last register reference found.  */
06583     char *disp;                    /* Displacement string being built.  */
06584     char *next_operand;            /* Resume point when splitting operands.  */
06585   };
06586 
06587 static struct intel_parser_s intel_parser;
06588 
06589 /* Token structure for parsing intel syntax.  */
06590 struct intel_token
06591   {
06592     int code;               /* Token code.  */
06593     const reg_entry *reg;   /* Register entry for register tokens.  */
06594     char *str;                     /* String representation.  */
06595   };
06596 
06597 static struct intel_token cur_token, prev_token;
06598 
06599 /* Token codes for the intel parser. Since T_SHORT is already used
06600    by COFF, undefine it first to prevent a warning.  */
06601 #define T_NIL        -1
06602 #define T_CONST             1
06603 #define T_REG        2
06604 #define T_BYTE              3
06605 #define T_WORD              4
06606 #define T_DWORD             5
06607 #define T_FWORD             6
06608 #define T_QWORD             7
06609 #define T_TBYTE             8
06610 #define T_XMMWORD    9
06611 #undef  T_SHORT
06612 #define T_SHORT             10
06613 #define T_OFFSET     11
06614 #define T_PTR        12
06615 #define T_ID         13
06616 #define T_SHL        14
06617 #define T_SHR        15
06618 
06619 /* Prototypes for intel parser functions.  */
06620 static int intel_match_token (int);
06621 static void intel_putback_token    (void);
06622 static void intel_get_token (void);
06623 static int intel_expr (void);
06624 static int intel_e04 (void);
06625 static int intel_e05 (void);
06626 static int intel_e06 (void);
06627 static int intel_e09 (void);
06628 static int intel_e10 (void);
06629 static int intel_e11 (void);
06630 
06631 static int
06632 i386_intel_operand (char *operand_string, int got_a_float)
06633 {
06634   int ret;
06635   char *p;
06636 
06637   p = intel_parser.op_string = xstrdup (operand_string);
06638   intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
06639 
06640   for (;;)
06641     {
06642       /* Initialize token holders.  */
06643       cur_token.code = prev_token.code = T_NIL;
06644       cur_token.reg = prev_token.reg = NULL;
06645       cur_token.str = prev_token.str = NULL;
06646 
06647       /* Initialize parser structure.  */
06648       intel_parser.got_a_float = got_a_float;
06649       intel_parser.op_modifier = 0;
06650       intel_parser.is_mem = 0;
06651       intel_parser.in_offset = 0;
06652       intel_parser.in_bracket = 0;
06653       intel_parser.reg = NULL;
06654       intel_parser.disp[0] = '\0';
06655       intel_parser.next_operand = NULL;
06656 
06657       /* Read the first token and start the parser.  */
06658       intel_get_token ();
06659       ret = intel_expr ();
06660 
06661       if (!ret)
06662        break;
06663 
06664       if (cur_token.code != T_NIL)
06665        {
06666          as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
06667                 current_templates->start->name, cur_token.str);
06668          ret = 0;
06669        }
06670       /* If we found a memory reference, hand it over to i386_displacement
06671         to fill in the rest of the operand fields.  */
06672       else if (intel_parser.is_mem)
06673        {
06674          if ((i.mem_operands == 1
06675               && (current_templates->start->opcode_modifier & IsString) == 0)
06676              || i.mem_operands == 2)
06677            {
06678              as_bad (_("too many memory references for '%s'"),
06679                     current_templates->start->name);
06680              ret = 0;
06681            }
06682          else
06683            {
06684              char *s = intel_parser.disp;
06685              i.mem_operands++;
06686 
06687              if (!quiet_warnings && intel_parser.is_mem < 0)
06688               /* See the comments in intel_bracket_expr.  */
06689               as_warn (_("Treating `%s' as memory reference"), operand_string);
06690 
06691              /* Add the displacement expression.  */
06692              if (*s != '\0')
06693               ret = i386_displacement (s, s + strlen (s));
06694              if (ret)
06695               {
06696                 /* Swap base and index in 16-bit memory operands like
06697                    [si+bx]. Since i386_index_check is also used in AT&T
06698                    mode we have to do that here.  */
06699                 if (i.base_reg
06700                     && i.index_reg
06701                     && (i.base_reg->reg_type & Reg16)
06702                     && (i.index_reg->reg_type & Reg16)
06703                     && i.base_reg->reg_num >= 6
06704                     && i.index_reg->reg_num < 6)
06705                   {
06706                     const reg_entry *base = i.index_reg;
06707 
06708                     i.index_reg = i.base_reg;
06709                     i.base_reg = base;
06710                   }
06711                 ret = i386_index_check (operand_string);
06712               }
06713            }
06714        }
06715 
06716       /* Constant and OFFSET expressions are handled by i386_immediate.  */
06717       else if ((intel_parser.op_modifier & (1 << T_OFFSET))
06718               || intel_parser.reg == NULL)
06719        ret = i386_immediate (intel_parser.disp);
06720 
06721       if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
06722        ret = 0;
06723       if (!ret || !intel_parser.next_operand)
06724        break;
06725       intel_parser.op_string = intel_parser.next_operand;
06726       this_operand = i.operands++;
06727     }
06728 
06729   free (p);
06730   free (intel_parser.disp);
06731 
06732   return ret;
06733 }
06734 
06735 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
06736 
06737 /* expr       e04 expr'
06738 
06739    expr'  cmpOp e04 expr'
06740        | Empty  */
06741 static int
06742 intel_expr (void)
06743 {
06744   /* XXX Implement the comparison operators.  */
06745   return intel_e04 ();
06746 }
06747 
06748 /* e04 e05 e04'
06749 
06750    e04'       addOp e05 e04'
06751        | Empty  */
06752 static int
06753 intel_e04 (void)
06754 {
06755   int nregs = -1;
06756 
06757   for (;;)
06758     {
06759       if (!intel_e05())
06760        return 0;
06761 
06762       if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
06763        i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
06764 
06765       if (cur_token.code == '+')
06766        nregs = -1;
06767       else if (cur_token.code == '-')
06768        nregs = NUM_ADDRESS_REGS;
06769       else
06770        return 1;
06771 
06772       strcat (intel_parser.disp, cur_token.str);
06773       intel_match_token (cur_token.code);
06774     }
06775 }
06776 
06777 /* e05 e06 e05'
06778 
06779    e05'       binOp e06 e05'
06780        | Empty  */
06781 static int
06782 intel_e05 (void)
06783 {
06784   int nregs = ~NUM_ADDRESS_REGS;
06785 
06786   for (;;)
06787     {
06788       if (!intel_e06())
06789        return 0;
06790 
06791       if (cur_token.code == '&'
06792          || cur_token.code == '|'
06793          || cur_token.code == '^')
06794        {
06795          char str[2];
06796 
06797          str[0] = cur_token.code;
06798          str[1] = 0;
06799          strcat (intel_parser.disp, str);
06800        }
06801       else
06802        break;
06803 
06804       intel_match_token (cur_token.code);
06805 
06806       if (nregs < 0)
06807        nregs = ~nregs;
06808     }
06809   if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
06810     i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
06811   return 1;
06812 }
06813 
06814 /* e06 e09 e06'
06815 
06816    e06'       mulOp e09 e06'
06817        | Empty  */
06818 static int
06819 intel_e06 (void)
06820 {
06821   int nregs = ~NUM_ADDRESS_REGS;
06822 
06823   for (;;)
06824     {
06825       if (!intel_e09())
06826        return 0;
06827 
06828       if (cur_token.code == '*'
06829          || cur_token.code == '/'
06830          || cur_token.code == '%')
06831        {
06832          char str[2];
06833 
06834          str[0] = cur_token.code;
06835          str[1] = 0;
06836          strcat (intel_parser.disp, str);
06837        }
06838       else if (cur_token.code == T_SHL)
06839        strcat (intel_parser.disp, "<<");
06840       else if (cur_token.code == T_SHR)
06841        strcat (intel_parser.disp, ">>");
06842       else
06843        break;
06844 
06845       intel_match_token (cur_token.code);
06846 
06847       if (nregs < 0)
06848        nregs = ~nregs;
06849     }
06850   if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
06851     i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
06852   return 1;
06853 }
06854 
06855 /* e09 OFFSET e09
06856        | SHORT e09
06857        | + e09
06858        | - e09
06859        | ~ e09
06860        | NOT e09
06861        | e10 e09'
06862 
06863    e09'       PTR e10 e09'
06864        | : e10 e09'
06865        | Empty */
06866 static int
06867 intel_e09 (void)
06868 {
06869   int nregs = ~NUM_ADDRESS_REGS;
06870   int in_offset = 0;
06871 
06872   for (;;)
06873     {
06874       /* Don't consume constants here.  */
06875       if (cur_token.code == '+' || cur_token.code == '-')
06876        {
06877          /* Need to look one token ahead - if the next token
06878             is a constant, the current token is its sign.  */
06879          int next_code;
06880 
06881          intel_match_token (cur_token.code);
06882          next_code = cur_token.code;
06883          intel_putback_token ();
06884          if (next_code == T_CONST)
06885            break;
06886        }
06887 
06888       /* e09  OFFSET e09  */
06889       if (cur_token.code == T_OFFSET)
06890        {
06891          if (!in_offset++)
06892            ++intel_parser.in_offset;
06893        }
06894 
06895       /* e09  SHORT e09  */
06896       else if (cur_token.code == T_SHORT)
06897        intel_parser.op_modifier |= 1 << T_SHORT;
06898 
06899       /* e09  + e09  */
06900       else if (cur_token.code == '+')
06901        strcat (intel_parser.disp, "+");
06902 
06903       /* e09  - e09
06904              | ~ e09
06905              | NOT e09  */
06906       else if (cur_token.code == '-' || cur_token.code == '~')
06907        {
06908          char str[2];
06909 
06910          if (nregs < 0)
06911            nregs = ~nregs;
06912          str[0] = cur_token.code;
06913          str[1] = 0;
06914          strcat (intel_parser.disp, str);
06915        }
06916 
06917       /* e09  e10 e09'  */
06918       else
06919        break;
06920 
06921       intel_match_token (cur_token.code);
06922     }
06923 
06924   for (;;)
06925     {
06926       if (!intel_e10 ())
06927        return 0;
06928 
06929       /* e09'  PTR e10 e09' */
06930       if (cur_token.code == T_PTR)
06931        {
06932          char suffix;
06933 
06934          if (prev_token.code == T_BYTE)
06935            suffix = BYTE_MNEM_SUFFIX;
06936 
06937          else if (prev_token.code == T_WORD)
06938            {
06939              if (current_templates->start->name[0] == 'l'
06940                 && current_templates->start->name[2] == 's'
06941                 && current_templates->start->name[3] == 0)
06942               suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
06943              else if (intel_parser.got_a_float == 2)    /* "fi..." */
06944               suffix = SHORT_MNEM_SUFFIX;
06945              else
06946               suffix = WORD_MNEM_SUFFIX;
06947            }
06948 
06949          else if (prev_token.code == T_DWORD)
06950            {
06951              if (current_templates->start->name[0] == 'l'
06952                 && current_templates->start->name[2] == 's'
06953                 && current_templates->start->name[3] == 0)
06954               suffix = WORD_MNEM_SUFFIX;
06955              else if (flag_code == CODE_16BIT
06956                      && (current_templates->start->opcode_modifier
06957                         & (Jump | JumpDword)))
06958               suffix = LONG_DOUBLE_MNEM_SUFFIX;
06959              else if (intel_parser.got_a_float == 1)    /* "f..." */
06960               suffix = SHORT_MNEM_SUFFIX;
06961              else
06962               suffix = LONG_MNEM_SUFFIX;
06963            }
06964 
06965          else if (prev_token.code == T_FWORD)
06966            {
06967              if (current_templates->start->name[0] == 'l'
06968                 && current_templates->start->name[2] == 's'
06969                 && current_templates->start->name[3] == 0)
06970               suffix = LONG_MNEM_SUFFIX;
06971              else if (!intel_parser.got_a_float)
06972               {
06973                 if (flag_code == CODE_16BIT)
06974                   add_prefix (DATA_PREFIX_OPCODE);
06975                 suffix = LONG_DOUBLE_MNEM_SUFFIX;
06976               }
06977              else
06978               suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
06979            }
06980 
06981          else if (prev_token.code == T_QWORD)
06982            {
06983              if (intel_parser.got_a_float == 1)  /* "f..." */
06984               suffix = LONG_MNEM_SUFFIX;
06985              else
06986               suffix = QWORD_MNEM_SUFFIX;
06987            }
06988 
06989          else if (prev_token.code == T_TBYTE)
06990            {
06991              if (intel_parser.got_a_float == 1)
06992               suffix = LONG_DOUBLE_MNEM_SUFFIX;
06993              else
06994               suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
06995            }
06996 
06997          else if (prev_token.code == T_XMMWORD)
06998            {
06999              /* XXX ignored for now, but accepted since gcc uses it */
07000              suffix = 0;
07001            }
07002 
07003          else
07004            {
07005              as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
07006              return 0;
07007            }
07008 
07009          /* Operands for jump/call using 'ptr' notation denote absolute
07010             addresses.  */
07011          if (current_templates->start->opcode_modifier & (Jump | JumpDword))
07012            i.types[this_operand] |= JumpAbsolute;
07013 
07014          if (current_templates->start->base_opcode == 0x8d /* lea */)
07015            ;
07016          else if (!i.suffix)
07017            i.suffix = suffix;
07018          else if (i.suffix != suffix)
07019            {
07020              as_bad (_("Conflicting operand modifiers"));
07021              return 0;
07022            }
07023 
07024        }
07025 
07026       /* e09'  : e10 e09'  */
07027       else if (cur_token.code == ':')
07028        {
07029          if (prev_token.code != T_REG)
07030            {
07031              /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
07032                segment/group identifier (which we don't have), using comma
07033                as the operand separator there is even less consistent, since
07034                there all branches only have a single operand.  */
07035              if (this_operand != 0
07036                 || intel_parser.in_offset
07037                 || intel_parser.in_bracket
07038                 || (!(current_templates->start->opcode_modifier
07039                      & (Jump|JumpDword|JumpInterSegment))
07040                     && !(current_templates->start->operand_types[0]
07041                         & JumpAbsolute)))
07042               return intel_match_token (T_NIL);
07043              /* Remember the start of the 2nd operand and terminate 1st
07044                operand here.
07045                XXX This isn't right, yet (when SSSS:OOOO is right operand of
07046                another expression), but it gets at least the simplest case
07047                (a plain number or symbol on the left side) right.  */
07048              intel_parser.next_operand = intel_parser.op_string;
07049              *--intel_parser.op_string = '\0';
07050              return intel_match_token (':');
07051            }
07052        }
07053 
07054       /* e09'  Empty  */
07055       else
07056        break;
07057 
07058       intel_match_token (cur_token.code);
07059 
07060     }
07061 
07062   if (in_offset)
07063     {
07064       --intel_parser.in_offset;
07065       if (nregs < 0)
07066        nregs = ~nregs;
07067       if (NUM_ADDRESS_REGS > nregs)
07068        {
07069          as_bad (_("Invalid operand to `OFFSET'"));
07070          return 0;
07071        }
07072       intel_parser.op_modifier |= 1 << T_OFFSET;
07073     }
07074 
07075   if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
07076     i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
07077   return 1;
07078 }
07079 
07080 static int
07081 intel_bracket_expr (void)
07082 {
07083   int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
07084   const char *start = intel_parser.op_string;
07085   int len;
07086 
07087   if (i.op[this_operand].regs)
07088     return intel_match_token (T_NIL);
07089 
07090   intel_match_token ('[');
07091 
07092   /* Mark as a memory operand only if it's not already known to be an
07093      offset expression.  If it's an offset expression, we need to keep
07094      the brace in.  */
07095   if (!intel_parser.in_offset)
07096     {
07097       ++intel_parser.in_bracket;
07098 
07099       /* Operands for jump/call inside brackets denote absolute addresses.  */
07100       if (current_templates->start->opcode_modifier & (Jump | JumpDword))
07101        i.types[this_operand] |= JumpAbsolute;
07102 
07103       /* Unfortunately gas always diverged from MASM in a respect that can't
07104         be easily fixed without risking to break code sequences likely to be
07105         encountered (the testsuite even check for this): MASM doesn't consider
07106         an expression inside brackets unconditionally as a memory reference.
07107         When that is e.g. a constant, an offset expression, or the sum of the
07108         two, this is still taken as a constant load. gas, however, always
07109         treated these as memory references. As a compromise, we'll try to make
07110         offset expressions inside brackets work the MASM way (since that's
07111         less likely to be found in real world code), but make constants alone
07112         continue to work the traditional gas way. In either case, issue a
07113         warning.  */
07114       intel_parser.op_modifier &= ~was_offset;
07115     }
07116   else
07117     strcat (intel_parser.disp, "[");
07118 
07119   /* Add a '+' to the displacement string if necessary.  */
07120   if (*intel_parser.disp != '\0'
07121       && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
07122     strcat (intel_parser.disp, "+");
07123 
07124   if (intel_expr ()
07125       && (len = intel_parser.op_string - start - 1,
07126          intel_match_token (']')))
07127     {
07128       /* Preserve brackets when the operand is an offset expression.  */
07129       if (intel_parser.in_offset)
07130        strcat (intel_parser.disp, "]");
07131       else
07132        {
07133          --intel_parser.in_bracket;
07134          if (i.base_reg || i.index_reg)
07135            intel_parser.is_mem = 1;
07136          if (!intel_parser.is_mem)
07137            {
07138              if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
07139               /* Defer the warning until all of the operand was parsed.  */
07140               intel_parser.is_mem = -1;
07141              else if (!quiet_warnings)
07142               as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
07143                       len, start, len, start);
07144            }
07145        }
07146       intel_parser.op_modifier |= was_offset;
07147 
07148       return 1;
07149     }
07150   return 0;
07151 }
07152 
07153 /* e10 e11 e10'
07154 
07155    e10'       [ expr ] e10'
07156        | Empty  */
07157 static int
07158 intel_e10 (void)
07159 {
07160   if (!intel_e11 ())
07161     return 0;
07162 
07163   while (cur_token.code == '[')
07164     {
07165       if (!intel_bracket_expr ())
07166        return 0;
07167     }
07168 
07169   return 1;
07170 }
07171 
07172 /* e11 ( expr )
07173        | [ expr ]
07174        | BYTE
07175        | WORD
07176        | DWORD
07177        | FWORD
07178        | QWORD
07179        | TBYTE
07180        | OWORD
07181        | XMMWORD
07182        | $
07183        | .
07184        | register
07185        | id
07186        | constant  */
07187 static int
07188 intel_e11 (void)
07189 {
07190   switch (cur_token.code)
07191     {
07192     /* e11  ( expr ) */
07193     case '(':
07194       intel_match_token ('(');
07195       strcat (intel_parser.disp, "(");
07196 
07197       if (intel_expr () && intel_match_token (')'))
07198        {
07199          strcat (intel_parser.disp, ")");
07200          return 1;
07201        }
07202       return 0;
07203 
07204     /* e11  [ expr ] */
07205     case '[':
07206       return intel_bracket_expr ();
07207 
07208     /* e11  $
07209            | .  */
07210     case '.':
07211       strcat (intel_parser.disp, cur_token.str);
07212       intel_match_token (cur_token.code);
07213 
07214       /* Mark as a memory operand only if it's not already known to be an
07215         offset expression.  */
07216       if (!intel_parser.in_offset)
07217        intel_parser.is_mem = 1;
07218 
07219       return 1;
07220 
07221     /* e11  register  */
07222     case T_REG:
07223       {
07224        const reg_entry *reg = intel_parser.reg = cur_token.reg;
07225 
07226        intel_match_token (T_REG);
07227 
07228        /* Check for segment change.  */
07229        if (cur_token.code == ':')
07230          {
07231            if (!(reg->reg_type & (SReg2 | SReg3)))
07232              {
07233               as_bad (_("`%s' is not a valid segment register"),
07234                      reg->reg_name);
07235               return 0;
07236              }
07237            else if (i.seg[i.mem_operands])
07238              as_warn (_("Extra segment override ignored"));
07239            else
07240              {
07241               if (!intel_parser.in_offset)
07242                 intel_parser.is_mem = 1;
07243               switch (reg->reg_num)
07244                 {
07245                 case 0:
07246                   i.seg[i.mem_operands] = &es;
07247                   break;
07248                 case 1:
07249                   i.seg[i.mem_operands] = &cs;
07250                   break;
07251                 case 2:
07252                   i.seg[i.mem_operands] = &ss;
07253                   break;
07254                 case 3:
07255                   i.seg[i.mem_operands] = &ds;
07256                   break;
07257                 case 4:
07258                   i.seg[i.mem_operands] = &fs;
07259                   break;
07260                 case 5:
07261                   i.seg[i.mem_operands] = &gs;
07262                   break;
07263                 }
07264              }
07265          }
07266 
07267        /* Not a segment register. Check for register scaling.  */
07268        else if (cur_token.code == '*')
07269          {
07270            if (!intel_parser.in_bracket)
07271              {
07272               as_bad (_("Register scaling only allowed in memory operands"));
07273               return 0;
07274              }
07275 
07276            if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
07277              reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
07278            else if (i.index_reg)
07279              reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
07280 
07281            /* What follows must be a valid scale.  */
07282            intel_match_token ('*');
07283            i.index_reg = reg;
07284            i.types[this_operand] |= BaseIndex;
07285 
07286            /* Set the scale after setting the register (otherwise,
07287               i386_scale will complain)  */
07288            if (cur_token.code == '+' || cur_token.code == '-')
07289              {
07290               char *str, sign = cur_token.code;
07291               intel_match_token (cur_token.code);
07292               if (cur_token.code != T_CONST)
07293                 {
07294                   as_bad (_("Syntax error: Expecting a constant, got `%s'"),
07295                          cur_token.str);
07296                   return 0;
07297                 }
07298               str = (char *) xmalloc (strlen (cur_token.str) + 2);
07299               strcpy (str + 1, cur_token.str);
07300               *str = sign;
07301               if (!i386_scale (str))
07302                 return 0;
07303               free (str);
07304              }
07305            else if (!i386_scale (cur_token.str))
07306              return 0;
07307            intel_match_token (cur_token.code);
07308          }
07309 
07310        /* No scaling. If this is a memory operand, the register is either a
07311           base register (first occurrence) or an index register (second
07312           occurrence).  */
07313        else if (intel_parser.in_bracket)
07314          {
07315 
07316            if (!i.base_reg)
07317              i.base_reg = reg;
07318            else if (!i.index_reg)
07319              i.index_reg = reg;
07320            else
07321              {
07322               as_bad (_("Too many register references in memory operand"));
07323               return 0;
07324              }
07325 
07326            i.types[this_operand] |= BaseIndex;
07327          }
07328 
07329        /* It's neither base nor index.  */
07330        else if (!intel_parser.in_offset && !intel_parser.is_mem)
07331          {
07332            i.types[this_operand] |= reg->reg_type & ~BaseIndex;
07333            i.op[this_operand].regs = reg;
07334            i.reg_operands++;
07335          }
07336        else
07337          {
07338            as_bad (_("Invalid use of register"));
07339            return 0;
07340          }
07341 
07342        /* Since registers are not part of the displacement string (except
07343           when we're parsing offset operands), we may need to remove any
07344           preceding '+' from the displacement string.  */
07345        if (*intel_parser.disp != '\0'
07346            && !intel_parser.in_offset)
07347          {
07348            char *s = intel_parser.disp;
07349            s += strlen (s) - 1;
07350            if (*s == '+')
07351              *s = '\0';
07352          }
07353 
07354        return 1;
07355       }
07356 
07357     /* e11  BYTE
07358            | WORD
07359            | DWORD
07360            | FWORD
07361            | QWORD
07362            | TBYTE
07363            | OWORD
07364            | XMMWORD  */
07365     case T_BYTE:
07366     case T_WORD:
07367     case T_DWORD:
07368     case T_FWORD:
07369     case T_QWORD:
07370     case T_TBYTE:
07371     case T_XMMWORD:
07372       intel_match_token (cur_token.code);
07373 
07374       if (cur_token.code == T_PTR)
07375        return 1;
07376 
07377       /* It must have been an identifier.  */
07378       intel_putback_token ();
07379       cur_token.code = T_ID;
07380       /* FALLTHRU */
07381 
07382     /* e11  id
07383            | constant  */
07384     case T_ID:
07385       if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
07386        {
07387          symbolS *symbolP;
07388 
07389          /* The identifier represents a memory reference only if it's not
07390             preceded by an offset modifier and if it's not an equate.  */
07391          symbolP = symbol_find(cur_token.str);
07392          if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
07393            intel_parser.is_mem = 1;
07394        }
07395        /* FALLTHRU */
07396 
07397     case T_CONST:
07398     case '-':
07399     case '+':
07400       {
07401        char *save_str, sign = 0;
07402 
07403        /* Allow constants that start with `+' or `-'.  */
07404        if (cur_token.code == '-' || cur_token.code == '+')
07405          {
07406            sign = cur_token.code;
07407            intel_match_token (cur_token.code);
07408            if (cur_token.code != T_CONST)
07409              {
07410               as_bad (_("Syntax error: Expecting a constant, got `%s'"),
07411                      cur_token.str);
07412               return 0;
07413              }
07414          }
07415 
07416        save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
07417        strcpy (save_str + !!sign, cur_token.str);
07418        if (sign)
07419          *save_str = sign;
07420 
07421        /* Get the next token to check for register scaling.  */
07422        intel_match_token (cur_token.code);
07423 
07424        /* Check if this constant is a scaling factor for an
07425           index register.  */
07426        if (cur_token.code == '*')
07427          {
07428            if (intel_match_token ('*') && cur_token.code == T_REG)
07429              {
07430               const reg_entry *reg = cur_token.reg;
07431 
07432               if (!intel_parser.in_bracket)
07433                 {
07434                   as_bad (_("Register scaling only allowed "
07435                            "in memory operands"));
07436                   return 0;
07437                 }
07438 
07439                /* Disallow things like [1*si].
07440                   sp and esp are invalid as index.  */
07441               if (reg->reg_type & Reg16)
07442                 reg = i386_regtab + REGNAM_AX + 4;
07443               else if (i.index_reg)
07444                 reg = i386_regtab + REGNAM_EAX + 4;
07445 
07446               /* The constant is followed by `* reg', so it must be
07447                  a valid scale.  */
07448               i.index_reg = reg;
07449               i.types[this_operand] |= BaseIndex;
07450 
07451               /* Set the scale after setting the register (otherwise,
07452                  i386_scale will complain)  */
07453               if (!i386_scale (save_str))
07454                 return 0;
07455               intel_match_token (T_REG);
07456 
07457               /* Since registers are not part of the displacement
07458                  string, we may need to remove any preceding '+' from
07459                  the displacement string.  */
07460               if (*intel_parser.disp != '\0')
07461                 {
07462                   char *s = intel_parser.disp;
07463                   s += strlen (s) - 1;
07464                   if (*s == '+')
07465                     *s = '\0';
07466                 }
07467 
07468               free (save_str);
07469 
07470               return 1;
07471              }
07472 
07473            /* The constant was not used for register scaling. Since we have
07474               already consumed the token following `*' we now need to put it
07475               back in the stream.  */
07476            intel_putback_token ();
07477          }
07478 
07479        /* Add the constant to the displacement string.  */
07480        strcat (intel_parser.disp, save_str);
07481        free (save_str);
07482 
07483        return 1;
07484       }
07485     }
07486 
07487   as_bad (_("Unrecognized token '%s'"), cur_token.str);
07488   return 0;
07489 }
07490 
07491 /* Match the given token against cur_token. If they match, read the next
07492    token from the operand string.  */
07493 static int
07494 intel_match_token (int code)
07495 {
07496   if (cur_token.code == code)
07497     {
07498       intel_get_token ();
07499       return 1;
07500     }
07501   else
07502     {
07503       as_bad (_("Unexpected token `%s'"), cur_token.str);
07504       return 0;
07505     }
07506 }
07507 
07508 /* Read a new token from intel_parser.op_string and store it in cur_token.  */
07509 static void
07510 intel_get_token (void)
07511 {
07512   char *end_op;
07513   const reg_entry *reg;
07514   struct intel_token new_token;
07515 
07516   new_token.code = T_NIL;
07517   new_token.reg = NULL;
07518   new_token.str = NULL;
07519 
07520   /* Free the memory allocated to the previous token and move
07521      cur_token to prev_token.  */
07522   if (prev_token.str)
07523     free (prev_token.str);
07524 
07525   prev_token = cur_token;
07526 
07527   /* Skip whitespace.  */
07528   while (is_space_char (*intel_parser.op_string))
07529     intel_parser.op_string++;
07530 
07531   /* Return an empty token if we find nothing else on the line.  */
07532   if (*intel_parser.op_string == '\0')
07533     {
07534       cur_token = new_token;
07535       return;
07536     }
07537 
07538   /* The new token cannot be larger than the remainder of the operand
07539      string.  */
07540   new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
07541   new_token.str[0] = '\0';
07542 
07543   if (strchr ("0123456789", *intel_parser.op_string))
07544     {
07545       char *p = new_token.str;
07546       char *q = intel_parser.op_string;
07547       new_token.code = T_CONST;
07548 
07549       /* Allow any kind of identifier char to encompass floating point and
07550         hexadecimal numbers.  */
07551       while (is_identifier_char (*q))
07552        *p++ = *q++;
07553       *p = '\0';
07554 
07555       /* Recognize special symbol names [0-9][bf].  */
07556       if (strlen (intel_parser.op_string) == 2
07557          && (intel_parser.op_string[1] == 'b'
07558              || intel_parser.op_string[1] == 'f'))
07559        new_token.code = T_ID;
07560     }
07561 
07562   else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
07563     {
07564       size_t len = end_op - intel_parser.op_string;
07565 
07566       new_token.code = T_REG;
07567       new_token.reg = reg;
07568 
07569       memcpy (new_token.str, intel_parser.op_string, len);
07570       new_token.str[len] = '\0';
07571     }
07572 
07573   else if (is_identifier_char (*intel_parser.op_string))
07574     {
07575       char *p = new_token.str;
07576       char *q = intel_parser.op_string;
07577 
07578       /* A '.' or '$' followed by an identifier char is an identifier.
07579         Otherwise, it's operator '.' followed by an expression.  */
07580       if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
07581        {
07582          new_token.code = '.';
07583          new_token.str[0] = '.';
07584          new_token.str[1] = '\0';
07585        }
07586       else
07587        {
07588          while (is_identifier_char (*q) || *q == '@')
07589            *p++ = *q++;
07590          *p = '\0';
07591 
07592          if (strcasecmp (new_token.str, "NOT") == 0)
07593            new_token.code = '~';
07594 
07595          else if (strcasecmp (new_token.str, "MOD") == 0)
07596            new_token.code = '%';
07597 
07598          else if (strcasecmp (new_token.str, "AND") == 0)
07599            new_token.code = '&';
07600 
07601          else if (strcasecmp (new_token.str, "OR") == 0)
07602            new_token.code = '|';
07603 
07604          else if (strcasecmp (new_token.str, "XOR") == 0)
07605            new_token.code = '^';
07606 
07607          else if (strcasecmp (new_token.str, "SHL") == 0)
07608            new_token.code = T_SHL;
07609 
07610          else if (strcasecmp (new_token.str, "SHR") == 0)
07611            new_token.code = T_SHR;
07612 
07613          else if (strcasecmp (new_token.str, "BYTE") == 0)
07614            new_token.code = T_BYTE;
07615 
07616          else if (strcasecmp (new_token.str, "WORD") == 0)
07617            new_token.code = T_WORD;
07618 
07619          else if (strcasecmp (new_token.str, "DWORD") == 0)
07620            new_token.code = T_DWORD;
07621 
07622          else if (strcasecmp (new_token.str, "FWORD") == 0)
07623            new_token.code = T_FWORD;
07624 
07625          else if (strcasecmp (new_token.str, "QWORD") == 0)
07626            new_token.code = T_QWORD;
07627 
07628          else if (strcasecmp (new_token.str, "TBYTE") == 0
07629                  /* XXX remove (gcc still uses it) */
07630                  || strcasecmp (new_token.str, "XWORD") == 0)
07631            new_token.code = T_TBYTE;
07632 
07633          else if (strcasecmp (new_token.str, "XMMWORD") == 0
07634                  || strcasecmp (new_token.str, "OWORD") == 0)
07635            new_token.code = T_XMMWORD;
07636 
07637          else if (strcasecmp (new_token.str, "PTR") == 0)
07638            new_token.code = T_PTR;
07639 
07640          else if (strcasecmp (new_token.str, "SHORT") == 0)
07641            new_token.code = T_SHORT;
07642 
07643          else if (strcasecmp (new_token.str, "OFFSET") == 0)
07644            {
07645              new_token.code = T_OFFSET;
07646 
07647              /* ??? This is not mentioned in the MASM grammar but gcc
07648                    makes use of it with -mintel-syntax.  OFFSET may be
07649                    followed by FLAT:  */
07650              if (strncasecmp (q, " FLAT:", 6) == 0)
07651               strcat (new_token.str, " FLAT:");
07652            }
07653 
07654          /* ??? This is not mentioned in the MASM grammar.  */
07655          else if (strcasecmp (new_token.str, "FLAT") == 0)
07656            {
07657              new_token.code = T_OFFSET;
07658              if (*q == ':')
07659               strcat (new_token.str, ":");
07660              else
07661               as_bad (_("`:' expected"));
07662            }
07663 
07664          else
07665            new_token.code = T_ID;
07666        }
07667     }
07668 
07669   else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
07670     {
07671       new_token.code = *intel_parser.op_string;
07672       new_token.str[0] = *intel_parser.op_string;
07673       new_token.str[1] = '\0';
07674     }
07675 
07676   else if (strchr ("<>", *intel_parser.op_string)
07677           && *intel_parser.op_string == *(intel_parser.op_string + 1))
07678     {
07679       new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
07680       new_token.str[0] = *intel_parser.op_string;
07681       new_token.str[1] = *intel_parser.op_string;
07682       new_token.str[2] = '\0';
07683     }
07684 
07685   else
07686     as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
07687 
07688   intel_parser.op_string += strlen (new_token.str);
07689   cur_token = new_token;
07690 }
07691 
07692 /* Put cur_token back into the token stream and make cur_token point to
07693    prev_token.  */
07694 static void
07695 intel_putback_token (void)
07696 {
07697   if (cur_token.code != T_NIL)
07698     {
07699       intel_parser.op_string -= strlen (cur_token.str);
07700       free (cur_token.str);
07701     }
07702   cur_token = prev_token;
07703 
07704   /* Forget prev_token.  */
07705   prev_token.code = T_NIL;
07706   prev_token.reg = NULL;
07707   prev_token.str = NULL;
07708 }
07709 
07710 int
07711 tc_x86_regname_to_dw2regnum (char *regname)
07712 {
07713   unsigned int regnum;
07714   unsigned int regnames_count;
07715   static const char *const regnames_32[] =
07716     {
07717       "eax", "ecx", "edx", "ebx",
07718       "esp", "ebp", "esi", "edi",
07719       "eip", "eflags", NULL,
07720       "st0", "st1", "st2", "st3",
07721       "st4", "st5", "st6", "st7",
07722       NULL, NULL,
07723       "xmm0", "xmm1", "xmm2", "xmm3",
07724       "xmm4", "xmm5", "xmm6", "xmm7",
07725       "mm0", "mm1", "mm2", "mm3",
07726       "mm4", "mm5", "mm6", "mm7",
07727       "fcw", "fsw", "mxcsr",
07728       "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
07729       "tr", "ldtr"
07730     };
07731   static const char *const regnames_64[] =
07732     {
07733       "rax", "rdx", "rcx", "rbx",
07734       "rsi", "rdi", "rbp", "rsp",
07735       "r8",  "r9",  "r10", "r11",
07736       "r12", "r13", "r14", "r15",
07737       "rip",
07738       "xmm0",  "xmm1",  "xmm2",  "xmm3",
07739       "xmm4",  "xmm5",  "xmm6",  "xmm7",
07740       "xmm8",  "xmm9",  "xmm10", "xmm11",
07741       "xmm12", "xmm13", "xmm14", "xmm15",
07742       "st0", "st1", "st2", "st3",
07743       "st4", "st5", "st6", "st7",
07744       "mm0", "mm1", "mm2", "mm3",
07745       "mm4", "mm5", "mm6", "mm7",
07746       "rflags",
07747       "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
07748       "fs.base", "gs.base", NULL, NULL,
07749       "tr", "ldtr",
07750       "mxcsr", "fcw", "fsw"
07751     };
07752   const char *const *regnames;
07753 
07754   if (flag_code == CODE_64BIT)
07755     {
07756       regnames = regnames_64;
07757       regnames_count = ARRAY_SIZE (regnames_64);
07758     }
07759   else
07760     {
07761       regnames = regnames_32;
07762       regnames_count = ARRAY_SIZE (regnames_32);
07763     }
07764 
07765   for (regnum = 0; regnum < regnames_count; regnum++)
07766     if (regnames[regnum] != NULL
07767        && strcmp (regname, regnames[regnum]) == 0)
07768       return regnum;
07769 
07770   return -1;
07771 }
07772 
07773 void
07774 tc_x86_frame_initial_instructions (void)
07775 {
07776   static unsigned int sp_regno;
07777 
07778   if (!sp_regno)
07779     sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
07780                                        ? "rsp" : "esp");
07781 
07782   cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
07783   cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
07784 }
07785 
07786 int
07787 i386_elf_section_type (const char *str, size_t len)
07788 {
07789   if (flag_code == CODE_64BIT
07790       && len == sizeof ("unwind") - 1
07791       && strncmp (str, "unwind", 6) == 0)
07792     return SHT_X86_64_UNWIND;
07793 
07794   return -1;
07795 }
07796 
07797 #ifdef TE_PE
07798 void
07799 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
07800 {
07801   expressionS expr;
07802 
07803   expr.X_op = O_secrel;
07804   expr.X_add_symbol = symbol;
07805   expr.X_add_number = 0;
07806   emit_expr (&expr, size);
07807 }
07808 #endif
07809 
07810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
07811 /* For ELF on x86-64, add support for SHF_X86_64_LARGE.  */
07812 
07813 int
07814 x86_64_section_letter (int letter, char **ptr_msg)
07815 {
07816   if (flag_code == CODE_64BIT)
07817     {
07818       if (letter == 'l')
07819        return SHF_X86_64_LARGE;
07820 
07821       *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
07822     }
07823   else
07824     *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
07825   return -1;
07826 }
07827 
07828 int
07829 x86_64_section_word (char *str, size_t len)
07830 {
07831   if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
07832     return SHF_X86_64_LARGE;
07833 
07834   return -1;
07835 }
07836 
07837 static void
07838 handle_large_common (int small ATTRIBUTE_UNUSED)
07839 {
07840   if (flag_code != CODE_64BIT)
07841     {
07842       s_comm_internal (0, elf_common_parse);
07843       as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
07844     }
07845   else
07846     {
07847       static segT lbss_section;
07848       asection *saved_com_section_ptr = elf_com_section_ptr;
07849       asection *saved_bss_section = bss_section;
07850 
07851       if (lbss_section == NULL)
07852        {
07853          flagword applicable;
07854          segT seg = now_seg;
07855          subsegT subseg = now_subseg;
07856 
07857          /* The .lbss section is for local .largecomm symbols.  */
07858          lbss_section = subseg_new (".lbss", 0);
07859          applicable = bfd_applicable_section_flags (stdoutput);
07860          bfd_set_section_flags (stdoutput, lbss_section,
07861                              applicable & SEC_ALLOC);
07862          seg_info (lbss_section)->bss = 1;
07863 
07864          subseg_set (seg, subseg);
07865        }
07866 
07867       elf_com_section_ptr = &_bfd_elf_large_com_section;
07868       bss_section = lbss_section;
07869 
07870       s_comm_internal (0, elf_common_parse);
07871 
07872       elf_com_section_ptr = saved_com_section_ptr;
07873       bss_section = saved_bss_section;
07874     }
07875 }
07876 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */