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cell-binutils  2.17cvs20070401
tc-d30v.c
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00001 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
00002    Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
00003    Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with GAS; see the file COPYING.  If not, write to
00019    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
00020    Boston, MA 02110-1301, USA.  */
00021 
00022 #include "as.h"
00023 #include "safe-ctype.h"
00024 #include "subsegs.h"
00025 #include "opcode/d30v.h"
00026 
00027 const char comment_chars[]        = ";";
00028 const char line_comment_chars[]   = "#";
00029 const char line_separator_chars[] = "";
00030 const char *md_shortopts          = "OnNcC";
00031 const char EXP_CHARS[]            = "eE";
00032 const char FLT_CHARS[]            = "dD";
00033 
00034 #if HAVE_LIMITS_H
00035 #include <limits.h>
00036 #endif
00037 
00038 #ifndef CHAR_BIT
00039 #define CHAR_BIT 8
00040 #endif
00041 
00042 #define NOP_MULTIPLY 1
00043 #define NOP_ALL 2
00044 static int warn_nops = 0;
00045 static int Optimizing = 0;
00046 static int warn_register_name_conflicts = 1;
00047 
00048 #define FORCE_SHORT  1
00049 #define FORCE_LONG   2
00050 
00051 /* EXEC types.  */
00052 typedef enum _exec_type
00053 {
00054   EXEC_UNKNOWN,                    /* No order specified.  */
00055   EXEC_PARALLEL,            /* Done in parallel (FM=00).  */
00056   EXEC_SEQ,                 /* Sequential (FM=01).  */
00057   EXEC_REVSEQ               /* Reverse sequential (FM=10).  */
00058 } exec_type_enum;
00059 
00060 /* Fixups.  */
00061 #define MAX_INSN_FIXUPS  5
00062 
00063 struct d30v_fixup
00064 {
00065   expressionS exp;
00066   int operand;
00067   int pcrel;
00068   int size;
00069   bfd_reloc_code_real_type reloc;
00070 };
00071 
00072 typedef struct _fixups
00073 {
00074   int fc;
00075   struct d30v_fixup fix[MAX_INSN_FIXUPS];
00076   struct _fixups *next;
00077 } Fixups;
00078 
00079 static Fixups FixUps[2];
00080 static Fixups *fixups;
00081 
00082 /* Whether current and previous instruction are word multiply insns.  */
00083 static int cur_mul32_p = 0;
00084 static int prev_mul32_p = 0;
00085 
00086 /*  The flag_explicitly_parallel is true iff the instruction being assembled
00087     has been explicitly written as a parallel short-instruction pair by the
00088     human programmer.  It is used in parallel_ok () to distinguish between
00089     those dangerous parallelizations attempted by the human, which are to be
00090     allowed, and those attempted by the assembler, which are not.  It is set
00091     from md_assemble ().  */
00092 static int flag_explicitly_parallel = 0;
00093 static int flag_xp_state = 0;
00094 
00095 /* Whether current and previous left sub-instruction disables
00096    execution of right sub-instruction.  */
00097 static int cur_left_kills_right_p = 0;
00098 static int prev_left_kills_right_p = 0;
00099 
00100 /* The known current alignment of the current section.  */
00101 static int d30v_current_align;
00102 static segT d30v_current_align_seg;
00103 
00104 /* The last seen label in the current section.  This is used to auto-align
00105    labels preceding instructions.  */
00106 static symbolS *d30v_last_label;
00107 
00108 /* Two nops.  */
00109 #define NOP_LEFT   ((long long) NOP << 32)
00110 #define NOP_RIGHT  ((long long) NOP)
00111 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
00112 
00113 struct option md_longopts[] =
00114 {
00115   {NULL, no_argument, NULL, 0}
00116 };
00117 
00118 size_t md_longopts_size = sizeof (md_longopts);
00119 
00120 /* Opcode hash table.  */
00121 static struct hash_control *d30v_hash;
00122 
00123 /* Do a binary search of the pre_defined_registers array to see if
00124    NAME is a valid regiter name.  Return the register number from the
00125    array on success, or -1 on failure.  */
00126 
00127 static int
00128 reg_name_search (char *name)
00129 {
00130   int middle, low, high;
00131   int cmp;
00132 
00133   low = 0;
00134   high = reg_name_cnt () - 1;
00135 
00136   do
00137     {
00138       middle = (low + high) / 2;
00139       cmp = strcasecmp (name, pre_defined_registers[middle].name);
00140       if (cmp < 0)
00141        high = middle - 1;
00142       else if (cmp > 0)
00143        low = middle + 1;
00144       else
00145        {
00146          if (symbol_find (name) != NULL)
00147            {
00148              if (warn_register_name_conflicts)
00149               as_warn (_("Register name %s conflicts with symbol of the same name"),
00150                       name);
00151            }
00152 
00153          return pre_defined_registers[middle].value;
00154        }
00155     }
00156   while (low <= high);
00157 
00158   return -1;
00159 }
00160 
00161 /* Check the string at input_line_pointer to see if it is a valid
00162    register name.  */
00163 
00164 static int
00165 register_name (expressionS *expressionP)
00166 {
00167   int reg_number;
00168   char c, *p = input_line_pointer;
00169 
00170   while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
00171     p++;
00172 
00173   c = *p;
00174   if (c)
00175     *p++ = 0;
00176 
00177   /* Look to see if it's in the register table.  */
00178   reg_number = reg_name_search (input_line_pointer);
00179   if (reg_number >= 0)
00180     {
00181       expressionP->X_op = O_register;
00182       /* Temporarily store a pointer to the string here.  */
00183       expressionP->X_op_symbol = (symbolS *) input_line_pointer;
00184       expressionP->X_add_number = reg_number;
00185       input_line_pointer = p;
00186       return 1;
00187     }
00188   if (c)
00189     *(p - 1) = c;
00190   return 0;
00191 }
00192 
00193 static int
00194 check_range (unsigned long num, int bits, int flags)
00195 {
00196   long min, max;
00197 
00198   /* Don't bother checking 32-bit values.  */
00199   if (bits == 32)
00200     {
00201       if (sizeof (unsigned long) * CHAR_BIT == 32)
00202        return 0;
00203 
00204       /* We don't record signed or unsigned for 32-bit quantities.
00205         Allow either.  */
00206       min = -((unsigned long) 1 << (bits - 1));
00207       max = ((unsigned long) 1 << bits) - 1;
00208       return (long) num < min || (long) num > max;
00209     }
00210 
00211   if (flags & OPERAND_SHIFT)
00212     {
00213       /* We know that all shifts are right by three bits.  */
00214       num >>= 3;
00215 
00216       if (flags & OPERAND_SIGNED)
00217        {
00218          unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1;
00219          num = (num ^ sign_bit) - sign_bit;
00220        }
00221     }
00222 
00223   if (flags & OPERAND_SIGNED)
00224     {
00225       max = ((unsigned long) 1 << (bits - 1)) - 1;
00226       min = - ((unsigned long) 1 << (bits - 1));
00227       return (long) num > max || (long) num < min;
00228     }
00229   else
00230     {
00231       max = ((unsigned long) 1 << bits) - 1;
00232       return num > (unsigned long) max;
00233     }
00234 }
00235 
00236 void
00237 md_show_usage (FILE *stream)
00238 {
00239   fprintf (stream, _("\nD30V options:\n\
00240 -O                      Make adjacent short instructions parallel if possible.\n\
00241 -n                      Warn about all NOPs inserted by the assembler.\n\
00242 -N                   Warn about NOPs inserted after word multiplies.\n\
00243 -c                      Warn about symbols whoes names match register names.\n\
00244 -C                      Opposite of -C.  -c is the default.\n"));
00245 }
00246 
00247 int
00248 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
00249 {
00250   switch (c)
00251     {
00252       /* Optimize.  Will attempt to parallelize operations.  */
00253     case 'O':
00254       Optimizing = 1;
00255       break;
00256 
00257       /* Warn about all NOPS that the assembler inserts.  */
00258     case 'n':
00259       warn_nops = NOP_ALL;
00260       break;
00261 
00262       /* Warn about the NOPS that the assembler inserts because of the
00263         multiply hazard.  */
00264     case 'N':
00265       warn_nops = NOP_MULTIPLY;
00266       break;
00267 
00268     case 'c':
00269       warn_register_name_conflicts = 1;
00270       break;
00271 
00272     case 'C':
00273       warn_register_name_conflicts = 0;
00274       break;
00275 
00276     default:
00277       return 0;
00278     }
00279   return 1;
00280 }
00281 
00282 symbolS *
00283 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
00284 {
00285   return 0;
00286 }
00287 
00288 /* Turn a string in input_line_pointer into a floating point constant
00289    of type TYPE, and store the appropriate bytes in *LITP.  The number
00290    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
00291    returned, or NULL on OK.  */
00292 
00293 char *
00294 md_atof (int type, char *litP, int *sizeP)
00295 {
00296   int prec;
00297   LITTLENUM_TYPE words[4];
00298   char *t;
00299   int i;
00300 
00301   switch (type)
00302     {
00303     case 'f':
00304       prec = 2;
00305       break;
00306     case 'd':
00307       prec = 4;
00308       break;
00309     default:
00310       *sizeP = 0;
00311       return _("bad call to md_atof");
00312     }
00313 
00314   t = atof_ieee (input_line_pointer, type, words);
00315   if (t)
00316     input_line_pointer = t;
00317 
00318   *sizeP = prec * 2;
00319 
00320   for (i = 0; i < prec; i++)
00321     {
00322       md_number_to_chars (litP, (valueT) words[i], 2);
00323       litP += 2;
00324     }
00325   return NULL;
00326 }
00327 
00328 void
00329 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
00330                asection *sec ATTRIBUTE_UNUSED,
00331                fragS *fragP ATTRIBUTE_UNUSED)
00332 {
00333   abort ();
00334 }
00335 
00336 valueT
00337 md_section_align (asection *seg, valueT addr)
00338 {
00339   int align = bfd_get_section_alignment (stdoutput, seg);
00340   return ((addr + (1 << align) - 1) & (-1 << align));
00341 }
00342 
00343 void
00344 md_begin (void)
00345 {
00346   struct d30v_opcode *opcode;
00347   d30v_hash = hash_new ();
00348 
00349   /* Insert opcode names into a hash table.  */
00350   for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++)
00351       hash_insert (d30v_hash, opcode->name, (char *) opcode);
00352 
00353   fixups = &FixUps[0];
00354   FixUps[0].next = &FixUps[1];
00355   FixUps[1].next = &FixUps[0];
00356 
00357   d30v_current_align_seg = now_seg;
00358 }
00359 
00360 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
00361    from an expression.  */
00362 
00363 static int
00364 postfix (char *p)
00365 {
00366   while (*p != '-' && *p != '+')
00367     {
00368       if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',')
00369        break;
00370       p++;
00371     }
00372 
00373   if (*p == '-')
00374     {
00375       *p = ' ';
00376       return -1;
00377     }
00378 
00379   if (*p == '+')
00380     {
00381       *p = ' ';
00382       return 1;
00383     }
00384 
00385   return 0;
00386 }
00387 
00388 static bfd_reloc_code_real_type
00389 get_reloc (struct d30v_operand *op, int rel_flag)
00390 {
00391   switch (op->bits)
00392     {
00393     case 6:
00394       if (op->flags & OPERAND_SHIFT)
00395        return BFD_RELOC_D30V_9_PCREL;
00396       else
00397        return BFD_RELOC_D30V_6;
00398       break;
00399     case 12:
00400       if (!(op->flags & OPERAND_SHIFT))
00401        as_warn (_("unexpected 12-bit reloc type"));
00402       if (rel_flag == RELOC_PCREL)
00403        return BFD_RELOC_D30V_15_PCREL;
00404       else
00405        return BFD_RELOC_D30V_15;
00406     case 18:
00407       if (!(op->flags & OPERAND_SHIFT))
00408        as_warn (_("unexpected 18-bit reloc type"));
00409       if (rel_flag == RELOC_PCREL)
00410        return BFD_RELOC_D30V_21_PCREL;
00411       else
00412        return BFD_RELOC_D30V_21;
00413     case 32:
00414       if (rel_flag == RELOC_PCREL)
00415        return BFD_RELOC_D30V_32_PCREL;
00416       else
00417        return BFD_RELOC_D30V_32;
00418     default:
00419       return 0;
00420     }
00421 }
00422 
00423 /* Parse a string of operands and return an array of expressions.  */
00424 
00425 static int
00426 get_operands (expressionS exp[], int cmp_hack)
00427 {
00428   char *p = input_line_pointer;
00429   int numops = 0;
00430   int post = 0;
00431 
00432   if (cmp_hack)
00433     {
00434       exp[numops].X_op = O_absent;
00435       exp[numops++].X_add_number = cmp_hack - 1;
00436     }
00437 
00438   while (*p)
00439     {
00440       while (*p == ' ' || *p == '\t' || *p == ',')
00441        p++;
00442 
00443       if (*p == 0 || *p == '\n' || *p == '\r')
00444        break;
00445 
00446       if (*p == '@')
00447        {
00448          p++;
00449          exp[numops].X_op = O_absent;
00450          if (*p == '(')
00451            {
00452              p++;
00453              exp[numops].X_add_number = OPERAND_ATPAR;
00454              post = postfix (p);
00455            }
00456          else if (*p == '-')
00457            {
00458              p++;
00459              exp[numops].X_add_number = OPERAND_ATMINUS;
00460            }
00461          else
00462            {
00463              exp[numops].X_add_number = OPERAND_ATSIGN;
00464              post = postfix (p);
00465            }
00466          numops++;
00467          continue;
00468        }
00469 
00470       if (*p == ')')
00471        {
00472          /* Just skip the trailing paren.  */
00473          p++;
00474          continue;
00475        }
00476 
00477       input_line_pointer = p;
00478 
00479       /* Check to see if it might be a register name.  */
00480       if (!register_name (&exp[numops]))
00481        {
00482          /* Parse as an expression.  */
00483          expression (&exp[numops]);
00484        }
00485 
00486       if (exp[numops].X_op == O_illegal)
00487        as_bad (_("illegal operand"));
00488       else if (exp[numops].X_op == O_absent)
00489        as_bad (_("missing operand"));
00490 
00491       numops++;
00492       p = input_line_pointer;
00493 
00494       switch (post)
00495        {
00496        case -1:
00497          /* Postdecrement mode.  */
00498          exp[numops].X_op = O_absent;
00499          exp[numops++].X_add_number = OPERAND_MINUS;
00500          break;
00501        case 1:
00502          /* Postincrement mode.  */
00503          exp[numops].X_op = O_absent;
00504          exp[numops++].X_add_number = OPERAND_PLUS;
00505          break;
00506        }
00507       post = 0;
00508     }
00509 
00510   exp[numops].X_op = 0;
00511 
00512   return numops;
00513 }
00514 
00515 /* Generate the instruction.
00516    It does everything but write the FM bits.  */
00517 
00518 static long long
00519 build_insn (struct d30v_insn *opcode, expressionS *opers)
00520 {
00521   int i, length, bits, shift, flags;
00522   unsigned long number, id = 0;
00523   long long insn;
00524   struct d30v_opcode *op = opcode->op;
00525   struct d30v_format *form = opcode->form;
00526 
00527   insn =
00528     opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
00529 
00530   for (i = 0; form->operands[i]; i++)
00531     {
00532       flags = d30v_operand_table[form->operands[i]].flags;
00533 
00534       /* Must be a register or number.  */
00535       if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM)
00536          && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
00537        continue;
00538 
00539       bits = d30v_operand_table[form->operands[i]].bits;
00540       if (flags & OPERAND_SHIFT)
00541        bits += 3;
00542 
00543       length = d30v_operand_table[form->operands[i]].length;
00544       shift = 12 - d30v_operand_table[form->operands[i]].position;
00545       if (opers[i].X_op != O_symbol)
00546        number = opers[i].X_add_number;
00547       else
00548        number = 0;
00549       if (flags & OPERAND_REG)
00550        {
00551          /* Check for mvfsys or mvtsys control registers.  */
00552          if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
00553            {
00554              /* PSWL or PSWH.  */
00555              id = (number & 0x7f) - MAX_CONTROL_REG;
00556              number = 0;
00557            }
00558          else if (number & OPERAND_FLAG)
00559            /* NUMBER is a flag register.  */
00560            id = 3;
00561 
00562          number &= 0x7F;
00563        }
00564       else if (flags & OPERAND_SPECIAL)
00565        number = id;
00566 
00567       if (opers[i].X_op != O_register && opers[i].X_op != O_constant
00568          && !(flags & OPERAND_NAME))
00569        {
00570          /* Now create a fixup.  */
00571          if (fixups->fc >= MAX_INSN_FIXUPS)
00572            as_fatal (_("too many fixups"));
00573 
00574          fixups->fix[fixups->fc].reloc =
00575            get_reloc ((struct d30v_operand *) &d30v_operand_table[form->operands[i]], op->reloc_flag);
00576          fixups->fix[fixups->fc].size = 4;
00577          fixups->fix[fixups->fc].exp = opers[i];
00578          fixups->fix[fixups->fc].operand = form->operands[i];
00579          if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
00580            fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
00581          else
00582            fixups->fix[fixups->fc].pcrel = op->reloc_flag;
00583          (fixups->fc)++;
00584        }
00585 
00586       /* Truncate to the proper number of bits.  */
00587       if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
00588        as_bad (_("operand out of range: %ld"), number);
00589       if (bits < 31)
00590        number &= 0x7FFFFFFF >> (31 - bits);
00591       if (flags & OPERAND_SHIFT)
00592        number >>= 3;
00593       if (bits == 32)
00594        {
00595          /* It's a LONG instruction.  */
00596          insn |= ((number & 0xffffffff) >> 26);  /* Top 6 bits.  */
00597          insn <<= 32;                     /* Shift the first word over.  */
00598          insn |= ((number & 0x03FC0000) << 2);          /* Next 8 bits.  */
00599          insn |= number & 0x0003FFFF;                   /* Bottom 18 bits.  */
00600        }
00601       else
00602        insn |= number << shift;
00603     }
00604 
00605   return insn;
00606 }
00607 
00608 static void
00609 d30v_number_to_chars (char *buf,   /* Return 'nbytes' of chars here.  */
00610                     long long value,      /* The value of the bits.  */
00611                     int n)         /* Number of bytes in the output.  */
00612 {
00613   while (n--)
00614     {
00615       buf[n] = value & 0xff;
00616       value >>= 8;
00617     }
00618 }
00619 
00620 /* Write out a long form instruction.  */
00621 
00622 static void
00623 write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
00624            long long insn,
00625            Fixups *fx)
00626 {
00627   int i, where;
00628   char *f = frag_more (8);
00629 
00630   insn |= FM11;
00631   d30v_number_to_chars (f, insn, 8);
00632 
00633   for (i = 0; i < fx->fc; i++)
00634     {
00635       if (fx->fix[i].reloc)
00636        {
00637          where = f - frag_now->fr_literal;
00638          fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
00639                      fx->fix[i].pcrel, fx->fix[i].reloc);
00640        }
00641     }
00642 
00643   fx->fc = 0;
00644 }
00645 
00646 /* Write out a short form instruction by itself.  */
00647 
00648 static void
00649 write_1_short (struct d30v_insn *opcode,
00650               long long insn,
00651               Fixups *fx,
00652               int use_sequential)
00653 {
00654   char *f = frag_more (8);
00655   int i, where;
00656 
00657   if (warn_nops == NOP_ALL)
00658     as_warn (_("%s NOP inserted"), use_sequential ?
00659             _("sequential") : _("parallel"));
00660 
00661   /* The other container needs to be NOP.  */
00662   if (use_sequential)
00663     {
00664       /* Use a sequential NOP rather than a parallel one,
00665         as the current instruction is a FLAG_MUL32 type one
00666         and the next instruction is a load.  */
00667 
00668       /* According to 4.3.1: for FM=01, sub-instructions performed
00669         only by IU cannot be encoded in L-container.  */
00670       if (opcode->op->unit == IU)
00671        /* Right then left.  */
00672        insn |= FM10 | NOP_LEFT;
00673       else
00674        /* Left then right.  */
00675        insn = FM01 | (insn << 32) | NOP_RIGHT;
00676     }
00677   else
00678     {
00679       /* According to 4.3.1: for FM=00, sub-instructions performed
00680         only by IU cannot be encoded in L-container.  */
00681       if (opcode->op->unit == IU)
00682        /* Right container.  */
00683        insn |= FM00 | NOP_LEFT;
00684       else
00685        /* Left container.  */
00686        insn = FM00 | (insn << 32) | NOP_RIGHT;
00687     }
00688 
00689   d30v_number_to_chars (f, insn, 8);
00690 
00691   for (i = 0; i < fx->fc; i++)
00692     {
00693       if (fx->fix[i].reloc)
00694        {
00695          where = f - frag_now->fr_literal;
00696          fix_new_exp (frag_now,
00697                      where,
00698                      fx->fix[i].size,
00699                      &(fx->fix[i].exp),
00700                      fx->fix[i].pcrel,
00701                      fx->fix[i].reloc);
00702        }
00703     }
00704 
00705   fx->fc = 0;
00706 }
00707 
00708 /* Check 2 instructions and determine if they can be safely
00709    executed in parallel.  Return 1 if they can be.  */
00710 
00711 static int
00712 parallel_ok (struct d30v_insn *op1,
00713             unsigned long insn1,
00714             struct d30v_insn *op2,
00715             unsigned long insn2,
00716             exec_type_enum exec_type)
00717 {
00718   int i, j, shift, regno, bits, ecc;
00719   unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
00720   unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
00721   struct d30v_format *f;
00722   struct d30v_opcode *op;
00723 
00724   /* Section 4.3: Both instructions must not be IU or MU only.  */
00725   if ((op1->op->unit == IU && op2->op->unit == IU)
00726       || (op1->op->unit == MU && op2->op->unit == MU))
00727     return 0;
00728 
00729   /* First instruction must not be a jump to safely optimize, unless this
00730      is an explicit parallel operation.  */
00731   if (exec_type != EXEC_PARALLEL
00732       && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
00733     return 0;
00734 
00735   /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
00736      then it is safe to allow the two to be done as parallel ops, since only
00737      one will ever be executed at a time.  */
00738   if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
00739       || (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
00740       || (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
00741       || (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
00742     return 1;
00743 
00744   /* [0] r0-r31
00745      [1] r32-r63
00746      [2] a0, a1, flag registers.  */
00747   for (j = 0; j < 2; j++)
00748     {
00749       if (j == 0)
00750        {
00751          f = op1->form;
00752          op = op1->op;
00753          ecc = op1->ecc;
00754          ins = insn1;
00755        }
00756       else
00757        {
00758          f = op2->form;
00759          op = op2->op;
00760          ecc = op2->ecc;
00761          ins = insn2;
00762        }
00763 
00764       flag_reg[j] = 0;
00765       mod_reg[j][0] = mod_reg[j][1] = 0;
00766       used_reg[j][0] = used_reg[j][1] = 0;
00767 
00768       if (flag_explicitly_parallel)
00769        {
00770          /* For human specified parallel instructions we have been asked
00771             to ignore the possibility that both instructions could modify
00772             bits in the PSW, so we initialise the mod & used arrays to 0.
00773             We have been asked, however, to refuse to allow parallel
00774             instructions which explicitly set the same flag register,
00775             eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
00776             for the use of a flag register and set a bit in the mod or used
00777             array appropriately.  */
00778          mod_reg[j][2]  = 0;
00779          used_reg[j][2] = 0;
00780        }
00781       else
00782        {
00783          mod_reg[j][2] = (op->flags_set & FLAG_ALL);
00784          used_reg[j][2] = (op->flags_used & FLAG_ALL);
00785        }
00786 
00787       /* BSR/JSR always sets R62.  */
00788       if (op->flags_used & FLAG_JSR)
00789        mod_reg[j][1] = (1L << (62 - 32));
00790 
00791       /* Conditional execution affects the flags_used.  */
00792       switch (ecc)
00793        {
00794        case ECC_TX:
00795        case ECC_FX:
00796          used_reg[j][2] |= flag_reg[j] = FLAG_0;
00797          break;
00798 
00799        case ECC_XT:
00800        case ECC_XF:
00801          used_reg[j][2] |= flag_reg[j] = FLAG_1;
00802          break;
00803 
00804        case ECC_TT:
00805        case ECC_TF:
00806          used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
00807          break;
00808        }
00809 
00810       for (i = 0; f->operands[i]; i++)
00811        {
00812          flags = d30v_operand_table[f->operands[i]].flags;
00813          shift = 12 - d30v_operand_table[f->operands[i]].position;
00814          bits = d30v_operand_table[f->operands[i]].bits;
00815          if (bits == 32)
00816            mask = 0xffffffff;
00817          else
00818            mask = 0x7FFFFFFF >> (31 - bits);
00819 
00820          if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
00821            {
00822              /* This is a post-increment or post-decrement.
00823                The previous register needs to be marked as modified.  */
00824              shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
00825              regno = (ins >> shift) & 0x3f;
00826              if (regno >= 32)
00827               mod_reg[j][1] |= 1L << (regno - 32);
00828              else
00829               mod_reg[j][0] |= 1L << regno;
00830            }
00831          else if (flags & OPERAND_REG)
00832            {
00833              regno = (ins >> shift) & mask;
00834              /* The memory write functions don't have a destination
00835                  register.  */
00836              if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
00837               {
00838                 /* MODIFIED registers and flags.  */
00839                 if (flags & OPERAND_ACC)
00840                   {
00841                     if (regno == 0)
00842                      mod_reg[j][2] |= FLAG_A0;
00843                     else if (regno == 1)
00844                      mod_reg[j][2] |= FLAG_A1;
00845                     else
00846                      abort ();
00847                   }
00848                 else if (flags & OPERAND_FLAG)
00849                   mod_reg[j][2] |= 1L << regno;
00850                 else if (!(flags & OPERAND_CONTROL))
00851                   {
00852                     int r, z;
00853 
00854                     /* Need to check if there are two destination
00855                       registers, for example ld2w.  */
00856                     if (flags & OPERAND_2REG)
00857                      z = 1;
00858                     else
00859                      z = 0;
00860 
00861                     for (r = regno; r <= regno + z; r++)
00862                      {
00863                        if (r >= 32)
00864                          mod_reg[j][1] |= 1L << (r - 32);
00865                        else
00866                          mod_reg[j][0] |= 1L << r;
00867                      }
00868                   }
00869               }
00870              else
00871               {
00872                 /* USED, but not modified registers and flags.  */
00873                 if (flags & OPERAND_ACC)
00874                   {
00875                     if (regno == 0)
00876                      used_reg[j][2] |= FLAG_A0;
00877                     else if (regno == 1)
00878                      used_reg[j][2] |= FLAG_A1;
00879                     else
00880                      abort ();
00881                   }
00882                 else if (flags & OPERAND_FLAG)
00883                   used_reg[j][2] |= 1L << regno;
00884                 else if (!(flags & OPERAND_CONTROL))
00885                   {
00886                     int r, z;
00887 
00888                     /* Need to check if there are two source
00889                       registers, for example st2w.  */
00890                     if (flags & OPERAND_2REG)
00891                      z = 1;
00892                     else
00893                      z = 0;
00894 
00895                     for (r = regno; r <= regno + z; r++)
00896                      {
00897                        if (r >= 32)
00898                          used_reg[j][1] |= 1L << (r - 32);
00899                        else
00900                          used_reg[j][0] |= 1L << r;
00901                      }
00902                   }
00903               }
00904            }
00905        }
00906     }
00907 
00908   flags_set1 = op1->op->flags_set;
00909   flags_set2 = op2->op->flags_set;
00910   flags_used1 = op1->op->flags_used;
00911   flags_used2 = op2->op->flags_used;
00912 
00913   /* Check for illegal combinations with ADDppp/SUBppp.  */
00914   if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
00915        && (flags_used2 & FLAG_ADDSUBppp) != 0)
00916       || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
00917          && (flags_used1 & FLAG_ADDSUBppp) != 0))
00918     return 0;
00919 
00920   /* Load instruction combined with half-word multiply is illegal.  */
00921   if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
00922       || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
00923     return 0;
00924 
00925   /* Specifically allow add || add by removing carry, overflow bits dependency.
00926      This is safe, even if an addc follows since the IU takes the argument in
00927      the right container, and it writes its results last.
00928      However, don't paralellize add followed by addc or sub followed by
00929      subb.  */
00930   if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
00931       && (used_reg[0][2] & ~flag_reg[0]) == 0
00932       && (used_reg[1][2] & ~flag_reg[1]) == 0
00933       && op1->op->unit == EITHER && op2->op->unit == EITHER)
00934     {
00935       mod_reg[0][2] = mod_reg[1][2] = 0;
00936     }
00937 
00938   for (j = 0; j < 3; j++)
00939     {
00940       /* If the second instruction depends on the first, we obviously
00941         cannot parallelize.  Note, the mod flag implies use, so
00942         check that as well.  */
00943       /* If flag_explicitly_parallel is set, then the case of the
00944         second instruction using a register the first instruction
00945         modifies is assumed to be okay; we trust the human.  We
00946         don't trust the human if both instructions modify the same
00947         register but we do trust the human if they modify the same
00948         flags.  */
00949       /* We have now been requested not to trust the human if the
00950         instructions modify the same flag registers either.  */
00951       if (flag_explicitly_parallel)
00952        {
00953          if ((mod_reg[0][j] & mod_reg[1][j]) != 0)
00954            return 0;
00955        }
00956       else
00957        if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
00958          return 0;
00959     }
00960 
00961   return 1;
00962 }
00963 
00964 /* Write out a short form instruction if possible.
00965    Return number of instructions not written out.  */
00966 
00967 static int
00968 write_2_short (struct d30v_insn *opcode1,
00969               long long insn1,
00970               struct d30v_insn *opcode2,
00971               long long insn2,
00972               exec_type_enum exec_type,
00973               Fixups *fx)
00974 {
00975   long long insn = NOP2;
00976   char *f;
00977   int i, j, where;
00978 
00979   if (exec_type == EXEC_SEQ
00980       && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
00981       && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
00982       && ((opcode1->ecc == ECC_AL) || ! Optimizing))
00983     {
00984       /* Unconditional, non-delayed branches kill instructions in
00985         the right bin.  Conditional branches don't always but if
00986         we are not optimizing, then we have been asked to produce
00987         an error about such constructs.  For the purposes of this
00988         test, subroutine calls are considered to be branches.  */
00989       write_1_short (opcode1, insn1, fx->next, FALSE);
00990       return 1;
00991     }
00992 
00993   /* Note: we do not have to worry about subroutine calls occurring
00994      in the right hand container.  The return address is always
00995      aligned to the next 64 bit boundary, be that 64 or 32 bit away.  */
00996   switch (exec_type)
00997     {
00998     case EXEC_UNKNOWN:      /* Order not specified.  */
00999       if (Optimizing
01000          && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
01001          && ! (   (opcode1->op->unit == EITHER_BUT_PREFER_MU
01002                || opcode1->op->unit == MU)
01003               &&
01004               (   opcode2->op->unit == EITHER_BUT_PREFER_MU
01005                || opcode2->op->unit == MU)))
01006        {
01007          /* Parallel.  */
01008          exec_type = EXEC_PARALLEL;
01009 
01010          if (opcode1->op->unit == IU
01011              || opcode2->op->unit == MU
01012              || opcode2->op->unit == EITHER_BUT_PREFER_MU)
01013            insn = FM00 | (insn2 << 32) | insn1;
01014          else
01015            {
01016              insn = FM00 | (insn1 << 32) | insn2;
01017              fx = fx->next;
01018            }
01019        }
01020       else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
01021               && ((opcode1->op->flags_used & FLAG_DELAY) == 0))
01022               || opcode1->op->flags_used & FLAG_RP)
01023        {
01024          /* We must emit (non-delayed) branch type instructions
01025             on their own with nothing in the right container.  */
01026          /* We must treat repeat instructions likewise, since the
01027             following instruction has to be separate from the repeat
01028             in order to be repeated.  */
01029          write_1_short (opcode1, insn1, fx->next, FALSE);
01030          return 1;
01031        }
01032       else if (prev_left_kills_right_p)
01033        {
01034          /* The left instruction kils the right slot, so we
01035             must leave it empty.  */
01036          write_1_short (opcode1, insn1, fx->next, FALSE);
01037          return 1;
01038        }
01039       else if (opcode1->op->unit == IU)
01040        {
01041          if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
01042            {
01043              /* Case 103810 is a request from Mitsubishi that opcodes
01044                with EITHER_BUT_PREFER_MU should not be executed in
01045                reverse sequential order.  */
01046              write_1_short (opcode1, insn1, fx->next, FALSE);
01047              return 1;
01048            }
01049 
01050          /* Reverse sequential.  */
01051          insn = FM10 | (insn2 << 32) | insn1;
01052          exec_type = EXEC_REVSEQ;
01053        }
01054       else
01055        {
01056          /* Sequential.  */
01057          insn = FM01 | (insn1 << 32) | insn2;
01058          fx = fx->next;
01059          exec_type = EXEC_SEQ;
01060        }
01061       break;
01062 
01063     case EXEC_PARALLEL:     /* Parallel.  */
01064       flag_explicitly_parallel = flag_xp_state;
01065       if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
01066        as_bad (_("Instructions may not be executed in parallel"));
01067       else if (opcode1->op->unit == IU)
01068        {
01069          if (opcode2->op->unit == IU)
01070            as_bad (_("Two IU instructions may not be executed in parallel"));
01071          as_warn (_("Swapping instruction order"));
01072          insn = FM00 | (insn2 << 32) | insn1;
01073        }
01074       else if (opcode2->op->unit == MU)
01075        {
01076          if (opcode1->op->unit == MU)
01077            as_bad (_("Two MU instructions may not be executed in parallel"));
01078          else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
01079            as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
01080          as_warn (_("Swapping instruction order"));
01081          insn = FM00 | (insn2 << 32) | insn1;
01082        }
01083       else
01084        {
01085          if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
01086            as_warn (_("Executing %s in IU may not work in parallel execution"),
01087                    opcode2->op->name);
01088 
01089          insn = FM00 | (insn1 << 32) | insn2;
01090          fx = fx->next;
01091        }
01092       flag_explicitly_parallel = 0;
01093       break;
01094 
01095     case EXEC_SEQ:   /* Sequential.  */
01096       if (opcode1->op->unit == IU)
01097        as_bad (_("IU instruction may not be in the left container"));
01098       if (prev_left_kills_right_p)
01099        as_bad (_("special left instruction `%s' kills instruction "
01100                 "`%s' in right container"),
01101               opcode1->op->name, opcode2->op->name);
01102       insn = FM01 | (insn1 << 32) | insn2;
01103       fx = fx->next;
01104       break;
01105 
01106     case EXEC_REVSEQ:       /* Reverse sequential.  */
01107       if (opcode2->op->unit == MU)
01108        as_bad (_("MU instruction may not be in the right container"));
01109       if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
01110        as_warn (_("Executing %s in reverse serial with %s may not work"),
01111                opcode1->op->name, opcode2->op->name);
01112       else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
01113        as_warn (_("Executing %s in IU in reverse serial may not work"),
01114                opcode2->op->name);
01115       insn = FM10 | (insn1 << 32) | insn2;
01116       fx = fx->next;
01117       break;
01118 
01119     default:
01120       as_fatal (_("unknown execution type passed to write_2_short()"));
01121     }
01122 
01123   f = frag_more (8);
01124   d30v_number_to_chars (f, insn, 8);
01125 
01126   /* If the previous instruction was a 32-bit multiply but it is put into a
01127      parallel container, mark the current instruction as being a 32-bit
01128      multiply.  */
01129   if (prev_mul32_p && exec_type == EXEC_PARALLEL)
01130     cur_mul32_p = 1;
01131 
01132   for (j = 0; j < 2; j++)
01133     {
01134       for (i = 0; i < fx->fc; i++)
01135        {
01136          if (fx->fix[i].reloc)
01137            {
01138              where = (f - frag_now->fr_literal) + 4 * j;
01139 
01140              fix_new_exp (frag_now,
01141                         where,
01142                         fx->fix[i].size,
01143                         &(fx->fix[i].exp),
01144                         fx->fix[i].pcrel,
01145                         fx->fix[i].reloc);
01146            }
01147        }
01148 
01149       fx->fc = 0;
01150       fx = fx->next;
01151     }
01152 
01153   return 0;
01154 }
01155 
01156 /* Get a pointer to an entry in the format table.
01157    It must look at all formats for an opcode and use the operands
01158    to choose the correct one.  Return NULL on error.  */
01159 
01160 static struct d30v_format *
01161 find_format (struct d30v_opcode *opcode,
01162             expressionS myops[],
01163             int fsize,
01164             int cmp_hack)
01165 {
01166   int numops, match, index, i = 0, j, k;
01167   struct d30v_format *fm;
01168 
01169   if (opcode == NULL)
01170     return NULL;
01171 
01172   /* Get all the operands and save them as expressions.  */
01173   numops = get_operands (myops, cmp_hack);
01174 
01175   while ((index = opcode->format[i++]) != 0)
01176     {
01177       if (fsize == FORCE_SHORT && index >= LONG)
01178        continue;
01179 
01180       if (fsize == FORCE_LONG && index < LONG)
01181        continue;
01182 
01183       fm = (struct d30v_format *) &d30v_format_table[index];
01184       k = index;
01185       while (fm->form == index)
01186        {
01187          match = 1;
01188          /* Now check the operands for compatibility.  */
01189          for (j = 0; match && fm->operands[j]; j++)
01190            {
01191              int flags = d30v_operand_table[fm->operands[j]].flags;
01192              int bits = d30v_operand_table[fm->operands[j]].bits;
01193              int X_op = myops[j].X_op;
01194              int num = myops[j].X_add_number;
01195 
01196              if (flags & OPERAND_SPECIAL)
01197               break;
01198              else if (X_op == O_illegal)
01199               match = 0;
01200              else if (flags & OPERAND_REG)
01201               {
01202                 if (X_op != O_register
01203                     || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
01204                     || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
01205                     || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
01206                     || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
01207                     || ((flags & OPERAND_CONTROL)
01208                        && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
01209                   match = 0;
01210               }
01211              else if (((flags & OPERAND_MINUS)
01212                      && (X_op != O_absent || num != OPERAND_MINUS))
01213                      || ((flags & OPERAND_PLUS)
01214                         && (X_op != O_absent || num != OPERAND_PLUS))
01215                      || ((flags & OPERAND_ATMINUS)
01216                         && (X_op != O_absent || num != OPERAND_ATMINUS))
01217                      || ((flags & OPERAND_ATPAR)
01218                         && (X_op != O_absent || num != OPERAND_ATPAR))
01219                      || ((flags & OPERAND_ATSIGN)
01220                         && (X_op != O_absent || num != OPERAND_ATSIGN)))
01221               match = 0;
01222              else if (flags & OPERAND_NUM)
01223               {
01224                 /* A number can be a constant or symbol expression.  */
01225 
01226                 /* If we have found a register name, but that name
01227                    also matches a symbol, then re-parse the name as
01228                    an expression.  */
01229                 if (X_op == O_register
01230                     && symbol_find ((char *) myops[j].X_op_symbol))
01231                   {
01232                     input_line_pointer = (char *) myops[j].X_op_symbol;
01233                     expression (&myops[j]);
01234                   }
01235 
01236                 /* Turn an expression into a symbol for later resolution.  */
01237                 if (X_op != O_absent && X_op != O_constant
01238                     && X_op != O_symbol && X_op != O_register
01239                     && X_op != O_big)
01240                   {
01241                     symbolS *sym = make_expr_symbol (&myops[j]);
01242                     myops[j].X_op = X_op = O_symbol;
01243                     myops[j].X_add_symbol = sym;
01244                     myops[j].X_add_number = num = 0;
01245                   }
01246 
01247                 if (fm->form >= LONG)
01248                   {
01249                     /* If we're testing for a LONG format, either fits.  */
01250                     if (X_op != O_constant && X_op != O_symbol)
01251                      match = 0;
01252                   }
01253                 else if (fm->form < LONG
01254                         && ((fsize == FORCE_SHORT && X_op == O_symbol)
01255                             || (fm->form == SHORT_D2 && j == 0)))
01256                   match = 1;
01257 
01258                 /* This is the tricky part.  Will the constant or symbol
01259                    fit into the space in the current format?  */
01260                 else if (X_op == O_constant)
01261                   {
01262                     if (check_range (num, bits, flags))
01263                      match = 0;
01264                   }
01265                 else if (X_op == O_symbol
01266                         && S_IS_DEFINED (myops[j].X_add_symbol)
01267                         && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
01268                         && opcode->reloc_flag == RELOC_PCREL)
01269                   {
01270                     /* If the symbol is defined, see if the value will fit
01271                       into the form we're considering.  */
01272                     fragS *f;
01273                     long value;
01274 
01275                     /* Calculate the current address by running through the
01276                       previous frags and adding our current offset.  */
01277                     value = 0;
01278                     for (f = frchain_now->frch_root; f; f = f->fr_next)
01279                      value += f->fr_fix + f->fr_offset;
01280                     value = (S_GET_VALUE (myops[j].X_add_symbol) - value
01281                             - (obstack_next_free (&frchain_now->frch_obstack)
01282                               - frag_now->fr_literal));
01283                     if (check_range (value, bits, flags))
01284                      match = 0;
01285                   }
01286                 else
01287                   match = 0;
01288               }
01289            }
01290          /* We're only done if the operands matched so far AND there
01291             are no more to check.  */
01292          if (match && myops[j].X_op == 0)
01293            {
01294              /* Final check - issue a warning if an odd numbered register
01295                is used as the first register in an instruction that reads
01296                or writes 2 registers.  */
01297 
01298              for (j = 0; fm->operands[j]; j++)
01299               if (myops[j].X_op == O_register
01300                   && (myops[j].X_add_number & 1)
01301                   && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
01302                 as_warn (_("Odd numbered register used as target of multi-register instruction"));
01303 
01304              return fm;
01305            }
01306          fm = (struct d30v_format *) &d30v_format_table[++k];
01307        }
01308     }
01309   return NULL;
01310 }
01311 
01312 /* Assemble a single instruction and return an opcode.
01313    Return -1 (an invalid opcode) on error.  */
01314 
01315 #define NAME_BUF_LEN 20
01316 
01317 static long long
01318 do_assemble (char *str,
01319             struct d30v_insn *opcode,
01320             int shortp,
01321             int is_parallel)
01322 {
01323   char *op_start;
01324   char *save;
01325   char *op_end;
01326   char           name[NAME_BUF_LEN];
01327   int            cmp_hack;
01328   int            nlen = 0;
01329   int            fsize = (shortp ? FORCE_SHORT : 0);
01330   expressionS    myops[6];
01331   long long      insn;
01332 
01333   /* Drop leading whitespace.  */
01334   while (*str == ' ')
01335     str++;
01336 
01337   /* Find the opcode end.  */
01338   for (op_start = op_end = str;
01339        *op_end
01340        && nlen < (NAME_BUF_LEN - 1)
01341        && *op_end != '/'
01342        && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
01343        op_end++)
01344     {
01345       name[nlen] = TOLOWER (op_start[nlen]);
01346       nlen++;
01347     }
01348 
01349   if (nlen == 0)
01350     return -1;
01351 
01352   name[nlen] = 0;
01353 
01354   /* If there is an execution condition code, handle it.  */
01355   if (*op_end == '/')
01356     {
01357       int i = 0;
01358       while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
01359        i++;
01360 
01361       if (i == ECC_MAX)
01362        {
01363          char tmp[4];
01364          strncpy (tmp, op_end + 1, 2);
01365          tmp[2] = 0;
01366          as_bad (_("unknown condition code: %s"), tmp);
01367          return -1;
01368        }
01369       opcode->ecc = i;
01370       op_end += 3;
01371     }
01372   else
01373     opcode->ecc = ECC_AL;
01374 
01375   /* CMP and CMPU change their name based on condition codes.  */
01376   if (!strncmp (name, "cmp", 3))
01377     {
01378       int p, i;
01379       char **str = (char **) d30v_cc_names;
01380       if (name[3] == 'u')
01381        p = 4;
01382       else
01383        p = 3;
01384 
01385       for (i = 1; *str && strncmp (*str, &name[p], 2); i++, str++)
01386        ;
01387 
01388       /* cmpu only supports some condition codes.  */
01389       if (p == 4)
01390        {
01391          if (i < 3 || i > 6)
01392            {
01393              name[p + 2] = 0;
01394              as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
01395            }
01396        }
01397 
01398       if (!*str)
01399        {
01400          name[p + 2] = 0;
01401          as_bad (_("unknown condition code: %s"), &name[p]);
01402        }
01403 
01404       cmp_hack = i;
01405       name[p] = 0;
01406     }
01407   else
01408     cmp_hack = 0;
01409 
01410   /* Need to look for .s or .l.  */
01411   if (name[nlen - 2] == '.')
01412     {
01413       switch (name[nlen - 1])
01414        {
01415        case 's':
01416          fsize = FORCE_SHORT;
01417          break;
01418        case 'l':
01419          fsize = FORCE_LONG;
01420          break;
01421        }
01422       name[nlen - 2] = 0;
01423     }
01424 
01425   /* Find the first opcode with the proper name.  */
01426   opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
01427   if (opcode->op == NULL)
01428     {
01429       as_bad (_("unknown opcode: %s"), name);
01430       return -1;
01431     }
01432 
01433   save = input_line_pointer;
01434   input_line_pointer = op_end;
01435   while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
01436     {
01437       opcode->op++;
01438       if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
01439        {
01440          as_bad (_("operands for opcode `%s' do not match any valid format"),
01441                 name);
01442          return -1;
01443        }
01444     }
01445   input_line_pointer = save;
01446 
01447   insn = build_insn (opcode, myops);
01448 
01449   /* Propagate multiply status.  */
01450   if (insn != -1)
01451     {
01452       if (is_parallel && prev_mul32_p)
01453        cur_mul32_p = 1;
01454       else
01455        {
01456          prev_mul32_p = cur_mul32_p;
01457          cur_mul32_p  = (opcode->op->flags_used & FLAG_MUL32) != 0;
01458        }
01459     }
01460 
01461   /* Propagate left_kills_right status.  */
01462   if (insn != -1)
01463     {
01464       prev_left_kills_right_p = cur_left_kills_right_p;
01465 
01466       if (opcode->op->flags_set & FLAG_LKR)
01467        {
01468          cur_left_kills_right_p = 1;
01469 
01470          if (strcmp (opcode->op->name, "mvtsys") == 0)
01471            {
01472              /* Left kills right for only mvtsys only for
01473                  PSW/PSWH/PSWL/flags target.  */
01474              if ((myops[0].X_op == O_register) &&
01475                 ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
01476                  (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
01477                  (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
01478                  (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
01479                  (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
01480                  (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
01481                  (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
01482                  (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
01483                  (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
01484                  (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
01485                  (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
01486               {
01487                 cur_left_kills_right_p = 1;
01488               }
01489              else
01490               {
01491                 /* Other mvtsys target registers don't kill right
01492                      instruction.  */
01493                 cur_left_kills_right_p = 0;
01494               }
01495            } /* mvtsys */
01496        }
01497       else
01498        cur_left_kills_right_p = 0;
01499     }
01500 
01501   return insn;
01502 }
01503 
01504 /* Called internally to handle all alignment needs.  This takes care
01505    of eliding calls to frag_align if'n the cached current alignment
01506    says we've already got it, as well as taking care of the auto-aligning
01507    labels wrt code.  */
01508 
01509 static void
01510 d30v_align (int n, char *pfill, symbolS *label)
01511 {
01512   /* The front end is prone to changing segments out from under us
01513      temporarily when -g is in effect.  */
01514   int switched_seg_p = (d30v_current_align_seg != now_seg);
01515 
01516   /* Do not assume that if 'd30v_current_align >= n' and
01517      '! switched_seg_p' that it is safe to avoid performing
01518      this alignment request.  The alignment of the current frag
01519      can be changed under our feet, for example by a .ascii
01520      directive in the source code.  cf testsuite/gas/d30v/reloc.s  */
01521   d30v_cleanup (FALSE);
01522 
01523   if (pfill == NULL)
01524     {
01525       if (n > 2
01526          && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
01527        {
01528          static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
01529 
01530          /* First, make sure we're on a four-byte boundary, in case
01531             someone has been putting .byte values the text section.  */
01532          if (d30v_current_align < 2 || switched_seg_p)
01533            frag_align (2, 0, 0);
01534          frag_align_pattern (n, nop, sizeof nop, 0);
01535        }
01536       else
01537        frag_align (n, 0, 0);
01538     }
01539   else
01540     frag_align (n, *pfill, 0);
01541 
01542   if (!switched_seg_p)
01543     d30v_current_align = n;
01544 
01545   if (label != NULL)
01546     {
01547       symbolS     *sym;
01548       int          label_seen = FALSE;
01549       struct frag *old_frag;
01550       valueT       old_value;
01551       valueT       new_value;
01552 
01553       assert (S_GET_SEGMENT (label) == now_seg);
01554 
01555       old_frag  = symbol_get_frag (label);
01556       old_value = S_GET_VALUE (label);
01557       new_value = (valueT) frag_now_fix ();
01558 
01559       /* It is possible to have more than one label at a particular
01560         address, especially if debugging is enabled, so we must
01561         take care to adjust all the labels at this address in this
01562         fragment.  To save time we search from the end of the symbol
01563         list, backwards, since the symbols we are interested in are
01564         almost certainly the ones that were most recently added.
01565         Also to save time we stop searching once we have seen at least
01566         one matching label, and we encounter a label that is no longer
01567         in the target fragment.  Note, this search is guaranteed to
01568         find at least one match when sym == label, so no special case
01569         code is necessary.  */
01570       for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
01571        {
01572          if (symbol_get_frag (sym) == old_frag
01573              && S_GET_VALUE (sym) == old_value)
01574            {
01575              label_seen = TRUE;
01576              symbol_set_frag (sym, frag_now);
01577              S_SET_VALUE (sym, new_value);
01578            }
01579          else if (label_seen && symbol_get_frag (sym) != old_frag)
01580            break;
01581        }
01582     }
01583 
01584   record_alignment (now_seg, n);
01585 }
01586 
01587 /* This is the main entry point for the machine-dependent assembler.
01588    STR points to a machine-dependent instruction.  This function is
01589    supposed to emit the frags/bytes it assembles to.  For the D30V, it
01590    mostly handles the special VLIW parsing and packing and leaves the
01591    difficult stuff to do_assemble ().  */
01592 
01593 static long long prev_insn = -1;
01594 static struct d30v_insn prev_opcode;
01595 static subsegT prev_subseg;
01596 static segT prev_seg = 0;
01597 
01598 void
01599 md_assemble (char *str)
01600 {
01601   struct d30v_insn opcode;
01602   long long insn;
01603   /* Execution type; parallel, etc.  */
01604   exec_type_enum extype = EXEC_UNKNOWN;
01605   /* Saved extype.  Used for multiline instructions.  */
01606   static exec_type_enum etype = EXEC_UNKNOWN;
01607   char *str2;
01608 
01609   if ((prev_insn != -1) && prev_seg
01610       && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
01611     d30v_cleanup (FALSE);
01612 
01613   if (d30v_current_align < 3)
01614     d30v_align (3, NULL, d30v_last_label);
01615   else if (d30v_current_align > 3)
01616     d30v_current_align = 3;
01617   d30v_last_label = NULL;
01618 
01619   flag_explicitly_parallel = 0;
01620   flag_xp_state = 0;
01621   if (etype == EXEC_UNKNOWN)
01622     {
01623       /* Look for the special multiple instruction separators.  */
01624       str2 = strstr (str, "||");
01625       if (str2)
01626        {
01627          extype = EXEC_PARALLEL;
01628          flag_xp_state = 1;
01629        }
01630       else
01631        {
01632          str2 = strstr (str, "->");
01633          if (str2)
01634            extype = EXEC_SEQ;
01635          else
01636            {
01637              str2 = strstr (str, "<-");
01638              if (str2)
01639               extype = EXEC_REVSEQ;
01640            }
01641        }
01642 
01643       /* STR2 points to the separator, if one.  */
01644       if (str2)
01645        {
01646          *str2 = 0;
01647 
01648          /* If two instructions are present and we already have one saved,
01649             then first write it out.  */
01650          d30v_cleanup (FALSE);
01651 
01652          /* Assemble first instruction and save it.  */
01653          prev_insn = do_assemble (str, &prev_opcode, 1, 0);
01654          if (prev_insn == -1)
01655            as_bad (_("Cannot assemble instruction"));
01656          if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
01657            as_bad (_("First opcode is long.  Unable to mix instructions as specified."));
01658          fixups = fixups->next;
01659          str = str2 + 2;
01660          prev_seg = now_seg;
01661          prev_subseg = now_subseg;
01662        }
01663     }
01664 
01665   insn = do_assemble (str, &opcode,
01666                     (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
01667                     extype == EXEC_PARALLEL);
01668   if (insn == -1)
01669     {
01670       if (extype != EXEC_UNKNOWN)
01671        etype = extype;
01672       as_bad (_("Cannot assemble instruction"));
01673       return;
01674     }
01675 
01676   if (etype != EXEC_UNKNOWN)
01677     {
01678       extype = etype;
01679       etype = EXEC_UNKNOWN;
01680     }
01681 
01682   /* Word multiply instructions must not be followed by either a load or a
01683      16-bit multiply instruction in the next cycle.  */
01684   if (   (extype != EXEC_REVSEQ)
01685       && prev_mul32_p
01686       && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
01687     {
01688       /* However, load and multiply should able to be combined in a parallel
01689         operation, so check for that first.  */
01690       if (prev_insn != -1
01691          && (opcode.op->flags_used & FLAG_MEM)
01692          && opcode.form->form < LONG
01693          && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
01694          && parallel_ok (&prev_opcode, (long) prev_insn,
01695                        &opcode, (long) insn, extype)
01696          && write_2_short (&prev_opcode, (long) prev_insn,
01697                          &opcode, (long) insn, extype, fixups) == 0)
01698        {
01699          /* No instructions saved.  */
01700          prev_insn = -1;
01701          return;
01702        }
01703       else
01704        {
01705          /* Can't parallelize, flush previous instruction and emit a
01706             word of NOPS, unless the previous instruction is a NOP,
01707             in which case just flush it, as this will generate a word
01708             of NOPs for us.  */
01709 
01710          if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
01711            d30v_cleanup (FALSE);
01712          else
01713            {
01714              char *f;
01715 
01716              if (prev_insn != -1)
01717               d30v_cleanup (TRUE);
01718              else
01719               {
01720                 f = frag_more (8);
01721                 d30v_number_to_chars (f, NOP2, 8);
01722 
01723                 if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
01724                   {
01725                     if (opcode.op->flags_used & FLAG_MEM)
01726                      as_warn (_("word of NOPs added between word multiply and load"));
01727                     else
01728                      as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
01729                   }
01730               }
01731            }
01732 
01733          extype = EXEC_UNKNOWN;
01734        }
01735     }
01736   else if (   (extype == EXEC_REVSEQ)
01737           && cur_mul32_p
01738           && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
01739     {
01740       /* Can't parallelize, flush current instruction and add a
01741          sequential NOP.  */
01742       write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
01743 
01744       /* Make the previous instruction the current one.  */
01745       extype = EXEC_UNKNOWN;
01746       insn = prev_insn;
01747       now_seg = prev_seg;
01748       now_subseg = prev_subseg;
01749       prev_insn = -1;
01750       cur_mul32_p = prev_mul32_p;
01751       prev_mul32_p = 0;
01752       memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
01753     }
01754 
01755   /* If this is a long instruction, write it and any previous short
01756      instruction.  */
01757   if (opcode.form->form >= LONG)
01758     {
01759       if (extype != EXEC_UNKNOWN)
01760        as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
01761       d30v_cleanup (FALSE);
01762       write_long (&opcode, insn, fixups);
01763       prev_insn = -1;
01764     }
01765   else if ((prev_insn != -1)
01766           && (write_2_short
01767               (&prev_opcode, (long) prev_insn, &opcode,
01768               (long) insn, extype, fixups) == 0))
01769     {
01770       /* No instructions saved.  */
01771       prev_insn = -1;
01772     }
01773   else
01774     {
01775       if (extype != EXEC_UNKNOWN)
01776        as_bad (_("Unable to mix instructions as specified"));
01777 
01778       /* Save off last instruction so it may be packed on next pass.  */
01779       memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
01780       prev_insn = insn;
01781       prev_seg = now_seg;
01782       prev_subseg = now_subseg;
01783       fixups = fixups->next;
01784       prev_mul32_p = cur_mul32_p;
01785     }
01786 }
01787 
01788 /* If while processing a fixup, a reloc really needs to be created,
01789    then it is done here.  */
01790 
01791 arelent *
01792 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
01793 {
01794   arelent *reloc;
01795   reloc = xmalloc (sizeof (arelent));
01796   reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
01797   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
01798   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
01799   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
01800   if (reloc->howto == NULL)
01801     {
01802       as_bad_where (fixp->fx_file, fixp->fx_line,
01803                   _("reloc %d not supported by object file format"),
01804                   (int) fixp->fx_r_type);
01805       return NULL;
01806     }
01807 
01808   reloc->addend = 0;
01809   return reloc;
01810 }
01811 
01812 int
01813 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
01814                             asection *seg ATTRIBUTE_UNUSED)
01815 {
01816   abort ();
01817   return 0;
01818 }
01819 
01820 long
01821 md_pcrel_from_section (fixS *fixp, segT sec)
01822 {
01823   if (fixp->fx_addsy != (symbolS *) NULL
01824       && (!S_IS_DEFINED (fixp->fx_addsy)
01825          || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
01826     return 0;
01827   return fixp->fx_frag->fr_address + fixp->fx_where;
01828 }
01829 
01830 /* Called after the assembler has finished parsing the input file or
01831    after a label is defined.  Because the D30V assembler sometimes
01832    saves short instructions to see if it can package them with the
01833    next instruction, there may be a short instruction that still needs
01834    written.  */
01835 
01836 int
01837 d30v_cleanup (int use_sequential)
01838 {
01839   segT seg;
01840   subsegT subseg;
01841 
01842   if (prev_insn != -1)
01843     {
01844       seg = now_seg;
01845       subseg = now_subseg;
01846       subseg_set (prev_seg, prev_subseg);
01847       write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
01848                    use_sequential);
01849       subseg_set (seg, subseg);
01850       prev_insn = -1;
01851       if (use_sequential)
01852        prev_mul32_p = FALSE;
01853     }
01854 
01855   return 1;
01856 }
01857 
01858 /* This function is called at the start of every line.  It checks to
01859    see if the first character is a '.', which indicates the start of a
01860    pseudo-op.  If it is, then write out any unwritten instructions.  */
01861 
01862 void
01863 d30v_start_line (void)
01864 {
01865   char *c = input_line_pointer;
01866 
01867   while (ISSPACE (*c))
01868     c++;
01869 
01870   if (*c == '.')
01871     d30v_cleanup (FALSE);
01872 }
01873 
01874 static void
01875 check_size (long value, int bits, char *file, int line)
01876 {
01877   int tmp, max;
01878 
01879   if (value < 0)
01880     tmp = ~value;
01881   else
01882     tmp = value;
01883 
01884   max = (1 << (bits - 1)) - 1;
01885 
01886   if (tmp > max)
01887     as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
01888 }
01889 
01890 /* d30v_frob_label() is called when after a label is recognized.  */
01891 
01892 void
01893 d30v_frob_label (symbolS *lab)
01894 {
01895   /* Emit any pending instructions.  */
01896   d30v_cleanup (FALSE);
01897 
01898   /* Update the label's address with the current output pointer.  */
01899   symbol_set_frag (lab, frag_now);
01900   S_SET_VALUE (lab, (valueT) frag_now_fix ());
01901 
01902   /* Record this label for future adjustment after we find out what
01903      kind of data it references, and the required alignment therewith.  */
01904   d30v_last_label = lab;
01905 }
01906 
01907 /* Hook into cons for capturing alignment changes.  */
01908 
01909 void
01910 d30v_cons_align (int size)
01911 {
01912   int log_size;
01913 
01914   log_size = 0;
01915   while ((size >>= 1) != 0)
01916     ++log_size;
01917 
01918   if (d30v_current_align < log_size)
01919     d30v_align (log_size, (char *) NULL, NULL);
01920   else if (d30v_current_align > log_size)
01921     d30v_current_align = log_size;
01922   d30v_last_label = NULL;
01923 }
01924 
01925 void
01926 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
01927 {
01928   char *where;
01929   unsigned long insn, insn2;
01930   long value = *valP;
01931 
01932   if (fixP->fx_addsy == (symbolS *) NULL)
01933     fixP->fx_done = 1;
01934 
01935   /* We don't support subtracting a symbol.  */
01936   if (fixP->fx_subsy != (symbolS *) NULL)
01937     as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
01938 
01939   /* Fetch the instruction, insert the fully resolved operand
01940      value, and stuff the instruction back again.  */
01941   where = fixP->fx_frag->fr_literal + fixP->fx_where;
01942   insn = bfd_getb32 ((unsigned char *) where);
01943 
01944   switch (fixP->fx_r_type)
01945     {
01946     case BFD_RELOC_8:  /* Check for a bad .byte directive.  */
01947       if (fixP->fx_addsy != NULL)
01948        as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
01949               fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
01950       else if (((unsigned)value) > 0xff)
01951        as_bad (_("line %d: unable to place value %lx into a byte"),
01952               fixP->fx_line, value);
01953       else
01954        *(unsigned char *) where = value;
01955       break;
01956 
01957     case BFD_RELOC_16:  /* Check for a bad .short directive.  */
01958       if (fixP->fx_addsy != NULL)
01959        as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
01960               fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
01961       else if (((unsigned)value) > 0xffff)
01962        as_bad (_("line %d: unable to place value %lx into a short"),
01963               fixP->fx_line, value);
01964       else
01965        bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
01966       break;
01967 
01968     case BFD_RELOC_64:  /* Check for a bad .quad directive.  */
01969       if (fixP->fx_addsy != NULL)
01970        as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
01971               fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
01972       else
01973        {
01974          bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
01975          bfd_putb32 (0, ((unsigned char *) where) + 4);
01976        }
01977       break;
01978 
01979     case BFD_RELOC_D30V_6:
01980       check_size (value, 6, fixP->fx_file, fixP->fx_line);
01981       insn |= value & 0x3F;
01982       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
01983       break;
01984 
01985     case BFD_RELOC_D30V_9_PCREL:
01986       if (fixP->fx_where & 0x7)
01987        {
01988          if (fixP->fx_done)
01989            value += 4;
01990          else
01991            fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
01992        }
01993       check_size (value, 9, fixP->fx_file, fixP->fx_line);
01994       insn |= ((value >> 3) & 0x3F) << 12;
01995       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
01996       break;
01997 
01998     case BFD_RELOC_D30V_15:
01999       check_size (value, 15, fixP->fx_file, fixP->fx_line);
02000       insn |= (value >> 3) & 0xFFF;
02001       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
02002       break;
02003 
02004     case BFD_RELOC_D30V_15_PCREL:
02005       if (fixP->fx_where & 0x7)
02006        {
02007          if (fixP->fx_done)
02008            value += 4;
02009          else
02010            fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
02011        }
02012       check_size (value, 15, fixP->fx_file, fixP->fx_line);
02013       insn |= (value >> 3) & 0xFFF;
02014       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
02015       break;
02016 
02017     case BFD_RELOC_D30V_21:
02018       check_size (value, 21, fixP->fx_file, fixP->fx_line);
02019       insn |= (value >> 3) & 0x3FFFF;
02020       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
02021       break;
02022 
02023     case BFD_RELOC_D30V_21_PCREL:
02024       if (fixP->fx_where & 0x7)
02025        {
02026          if (fixP->fx_done)
02027            value += 4;
02028          else
02029            fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
02030        }
02031       check_size (value, 21, fixP->fx_file, fixP->fx_line);
02032       insn |= (value >> 3) & 0x3FFFF;
02033       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
02034       break;
02035 
02036     case BFD_RELOC_D30V_32:
02037       insn2 = bfd_getb32 ((unsigned char *) where + 4);
02038       insn |= (value >> 26) & 0x3F;              /* Top 6 bits.  */
02039       insn2 |= ((value & 0x03FC0000) << 2);      /* Next 8 bits.  */
02040       insn2 |= value & 0x0003FFFF;        /* Bottom 18 bits.  */
02041       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
02042       bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
02043       break;
02044 
02045     case BFD_RELOC_D30V_32_PCREL:
02046       insn2 = bfd_getb32 ((unsigned char *) where + 4);
02047       insn |= (value >> 26) & 0x3F;              /* Top 6 bits.  */
02048       insn2 |= ((value & 0x03FC0000) << 2);      /* Next 8 bits.  */
02049       insn2 |= value & 0x0003FFFF;        /* Bottom 18 bits.  */
02050       bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
02051       bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
02052       break;
02053 
02054     case BFD_RELOC_32:
02055       bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
02056       break;
02057 
02058     default:
02059       as_bad (_("line %d: unknown relocation type: 0x%x"),
02060              fixP->fx_line, fixP->fx_r_type);
02061     }
02062 }
02063 
02064 /* Handle the .align pseudo-op.  This aligns to a power of two.  We
02065    hook here to latch the current alignment.  */
02066 
02067 static void
02068 s_d30v_align (int ignore ATTRIBUTE_UNUSED)
02069 {
02070   int align;
02071   char fill, *pfill = NULL;
02072   long max_alignment = 15;
02073 
02074   align = get_absolute_expression ();
02075   if (align > max_alignment)
02076     {
02077       align = max_alignment;
02078       as_warn (_("Alignment too large: %d assumed"), align);
02079     }
02080   else if (align < 0)
02081     {
02082       as_warn (_("Alignment negative: 0 assumed"));
02083       align = 0;
02084     }
02085 
02086   if (*input_line_pointer == ',')
02087     {
02088       input_line_pointer++;
02089       fill = get_absolute_expression ();
02090       pfill = &fill;
02091     }
02092 
02093   d30v_last_label = NULL;
02094   d30v_align (align, pfill, NULL);
02095 
02096   demand_empty_rest_of_line ();
02097 }
02098 
02099 /* Handle the .text pseudo-op.  This is like the usual one, but it
02100    clears the saved last label and resets known alignment.  */
02101 
02102 static void
02103 s_d30v_text (int i)
02104 
02105 {
02106   s_text (i);
02107   d30v_last_label = NULL;
02108   d30v_current_align = 0;
02109   d30v_current_align_seg = now_seg;
02110 }
02111 
02112 /* Handle the .data pseudo-op.  This is like the usual one, but it
02113    clears the saved last label and resets known alignment.  */
02114 
02115 static void
02116 s_d30v_data (int i)
02117 {
02118   s_data (i);
02119   d30v_last_label = NULL;
02120   d30v_current_align = 0;
02121   d30v_current_align_seg = now_seg;
02122 }
02123 
02124 /* Handle the .section pseudo-op.  This is like the usual one, but it
02125    clears the saved last label and resets known alignment.  */
02126 
02127 static void
02128 s_d30v_section (int ignore)
02129 {
02130   obj_elf_section (ignore);
02131   d30v_last_label = NULL;
02132   d30v_current_align = 0;
02133   d30v_current_align_seg = now_seg;
02134 }
02135 
02136 /* The target specific pseudo-ops which we support.  */
02137 const pseudo_typeS md_pseudo_table[] =
02138 {
02139   { "word", cons, 4 },
02140   { "hword", cons, 2 },
02141   { "align", s_d30v_align, 0 },
02142   { "text", s_d30v_text, 0 },
02143   { "data", s_d30v_data, 0 },
02144   { "section", s_d30v_section, 0 },
02145   { "section.s", s_d30v_section, 0 },
02146   { "sect", s_d30v_section, 0 },
02147   { "sect.s", s_d30v_section, 0 },
02148   { NULL, NULL, 0 }
02149 };
02150