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cell-binutils  2.17cvs20070401
tc-d10v.c
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00001 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
00002    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007
00003    Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with GAS; see the file COPYING.  If not, write to
00019    the Free Software Foundation, 51 Franklin Street - Fifth Floor,
00020    Boston, MA 02110-1301, USA.  */
00021 
00022 #include "as.h"
00023 #include "safe-ctype.h"
00024 #include "subsegs.h"
00025 #include "opcode/d10v.h"
00026 #include "elf/ppc.h"
00027 
00028 const char comment_chars[]        = ";";
00029 const char line_comment_chars[]   = "#";
00030 const char line_separator_chars[] = "";
00031 const char *md_shortopts          = "O";
00032 const char EXP_CHARS[]            = "eE";
00033 const char FLT_CHARS[]            = "dD";
00034 
00035 int Optimizing = 0;
00036 
00037 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
00038                     && (X)->X_op_symbol != NULL \
00039                     && symbol_constant_p ((X)->X_op_symbol) \
00040                     && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
00041 #define AT_WORD_RIGHT_SHIFT 2
00042 
00043 /* Fixups.  */
00044 #define MAX_INSN_FIXUPS  5
00045 
00046 struct d10v_fixup
00047 {
00048   expressionS exp;
00049   int operand;
00050   int pcrel;
00051   int size;
00052   bfd_reloc_code_real_type reloc;
00053 };
00054 
00055 typedef struct _fixups
00056 {
00057   int fc;
00058   struct d10v_fixup fix[MAX_INSN_FIXUPS];
00059   struct _fixups *next;
00060 } Fixups;
00061 
00062 static Fixups FixUps[2];
00063 static Fixups *fixups;
00064 
00065 static int do_not_ignore_hash = 0;
00066 
00067 typedef int packing_type;
00068 #define PACK_UNSPEC  (0)    /* Packing order not specified.  */
00069 #define PACK_PARALLEL       (1)    /* "||"  */
00070 #define PACK_LEFT_RIGHT (2) /* "->"  */
00071 #define PACK_RIGHT_LEFT (3) /* "<-"  */
00072 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup.  */
00073 
00074 /* TRUE if instruction swapping warnings should be inhibited.
00075    --nowarnswap.  */
00076 static bfd_boolean flag_warn_suppress_instructionswap;
00077 
00078 /* TRUE if instruction packing should be performed when --gstabs is specified.
00079    --gstabs-packing, --no-gstabs-packing.  */
00080 static bfd_boolean flag_allow_gstabs_packing = 1;
00081 
00082 /* Local functions.  */
00083 
00084 enum options
00085 {
00086   OPTION_NOWARNSWAP = OPTION_MD_BASE,
00087   OPTION_GSTABSPACKING,
00088   OPTION_NOGSTABSPACKING
00089 };
00090 
00091 struct option md_longopts[] =
00092 {
00093   {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
00094   {"gstabspacking",  no_argument, NULL, OPTION_GSTABSPACKING},
00095   {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
00096   {"nogstabspacking",   no_argument, NULL, OPTION_NOGSTABSPACKING},
00097   {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
00098   {NULL, no_argument, NULL, 0}
00099 };
00100 
00101 size_t md_longopts_size = sizeof (md_longopts);
00102 
00103 /* Opcode hash table.  */
00104 static struct hash_control *d10v_hash;
00105 
00106 /* Do a binary search of the d10v_predefined_registers array to see if
00107    NAME is a valid regiter name.  Return the register number from the
00108    array on success, or -1 on failure.  */
00109 
00110 static int
00111 reg_name_search (char *name)
00112 {
00113   int middle, low, high;
00114   int cmp;
00115 
00116   low = 0;
00117   high = d10v_reg_name_cnt () - 1;
00118 
00119   do
00120     {
00121       middle = (low + high) / 2;
00122       cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
00123       if (cmp < 0)
00124        high = middle - 1;
00125       else if (cmp > 0)
00126        low = middle + 1;
00127       else
00128        return d10v_predefined_registers[middle].value;
00129     }
00130   while (low <= high);
00131   return -1;
00132 }
00133 
00134 /* Check the string at input_line_pointer
00135    to see if it is a valid register name.  */
00136 
00137 static int
00138 register_name (expressionS *expressionP)
00139 {
00140   int reg_number;
00141   char c, *p = input_line_pointer;
00142 
00143   while (*p
00144         && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
00145     p++;
00146 
00147   c = *p;
00148   if (c)
00149     *p++ = 0;
00150 
00151   /* Look to see if it's in the register table.  */
00152   reg_number = reg_name_search (input_line_pointer);
00153   if (reg_number >= 0)
00154     {
00155       expressionP->X_op = O_register;
00156       /* Temporarily store a pointer to the string here.  */
00157       expressionP->X_op_symbol = (symbolS *) input_line_pointer;
00158       expressionP->X_add_number = reg_number;
00159       input_line_pointer = p;
00160       return 1;
00161     }
00162   if (c)
00163     *(p - 1) = c;
00164   return 0;
00165 }
00166 
00167 static int
00168 check_range (unsigned long num, int bits, int flags)
00169 {
00170   long min, max;
00171   int retval = 0;
00172 
00173   /* Don't bother checking 16-bit values.  */
00174   if (bits == 16)
00175     return 0;
00176 
00177   if (flags & OPERAND_SHIFT)
00178     {
00179       /* All special shift operands are unsigned and <= 16.
00180         We allow 0 for now.  */
00181       if (num > 16)
00182        return 1;
00183       else
00184        return 0;
00185     }
00186 
00187   if (flags & OPERAND_SIGNED)
00188     {
00189       /* Signed 3-bit integers are restricted to the (-2, 3) range.  */
00190       if (flags & RESTRICTED_NUM3)
00191        {
00192          if ((long) num < -2 || (long) num > 3)
00193            retval = 1;
00194        }
00195       else
00196        {
00197          max = (1 << (bits - 1)) - 1;
00198          min = - (1 << (bits - 1));
00199          if (((long) num > max) || ((long) num < min))
00200            retval = 1;
00201        }
00202     }
00203   else
00204     {
00205       max = (1 << bits) - 1;
00206       min = 0;
00207       if (((long) num > max) || ((long) num < min))
00208        retval = 1;
00209     }
00210   return retval;
00211 }
00212 
00213 void
00214 md_show_usage (FILE *stream)
00215 {
00216   fprintf (stream, _("D10V options:\n\
00217 -O                      Optimize.  Will do some operations in parallel.\n\
00218 --gstabs-packing        Pack adjacent short instructions together even\n\
00219                         when --gstabs is specified.  On by default.\n\
00220 --no-gstabs-packing     If --gstabs is specified, do not pack adjacent\n\
00221                         instructions together.\n"));
00222 }
00223 
00224 int
00225 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
00226 {
00227   switch (c)
00228     {
00229     case 'O':
00230       /* Optimize. Will attempt to parallelize operations.  */
00231       Optimizing = 1;
00232       break;
00233     case OPTION_NOWARNSWAP:
00234       flag_warn_suppress_instructionswap = 1;
00235       break;
00236     case OPTION_GSTABSPACKING:
00237       flag_allow_gstabs_packing = 1;
00238       break;
00239     case OPTION_NOGSTABSPACKING:
00240       flag_allow_gstabs_packing = 0;
00241       break;
00242     default:
00243       return 0;
00244     }
00245   return 1;
00246 }
00247 
00248 symbolS *
00249 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
00250 {
00251   return 0;
00252 }
00253 
00254 /* Turn a string in input_line_pointer into a floating point constant
00255    of type TYPE, and store the appropriate bytes in *LITP.  The number
00256    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
00257    returned, or NULL on OK.  */
00258 
00259 char *
00260 md_atof (int type, char *litP, int *sizeP)
00261 {
00262   int prec;
00263   LITTLENUM_TYPE words[4];
00264   char *t;
00265   int i;
00266 
00267   switch (type)
00268     {
00269     case 'f':
00270       prec = 2;
00271       break;
00272     case 'd':
00273       prec = 4;
00274       break;
00275     default:
00276       *sizeP = 0;
00277       return _("bad call to md_atof");
00278     }
00279 
00280   t = atof_ieee (input_line_pointer, type, words);
00281   if (t)
00282     input_line_pointer = t;
00283 
00284   *sizeP = prec * 2;
00285 
00286   for (i = 0; i < prec; i++)
00287     {
00288       md_number_to_chars (litP, (valueT) words[i], 2);
00289       litP += 2;
00290     }
00291   return NULL;
00292 }
00293 
00294 void
00295 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
00296                asection *sec ATTRIBUTE_UNUSED,
00297                fragS *fragP ATTRIBUTE_UNUSED)
00298 {
00299   abort ();
00300 }
00301 
00302 valueT
00303 md_section_align (asection *seg, valueT addr)
00304 {
00305   int align = bfd_get_section_alignment (stdoutput, seg);
00306   return ((addr + (1 << align) - 1) & (-1 << align));
00307 }
00308 
00309 void
00310 md_begin (void)
00311 {
00312   char *prev_name = "";
00313   struct d10v_opcode *opcode;
00314   d10v_hash = hash_new ();
00315 
00316   /* Insert unique names into hash table.  The D10v instruction set
00317      has many identical opcode names that have different opcodes based
00318      on the operands.  This hash table then provides a quick index to
00319      the first opcode with a particular name in the opcode table.  */
00320 
00321   for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
00322     {
00323       if (strcmp (prev_name, opcode->name))
00324        {
00325          prev_name = (char *) opcode->name;
00326          hash_insert (d10v_hash, opcode->name, (char *) opcode);
00327        }
00328     }
00329 
00330   fixups = &FixUps[0];
00331   FixUps[0].next = &FixUps[1];
00332   FixUps[1].next = &FixUps[0];
00333 }
00334 
00335 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
00336    from an expression.  */
00337 
00338 static int
00339 postfix (char *p)
00340 {
00341   while (*p != '-' && *p != '+')
00342     {
00343       if (*p == 0 || *p == '\n' || *p == '\r')
00344        break;
00345       p++;
00346     }
00347 
00348   if (*p == '-')
00349     {
00350       *p = ' ';
00351       return -1;
00352     }
00353   if (*p == '+')
00354     {
00355       *p = ' ';
00356       return 1;
00357     }
00358 
00359   return 0;
00360 }
00361 
00362 static bfd_reloc_code_real_type
00363 get_reloc (struct d10v_operand *op)
00364 {
00365   int bits = op->bits;
00366 
00367   if (bits <= 4)
00368     return 0;
00369 
00370   if (op->flags & OPERAND_ADDR)
00371     {
00372       if (bits == 8)
00373        return BFD_RELOC_D10V_10_PCREL_R;
00374       else
00375        return BFD_RELOC_D10V_18_PCREL;
00376     }
00377 
00378   return BFD_RELOC_16;
00379 }
00380 
00381 /* Parse a string of operands.  Return an array of expressions.  */
00382 
00383 static int
00384 get_operands (expressionS exp[])
00385 {
00386   char *p = input_line_pointer;
00387   int numops = 0;
00388   int post = 0;
00389   int uses_at = 0;
00390 
00391   while (*p)
00392     {
00393       while (*p == ' ' || *p == '\t' || *p == ',')
00394        p++;
00395       if (*p == 0 || *p == '\n' || *p == '\r')
00396        break;
00397 
00398       if (*p == '@')
00399        {
00400          uses_at = 1;
00401 
00402          p++;
00403          exp[numops].X_op = O_absent;
00404          if (*p == '(')
00405            {
00406              p++;
00407              exp[numops].X_add_number = OPERAND_ATPAR;
00408            }
00409          else if (*p == '-')
00410            {
00411              p++;
00412              exp[numops].X_add_number = OPERAND_ATMINUS;
00413            }
00414          else
00415            {
00416              exp[numops].X_add_number = OPERAND_ATSIGN;
00417              if (*p == '+')
00418               {
00419                 numops++;
00420                 exp[numops].X_op = O_absent;
00421                 exp[numops].X_add_number = OPERAND_PLUS;
00422                 p++;
00423               }
00424              post = postfix (p);
00425            }
00426          numops++;
00427          continue;
00428        }
00429 
00430       if (*p == ')')
00431        {
00432          /* Just skip the trailing paren.  */
00433          p++;
00434          continue;
00435        }
00436 
00437       input_line_pointer = p;
00438 
00439       /* Check to see if it might be a register name.  */
00440       if (!register_name (&exp[numops]))
00441        {
00442          /* Parse as an expression.  */
00443          if (uses_at)
00444            {
00445              /* Any expression that involves the indirect addressing
00446                cannot also involve immediate addressing.  Therefore
00447                the use of the hash character is illegal.  */
00448              int save = do_not_ignore_hash;
00449              do_not_ignore_hash = 1;
00450 
00451              expression (&exp[numops]);
00452 
00453              do_not_ignore_hash = save;
00454            }
00455          else
00456            expression (&exp[numops]);
00457        }
00458 
00459       if (strncasecmp (input_line_pointer, "@word", 5) == 0)
00460        {
00461          input_line_pointer += 5;
00462          if (exp[numops].X_op == O_register)
00463            {
00464              /* If it looked like a register name but was followed by
00465                  "@word" then it was really a symbol, so change it to
00466                  one.  */
00467              exp[numops].X_op = O_symbol;
00468              exp[numops].X_add_symbol =
00469               symbol_find_or_make ((char *) exp[numops].X_op_symbol);
00470            }
00471 
00472          /* Check for identifier@word+constant.  */
00473          if (*input_line_pointer == '-' || *input_line_pointer == '+')
00474            {
00475              expressionS new_exp;
00476              expression (&new_exp);
00477              exp[numops].X_add_number = new_exp.X_add_number;
00478            }
00479 
00480          /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT.  */
00481          {
00482            expressionS new_exp;
00483            memset (&new_exp, 0, sizeof new_exp);
00484            new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
00485            new_exp.X_op = O_constant;
00486            new_exp.X_unsigned = 1;
00487            exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
00488            exp[numops].X_op = O_right_shift;
00489          }
00490 
00491          know (AT_WORD_P (&exp[numops]));
00492        }
00493 
00494       if (exp[numops].X_op == O_illegal)
00495        as_bad (_("illegal operand"));
00496       else if (exp[numops].X_op == O_absent)
00497        as_bad (_("missing operand"));
00498 
00499       numops++;
00500       p = input_line_pointer;
00501     }
00502 
00503   switch (post)
00504     {
00505     case -1:  /* Postdecrement mode.  */
00506       exp[numops].X_op = O_absent;
00507       exp[numops++].X_add_number = OPERAND_MINUS;
00508       break;
00509     case 1:   /* Postincrement mode.  */
00510       exp[numops].X_op = O_absent;
00511       exp[numops++].X_add_number = OPERAND_PLUS;
00512       break;
00513     }
00514 
00515   exp[numops].X_op = 0;
00516   return numops;
00517 }
00518 
00519 static unsigned long
00520 d10v_insert_operand (unsigned long insn,
00521                    int op_type,
00522                    offsetT value,
00523                    int left,
00524                    fixS *fix)
00525 {
00526   int shift, bits;
00527 
00528   shift = d10v_operands[op_type].shift;
00529   if (left)
00530     shift += 15;
00531 
00532   bits = d10v_operands[op_type].bits;
00533 
00534   /* Truncate to the proper number of bits.  */
00535   if (check_range (value, bits, d10v_operands[op_type].flags))
00536     as_bad_where (fix->fx_file, fix->fx_line,
00537                 _("operand out of range: %ld"), (long) value);
00538 
00539   value &= 0x7FFFFFFF >> (31 - bits);
00540   insn |= (value << shift);
00541 
00542   return insn;
00543 }
00544 
00545 /* Take a pointer to the opcode entry in the opcode table and the
00546    array of operand expressions.  Return the instruction.  */
00547 
00548 static unsigned long
00549 build_insn (struct d10v_opcode *opcode,
00550            expressionS *opers,
00551            unsigned long insn)
00552 {
00553   int i, bits, shift, flags, format;
00554   unsigned long number;
00555 
00556   /* The insn argument is only used for the DIVS kludge.  */
00557   if (insn)
00558     format = LONG_R;
00559   else
00560     {
00561       insn = opcode->opcode;
00562       format = opcode->format;
00563     }
00564 
00565   for (i = 0; opcode->operands[i]; i++)
00566     {
00567       flags = d10v_operands[opcode->operands[i]].flags;
00568       bits = d10v_operands[opcode->operands[i]].bits;
00569       shift = d10v_operands[opcode->operands[i]].shift;
00570       number = opers[i].X_add_number;
00571 
00572       if (flags & OPERAND_REG)
00573        {
00574          number &= REGISTER_MASK;
00575          if (format == LONG_L)
00576            shift += 15;
00577        }
00578 
00579       if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
00580        {
00581          /* Now create a fixup.  */
00582 
00583          if (fixups->fc >= MAX_INSN_FIXUPS)
00584            as_fatal (_("too many fixups"));
00585 
00586          if (AT_WORD_P (&opers[i]))
00587            {
00588              /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD).  */
00589              fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
00590              opers[i].X_op = O_symbol;
00591              opers[i].X_op_symbol = NULL; /* Should free it.  */
00592              /* number is left shifted by AT_WORD_RIGHT_SHIFT so
00593                  that, it is aligned with the symbol's value.  Later,
00594                  BFD_RELOC_D10V_18 will right shift (symbol_value +
00595                  X_add_number).  */
00596              number <<= AT_WORD_RIGHT_SHIFT;
00597              opers[i].X_add_number = number;
00598            }
00599          else
00600            {
00601              fixups->fix[fixups->fc].reloc =
00602               get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
00603 
00604              /* Check that an immediate was passed to ops that expect one.  */
00605              if ((flags & OPERAND_NUM)
00606                 && (fixups->fix[fixups->fc].reloc == 0))
00607               as_bad (_("operand is not an immediate"));
00608            }
00609 
00610          if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
00611              fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
00612            fixups->fix[fixups->fc].size = 2;
00613          else
00614            fixups->fix[fixups->fc].size = 4;
00615 
00616          fixups->fix[fixups->fc].exp = opers[i];
00617          fixups->fix[fixups->fc].operand = opcode->operands[i];
00618          fixups->fix[fixups->fc].pcrel =
00619            (flags & OPERAND_ADDR) ? TRUE : FALSE;
00620          (fixups->fc)++;
00621        }
00622 
00623       /* Truncate to the proper number of bits.  */
00624       if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
00625        as_bad (_("operand out of range: %lu"), number);
00626       number &= 0x7FFFFFFF >> (31 - bits);
00627       insn = insn | (number << shift);
00628     }
00629 
00630   /* kludge: for DIVS, we need to put the operands in twice on the second
00631      pass, format is changed to LONG_R to force the second set of operands
00632      to not be shifted over 15.  */
00633   if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
00634     insn = build_insn (opcode, opers, insn);
00635 
00636   return insn;
00637 }
00638 
00639 /* Write out a long form instruction.  */
00640 
00641 static void
00642 write_long (unsigned long insn, Fixups *fx)
00643 {
00644   int i, where;
00645   char *f = frag_more (4);
00646 
00647   insn |= FM11;
00648   number_to_chars_bigendian (f, insn, 4);
00649 
00650   for (i = 0; i < fx->fc; i++)
00651     {
00652       if (fx->fix[i].reloc)
00653        {
00654          where = f - frag_now->fr_literal;
00655          if (fx->fix[i].size == 2)
00656            where += 2;
00657 
00658          if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
00659            fx->fix[i].operand |= 4096;
00660 
00661          fix_new_exp (frag_now,
00662                      where,
00663                      fx->fix[i].size,
00664                      &(fx->fix[i].exp),
00665                      fx->fix[i].pcrel,
00666                      fx->fix[i].operand|2048);
00667        }
00668     }
00669   fx->fc = 0;
00670 }
00671 
00672 /* Write out a short form instruction by itself.  */
00673 
00674 static void
00675 write_1_short (struct d10v_opcode *opcode,
00676               unsigned long insn,
00677               Fixups *fx)
00678 {
00679   char *f = frag_more (4);
00680   int i, where;
00681 
00682   if (opcode->exec_type & PARONLY)
00683     as_fatal (_("Instruction must be executed in parallel with another instruction."));
00684 
00685   /* The other container needs to be NOP.
00686      According to 4.3.1: for FM=00, sub-instructions performed only by IU
00687      cannot be encoded in L-container.  */
00688   if (opcode->unit == IU)
00689     insn |= FM00 | (NOP << 15);           /* Right container.  */
00690   else
00691     insn = FM00 | (insn << 15) | NOP;     /* Left container.  */
00692 
00693   number_to_chars_bigendian (f, insn, 4);
00694   for (i = 0; i < fx->fc; i++)
00695     {
00696       if (fx->fix[i].reloc)
00697        {
00698          where = f - frag_now->fr_literal;
00699          if (fx->fix[i].size == 2)
00700            where += 2;
00701 
00702          if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
00703            fx->fix[i].operand |= 4096;
00704 
00705          /* If it's an R reloc, we may have to switch it to L.  */
00706          if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
00707              && (opcode->unit != IU))
00708            fx->fix[i].operand |= 1024;
00709 
00710          fix_new_exp (frag_now,
00711                      where,
00712                      fx->fix[i].size,
00713                      &(fx->fix[i].exp),
00714                      fx->fix[i].pcrel,
00715                      fx->fix[i].operand|2048);
00716        }
00717     }
00718   fx->fc = 0;
00719 }
00720 
00721 /* Determine if there are any resource conflicts among two manually
00722    parallelized instructions.  Some of this was lifted from parallel_ok.  */
00723 
00724 static void
00725 check_resource_conflict (struct d10v_opcode *op1,
00726                       unsigned long insn1,
00727                       struct d10v_opcode *op2,
00728                       unsigned long insn2)
00729 {
00730   int i, j, flags, mask, shift, regno;
00731   unsigned long ins, mod[2];
00732   struct d10v_opcode *op;
00733 
00734   if ((op1->exec_type & SEQ)
00735       || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
00736     {
00737       as_warn (_("packing conflict: %s must dispatch sequentially"),
00738              op1->name);
00739       return;
00740     }
00741 
00742   if ((op2->exec_type & SEQ)
00743       || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
00744     {
00745       as_warn (_("packing conflict: %s must dispatch sequentially"),
00746              op2->name);
00747       return;
00748     }
00749 
00750    /* See if both instructions write to the same resource.
00751 
00752       The idea here is to create two sets of bitmasks (mod and used) which
00753       indicate which registers are modified or used by each instruction.
00754       The operation can only be done in parallel if neither instruction
00755       modifies the same register. Accesses to control registers and memory
00756       are treated as accesses to a single register. So if both instructions
00757       write memory or if the first instruction writes memory and the second
00758       reads, then they cannot be done in parallel. We treat reads to the PSW
00759       (which includes C, F0, and F1) in isolation. So simultaneously writing
00760       C and F0 in two different sub-instructions is permitted.  */
00761 
00762   /* The bitmasks (mod and used) look like this (bit 31 = MSB).
00763      r0-r15     0-15
00764      a0-a1      16-17
00765      cr (not psw) 18
00766      psw(other)   19
00767      mem        20
00768      psw(C flag)  21
00769      psw(F0 flag) 22  */
00770 
00771   for (j = 0; j < 2; j++)
00772     {
00773       if (j == 0)
00774        {
00775          op = op1;
00776          ins = insn1;
00777        }
00778       else
00779        {
00780          op = op2;
00781          ins = insn2;
00782        }
00783       mod[j] = 0;
00784       if (op->exec_type & BRANCH_LINK)
00785        mod[j] |= 1 << 13;
00786 
00787       for (i = 0; op->operands[i]; i++)
00788        {
00789          flags = d10v_operands[op->operands[i]].flags;
00790          shift = d10v_operands[op->operands[i]].shift;
00791          mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
00792          if (flags & OPERAND_REG)
00793            {
00794              regno = (ins >> shift) & mask;
00795              if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
00796               regno += 16;
00797              else if (flags & OPERAND_CONTROL)   /* mvtc or mvfc */
00798               {
00799                 if (regno == 0)
00800                   regno = 19;
00801                 else
00802                   regno = 18;
00803               }
00804              else if (flags & OPERAND_FFLAG)
00805               regno = 22;
00806              else if (flags & OPERAND_CFLAG)
00807               regno = 21;
00808 
00809              if (flags & OPERAND_DEST
00810                 /* Auto inc/dec also modifies the register.  */
00811                 || (op->operands[i + 1] != 0
00812                     && (d10v_operands[op->operands[i + 1]].flags
00813                        & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
00814               {
00815                 mod[j] |= 1 << regno;
00816                 if (flags & OPERAND_EVEN)
00817                   mod[j] |= 1 << (regno + 1);
00818               }
00819            }
00820          else if (flags & OPERAND_ATMINUS)
00821            {
00822              /* SP implicitly used/modified.  */
00823              mod[j] |= 1 << 15;
00824            }
00825        }
00826 
00827       if (op->exec_type & WMEM)
00828        mod[j] |= 1 << 20;
00829       else if (op->exec_type & WF0)
00830        mod[j] |= 1 << 22;
00831       else if (op->exec_type & WCAR)
00832        mod[j] |= 1 << 21;
00833     }
00834 
00835   if ((mod[0] & mod[1]) == 0)
00836     return;
00837   else
00838     {
00839       unsigned long x;
00840       x = mod[0] & mod[1];
00841 
00842       for (j = 0; j <= 15; j++)
00843        if (x & (1 << j))
00844          as_warn (_("resource conflict (R%d)"), j);
00845       for (j = 16; j <= 17; j++)
00846        if (x & (1 << j))
00847          as_warn (_("resource conflict (A%d)"), j - 16);
00848       if (x & (1 << 19))
00849        as_warn (_("resource conflict (PSW)"));
00850       if (x & (1 << 21))
00851        as_warn (_("resource conflict (C flag)"));
00852       if (x & (1 << 22))
00853        as_warn (_("resource conflict (F flag)"));
00854     }
00855 }
00856 
00857 /* Check 2 instructions and determine if they can be safely
00858    executed in parallel.  Return 1 if they can be.  */
00859 
00860 static int
00861 parallel_ok (struct d10v_opcode *op1,
00862             unsigned long insn1,
00863             struct d10v_opcode *op2,
00864             unsigned long insn2,
00865             packing_type exec_type)
00866 {
00867   int i, j, flags, mask, shift, regno;
00868   unsigned long ins, mod[2], used[2];
00869   struct d10v_opcode *op;
00870 
00871   if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
00872       || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
00873       || (op1->unit == BOTH) || (op2->unit == BOTH)
00874       || (op1->unit == IU && op2->unit == IU)
00875       || (op1->unit == MU && op2->unit == MU))
00876     return 0;
00877 
00878   /* If this is auto parallelization, and the first instruction is a
00879      branch or should not be packed, then don't parallelize.  */
00880   if (exec_type == PACK_UNSPEC
00881       && (op1->exec_type & (ALONE | BRANCH)))
00882     return 0;
00883 
00884   /* The idea here is to create two sets of bitmasks (mod and used)
00885      which indicate which registers are modified or used by each
00886      instruction.  The operation can only be done in parallel if
00887      instruction 1 and instruction 2 modify different registers, and
00888      the first instruction does not modify registers that the second
00889      is using (The second instruction can modify registers that the
00890      first is using as they are only written back after the first
00891      instruction has completed).  Accesses to control registers, PSW,
00892      and memory are treated as accesses to a single register.  So if
00893      both instructions write memory or if the first instruction writes
00894      memory and the second reads, then they cannot be done in
00895      parallel.  Likewise, if the first instruction mucks with the psw
00896      and the second reads the PSW (which includes C, F0, and F1), then
00897      they cannot operate safely in parallel.  */
00898 
00899   /* The bitmasks (mod and used) look like this (bit 31 = MSB).
00900      r0-r15     0-15
00901      a0-a1      16-17
00902      cr (not psw) 18
00903      psw        19
00904      mem        20  */
00905 
00906   for (j = 0; j < 2; j++)
00907     {
00908       if (j == 0)
00909        {
00910          op = op1;
00911          ins = insn1;
00912        }
00913       else
00914        {
00915          op = op2;
00916          ins = insn2;
00917        }
00918       mod[j] = used[j] = 0;
00919       if (op->exec_type & BRANCH_LINK)
00920        mod[j] |= 1 << 13;
00921 
00922       for (i = 0; op->operands[i]; i++)
00923        {
00924          flags = d10v_operands[op->operands[i]].flags;
00925          shift = d10v_operands[op->operands[i]].shift;
00926          mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
00927          if (flags & OPERAND_REG)
00928            {
00929              regno = (ins >> shift) & mask;
00930              if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
00931               regno += 16;
00932              else if (flags & OPERAND_CONTROL)   /* mvtc or mvfc.  */
00933               {
00934                 if (regno == 0)
00935                   regno = 19;
00936                 else
00937                   regno = 18;
00938               }
00939              else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
00940               regno = 19;
00941 
00942              if (flags & OPERAND_DEST)
00943               {
00944                 mod[j] |= 1 << regno;
00945                 if (flags & OPERAND_EVEN)
00946                   mod[j] |= 1 << (regno + 1);
00947               }
00948              else
00949               {
00950                 used[j] |= 1 << regno;
00951                 if (flags & OPERAND_EVEN)
00952                   used[j] |= 1 << (regno + 1);
00953 
00954                 /* Auto inc/dec also modifies the register.  */
00955                 if (op->operands[i + 1] != 0
00956                     && (d10v_operands[op->operands[i + 1]].flags
00957                        & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
00958                   mod[j] |= 1 << regno;
00959               }
00960            }
00961          else if (flags & OPERAND_ATMINUS)
00962            {
00963              /* SP implicitly used/modified.  */
00964              mod[j] |= 1 << 15;
00965              used[j] |= 1 << 15;
00966            }
00967        }
00968       if (op->exec_type & RMEM)
00969        used[j] |= 1 << 20;
00970       else if (op->exec_type & WMEM)
00971        mod[j] |= 1 << 20;
00972       else if (op->exec_type & RF0)
00973        used[j] |= 1 << 19;
00974       else if (op->exec_type & WF0)
00975        mod[j] |= 1 << 19;
00976       else if (op->exec_type & WCAR)
00977        mod[j] |= 1 << 19;
00978     }
00979   if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
00980     return 1;
00981   return 0;
00982 }
00983 
00984 /* Expects two short instructions.
00985    If possible, writes out both as a single packed instruction.
00986    Otherwise, writes out the first one, packed with a NOP.
00987    Returns number of instructions not written out.  */
00988 
00989 static int
00990 write_2_short (struct d10v_opcode *opcode1,
00991               unsigned long insn1,
00992               struct d10v_opcode *opcode2,
00993               unsigned long insn2,
00994               packing_type exec_type,
00995               Fixups *fx)
00996 {
00997   unsigned long insn;
00998   char *f;
00999   int i, j, where;
01000 
01001   if ((exec_type != PACK_PARALLEL)
01002       && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
01003     as_fatal (_("Instruction must be executed in parallel"));
01004 
01005   if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
01006     as_fatal (_("Long instructions may not be combined."));
01007 
01008   switch (exec_type)
01009     {
01010     case PACK_UNSPEC:       /* Order not specified.  */
01011       if (opcode1->exec_type & ALONE)
01012        {
01013          /* Case of a short branch on a separate GAS line.  Pack with NOP.  */
01014          write_1_short (opcode1, insn1, fx->next);
01015          return 1;
01016        }
01017       if (Optimizing
01018          && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
01019        {
01020          /* Parallel.  */
01021          if (opcode1->unit == IU)
01022            insn = FM00 | (insn2 << 15) | insn1;
01023          else if (opcode2->unit == MU)
01024            insn = FM00 | (insn2 << 15) | insn1;
01025          else
01026            insn = FM00 | (insn1 << 15) | insn2;
01027        }
01028       else if (opcode1->unit == IU)
01029        /* Reverse sequential with IU opcode1 on right and done first.  */
01030        insn = FM10 | (insn2 << 15) | insn1;
01031       else
01032        /* Sequential with non-IU opcode1 on left and done first.  */
01033        insn = FM01 | (insn1 << 15) | insn2;
01034       break;
01035 
01036     case PACK_PARALLEL:
01037       if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
01038        as_fatal
01039          (_("One of these instructions may not be executed in parallel."));
01040       if (opcode1->unit == IU)
01041        {
01042          if (opcode2->unit == IU)
01043            as_fatal (_("Two IU instructions may not be executed in parallel"));
01044          if (!flag_warn_suppress_instructionswap)
01045            as_warn (_("Swapping instruction order"));
01046          insn = FM00 | (insn2 << 15) | insn1;
01047        }
01048       else if (opcode2->unit == MU)
01049        {
01050          if (opcode1->unit == MU)
01051            as_fatal (_("Two MU instructions may not be executed in parallel"));
01052          if (!flag_warn_suppress_instructionswap)
01053            as_warn (_("Swapping instruction order"));
01054          insn = FM00 | (insn2 << 15) | insn1;
01055        }
01056       else
01057        insn = FM00 | (insn1 << 15) | insn2;
01058       check_resource_conflict (opcode1, insn1, opcode2, insn2);
01059       break;
01060 
01061     case PACK_LEFT_RIGHT:
01062       if (opcode1->unit != IU)
01063        insn = FM01 | (insn1 << 15) | insn2;
01064       else if (opcode2->unit == MU || opcode2->unit == EITHER)
01065        {
01066          if (!flag_warn_suppress_instructionswap)
01067            as_warn (_("Swapping instruction order"));
01068          insn = FM10 | (insn2 << 15) | insn1;
01069        }
01070       else
01071        as_fatal (_("IU instruction may not be in the left container"));
01072       if (opcode1->exec_type & ALONE)
01073        as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
01074       break;
01075 
01076     case PACK_RIGHT_LEFT:
01077       if (opcode2->unit != MU)
01078        insn = FM10 | (insn1 << 15) | insn2;
01079       else if (opcode1->unit == IU || opcode1->unit == EITHER)
01080        {
01081          if (!flag_warn_suppress_instructionswap)
01082            as_warn (_("Swapping instruction order"));
01083          insn = FM01 | (insn2 << 15) | insn1;
01084        }
01085       else
01086        as_fatal (_("MU instruction may not be in the right container"));
01087       if (opcode2->exec_type & ALONE)
01088        as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
01089       break;
01090 
01091     default:
01092       as_fatal (_("unknown execution type passed to write_2_short()"));
01093     }
01094 
01095   f = frag_more (4);
01096   number_to_chars_bigendian (f, insn, 4);
01097 
01098   /* Process fixup chains.  fx refers to insn2 when j == 0, and to
01099      insn1 when j == 1.  Yes, it's reversed.  */
01100 
01101   for (j = 0; j < 2; j++)
01102     {
01103       for (i = 0; i < fx->fc; i++)
01104        {
01105          if (fx->fix[i].reloc)
01106            {
01107              where = f - frag_now->fr_literal;
01108              if (fx->fix[i].size == 2)
01109               where += 2;
01110 
01111              if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
01112                 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
01113                    the instruction in the L container has to be
01114                    adjusted to BDF_RELOC_D10V_10_PCREL_L.  When
01115                    j==0, we're processing insn2's operands, so we
01116                    want to mark the operand if insn2 is *not* in the
01117                    R container.  When j==1, we're processing insn1's
01118                    operands, so we want to mark the operand if insn2
01119                    *is* in the R container.  Note that, if two
01120                    instructions are identical, we're never going to
01121                    swap them, so the test is safe.  */
01122                 && j == ((insn & 0x7fff) == insn2))
01123               fx->fix[i].operand |= 1024;
01124 
01125              if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
01126               fx->fix[i].operand |= 4096;
01127 
01128              fix_new_exp (frag_now,
01129                         where,
01130                         fx->fix[i].size,
01131                         &(fx->fix[i].exp),
01132                         fx->fix[i].pcrel,
01133                         fx->fix[i].operand|2048);
01134            }
01135        }
01136       fx->fc = 0;
01137       fx = fx->next;
01138     }
01139   return 0;
01140 }
01141 
01142 /* This is the main entry point for the machine-dependent assembler.
01143    str points to a machine-dependent instruction.  This function is
01144    supposed to emit the frags/bytes it assembles to.  For the D10V, it
01145    mostly handles the special VLIW parsing and packing and leaves the
01146    difficult stuff to do_assemble().  */
01147 
01148 static unsigned long prev_insn;
01149 static struct d10v_opcode *prev_opcode = 0;
01150 static subsegT prev_subseg;
01151 static segT prev_seg = 0;;
01152 
01153 /* Find the symbol which has the same name as the register in exp.  */
01154 
01155 static symbolS *
01156 find_symbol_matching_register (expressionS *exp)
01157 {
01158   int i;
01159 
01160   if (exp->X_op != O_register)
01161     return NULL;
01162 
01163   /* Find the name of the register.  */
01164   for (i = d10v_reg_name_cnt (); i--;)
01165     if (d10v_predefined_registers[i].value == exp->X_add_number)
01166       break;
01167 
01168   if (i < 0)
01169     abort ();
01170 
01171   /* Now see if a symbol has been defined with the same name.  */
01172   return symbol_find (d10v_predefined_registers[i].name);
01173 }
01174 
01175 /* Get a pointer to an entry in the opcode table.
01176    The function must look at all opcodes with the same name and use
01177    the operands to choose the correct opcode.  */
01178 
01179 static struct d10v_opcode *
01180 find_opcode (struct d10v_opcode *opcode, expressionS myops[])
01181 {
01182   int i, match;
01183   struct d10v_opcode *next_opcode;
01184 
01185   /* Get all the operands and save them as expressions.  */
01186   get_operands (myops);
01187 
01188   /* Now see if the operand is a fake.  If so, find the correct size
01189      instruction, if possible.  */
01190   if (opcode->format == OPCODE_FAKE)
01191     {
01192       int opnum = opcode->operands[0];
01193       int flags;
01194 
01195       if (myops[opnum].X_op == O_register)
01196        {
01197          myops[opnum].X_op = O_symbol;
01198          myops[opnum].X_add_symbol =
01199            symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
01200          myops[opnum].X_add_number = 0;
01201          myops[opnum].X_op_symbol = NULL;
01202        }
01203 
01204       next_opcode = opcode + 1;
01205 
01206       /* If the first operand is supposed to be a register, make sure
01207         we got a valid one.  */
01208       flags = d10v_operands[next_opcode->operands[0]].flags;
01209       if (flags & OPERAND_REG)
01210        {
01211          int X_op = myops[0].X_op;
01212          int num = myops[0].X_add_number;
01213 
01214          if (X_op != O_register
01215              || (num & ~flags
01216                 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
01217                    | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))
01218              || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
01219            {
01220              as_bad (_("bad opcode or operands"));
01221              return 0;
01222            }
01223        }
01224 
01225       if (myops[opnum].X_op == O_constant
01226          || (myops[opnum].X_op == O_symbol
01227              && S_IS_DEFINED (myops[opnum].X_add_symbol)
01228              && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
01229        {
01230          for (i = 0; opcode->operands[i + 1]; i++)
01231            {
01232              int bits = d10v_operands[next_opcode->operands[opnum]].bits;
01233              int flags = d10v_operands[next_opcode->operands[opnum]].flags;
01234              if (flags & OPERAND_ADDR)
01235               bits += 2;
01236 
01237              if (myops[opnum].X_op == O_constant)
01238               {
01239                 if (!check_range (myops[opnum].X_add_number, bits, flags))
01240                   break;
01241               }
01242              else
01243               {
01244                 fragS *sym_frag;
01245                 fragS *f;
01246                 unsigned long current_position;
01247                 unsigned long symbol_position;
01248                 unsigned long value;
01249                 bfd_boolean found_symbol;
01250 
01251                 /* Calculate the address of the current instruction
01252                    and the address of the symbol.  Do this by summing
01253                    the offsets of previous frags until we reach the
01254                    frag containing the symbol, and the current frag.  */
01255                 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
01256                 found_symbol = FALSE;
01257 
01258                 current_position =
01259                   obstack_next_free (&frchain_now->frch_obstack)
01260                   - frag_now->fr_literal;
01261                 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
01262 
01263                 for (f = frchain_now->frch_root; f; f = f->fr_next)
01264                   {
01265                     current_position += f->fr_fix + f->fr_offset;
01266 
01267                     if (f == sym_frag)
01268                      found_symbol = TRUE;
01269 
01270                     if (! found_symbol)
01271                      symbol_position += f->fr_fix + f->fr_offset;
01272                   }
01273 
01274                 value = symbol_position;
01275 
01276                 if (flags & OPERAND_ADDR)
01277                   value -= current_position;
01278 
01279                 if (AT_WORD_P (&myops[opnum]))
01280                   {
01281                     if (bits > 4)
01282                      {
01283                        bits += 2;
01284                        if (!check_range (value, bits, flags))
01285                          break;
01286                      }
01287                   }
01288                 else if (!check_range (value, bits, flags))
01289                   break;
01290               }
01291              next_opcode++;
01292            }
01293 
01294          if (opcode->operands [i + 1] == 0)
01295            as_fatal (_("value out of range"));
01296          else
01297            opcode = next_opcode;
01298        }
01299       else
01300        /* Not a constant, so use a long instruction.  */
01301        opcode += 2;
01302     }
01303 
01304   match = 0;
01305 
01306   /* Now search the opcode table table for one with operands
01307      that matches what we've got.  */
01308   while (!match)
01309     {
01310       match = 1;
01311       for (i = 0; opcode->operands[i]; i++)
01312        {
01313          int flags = d10v_operands[opcode->operands[i]].flags;
01314          int X_op = myops[i].X_op;
01315          int num = myops[i].X_add_number;
01316 
01317          if (X_op == 0)
01318            {
01319              match = 0;
01320              break;
01321            }
01322 
01323          if (flags & OPERAND_REG)
01324            {
01325              if ((X_op != O_register)
01326                 || (num & ~flags
01327                     & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
01328                       | OPERAND_FFLAG | OPERAND_CFLAG
01329                       | OPERAND_CONTROL))
01330                 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
01331               {
01332                 match = 0;
01333                 break;
01334               }
01335            }
01336 
01337          if (((flags & OPERAND_MINUS)   && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
01338              ((flags & OPERAND_PLUS)    && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
01339              ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
01340              ((flags & OPERAND_ATPAR)   && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
01341              ((flags & OPERAND_ATSIGN)  && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR)))))
01342            {
01343              match = 0;
01344              break;
01345            }
01346 
01347          /* Unfortunately, for the indirect operand in instructions such
01348             as ``ldb r1, @(c,r14)'' this function can be passed
01349             X_op == O_register (because 'c' is a valid register name).
01350             However we cannot just ignore the case when X_op == O_register
01351             but flags & OPERAND_REG is null, so we check to see if a symbol
01352             of the same name as the register exists.  If the symbol does
01353             exist, then the parser was unable to distinguish the two cases
01354             and we fix things here. (Ref: PR14826)  */
01355 
01356          if (!(flags & OPERAND_REG) && (X_op == O_register))
01357            {
01358              symbolS * sym;
01359 
01360              sym = find_symbol_matching_register (& myops[i]);
01361 
01362              if (sym != NULL)
01363               {
01364                 myops[i].X_op = X_op = O_symbol;
01365                 myops[i].X_add_symbol = sym;
01366               }
01367              else
01368               as_bad
01369                 (_("illegal operand - register name found where none expected"));
01370            }
01371        }
01372 
01373       /* We're only done if the operands matched so far AND there
01374             are no more to check.  */
01375       if (match && myops[i].X_op == 0)
01376        break;
01377       else
01378        match = 0;
01379 
01380       next_opcode = opcode + 1;
01381 
01382       if (next_opcode->opcode == 0)
01383        break;
01384 
01385       if (strcmp (next_opcode->name, opcode->name))
01386        break;
01387 
01388       opcode = next_opcode;
01389     }
01390 
01391   if (!match)
01392     {
01393       as_bad (_("bad opcode or operands"));
01394       return 0;
01395     }
01396 
01397   /* Check that all registers that are required to be even are.
01398      Also, if any operands were marked as registers, but were really symbols,
01399      fix that here.  */
01400   for (i = 0; opcode->operands[i]; i++)
01401     {
01402       if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
01403          (myops[i].X_add_number & 1))
01404        as_fatal (_("Register number must be EVEN"));
01405       if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP)
01406          && (myops[i].X_add_number & OPERAND_SP))
01407        as_bad (_("Unsupported use of sp"));
01408       if (myops[i].X_op == O_register)
01409        {
01410          if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
01411            {
01412              myops[i].X_op = O_symbol;
01413              myops[i].X_add_symbol =
01414               symbol_find_or_make ((char *) myops[i].X_op_symbol);
01415              myops[i].X_add_number = 0;
01416              myops[i].X_op_symbol = NULL;
01417            }
01418        }
01419       if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL)
01420          && (myops[i].X_add_number == OPERAND_CONTROL + 4
01421              || myops[i].X_add_number == OPERAND_CONTROL + 5
01422              || myops[i].X_add_number == OPERAND_CONTROL + 6
01423              || myops[i].X_add_number == OPERAND_CONTROL + 12
01424              || myops[i].X_add_number == OPERAND_CONTROL + 13
01425              || myops[i].X_add_number == OPERAND_CONTROL + 15))
01426        as_warn (_("cr%ld is a reserved control register"),
01427                myops[i].X_add_number - OPERAND_CONTROL);
01428     }
01429   return opcode;
01430 }
01431 
01432 /* Assemble a single instruction.
01433    Return an opcode, or -1 (an invalid opcode) on error.  */
01434 
01435 static unsigned long
01436 do_assemble (char *str, struct d10v_opcode **opcode)
01437 {
01438   unsigned char *op_start, *op_end;
01439   char *save;
01440   char name[20];
01441   int nlen = 0;
01442   expressionS myops[6];
01443 
01444   /* Drop leading whitespace.  */
01445   while (*str == ' ')
01446     str++;
01447 
01448   /* Find the opcode end.  */
01449   for (op_start = op_end = (unsigned char *) str;
01450        *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
01451        op_end++)
01452     {
01453       name[nlen] = TOLOWER (op_start[nlen]);
01454       nlen++;
01455     }
01456   name[nlen] = 0;
01457 
01458   if (nlen == 0)
01459     return -1;
01460 
01461   /* Find the first opcode with the proper name.  */
01462   *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
01463   if (*opcode == NULL)
01464     return -1;
01465 
01466   save = input_line_pointer;
01467   input_line_pointer = (char *) op_end;
01468   *opcode = find_opcode (*opcode, myops);
01469   if (*opcode == 0)
01470     return -1;
01471   input_line_pointer = save;
01472 
01473   return build_insn ((*opcode), myops, 0);
01474 }
01475 
01476 /* If while processing a fixup, a reloc really needs to be created.
01477    Then it is done here.  */
01478 
01479 arelent *
01480 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
01481 {
01482   arelent *reloc;
01483   reloc = xmalloc (sizeof (arelent));
01484   reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
01485   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
01486   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
01487   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
01488   if (reloc->howto == (reloc_howto_type *) NULL)
01489     {
01490       as_bad_where (fixp->fx_file, fixp->fx_line,
01491                   _("reloc %d not supported by object file format"),
01492                   (int) fixp->fx_r_type);
01493       return NULL;
01494     }
01495 
01496   if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
01497     reloc->address = fixp->fx_offset;
01498 
01499   reloc->addend = 0;
01500 
01501   return reloc;
01502 }
01503 
01504 int
01505 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
01506                             asection *seg ATTRIBUTE_UNUSED)
01507 {
01508   abort ();
01509   return 0;
01510 }
01511 
01512 long
01513 md_pcrel_from_section (fixS *fixp, segT sec)
01514 {
01515   if (fixp->fx_addsy != (symbolS *) NULL
01516       && (!S_IS_DEFINED (fixp->fx_addsy)
01517          || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
01518     return 0;
01519   return fixp->fx_frag->fr_address + fixp->fx_where;
01520 }
01521 
01522 void
01523 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
01524 {
01525   char *where;
01526   unsigned long insn;
01527   long value = *valP;
01528   int op_type;
01529   int left = 0;
01530 
01531   if (fixP->fx_addsy == (symbolS *) NULL)
01532     fixP->fx_done = 1;
01533 
01534   /* We don't actually support subtracting a symbol.  */
01535   if (fixP->fx_subsy != (symbolS *) NULL)
01536     as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
01537 
01538   op_type = fixP->fx_r_type;
01539   if (op_type & 2048)
01540     {
01541       op_type -= 2048;
01542       if (op_type & 1024)
01543        {
01544          op_type -= 1024;
01545          fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
01546          left = 1;
01547        }
01548       else if (op_type & 4096)
01549        {
01550          op_type -= 4096;
01551          fixP->fx_r_type = BFD_RELOC_D10V_18;
01552        }
01553       else
01554        fixP->fx_r_type =
01555          get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
01556     }
01557 
01558   /* Fetch the instruction, insert the fully resolved operand
01559      value, and stuff the instruction back again.  */
01560   where = fixP->fx_frag->fr_literal + fixP->fx_where;
01561   insn = bfd_getb32 ((unsigned char *) where);
01562 
01563   switch (fixP->fx_r_type)
01564     {
01565     case BFD_RELOC_D10V_10_PCREL_L:
01566     case BFD_RELOC_D10V_10_PCREL_R:
01567     case BFD_RELOC_D10V_18_PCREL:
01568       /* If the fix is relative to a global symbol, not a section
01569         symbol, then ignore the offset.
01570          XXX - Do we have to worry about branches to a symbol + offset ?  */
01571       if (fixP->fx_addsy != NULL
01572          && S_IS_EXTERNAL (fixP->fx_addsy) )
01573         {
01574           segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
01575           segment_info_type *segf = seg_info(fseg);
01576 
01577          if ( segf && segf->sym != fixP->fx_addsy)
01578            value = 0;
01579         }
01580       /* Drop through.  */
01581     case BFD_RELOC_D10V_18:
01582       /* Instruction addresses are always right-shifted by 2.  */
01583       value >>= AT_WORD_RIGHT_SHIFT;
01584       if (fixP->fx_size == 2)
01585        bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
01586       else
01587        {
01588          struct d10v_opcode *rep, *repi;
01589 
01590          rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
01591          repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
01592          if ((insn & FM11) == FM11
01593              && ((repi != NULL
01594                  && (insn & repi->mask) == (unsigned) repi->opcode)
01595                 || (rep != NULL
01596                     && (insn & rep->mask) == (unsigned) rep->opcode))
01597              && value < 4)
01598            as_fatal
01599              (_("line %d: rep or repi must include at least 4 instructions"),
01600               fixP->fx_line);
01601          insn =
01602            d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP);
01603          bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
01604        }
01605       break;
01606     case BFD_RELOC_32:
01607       bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
01608       break;
01609     case BFD_RELOC_16:
01610       bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
01611       break;
01612 
01613     case BFD_RELOC_VTABLE_INHERIT:
01614     case BFD_RELOC_VTABLE_ENTRY:
01615       fixP->fx_done = 0;
01616       return;
01617 
01618     default:
01619       as_fatal (_("line %d: unknown relocation type: 0x%x"),
01620               fixP->fx_line, fixP->fx_r_type);
01621     }
01622 }
01623 
01624 /* d10v_cleanup() is called after the assembler has finished parsing
01625    the input file, when a label is read from the input file, or when a
01626    stab directive is output.  Because the D10V assembler sometimes
01627    saves short instructions to see if it can package them with the
01628    next instruction, there may be a short instruction that still needs
01629    to be written.
01630 
01631    NOTE: accesses a global, etype.
01632    NOTE: invoked by various macros such as md_cleanup: see.  */
01633 
01634 int
01635 d10v_cleanup (void)
01636 {
01637   segT seg;
01638   subsegT subseg;
01639 
01640   /* If cleanup was invoked because the assembler encountered, e.g., a
01641      user label, we write out the pending instruction, if any.  If it
01642      was invoked because the assembler is outputting a piece of line
01643      debugging information, though, we write out the pending
01644      instruction only if the --no-gstabs-packing command line switch
01645      has been specified.  */
01646   if (prev_opcode
01647       && etype == PACK_UNSPEC
01648       && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
01649     {
01650       seg = now_seg;
01651       subseg = now_subseg;
01652 
01653       if (prev_seg)
01654        subseg_set (prev_seg, prev_subseg);
01655 
01656       write_1_short (prev_opcode, prev_insn, fixups->next);
01657       subseg_set (seg, subseg);
01658       prev_opcode = NULL;
01659     }
01660   return 1;
01661 }
01662 
01663 /* Like normal .word, except support @word.
01664    Clobbers input_line_pointer, checks end-of-line.  */
01665 
01666 static void
01667 d10v_dot_word (int dummy ATTRIBUTE_UNUSED)
01668 {
01669   expressionS exp;
01670   char *p;
01671 
01672   if (is_it_end_of_statement ())
01673     {
01674       demand_empty_rest_of_line ();
01675       return;
01676     }
01677 
01678   do
01679     {
01680       expression (&exp);
01681       if (!strncasecmp (input_line_pointer, "@word", 5))
01682        {
01683          exp.X_add_number = 0;
01684          input_line_pointer += 5;
01685 
01686          p = frag_more (2);
01687          fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
01688                      &exp, 0, BFD_RELOC_D10V_18);
01689        }
01690       else
01691        emit_expr (&exp, 2);
01692     }
01693   while (*input_line_pointer++ == ',');
01694 
01695   input_line_pointer--;            /* Put terminator back into stream.  */
01696   demand_empty_rest_of_line ();
01697 }
01698 
01699 /* Mitsubishi asked that we support some old syntax that apparently
01700    had immediate operands starting with '#'.  This is in some of their
01701    sample code but is not documented (although it appears in some
01702    examples in their assembler manual). For now, we'll solve this
01703    compatibility problem by simply ignoring any '#' at the beginning
01704    of an operand.  */
01705 
01706 /* Operands that begin with '#' should fall through to here.
01707    From expr.c.  */
01708 
01709 void
01710 md_operand (expressionS *expressionP)
01711 {
01712   if (*input_line_pointer == '#' && ! do_not_ignore_hash)
01713     {
01714       input_line_pointer++;
01715       expression (expressionP);
01716     }
01717 }
01718 
01719 bfd_boolean
01720 d10v_fix_adjustable (fixS *fixP)
01721 {
01722   /* We need the symbol name for the VTABLE entries.  */
01723   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
01724       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
01725     return 0;
01726 
01727   return 1;
01728 }
01729 
01730 /* The target specific pseudo-ops which we support.  */
01731 const pseudo_typeS md_pseudo_table[] =
01732 {
01733   { "word",   d10v_dot_word,       2 },
01734   { NULL,       NULL,           0 }
01735 };
01736 
01737 void
01738 md_assemble (char *str)
01739 {
01740   /* etype is saved extype.  For multi-line instructions.  */
01741   packing_type extype = PACK_UNSPEC;             /* Parallel, etc.  */
01742   struct d10v_opcode *opcode;
01743   unsigned long insn;
01744   char *str2;
01745 
01746   if (etype == PACK_UNSPEC)
01747     {
01748       /* Look for the special multiple instruction separators.  */
01749       str2 = strstr (str, "||");
01750       if (str2)
01751        extype = PACK_PARALLEL;
01752       else
01753        {
01754          str2 = strstr (str, "->");
01755          if (str2)
01756            extype = PACK_LEFT_RIGHT;
01757          else
01758            {
01759              str2 = strstr (str, "<-");
01760              if (str2)
01761               extype = PACK_RIGHT_LEFT;
01762            }
01763        }
01764 
01765       /* str2 points to the separator, if there is one.  */
01766       if (str2)
01767        {
01768          *str2 = 0;
01769 
01770          /* If two instructions are present and we already have one saved,
01771             then first write out the saved one.  */
01772          d10v_cleanup ();
01773 
01774          /* Assemble first instruction and save it.  */
01775          prev_insn = do_assemble (str, &prev_opcode);
01776          prev_seg = now_seg;
01777          prev_subseg = now_subseg;
01778          if (prev_insn == (unsigned long) -1)
01779            as_fatal (_("can't find previous opcode "));
01780          fixups = fixups->next;
01781          str = str2 + 2;
01782        }
01783     }
01784 
01785   insn = do_assemble (str, &opcode);
01786   if (insn == (unsigned long) -1)
01787     {
01788       if (extype != PACK_UNSPEC)
01789        etype = extype;
01790       else
01791        as_bad (_("could not assemble: %s"), str);
01792       return;
01793     }
01794 
01795   if (etype != PACK_UNSPEC)
01796     {
01797       extype = etype;
01798       etype = PACK_UNSPEC;
01799     }
01800 
01801   /* If this is a long instruction, write it and any previous short
01802      instruction.  */
01803   if (opcode->format & LONG_OPCODE)
01804     {
01805       if (extype != PACK_UNSPEC)
01806        as_fatal (_("Unable to mix instructions as specified"));
01807       d10v_cleanup ();
01808       write_long (insn, fixups);
01809       prev_opcode = NULL;
01810       return;
01811     }
01812 
01813   if (prev_opcode
01814       && prev_seg
01815       && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
01816     d10v_cleanup ();
01817 
01818   if (prev_opcode
01819       && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
01820                            fixups)))
01821     {
01822       /* No instructions saved.  */
01823       prev_opcode = NULL;
01824     }
01825   else
01826     {
01827       if (extype != PACK_UNSPEC)
01828        as_fatal (_("Unable to mix instructions as specified"));
01829       /* Save last instruction so it may be packed on next pass.  */
01830       prev_opcode = opcode;
01831       prev_insn = insn;
01832       prev_seg = now_seg;
01833       prev_subseg = now_subseg;
01834       fixups = fixups->next;
01835     }
01836 }
01837