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cell-binutils  2.17cvs20070401
tc-cris.c
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00001 /* tc-cris.c -- Assembler code for the CRIS CPU core.
00002    Copyright 2000, 2001, 2002, 2003, 2004, 2006
00003    Free Software Foundation, Inc.
00004 
00005    Contributed by Axis Communications AB, Lund, Sweden.
00006    Originally written for GAS 1.38.1 by Mikael Asker.
00007    Updates, BFDizing, GNUifying and ELF support by Hans-Peter Nilsson.
00008 
00009    This file is part of GAS, the GNU Assembler.
00010 
00011    GAS is free software; you can redistribute it and/or modify
00012    it under the terms of the GNU General Public License as published by
00013    the Free Software Foundation; either version 2, or (at your option)
00014    any later version.
00015 
00016    GAS is distributed in the hope that it will be useful,
00017    but WITHOUT ANY WARRANTY; without even the implied warranty of
00018    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019    GNU General Public License for more details.
00020 
00021    You should have received a copy of the GNU General Public License
00022    along with GAS; see the file COPYING.  If not, write to the
00023    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
00024    MA 02110-1301, USA.  */
00025 
00026 #include "as.h"
00027 #include "safe-ctype.h"
00028 #include "subsegs.h"
00029 #include "opcode/cris.h"
00030 #include "dwarf2dbg.h"
00031 
00032 /* Conventions used here:
00033    Generally speaking, pointers to binutils types such as "fragS" and
00034    "expressionS" get parameter and variable names ending in "P", such as
00035    "fragP", to harmonize with the rest of the binutils code.  Other
00036    pointers get a "p" suffix, such as "bufp".  Any function or type-name
00037    that could clash with a current or future binutils or GAS function get
00038    a "cris_" prefix.  */
00039 
00040 #define SYNTAX_RELAX_REG_PREFIX "no_register_prefix"
00041 #define SYNTAX_ENFORCE_REG_PREFIX "register_prefix"
00042 #define SYNTAX_USER_SYM_LEADING_UNDERSCORE "leading_underscore"
00043 #define SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE "no_leading_underscore"
00044 #define REGISTER_PREFIX_CHAR '$'
00045 
00046 /* True for expressions where getting X_add_symbol and X_add_number is
00047    enough to get the "base" and "offset"; no need to make_expr_symbol.
00048    It's not enough to check if X_op_symbol is NULL; that misses unary
00049    operations like O_uminus.  */
00050 #define SIMPLE_EXPR(EXP) \
00051  ((EXP)->X_op == O_constant || (EXP)->X_op == O_symbol)
00052 
00053 /* Like in ":GOT", ":GOTOFF" etc.  Other ports use '@', but that's in
00054    line_separator_chars for CRIS, so we avoid it.  */
00055 #define PIC_SUFFIX_CHAR ':'
00056 
00057 /* This might be CRIS_INSN_NONE if we're assembling a prefix-insn only.
00058    Note that some prefix-insns might be assembled as CRIS_INSN_NORMAL.  */
00059 enum cris_insn_kind
00060 {
00061   CRIS_INSN_NORMAL, CRIS_INSN_NONE, CRIS_INSN_BRANCH, CRIS_INSN_MUL
00062 };
00063 
00064 /* An instruction will have one of these prefixes.
00065    Although the same bit-pattern, we handle BDAP with an immediate
00066    expression (eventually quick or [pc+]) different from when we only have
00067    register expressions.  */
00068 enum prefix_kind
00069 {
00070   PREFIX_NONE, PREFIX_BDAP_IMM, PREFIX_BDAP, PREFIX_BIAP, PREFIX_DIP,
00071   PREFIX_PUSH
00072 };
00073 
00074 /* The prefix for an instruction.  */
00075 struct cris_prefix
00076 {
00077   enum prefix_kind kind;
00078   int base_reg_number;
00079   unsigned int opcode;
00080 
00081   /* There might be an expression to be evaluated, like I in [rN+I].  */
00082   expressionS expr;
00083 
00084   /* If there's an expression, we might need a relocation.  Here's the
00085      type of what relocation to start relaxaton with.
00086      The relocation is assumed to start immediately after the prefix insn,
00087      so we don't provide an offset.  */
00088   enum bfd_reloc_code_real reloc;
00089 };
00090 
00091 /* The description of the instruction being assembled.  */
00092 struct cris_instruction
00093 {
00094   /* If CRIS_INSN_NONE, then this insn is of zero length.  */
00095   enum cris_insn_kind insn_type;
00096 
00097   /* If a special register was mentioned, this is its description, else
00098      it is NULL.  */
00099   const struct cris_spec_reg *spec_reg;
00100 
00101   unsigned int opcode;
00102 
00103   /* An insn may have at most one expression; theoretically there could be
00104      another in its prefix (but I don't see how that could happen).  */
00105   expressionS expr;
00106 
00107   /* The expression might need a relocation.  Here's one to start
00108      relaxation with.  */
00109   enum bfd_reloc_code_real reloc;
00110 
00111   /* The size in bytes of an immediate expression, or zero if
00112      nonapplicable.  */
00113   int imm_oprnd_size;
00114 };
00115 
00116 enum cris_archs
00117 {
00118   arch_cris_unknown,
00119   arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10,
00120   arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32
00121 };
00122 
00123 static enum cris_archs cris_arch_from_string (char **);
00124 static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage,
00125                                     enum cris_archs);
00126 
00127 static void cris_process_instruction (char *, struct cris_instruction *,
00128                                   struct cris_prefix *);
00129 static int get_bwd_size_modifier (char **, int *);
00130 static int get_bw_size_modifier (char **, int *);
00131 static int get_gen_reg (char **, int *);
00132 static int get_spec_reg (char **, const struct cris_spec_reg **);
00133 static int get_sup_reg (char **, int *);
00134 static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *,
00135                                       int *, int *, int *,
00136                                       expressionS *);
00137 static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *);
00138 static int cris_get_expression (char **, expressionS *);
00139 static int get_flags (char **, int *);
00140 static void gen_bdap (int, expressionS *);
00141 static int branch_disp (int);
00142 static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *,
00143                             long int);
00144 static void cris_number_to_imm (char *, long, int, fixS *, segT);
00145 static void cris_create_short_jump (char *, addressT, addressT, fragS *,
00146                                 symbolS *);
00147 static void s_syntax (int);
00148 static void s_cris_file (int);
00149 static void s_cris_loc (int);
00150 static void s_cris_arch (int);
00151 
00152 /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes.  */
00153 static void cris_get_pic_suffix (char **, bfd_reloc_code_real_type *,
00154                              expressionS *);
00155 static unsigned int cris_get_pic_reloc_size (bfd_reloc_code_real_type);
00156 
00157 /* All the .syntax functions.  */
00158 static void cris_force_reg_prefix (void);
00159 static void cris_relax_reg_prefix (void);
00160 static void cris_sym_leading_underscore (void);
00161 static void cris_sym_no_leading_underscore (void);
00162 static char *cris_insn_first_word_frag (void);
00163 
00164 /* Handle to the opcode hash table.  */
00165 static struct hash_control *op_hash = NULL;
00166 
00167 /* If we target cris-axis-linux-gnu (as opposed to generic cris-axis-elf),
00168    we default to no underscore and required register-prefixes.  The
00169    difference is in the default values.  */
00170 #ifdef TE_LINUX
00171 #define DEFAULT_CRIS_AXIS_LINUX_GNU TRUE
00172 #else
00173 #define DEFAULT_CRIS_AXIS_LINUX_GNU FALSE
00174 #endif
00175 
00176 /* Whether we demand that registers have a `$' prefix.  Default here.  */
00177 static bfd_boolean demand_register_prefix = DEFAULT_CRIS_AXIS_LINUX_GNU;
00178 
00179 /* Whether global user symbols have a leading underscore.  Default here.  */
00180 static bfd_boolean symbols_have_leading_underscore
00181   = !DEFAULT_CRIS_AXIS_LINUX_GNU;
00182 
00183 /* Whether or not we allow PIC, and expand to PIC-friendly constructs.  */
00184 static bfd_boolean pic = FALSE;
00185 
00186 /* If we're configured for "cris", default to allow all v0..v10
00187    instructions and register names.  */
00188 #ifndef DEFAULT_CRIS_ARCH
00189 #define DEFAULT_CRIS_ARCH cris_any_v0_v10
00190 #endif
00191 
00192 /* No whitespace in the CONCAT2 parameter list.  */
00193 static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH);
00194 
00195 const pseudo_typeS md_pseudo_table[] =
00196 {
00197   {"dword", cons, 4},
00198   {"syntax", s_syntax, 0},
00199   {"file", s_cris_file, 0},
00200   {"loc", s_cris_loc, 0},
00201   {"arch", s_cris_arch, 0},
00202   {NULL, 0, 0}
00203 };
00204 
00205 static int warn_for_branch_expansion = 0;
00206 
00207 /* Whether to emit error when a MULS/MULU could be located last on a
00208    cache-line.  */
00209 static int err_for_dangerous_mul_placement
00210  = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32);
00211 
00212 const char cris_comment_chars[] = ";";
00213 
00214 /* This array holds the chars that only start a comment at the beginning of
00215    a line.  If the line seems to have the form '# 123 filename'
00216    .line and .file directives will appear in the pre-processed output.  */
00217 /* Note that input_file.c hand-checks for '#' at the beginning of the
00218    first line of the input file.  This is because the compiler outputs
00219    #NO_APP at the beginning of its output.  */
00220 /* Also note that slash-star will always start a comment.  */
00221 const char line_comment_chars[] = "#";
00222 const char line_separator_chars[] = "@";
00223 
00224 /* Now all floating point support is shut off.  See md_atof.  */
00225 const char EXP_CHARS[] = "";
00226 const char FLT_CHARS[] = "";
00227 
00228 /* For CRIS, we encode the relax_substateTs (in e.g. fr_substate) as:
00229                      2              1               0
00230       ---/ /--+-----------------+-----------------+-----------------+
00231              |        what state ? |           how long ?                 |
00232       ---/ /--+-----------------+-----------------+-----------------+
00233 
00234    The "how long" bits are 00 = byte, 01 = word, 10 = dword (long).
00235    Not all lengths are legit for a given value of (what state).
00236 
00237    Groups for CRIS address relaxing:
00238 
00239    1. Bcc (pre-V32)
00240       length: byte, word, 10-byte expansion
00241 
00242    2. BDAP
00243       length: byte, word, dword
00244 
00245    3. MULS/MULU
00246       Not really a relaxation (no infrastructure to get delay-slots
00247       right), just an alignment and placement checker for the v10
00248       multiply/cache-bug.
00249 
00250    4. Bcc (V32 and later)
00251       length: byte, word, 14-byte expansion
00252 
00253    5. Bcc (V10+V32)
00254       length: byte, word, error
00255 
00256    6. BA (V32)
00257       length: byte, word, dword
00258 
00259    7. LAPC (V32)
00260       length: byte, dword
00261   */
00262 
00263 #define STATE_COND_BRANCH           (1)
00264 #define STATE_BASE_PLUS_DISP_PREFIX (2)
00265 #define STATE_MUL               (3)
00266 #define STATE_COND_BRANCH_V32       (4)
00267 #define STATE_COND_BRANCH_COMMON    (5)
00268 #define STATE_ABS_BRANCH_V32           (6)
00269 #define STATE_LAPC              (7)
00270 #define STATE_COND_BRANCH_PIC       (8)
00271 
00272 #define STATE_LENGTH_MASK       (3)
00273 #define STATE_BYTE              (0)
00274 #define STATE_WORD              (1)
00275 #define STATE_DWORD             (2)
00276 /* Symbol undefined.  */
00277 #define STATE_UNDF              (3)
00278 #define STATE_MAX_LENGTH        (3)
00279 
00280 /* These displacements are relative to the address following the opcode
00281    word of the instruction.  The first letter is Byte, Word.  The 2nd
00282    letter is Forward, Backward.  */
00283 
00284 #define BRANCH_BF ( 254)
00285 #define BRANCH_BB (-256)
00286 #define BRANCH_BF_V32 ( 252)
00287 #define BRANCH_BB_V32 (-258)
00288 #define BRANCH_WF (2 +  32767)
00289 #define BRANCH_WB (2 + -32768)
00290 #define BRANCH_WF_V32 (-2 + 32767)
00291 #define BRANCH_WB_V32 (-2 + -32768)
00292 
00293 #define BDAP_BF        ( 127)
00294 #define BDAP_BB        (-128)
00295 #define BDAP_WF        ( 32767)
00296 #define BDAP_WB        (-32768)
00297 
00298 #define ENCODE_RELAX(what, length) (((what) << 2) + (length))
00299 
00300 const relax_typeS md_cris_relax_table[] =
00301 {
00302   /* Error sentinel (0, 0).  */
00303   {1,        1,       0,  0},
00304 
00305   /* Unused (0, 1).  */
00306   {1,        1,       0,  0},
00307 
00308   /* Unused (0, 2).  */
00309   {1,        1,       0,  0},
00310 
00311   /* Unused (0, 3).  */
00312   {1,        1,       0,  0},
00313 
00314   /* Bcc o (1, 0).  */
00315   {BRANCH_BF, BRANCH_BB, 0,  ENCODE_RELAX (1, 1)},
00316 
00317   /* Bcc [PC+] (1, 1).  */
00318   {BRANCH_WF, BRANCH_WB, 2,  ENCODE_RELAX (1, 2)},
00319 
00320   /* BEXT/BWF, BA, JUMP (external), JUMP (always), Bnot_cc, JUMP (default)
00321      (1, 2).  */
00322   {0,        0,       10, 0},
00323 
00324   /* Unused (1, 3).  */
00325   {1,        1,       0,  0},
00326 
00327   /* BDAP o (2, 0).  */
00328   {BDAP_BF,   BDAP_BB,       0,  ENCODE_RELAX (2, 1)},
00329 
00330   /* BDAP.[bw] [PC+] (2, 1).  */
00331   {BDAP_WF,   BDAP_WB,       2,  ENCODE_RELAX (2, 2)},
00332 
00333   /* BDAP.d [PC+] (2, 2).  */
00334   {0,        0,       4,  0},
00335 
00336   /* Unused (2, 3).  */
00337   {1,        1,       0,  0},
00338 
00339   /* MULS/MULU (3, 0).  Positions (3, 1..3) are unused.  */
00340   {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
00341 
00342   /* V32: Bcc o (4, 0).  */
00343   {BRANCH_BF_V32, BRANCH_BB_V32, 0,  ENCODE_RELAX (4, 1)},
00344 
00345   /* V32: Bcc [PC+] (4, 1).  */
00346   {BRANCH_WF_V32, BRANCH_WB_V32, 2,  ENCODE_RELAX (4, 2)},
00347 
00348   /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6  (4, 2).  */
00349   {0,        0,       12, 0},
00350 
00351   /* Unused (4, 3).  */
00352   {1,        1,       0,  0},
00353 
00354   /* COMMON: Bcc o (5, 0).  The offsets are calculated as for v32.  Code
00355      should contain two nop insns (or four if offset size is large or
00356      unknown) after every label.  */
00357   {BRANCH_BF_V32, BRANCH_BB_V32, 0,  ENCODE_RELAX (5, 1)},
00358 
00359   /* COMMON: Bcc [PC+] (5, 1).  */
00360   {BRANCH_WF_V32, BRANCH_WB_V32, 2,  ENCODE_RELAX (5, 2)},
00361 
00362   /* COMMON: FIXME: ???.  Treat as error currently.  */
00363   {0,        0,       12, 0},
00364 
00365   /* Unused (5, 3).  */
00366   {1,        1,       0,  0},
00367 
00368   /* V32: BA o (6, 0).  */
00369   {BRANCH_BF_V32, BRANCH_BB_V32, 0,  ENCODE_RELAX (6, 1)},
00370 
00371   /* V32: BA.W (6, 1).  */
00372   {BRANCH_WF_V32, BRANCH_WB_V32, 2,  ENCODE_RELAX (6, 2)},
00373 
00374   /* V32: BA.D (6, 2).  */
00375   {0,        0,       4, 0},
00376 
00377   /* Unused (6, 3).  */
00378   {1,        1,       0,  0},
00379 
00380   /* LAPC: LAPCQ .+0..15*2,Rn  (7, 0).  */
00381   {14*2,   -1*2,      0,  ENCODE_RELAX (7, 2)},
00382 
00383   /* Unused (7, 1).
00384      While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ,
00385      that would affect flags, so we can't do that as it wouldn't be a
00386      proper insn expansion of LAPCQ.  This row is associated with a
00387      2-byte expansion, so it's unused rather than the next.  */
00388   {1,        1,       0,  0},
00389 
00390   /* LAPC: LAPC.D (7, 2).  */
00391   {0,        0,       4, 0},
00392 
00393   /* Unused (7, 3).  */
00394   {1,        1,       0,  0},
00395 
00396   /* PIC for pre-v32: Bcc o (8, 0).  */
00397   {BRANCH_BF, BRANCH_BB, 0,  ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)},
00398 
00399   /* Bcc [PC+] (8, 1).  */
00400   {BRANCH_WF, BRANCH_WB, 2,  ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)},
00401 
00402   /* 32-bit expansion, PIC (8, 2).  */
00403   {0,        0,       12, 0},
00404 
00405   /* Unused (8, 3).  */
00406   {1,        1,       0,  0}
00407 };
00408 
00409 #undef BDAP_BF
00410 #undef BDAP_BB
00411 #undef BDAP_WF
00412 #undef BDAP_WB
00413 
00414 /* Target-specific multicharacter options, not const-declared.  */
00415 struct option md_longopts[] =
00416 {
00417 #define OPTION_NO_US (OPTION_MD_BASE + 0)
00418   {"no-underscore", no_argument, NULL, OPTION_NO_US},
00419 #define OPTION_US (OPTION_MD_BASE + 1)
00420   {"underscore", no_argument, NULL, OPTION_US},
00421 #define OPTION_PIC (OPTION_US + 1)
00422   {"pic", no_argument, NULL, OPTION_PIC},
00423 #define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1)
00424   {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON},
00425 #define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1)
00426   {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF},
00427 #define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1)
00428   {"march", required_argument, NULL, OPTION_ARCH},
00429   {NULL, no_argument, NULL, 0}
00430 };
00431 
00432 /* Not const-declared.  */
00433 size_t md_longopts_size = sizeof (md_longopts);
00434 const char *md_shortopts = "hHN";
00435 
00436 /* At first glance, this may seems wrong and should be 4 (ba + nop); but
00437    since a short_jump must skip a *number* of long jumps, it must also be
00438    a long jump.  Here, we hope to make it a "ba [16bit_offs]" and a "nop"
00439    for the delay slot and hope that the jump table at most needs
00440    32767/4=8191 long-jumps.  A branch is better than a jump, since it is
00441    relative; we will not have a reloc to fix up somewhere.
00442 
00443    Note that we can't add relocs, because relaxation uses these fixed
00444    numbers, and md_create_short_jump is called after relaxation.  */
00445 
00446 int md_short_jump_size = 6;
00447 
00448 /* The v32 version has a delay-slot, hence two bytes longer.
00449    The pre-v32 PIC version uses a prefixed insn.  */
00450 #define cris_any_v0_v10_long_jump_size 6
00451 #define cris_any_v0_v10_long_jump_size_pic 8
00452 #define crisv32_long_jump_size 8
00453 
00454 int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size);
00455 
00456 /* Report output format.  Small changes in output format (like elf
00457    variants below) can happen until all options are parsed, but after
00458    that, the output format must remain fixed.  */
00459 
00460 const char *
00461 cris_target_format (void)
00462 {
00463   switch (OUTPUT_FLAVOR)
00464     {
00465     case bfd_target_aout_flavour:
00466       return "a.out-cris";
00467 
00468     case bfd_target_elf_flavour:
00469       if (symbols_have_leading_underscore)
00470        return "elf32-us-cris";
00471       return "elf32-cris";
00472 
00473     default:
00474       abort ();
00475       return NULL;
00476     }
00477 }
00478 
00479 /* Return a bfd_mach_cris... value corresponding to the value of
00480    cris_arch.  */
00481 
00482 unsigned int
00483 cris_mach (void)
00484 {
00485   unsigned int retval = 0;
00486 
00487   switch (cris_arch)
00488     {
00489     case arch_cris_common_v10_v32:
00490       retval = bfd_mach_cris_v10_v32;
00491       break;
00492 
00493     case arch_crisv32:
00494       retval = bfd_mach_cris_v32;
00495       break;
00496 
00497     case arch_crisv10:
00498     case arch_cris_any_v0_v10:
00499       retval = bfd_mach_cris_v0_v10;
00500       break;
00501 
00502     default:
00503       BAD_CASE (cris_arch);
00504     }
00505 
00506   return retval;
00507 }
00508 
00509 /* We need a port-specific relaxation function to cope with sym2 - sym1
00510    relative expressions with both symbols in the same segment (but not
00511    necessarily in the same frag as this insn), for example:
00512      move.d [pc+sym2-(sym1-2)],r10
00513     sym1:
00514    The offset can be 8, 16 or 32 bits long.  */
00515 
00516 long
00517 cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP,
00518                long stretch ATTRIBUTE_UNUSED)
00519 {
00520   long growth;
00521   offsetT aim = 0;
00522   symbolS *symbolP;
00523   const relax_typeS *this_type;
00524   const relax_typeS *start_type;
00525   relax_substateT next_state;
00526   relax_substateT this_state;
00527   const relax_typeS *table = TC_GENERIC_RELAX_TABLE;
00528 
00529   /* We only have to cope with frags as prepared by
00530      md_estimate_size_before_relax.  The dword cases may get here
00531      because of the different reasons that they aren't relaxable.  */
00532   switch (fragP->fr_subtype)
00533     {
00534     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
00535     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
00536     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
00537     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
00538     case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
00539     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
00540       /* When we get to these states, the frag won't grow any more.  */
00541       return 0;
00542 
00543     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
00544     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
00545       if (fragP->fr_symbol == NULL
00546          || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
00547        as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
00548                 __FUNCTION__, (long) fragP->fr_symbol);
00549       symbolP = fragP->fr_symbol;
00550       if (symbol_resolved_p (symbolP))
00551        as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
00552                 __FUNCTION__);
00553       aim = S_GET_VALUE (symbolP);
00554       break;
00555 
00556     case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
00557       /* Nothing to do here.  */
00558       return 0;
00559 
00560     default:
00561       as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
00562                 __FUNCTION__, fragP->fr_subtype);
00563     }
00564 
00565   /* The rest is stolen from relax_frag.  There's no obvious way to
00566      share the code, but fortunately no requirement to keep in sync as
00567      long as fragP->fr_symbol does not have its segment changed.  */
00568 
00569   this_state = fragP->fr_subtype;
00570   start_type = this_type = table + this_state;
00571 
00572   if (aim < 0)
00573     {
00574       /* Look backwards.  */
00575       for (next_state = this_type->rlx_more; next_state;)
00576        if (aim >= this_type->rlx_backward)
00577          next_state = 0;
00578        else
00579          {
00580            /* Grow to next state.  */
00581            this_state = next_state;
00582            this_type = table + this_state;
00583            next_state = this_type->rlx_more;
00584          }
00585     }
00586   else
00587     {
00588       /* Look forwards.  */
00589       for (next_state = this_type->rlx_more; next_state;)
00590        if (aim <= this_type->rlx_forward)
00591          next_state = 0;
00592        else
00593          {
00594            /* Grow to next state.  */
00595            this_state = next_state;
00596            this_type = table + this_state;
00597            next_state = this_type->rlx_more;
00598          }
00599     }
00600 
00601   growth = this_type->rlx_length - start_type->rlx_length;
00602   if (growth != 0)
00603     fragP->fr_subtype = this_state;
00604   return growth;
00605 }
00606 
00607 /* Prepare machine-dependent frags for relaxation.
00608 
00609    Called just before relaxation starts. Any symbol that is now undefined
00610    will not become defined.
00611 
00612    Return the correct fr_subtype in the frag.
00613 
00614    Return the initial "guess for fr_var" to caller.  The guess for fr_var
00615    is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
00616    or fr_var contributes to our returned value.
00617 
00618    Although it may not be explicit in the frag, pretend
00619    fr_var starts with a value.  */
00620 
00621 int
00622 md_estimate_size_before_relax (fragS *fragP, segT segment_type)
00623 {
00624   int old_fr_fix;
00625   symbolS *symbolP = fragP->fr_symbol;
00626 
00627 #define HANDLE_RELAXABLE(state)                                       \
00628     case ENCODE_RELAX (state, STATE_UNDF):                            \
00629       if (symbolP != NULL                                      \
00630          && S_GET_SEGMENT (symbolP) == segment_type                   \
00631          && !S_IS_WEAK (symbolP))                              \
00632        /* The symbol lies in the same segment - a relaxable           \
00633           case.  */                                            \
00634        fragP->fr_subtype                                       \
00635          = ENCODE_RELAX (state, STATE_BYTE);                          \
00636       else                                                     \
00637        /* Unknown or not the same segment, so not relaxable.  */      \
00638        fragP->fr_subtype                                       \
00639          = ENCODE_RELAX (state, STATE_DWORD);                         \
00640       fragP->fr_var                                            \
00641        = md_cris_relax_table[fragP->fr_subtype].rlx_length;           \
00642       break
00643 
00644   old_fr_fix = fragP->fr_fix;
00645 
00646   switch (fragP->fr_subtype)
00647     {
00648       HANDLE_RELAXABLE (STATE_COND_BRANCH);
00649       HANDLE_RELAXABLE (STATE_COND_BRANCH_V32);
00650       HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON);
00651       HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC);
00652       HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32);
00653 
00654     case ENCODE_RELAX (STATE_LAPC, STATE_UNDF):
00655       if (symbolP != NULL
00656          && S_GET_SEGMENT (symbolP) == segment_type
00657          && !S_IS_WEAK (symbolP))
00658        {
00659          /* The symbol lies in the same segment - a relaxable case.
00660             Check if we currently have an odd offset; we can't code
00661             that into the instruction.  Relaxing presumably only cause
00662             multiple-of-two changes, so we should only need to adjust
00663             for that here.  */
00664          bfd_vma target_address
00665            = (symbolP
00666               ? S_GET_VALUE (symbolP)
00667               : 0) + fragP->fr_offset;
00668          bfd_vma var_part_offset = fragP->fr_fix;
00669          bfd_vma address_of_var_part = fragP->fr_address + var_part_offset;
00670          long offset = target_address - (address_of_var_part - 2);
00671 
00672          fragP->fr_subtype
00673            = (offset & 1)
00674            ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD)
00675            : ENCODE_RELAX (STATE_LAPC, STATE_BYTE);
00676        }
00677       else
00678        /* Unknown or not the same segment, so not relaxable.  */
00679        fragP->fr_subtype
00680          = ENCODE_RELAX (STATE_LAPC, STATE_DWORD);
00681       fragP->fr_var
00682        = md_cris_relax_table[fragP->fr_subtype].rlx_length;
00683       break;
00684 
00685     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF):
00686       /* Note that we can not do anything sane with relaxing
00687         [rX + a_known_symbol_in_text], it will have to be a 32-bit
00688         value.
00689 
00690         We could play tricks with managing a constant pool and make
00691         a_known_symbol_in_text a "bdap [pc + offset]" pointing there
00692         (like the GOT for ELF shared libraries), but that's no use, it
00693         would in general be no shorter or faster code, only more
00694         complicated.  */
00695 
00696       if (S_GET_SEGMENT (symbolP) != absolute_section)
00697        {
00698          /* Go for dword if not absolute or same segment.  */
00699          fragP->fr_subtype
00700            = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD);
00701          fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
00702        }
00703       else if (!symbol_resolved_p (fragP->fr_symbol))
00704        {
00705          /* The symbol will eventually be completely resolved as an
00706             absolute expression, but right now it depends on the result
00707             of relaxation and we don't know anything else about the
00708             value.  We start relaxation with the assumption that it'll
00709             fit in a byte.  */
00710          fragP->fr_subtype
00711            = ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE);
00712          fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
00713        }
00714       else
00715        {
00716          /* Absolute expression.  */
00717          long int value;
00718          value = (symbolP != NULL
00719                  ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset;
00720 
00721          if (value >= -128 && value <= 127)
00722            {
00723              /* Byte displacement.  */
00724              (fragP->fr_opcode)[0] = value;
00725            }
00726          else
00727            {
00728              /* Word or dword displacement.  */
00729              int pow2_of_size = 1;
00730              char *writep;
00731 
00732              if (value < -32768 || value > 32767)
00733               {
00734                 /* Outside word range, make it a dword.  */
00735                 pow2_of_size = 2;
00736               }
00737 
00738              /* Modify the byte-offset BDAP into a word or dword offset
00739                BDAP. Or really, a BDAP rX,8bit into a
00740                BDAP.[wd] rX,[PC+] followed by a word or dword.  */
00741              (fragP->fr_opcode)[0] = BDAP_PC_LOW + pow2_of_size * 16;
00742 
00743              /* Keep the register number in the highest four bits.  */
00744              (fragP->fr_opcode)[1] &= 0xF0;
00745              (fragP->fr_opcode)[1] |= BDAP_INCR_HIGH;
00746 
00747              /* It grew by two or four bytes.  */
00748              fragP->fr_fix += 1 << pow2_of_size;
00749              writep = fragP->fr_literal + old_fr_fix;
00750              md_number_to_chars (writep, value, 1 << pow2_of_size);
00751            }
00752          frag_wane (fragP);
00753        }
00754       break;
00755 
00756     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE):
00757     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD):
00758     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
00759     case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE):
00760     case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD):
00761     case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
00762     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE):
00763     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD):
00764     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
00765     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE):
00766     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD):
00767     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
00768     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE):
00769     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD):
00770     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
00771     case ENCODE_RELAX (STATE_LAPC, STATE_BYTE):
00772     case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
00773     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
00774     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
00775     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
00776       /* When relaxing a section for the second time, we don't need to
00777         do anything except making sure that fr_var is set right.  */
00778       fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
00779       break;
00780 
00781     case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
00782       /* Nothing to do here.  */
00783       break;
00784 
00785     default:
00786       BAD_CASE (fragP->fr_subtype);
00787     }
00788 
00789   return fragP->fr_var + (fragP->fr_fix - old_fr_fix);
00790 }
00791 
00792 /* Perform post-processing of machine-dependent frags after relaxation.
00793    Called after relaxation is finished.
00794    In: Address of frag.
00795        fr_type == rs_machine_dependent.
00796        fr_subtype is what the address relaxed to.
00797 
00798    Out: Any fixS:s and constants are set up.
00799 
00800    The caller will turn the frag into a ".space 0".  */
00801 
00802 void
00803 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
00804                fragS *fragP)
00805 {
00806   /* Pointer to first byte in variable-sized part of the frag.  */
00807   char *var_partp;
00808 
00809   /* Pointer to first opcode byte in frag.  */
00810   char *opcodep;
00811 
00812   /* Used to check integrity of the relaxation.
00813      One of 2 = long, 1 = word, or 0 = byte.  */
00814   int length_code;
00815 
00816   /* Size in bytes of variable-sized part of frag.  */
00817   int var_part_size = 0;
00818 
00819   /* This is part of *fragP.  It contains all information about addresses
00820      and offsets to varying parts.  */
00821   symbolS *symbolP;
00822   unsigned long var_part_offset;
00823 
00824   /* Where, in file space, is _var of *fragP?  */
00825   unsigned long address_of_var_part = 0;
00826 
00827   /* Where, in file space, does addr point?  */
00828   unsigned long target_address;
00829 
00830   know (fragP->fr_type == rs_machine_dependent);
00831 
00832   length_code = fragP->fr_subtype & STATE_LENGTH_MASK;
00833   know (length_code >= 0 && length_code < STATE_MAX_LENGTH);
00834 
00835   var_part_offset = fragP->fr_fix;
00836   var_partp = fragP->fr_literal + var_part_offset;
00837   opcodep = fragP->fr_opcode;
00838 
00839   symbolP = fragP->fr_symbol;
00840   target_address = (symbolP ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset;
00841   address_of_var_part = fragP->fr_address + var_part_offset;
00842 
00843   switch (fragP->fr_subtype)
00844     {
00845     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE):
00846     case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE):
00847     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE):
00848     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE):
00849     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE):
00850       opcodep[0] = branch_disp ((target_address - address_of_var_part));
00851       var_part_size = 0;
00852       break;
00853 
00854     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD):
00855     case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD):
00856     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD):
00857     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD):
00858     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD):
00859       /* We had a quick immediate branch, now turn it into a word one i.e. a
00860         PC autoincrement.  */
00861       opcodep[0] = BRANCH_PC_LOW;
00862       opcodep[1] &= 0xF0;
00863       opcodep[1] |= BRANCH_INCR_HIGH;
00864       md_number_to_chars (var_partp,
00865                        (long)
00866                        (target_address
00867                         - (address_of_var_part
00868                            + (cris_arch == arch_crisv32
00869                              || cris_arch == arch_cris_common_v10_v32
00870                              ? -2 : 2))),
00871                        2);
00872       var_part_size = 2;
00873       break;
00874 
00875     case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
00876       gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
00877                        fragP->fr_symbol, (symbolS *) NULL,
00878                        fragP->fr_offset);
00879       /* Ten bytes added: a branch, nop and a jump.  */
00880       var_part_size = 2 + 2 + 4 + 2;
00881       break;
00882 
00883     case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
00884       gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
00885                        fragP->fr_symbol, (symbolS *) NULL,
00886                        fragP->fr_offset);
00887       /* Twelve bytes added: a branch, nop and a pic-branch-32.  */
00888       var_part_size = 2 + 2 + 4 + 2 + 2;
00889       break;
00890 
00891     case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
00892       gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
00893                        fragP->fr_symbol, (symbolS *) NULL,
00894                        fragP->fr_offset);
00895       /* Twelve bytes added: a branch, nop and another branch and nop.  */
00896       var_part_size = 2 + 2 + 2 + 4 + 2;
00897       break;
00898 
00899     case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
00900       as_bad_where (fragP->fr_file, fragP->fr_line,
00901                   _("Relaxation to long branches for .arch common_v10_v32\
00902  not implemented"));
00903       /* Pretend we have twelve bytes for sake of quelling further
00904          errors.  */
00905       var_part_size = 2 + 2 + 2 + 4 + 2;
00906       break;
00907 
00908     case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
00909       /* We had a quick immediate branch or a word immediate ba.  Now
00910         turn it into a dword one.  */
00911       opcodep[0] = BA_DWORD_OPCODE & 255;
00912       opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255;
00913       fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP,
00914               fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL);
00915       var_part_size = 4;
00916       break;
00917 
00918     case ENCODE_RELAX (STATE_LAPC, STATE_BYTE):
00919       {
00920        long offset = target_address - (address_of_var_part - 2);
00921 
00922        /* This is mostly a sanity check; useful occurrences (if there
00923           really are any) should have been caught in
00924           md_estimate_size_before_relax.  We can (at least
00925           theoretically) stumble over invalid code with odd sizes and
00926           .p2aligns within the code, so emit an error if that happens.
00927           (The generic relaxation machinery is not fit to check this.)  */
00928 
00929        if (offset & 1)
00930          as_bad_where (fragP->fr_file, fragP->fr_line,
00931                   _("Complicated LAPC target operand is not\
00932  a multiple of two.  Use LAPC.D"));
00933 
00934        /* FIXME: This *is* a sanity check.  Remove when done with.  */
00935        if (offset > 15*2 || offset < 0)
00936          as_fatal (_("Internal error found in md_convert_frag: offset %ld.\
00937   Please report this."),
00938                   offset);
00939 
00940        opcodep[0] |= (offset / 2) & 0xf;
00941        var_part_size = 0;
00942       }
00943       break;
00944 
00945     case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
00946       {
00947        md_number_to_chars (opcodep,
00948                          LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256,
00949                          2);
00950        /* Remember that the reloc is against the position *after* the
00951           relocated contents, so we need to adjust to the start of
00952           the insn.  */
00953        fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol,
00954                fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL);
00955        var_part_size = 4;
00956       }
00957       break;
00958 
00959     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
00960       if (symbolP == NULL)
00961        as_fatal (_("internal inconsistency in %s: bdapq no symbol"),
00962                   __FUNCTION__);
00963       opcodep[0] = S_GET_VALUE (symbolP);
00964       var_part_size = 0;
00965       break;
00966 
00967     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
00968       /* We had a BDAP 8-bit "quick immediate", now turn it into a 16-bit
00969         one that uses PC autoincrement.  */
00970       opcodep[0] = BDAP_PC_LOW + (1 << 4);
00971       opcodep[1] &= 0xF0;
00972       opcodep[1] |= BDAP_INCR_HIGH;
00973       if (symbolP == NULL)
00974        as_fatal (_("internal inconsistency in %s: bdap.w with no symbol"),
00975                 __FUNCTION__);
00976       md_number_to_chars (var_partp, S_GET_VALUE (symbolP), 2);
00977       var_part_size = 2;
00978       break;
00979 
00980     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
00981       /* We had a BDAP 16-bit "word", change the offset to a dword.  */
00982       opcodep[0] = BDAP_PC_LOW + (2 << 4);
00983       opcodep[1] &= 0xF0;
00984       opcodep[1] |= BDAP_INCR_HIGH;
00985       if (fragP->fr_symbol == NULL)
00986        md_number_to_chars (var_partp, fragP->fr_offset, 4);
00987       else
00988        fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol,
00989                fragP->fr_offset, 0, BFD_RELOC_32);
00990       var_part_size = 4;
00991       break;
00992 
00993     case ENCODE_RELAX (STATE_MUL, STATE_BYTE):
00994       /* This is the only time we check position and alignment of the
00995         placement-tracking frag.  */
00996       if (sec->alignment_power < 2)
00997        as_bad_where (fragP->fr_file, fragP->fr_line,
00998                     _("section alignment must be >= 4 bytes to check MULS/MULU safeness"));
00999       else
01000        {
01001          /* If the address after the MULS/MULU has alignment which is
01002             that of the section and may be that of a cache-size of the
01003             buggy versions, then the MULS/MULU can be placed badly.  */
01004          if ((address_of_var_part
01005               & ((1 << sec->alignment_power) - 1) & 31) == 0)
01006            as_bad_where (fragP->fr_file, fragP->fr_line,
01007                        _("dangerous MULS/MULU location; give it higher alignment"));
01008        }
01009       break;
01010 
01011     default:
01012       BAD_CASE (fragP->fr_subtype);
01013       break;
01014     }
01015 
01016   fragP->fr_fix += var_part_size;
01017 }
01018 
01019 /* Generate a short jump around a secondary jump table.
01020    Used by md_create_long_jump.
01021 
01022    This used to be md_create_short_jump, but is now called from
01023    md_create_long_jump instead, when sufficient, since the sizes of the
01024    jumps are the same for pre-v32.  */
01025 
01026 static void
01027 cris_create_short_jump (char *storep, addressT from_addr, addressT to_addr,
01028                      fragS *fragP ATTRIBUTE_UNUSED,
01029                      symbolS *to_symbol ATTRIBUTE_UNUSED)
01030 {
01031   long int distance;
01032 
01033   /* See md_create_long_jump about the comment on the "+ 2".  */
01034   long int max_minimal_minus_distance;
01035   long int max_minimal_plus_distance;
01036   int nop_opcode;
01037 
01038   if (cris_arch == arch_crisv32)
01039     {
01040       max_minimal_minus_distance = BRANCH_BB_V32 + 2;
01041       max_minimal_plus_distance = BRANCH_BF_V32 + 2;
01042       nop_opcode = NOP_OPCODE_V32;
01043     }
01044   else
01045     {
01046       max_minimal_minus_distance = BRANCH_BB + 2;
01047       max_minimal_plus_distance = BRANCH_BF + 2;
01048       nop_opcode = NOP_OPCODE;
01049     }
01050 
01051   distance = to_addr - from_addr;
01052 
01053   if (max_minimal_minus_distance <= distance
01054       && distance <= max_minimal_plus_distance)
01055     {
01056       /* Create a "short" short jump: "BA distance - 2".  */
01057       storep[0] = branch_disp (distance - 2);
01058       storep[1] = BA_QUICK_HIGH;
01059 
01060       /* A nop for the delay slot.  */
01061       md_number_to_chars (storep + 2, nop_opcode, 2);
01062 
01063       /* The extra word should be filled with something sane too.  Make it
01064         a nop to keep disassembly sane.  */
01065       md_number_to_chars (storep + 4, nop_opcode, 2);
01066     }
01067   else
01068     {
01069       /* Make it a "long" short jump: "BA (PC+)".  */
01070       md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2);
01071 
01072       /* ".WORD distance - 4".  */
01073       md_number_to_chars (storep + 2,
01074                        (long) (distance - 4
01075                               - (cris_arch == arch_crisv32
01076                                  ? -4 : 0)),
01077                        2);
01078 
01079       /* A nop for the delay slot.  */
01080       md_number_to_chars (storep + 4, nop_opcode, 2);
01081     }
01082 }
01083 
01084 /* Generate a long jump in a secondary jump table.
01085 
01086    storep  Where to store the jump instruction.
01087    from_addr  Address of the jump instruction.
01088    to_addr    Destination address of the jump.
01089    fragP      Which frag the destination address operand
01090              lies in.
01091    to_symbol  Destination symbol.  */
01092 
01093 void
01094 md_create_long_jump (char *storep, addressT from_addr, addressT to_addr,
01095                    fragS *fragP, symbolS *to_symbol)
01096 {
01097   long int distance;
01098 
01099   /* FIXME: What's that "+ 3"?  It comes from the magic numbers that
01100      used to be here, it's just translated to the limit macros used in
01101      the relax table.  But why + 3?  */
01102   long int max_short_minus_distance
01103     = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3;
01104 
01105   long int max_short_plus_distance
01106     = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3;
01107 
01108   /* Bail out for compatibility mode.  (It seems it can be implemented,
01109      perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump
01110      $acr", "nop"; but doesn't seem worth it at the moment.)  */
01111   if (cris_arch == arch_cris_common_v10_v32)
01112     as_fatal (_("Out-of-range .word offset handling\
01113  is not implemented for .arch common_v10_v32"));
01114 
01115   distance = to_addr - from_addr;
01116 
01117   if (max_short_minus_distance <= distance
01118       && distance <= max_short_plus_distance)
01119     /* Then make it a "short" long jump.  */
01120     cris_create_short_jump (storep, from_addr, to_addr, fragP,
01121                          to_symbol);
01122   else
01123     {
01124       /* We have a "long" long jump: "JUMP [PC+]".  If CRISv32, always
01125         make it a BA.  Else make it an "MOVE [PC=PC+N],P0" if we're supposed
01126         to emit PIC code.  */
01127       md_number_to_chars (storep,
01128                        cris_arch == arch_crisv32
01129                        ? BA_DWORD_OPCODE
01130                        : (pic ? MOVE_PC_INCR_OPCODE_PREFIX
01131                           : JUMP_PC_INCR_OPCODE),
01132                        2);
01133 
01134       /* Follow with a ".DWORD to_addr", PC-relative for PIC.  */
01135       fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol,
01136               cris_arch == arch_crisv32 ? 6 : 0,
01137               cris_arch == arch_crisv32 || pic ? 1 : 0,
01138               cris_arch == arch_crisv32 || pic
01139               ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
01140 
01141       /* Follow it with a "NOP" for CRISv32.  */
01142       if (cris_arch == arch_crisv32)
01143        md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2);
01144       else if (pic)
01145        /* ...and the rest of the move-opcode for pre-v32 PIC.  */
01146        md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2);
01147     }
01148 }
01149 
01150 /* Allocate space for the first piece of an insn, and mark it as the
01151    start of the insn for debug-format use.  */
01152 
01153 static char *
01154 cris_insn_first_word_frag (void)
01155 {
01156   char *insnp = frag_more (2);
01157 
01158   /* We need to mark the start of the insn by passing dwarf2_emit_insn
01159      the offset from the current fragment position.  This must be done
01160      after the first fragment is created but before any other fragments
01161      (fixed or varying) are created.  Note that the offset only
01162      corresponds to the "size" of the insn for a fixed-size,
01163      non-expanded insn.  */
01164   if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
01165     dwarf2_emit_insn (2);
01166 
01167   return insnp;
01168 }
01169 
01170 /* Port-specific assembler initialization.  */
01171 
01172 void
01173 md_begin (void)
01174 {
01175   const char *hashret = NULL;
01176   int i = 0;
01177 
01178   /* Set up a hash table for the instructions.  */
01179   op_hash = hash_new ();
01180   if (op_hash == NULL)
01181     as_fatal (_("Virtual memory exhausted"));
01182 
01183   /* Enable use of ".if ..asm.arch.cris.v32"
01184      and ".if ..asm.arch.cris.common_v10_v32" and a few others.  */
01185   symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section,
01186                                (cris_arch == arch_crisv32),
01187                                &zero_address_frag));
01188   symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section,
01189                                (cris_arch == arch_crisv10),
01190                                &zero_address_frag));
01191   symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32",
01192                                absolute_section,
01193                                (cris_arch == arch_cris_common_v10_v32),
01194                                &zero_address_frag));
01195   symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10",
01196                                absolute_section,
01197                                (cris_arch == arch_cris_any_v0_v10),
01198                                &zero_address_frag));
01199 
01200   while (cris_opcodes[i].name != NULL)
01201     {
01202       const char *name = cris_opcodes[i].name;
01203 
01204       if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version,
01205                                      cris_arch))
01206        {
01207          i++;
01208          continue;
01209        }
01210 
01211       /* Need to cast to get rid of "const".  FIXME: Fix hash_insert instead.  */
01212       hashret = hash_insert (op_hash, name, (void *) &cris_opcodes[i]);
01213 
01214       if (hashret != NULL && *hashret != '\0')
01215        as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name,
01216                 *hashret == 0 ? _("(unknown reason)") : hashret);
01217       do
01218        {
01219          if (cris_opcodes[i].match & cris_opcodes[i].lose)
01220            as_fatal (_("Buggy opcode: `%s' \"%s\"\n"), cris_opcodes[i].name,
01221                     cris_opcodes[i].args);
01222 
01223          ++i;
01224        }
01225       while (cris_opcodes[i].name != NULL
01226             && strcmp (cris_opcodes[i].name, name) == 0);
01227     }
01228 }
01229 
01230 /* Assemble a source line.  */
01231 
01232 void
01233 md_assemble (char *str)
01234 {
01235   struct cris_instruction output_instruction;
01236   struct cris_prefix prefix;
01237   char *opcodep;
01238   char *p;
01239 
01240   know (str);
01241 
01242   /* Do the low-level grunt - assemble to bits and split up into a prefix
01243      and ordinary insn.  */
01244   cris_process_instruction (str, &output_instruction, &prefix);
01245 
01246   /* Handle any prefixes to the instruction.  */
01247   switch (prefix.kind)
01248     {
01249     case PREFIX_NONE:
01250       break;
01251 
01252       /* When the expression is unknown for a BDAP, it can need 0, 2 or 4
01253         extra bytes, so we handle it separately.  */
01254     case PREFIX_BDAP_IMM:
01255       /* We only do it if the relocation is unspecified, i.e. not a PIC
01256         relocation.  */
01257       if (prefix.reloc == BFD_RELOC_NONE)
01258        {
01259          gen_bdap (prefix.base_reg_number, &prefix.expr);
01260          break;
01261        }
01262       /* Fall through.  */
01263     case PREFIX_BDAP:
01264     case PREFIX_BIAP:
01265     case PREFIX_DIP:
01266       opcodep = cris_insn_first_word_frag ();
01267 
01268       /* Output the prefix opcode.  */
01269       md_number_to_chars (opcodep, (long) prefix.opcode, 2);
01270 
01271       /* Having a specified reloc only happens for DIP and for BDAP with
01272         PIC operands, but it is ok to drop through here for the other
01273         prefixes as they can have no relocs specified.  */
01274       if (prefix.reloc != BFD_RELOC_NONE)
01275        {
01276          unsigned int relocsize
01277            = (prefix.kind == PREFIX_DIP
01278               ? 4 : cris_get_pic_reloc_size (prefix.reloc));
01279 
01280          p = frag_more (relocsize);
01281          fix_new_exp (frag_now, (p - frag_now->fr_literal), relocsize,
01282                      &prefix.expr, 0, prefix.reloc);
01283        }
01284       break;
01285 
01286     case PREFIX_PUSH:
01287       opcodep = cris_insn_first_word_frag ();
01288 
01289       /* Output the prefix opcode.  Being a "push", we add the negative
01290         size of the register to "sp".  */
01291       if (output_instruction.spec_reg != NULL)
01292        {
01293          /* Special register.  */
01294          opcodep[0] = -output_instruction.spec_reg->reg_size;
01295        }
01296       else
01297        {
01298          /* General register.  */
01299          opcodep[0] = -4;
01300        }
01301       opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8);
01302       break;
01303 
01304     default:
01305       BAD_CASE (prefix.kind);
01306     }
01307 
01308   /* If we only had a prefix insn, we're done.  */
01309   if (output_instruction.insn_type == CRIS_INSN_NONE)
01310     return;
01311 
01312   /* Done with the prefix.  Continue with the main instruction.  */
01313   if (prefix.kind == PREFIX_NONE)
01314     opcodep = cris_insn_first_word_frag ();
01315   else
01316     opcodep = frag_more (2);
01317 
01318   /* Output the instruction opcode.  */
01319   md_number_to_chars (opcodep, (long) (output_instruction.opcode), 2);
01320 
01321   /* Output the symbol-dependent instruction stuff.  */
01322   if (output_instruction.insn_type == CRIS_INSN_BRANCH)
01323     {
01324       segT to_seg = absolute_section;
01325       int is_undefined = 0;
01326       int length_code;
01327 
01328       if (output_instruction.expr.X_op != O_constant)
01329        {
01330          to_seg = S_GET_SEGMENT (output_instruction.expr.X_add_symbol);
01331 
01332          if (to_seg == undefined_section)
01333            is_undefined = 1;
01334        }
01335 
01336       if (to_seg == now_seg || is_undefined
01337          /* In CRISv32, there *is* a 32-bit absolute branch, so don't
01338             emit the 12-byte sequence for known symbols in other
01339             segments.  */
01340          || (cris_arch == arch_crisv32
01341              && output_instruction.opcode == BA_QUICK_OPCODE))
01342        {
01343          /* Handle complex expressions.  */
01344          valueT addvalue
01345            = (SIMPLE_EXPR (&output_instruction.expr)
01346               ? output_instruction.expr.X_add_number
01347               : 0);
01348          symbolS *sym
01349            = (SIMPLE_EXPR (&output_instruction.expr)
01350               ? output_instruction.expr.X_add_symbol
01351               : make_expr_symbol (&output_instruction.expr));
01352 
01353          /* If is_undefined, the expression may still become now_seg.
01354             That case is handled by md_estimate_size_before_relax.  */
01355          length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF;
01356 
01357          /* Make room for max twelve bytes of variable length for v32 mode
01358             or PIC, ten for v10 and older.  */
01359          frag_var (rs_machine_dependent,
01360                   (cris_arch == arch_crisv32
01361                    || cris_arch == arch_cris_common_v10_v32
01362                    || pic) ? 12 : 10, 0,
01363                   ENCODE_RELAX (cris_arch == arch_crisv32
01364                               ? (output_instruction.opcode
01365                                  == BA_QUICK_OPCODE
01366                                  ? STATE_ABS_BRANCH_V32
01367                                  : STATE_COND_BRANCH_V32)
01368                               : (cris_arch == arch_cris_common_v10_v32
01369                                  ? STATE_COND_BRANCH_COMMON
01370                                  : (pic ? STATE_COND_BRANCH_PIC
01371                                    : STATE_COND_BRANCH)),
01372                               length_code),
01373                   sym, addvalue, opcodep);
01374        }
01375       else
01376        {
01377          /* We have: to_seg != now_seg && to_seg != undefined_section.
01378             This means it is a branch to a known symbol in another
01379             section, perhaps an absolute address.  Emit a 32-bit branch.  */
01380          char *cond_jump
01381            = frag_more ((cris_arch == arch_crisv32
01382                        || cris_arch == arch_cris_common_v10_v32
01383                        || pic)
01384                       ? 12 : 10);
01385 
01386          gen_cond_branch_32 (opcodep, cond_jump, frag_now,
01387                            output_instruction.expr.X_add_symbol,
01388                            (symbolS *) NULL,
01389                            output_instruction.expr.X_add_number);
01390        }
01391     }
01392   else if (output_instruction.insn_type == CRIS_INSN_MUL
01393           && err_for_dangerous_mul_placement)
01394     /* Create a frag which which we track the location of the mul insn
01395        (in the last two bytes before the mul-frag).  */
01396     frag_variant (rs_machine_dependent, 0, 0,
01397                 ENCODE_RELAX (STATE_MUL, STATE_BYTE),
01398                 NULL, 0, opcodep);
01399   else
01400     {
01401       if (output_instruction.imm_oprnd_size > 0)
01402        {
01403          /* The instruction has an immediate operand.  */
01404          enum bfd_reloc_code_real reloc = BFD_RELOC_NONE;
01405 
01406          switch (output_instruction.imm_oprnd_size)
01407            {
01408              /* Any byte-size immediate constants are treated as
01409                word-size.  FIXME: Thus overflow check does not work
01410                correctly.  */
01411 
01412            case 2:
01413              /* Note that size-check for the explicit reloc has already
01414                been done when we get here.  */
01415              if (output_instruction.reloc != BFD_RELOC_NONE)
01416               reloc = output_instruction.reloc;
01417              else
01418               reloc = BFD_RELOC_16;
01419              break;
01420 
01421            case 4:
01422              /* Allow a relocation specified in the operand.  */
01423              if (output_instruction.reloc != BFD_RELOC_NONE)
01424               reloc = output_instruction.reloc;
01425              else
01426               reloc = BFD_RELOC_32;
01427              break;
01428 
01429            default:
01430              BAD_CASE (output_instruction.imm_oprnd_size);
01431            }
01432 
01433          p = frag_more (output_instruction.imm_oprnd_size);
01434          fix_new_exp (frag_now, (p - frag_now->fr_literal),
01435                      output_instruction.imm_oprnd_size,
01436                      &output_instruction.expr,
01437                      reloc == BFD_RELOC_32_PCREL
01438                      || reloc == BFD_RELOC_16_PCREL
01439                      || reloc == BFD_RELOC_8_PCREL, reloc);
01440        }
01441       else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET
01442               && output_instruction.expr.X_md != 0)
01443        {
01444          /* Handle complex expressions.  */
01445          valueT addvalue
01446            = (output_instruction.expr.X_op_symbol != NULL
01447               ? 0 : output_instruction.expr.X_add_number);
01448          symbolS *sym
01449            = (output_instruction.expr.X_op_symbol != NULL
01450               ? make_expr_symbol (&output_instruction.expr)
01451               : output_instruction.expr.X_add_symbol);
01452 
01453          /* This is a relaxing construct, so we need a frag_var rather
01454             than the fix_new_exp call below.  */
01455          frag_var (rs_machine_dependent,
01456                   4, 0,
01457                   ENCODE_RELAX (STATE_LAPC, STATE_UNDF),
01458                   sym, addvalue, opcodep);
01459        }
01460       else if (output_instruction.reloc != BFD_RELOC_NONE)
01461        {
01462          /* An immediate operand that has a relocation and needs to be
01463             processed further.  */
01464 
01465          /* It is important to use fix_new_exp here and everywhere else
01466             (and not fix_new), as fix_new_exp can handle "difference
01467             expressions" - where the expression contains a difference of
01468             two symbols in the same segment.  */
01469          fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2,
01470                      &output_instruction.expr,
01471                      output_instruction.reloc == BFD_RELOC_32_PCREL
01472                      || output_instruction.reloc == BFD_RELOC_16_PCREL
01473                      || output_instruction.reloc == BFD_RELOC_8_PCREL
01474                      || (output_instruction.reloc
01475                         == BFD_RELOC_CRIS_LAPCQ_OFFSET),
01476                      output_instruction.reloc);
01477        }
01478     }
01479 }
01480 
01481 /* Low level text-to-bits assembly.  */
01482 
01483 static void
01484 cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp,
01485                        struct cris_prefix *prefixp)
01486 {
01487   char *s;
01488   char modified_char = 0;
01489   const char *args;
01490   struct cris_opcode *instruction;
01491   char *operands;
01492   int match = 0;
01493   int mode;
01494   int regno;
01495   int size_bits;
01496 
01497   /* Reset these fields to a harmless state in case we need to return in
01498      error.  */
01499   prefixp->kind = PREFIX_NONE;
01500   prefixp->reloc = BFD_RELOC_NONE;
01501   out_insnp->insn_type = CRIS_INSN_NONE;
01502   out_insnp->imm_oprnd_size = 0;
01503 
01504   /* Find the end of the opcode mnemonic.  We assume (true in 2.9.1)
01505      that the caller has translated the opcode to lower-case, up to the
01506      first non-letter.  */
01507   for (operands = insn_text; ISLOWER (*operands); ++operands)
01508     ;
01509 
01510   /* Terminate the opcode after letters, but save the character there if
01511      it was of significance.  */
01512   switch (*operands)
01513     {
01514     case '\0':
01515       break;
01516 
01517     case '.':
01518       /* Put back the modified character later.  */
01519       modified_char = *operands;
01520       /* Fall through.  */
01521 
01522     case ' ':
01523       /* Consume the character after the mnemonic
01524         and replace it with '\0'.  */
01525       *operands++ = '\0';
01526       break;
01527 
01528     default:
01529       as_bad (_("Unknown opcode: `%s'"), insn_text);
01530       return;
01531     }
01532 
01533   /* Find the instruction.  */
01534   instruction = (struct cris_opcode *) hash_find (op_hash, insn_text);
01535   if (instruction == NULL)
01536     {
01537       as_bad (_("Unknown opcode: `%s'"), insn_text);
01538       return;
01539     }
01540 
01541   /* Put back the modified character.  */
01542   switch (modified_char)
01543     {
01544     case 0:
01545       break;
01546 
01547     default:
01548       *--operands = modified_char;
01549     }
01550 
01551   /* Try to match an opcode table slot.  */
01552   for (s = operands;;)
01553     {
01554       int imm_expr_found;
01555 
01556       /* Initialize *prefixp, perhaps after being modified for a
01557         "near match".  */
01558       prefixp->kind = PREFIX_NONE;
01559       prefixp->reloc = BFD_RELOC_NONE;
01560 
01561       /* Initialize *out_insnp.  */
01562       memset (out_insnp, 0, sizeof (*out_insnp));
01563       out_insnp->opcode = instruction->match;
01564       out_insnp->reloc = BFD_RELOC_NONE;
01565       out_insnp->insn_type = CRIS_INSN_NORMAL;
01566       out_insnp->imm_oprnd_size = 0;
01567 
01568       imm_expr_found = 0;
01569 
01570       /* Build the opcode, checking as we go to make sure that the
01571         operands match.  */
01572       for (args = instruction->args;; ++args)
01573        {
01574          switch (*args)
01575            {
01576            case '\0':
01577              /* If we've come to the end of arguments, we're done.  */
01578              if (*s == '\0')
01579               match = 1;
01580              break;
01581 
01582            case '!':
01583              /* Non-matcher character for disassembly.
01584                Ignore it here.  */
01585              continue;
01586 
01587            case '[':
01588            case ']':
01589            case ',':
01590            case ' ':
01591              /* These must match exactly.  */
01592              if (*s++ == *args)
01593               continue;
01594              break;
01595 
01596            case 'A':
01597              /* "ACR", case-insensitive.
01598                Handle a sometimes-mandatory dollar sign as register
01599                prefix.  */
01600              if (*s == REGISTER_PREFIX_CHAR)
01601               s++;
01602              else if (demand_register_prefix)
01603               break;
01604 
01605              if ((*s++ != 'a' && s[-1] != 'A')
01606                 || (*s++ != 'c' && s[-1] != 'C')
01607                 || (*s++ != 'r' && s[-1] != 'R'))
01608               break;
01609              continue;
01610 
01611            case 'B':
01612              /* This is not really an operand, but causes a "BDAP
01613                -size,SP" prefix to be output, for PUSH instructions.  */
01614              prefixp->kind = PREFIX_PUSH;
01615              continue;
01616 
01617            case 'b':
01618              /* This letter marks an operand that should not be matched
01619                in the assembler. It is a branch with 16-bit
01620                displacement.  The assembler will create them from the
01621                8-bit flavor when necessary.  The assembler does not
01622                support the [rN+] operand, as the [r15+] that is
01623                generated for 16-bit displacements.  */
01624              break;
01625 
01626            case 'c':
01627              /* A 5-bit unsigned immediate in bits <4:0>.  */
01628              if (! cris_get_expression (&s, &out_insnp->expr))
01629               break;
01630              else
01631               {
01632                 if (out_insnp->expr.X_op == O_constant
01633                     && (out_insnp->expr.X_add_number < 0
01634                        || out_insnp->expr.X_add_number > 31))
01635                   as_bad (_("Immediate value not in 5 bit unsigned range: %ld"),
01636                          out_insnp->expr.X_add_number);
01637 
01638                 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_5;
01639                 continue;
01640               }
01641 
01642            case 'C':
01643              /* A 4-bit unsigned immediate in bits <3:0>.  */
01644              if (! cris_get_expression (&s, &out_insnp->expr))
01645               break;
01646              else
01647               {
01648                 if (out_insnp->expr.X_op == O_constant
01649                     && (out_insnp->expr.X_add_number < 0
01650                        || out_insnp->expr.X_add_number > 15))
01651                   as_bad (_("Immediate value not in 4 bit unsigned range: %ld"),
01652                          out_insnp->expr.X_add_number);
01653 
01654                 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_4;
01655                 continue;
01656               }
01657 
01658              /* For 'd', check for an optional ".d" or ".D" at the
01659                  start of the operands, followed by a space character.  */
01660            case 'd':
01661              if (modified_char == '.' && *s == '.')
01662               {
01663                 if ((s[1] != 'd' && s[1] == 'D')
01664                     || ! ISSPACE (s[2]))
01665                   break;
01666                 s += 2;
01667                 continue;
01668               }
01669              continue;
01670 
01671            case 'D':
01672              /* General register in bits <15:12> and <3:0>.  */
01673              if (! get_gen_reg (&s, &regno))
01674               break;
01675              else
01676               {
01677                 out_insnp->opcode |= regno /* << 0 */;
01678                 out_insnp->opcode |= regno << 12;
01679                 continue;
01680               }
01681 
01682            case 'f':
01683              /* Flags from the condition code register.  */
01684              {
01685               int flags = 0;
01686 
01687               if (! get_flags (&s, &flags))
01688                 break;
01689 
01690               out_insnp->opcode |= ((flags & 0xf0) << 8) | (flags & 0xf);
01691               continue;
01692              }
01693 
01694            case 'i':
01695              /* A 6-bit signed immediate in bits <5:0>.  */
01696              if (! cris_get_expression (&s, &out_insnp->expr))
01697               break;
01698              else
01699               {
01700                 if (out_insnp->expr.X_op == O_constant
01701                     && (out_insnp->expr.X_add_number < -32
01702                        || out_insnp->expr.X_add_number > 31))
01703                   as_bad (_("Immediate value not in 6 bit range: %ld"),
01704                          out_insnp->expr.X_add_number);
01705                 out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_6;
01706                 continue;
01707               }
01708 
01709            case 'I':
01710              /* A 6-bit unsigned immediate in bits <5:0>.  */
01711              if (! cris_get_expression (&s, &out_insnp->expr))
01712               break;
01713              else
01714               {
01715                 if (out_insnp->expr.X_op == O_constant
01716                     && (out_insnp->expr.X_add_number < 0
01717                        || out_insnp->expr.X_add_number > 63))
01718                   as_bad (_("Immediate value not in 6 bit unsigned range: %ld"),
01719                          out_insnp->expr.X_add_number);
01720                 out_insnp->reloc = BFD_RELOC_CRIS_UNSIGNED_6;
01721                 continue;
01722               }
01723 
01724            case 'M':
01725              /* A size modifier, B, W or D, to be put in a bit position
01726                suitable for CLEAR instructions (i.e. reflecting a zero
01727                register).  */
01728              if (! get_bwd_size_modifier (&s, &size_bits))
01729               break;
01730              else
01731               {
01732                 switch (size_bits)
01733                   {
01734                   case 0:
01735                     out_insnp->opcode |= 0 << 12;
01736                     break;
01737 
01738                   case 1:
01739                     out_insnp->opcode |= 4 << 12;
01740                     break;
01741 
01742                   case 2:
01743                     out_insnp->opcode |= 8 << 12;
01744                     break;
01745                   }
01746                 continue;
01747               }
01748 
01749            case 'm':
01750              /* A size modifier, B, W or D, to be put in bits <5:4>.  */
01751              if (modified_char != '.'
01752                 || ! get_bwd_size_modifier (&s, &size_bits))
01753               break;
01754              else
01755               {
01756                 out_insnp->opcode |= size_bits << 4;
01757                 continue;
01758               }
01759 
01760            case 'o':
01761              /* A branch expression.  */
01762              if (! cris_get_expression (&s, &out_insnp->expr))
01763               break;
01764              else
01765               {
01766                 out_insnp->insn_type = CRIS_INSN_BRANCH;
01767                 continue;
01768               }
01769 
01770            case 'Q':
01771              /* A 8-bit quick BDAP expression, "expr,R".  */
01772              if (! cris_get_expression (&s, &out_insnp->expr))
01773               break;
01774 
01775              if (*s != ',')
01776               break;
01777 
01778              s++;
01779 
01780              if (!get_gen_reg (&s, &regno))
01781               break;
01782 
01783              out_insnp->opcode |= regno << 12;
01784              out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8;
01785              continue;
01786              
01787            case 'O':
01788              /* A BDAP expression for any size, "expr,R".  */
01789              if (! cris_get_expression (&s, &prefixp->expr))
01790               break;
01791              else
01792               {
01793                 if (*s != ',')
01794                   break;
01795 
01796                 s++;
01797 
01798                 if (!get_gen_reg (&s, &prefixp->base_reg_number))
01799                   break;
01800 
01801                 /* Since 'O' is used with an explicit bdap, we have no
01802                    "real" instruction.  */
01803                 prefixp->kind = PREFIX_BDAP_IMM;
01804                 prefixp->opcode
01805                   = BDAP_QUICK_OPCODE | (prefixp->base_reg_number << 12);
01806 
01807                 out_insnp->insn_type = CRIS_INSN_NONE;
01808                 continue;
01809               }
01810 
01811            case 'P':
01812              /* Special register in bits <15:12>.  */
01813              if (! get_spec_reg (&s, &out_insnp->spec_reg))
01814               break;
01815              else
01816               {
01817                 /* Use of some special register names come with a
01818                    specific warning.      Note that we have no ".cpu type"
01819                    pseudo yet, so some of this is just unused
01820                    framework.  */
01821                 if (out_insnp->spec_reg->warning)
01822                   as_warn (out_insnp->spec_reg->warning);
01823                 else if (out_insnp->spec_reg->applicable_version
01824                         == cris_ver_warning)
01825                   /* Others have a generic warning.  */
01826                   as_warn (_("Unimplemented register `%s' specified"),
01827                           out_insnp->spec_reg->name);
01828 
01829                 out_insnp->opcode
01830                   |= out_insnp->spec_reg->number << 12;
01831                 continue;
01832               }
01833 
01834            case 'p':
01835              /* This character is used in the disassembler to
01836                recognize a prefix instruction to fold into the
01837                addressing mode for the next instruction.  It is
01838                ignored here.  */
01839              continue;
01840 
01841            case 'R':
01842              /* General register in bits <15:12>.  */
01843              if (! get_gen_reg (&s, &regno))
01844               break;
01845              else
01846               {
01847                 out_insnp->opcode |= regno << 12;
01848                 continue;
01849               }
01850 
01851            case 'r':
01852              /* General register in bits <3:0>.  */
01853              if (! get_gen_reg (&s, &regno))
01854               break;
01855              else
01856               {
01857                 out_insnp->opcode |= regno /* << 0 */;
01858                 continue;
01859               }
01860 
01861            case 'S':
01862              /* Source operand in bit <10> and a prefix; a 3-operand
01863                prefix.  */
01864              if (! get_3op_or_dip_prefix_op (&s, prefixp))
01865               break;
01866              else
01867               continue;
01868 
01869            case 's':
01870              /* Source operand in bits <10>, <3:0> and optionally a
01871                prefix; i.e. an indirect operand or an side-effect
01872                prefix (where valid).  */
01873              if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode,
01874                                               &regno,
01875                                               &imm_expr_found,
01876                                               &out_insnp->expr))
01877               break;
01878              else
01879               {
01880                 if (prefixp->kind != PREFIX_NONE)
01881                   {
01882                     /* A prefix, so it has the autoincrement bit
01883                       set.  */
01884                     out_insnp->opcode |= (AUTOINCR_BIT << 8);
01885                   }
01886                 else
01887                   {
01888                     /* No prefix.  The "mode" variable contains bits like
01889                       whether or not this is autoincrement mode.  */
01890                     out_insnp->opcode |= (mode << 10);
01891 
01892                     /* If there was a PIC reloc specifier, then it was
01893                       attached to the prefix.  Note that we can't check
01894                       that the reloc size matches, since we don't have
01895                       all the operands yet in all cases.  */
01896                     if (prefixp->reloc != BFD_RELOC_NONE)
01897                      out_insnp->reloc = prefixp->reloc;
01898                   }
01899 
01900                 out_insnp->opcode |= regno /* << 0 */ ;
01901                 continue;
01902               }
01903 
01904            case 'N':
01905            case 'Y':
01906              /* Like 's', but immediate operand only.  Also does not
01907                modify insn.  There are no insns where a PIC reloc
01908                specifier makes sense.  */
01909              if (cris_get_expression (&s, &out_insnp->expr))
01910               {
01911                 imm_expr_found = 1;
01912                 continue;
01913               }
01914              break;
01915 
01916            case 'n':
01917              /* Like 'N', but PC-relative to the start of the insn.
01918                There might be a :PLT to request a PLT entry.  */
01919              if (cris_get_expression (&s, &out_insnp->expr))
01920               {
01921                 imm_expr_found = 1;
01922                 out_insnp->reloc = BFD_RELOC_32_PCREL;
01923 
01924                 /* We have to adjust the expression, because that
01925                    relocation is to the location *after* the
01926                    relocation.  So add 2 for the insn and 4 for the
01927                    relocation.  */
01928                 out_insnp->expr.X_add_number += 6;
01929 
01930                 if (pic && *s == PIC_SUFFIX_CHAR)
01931                   cris_get_pic_suffix (&s, &out_insnp->reloc,
01932                                     &out_insnp->expr);
01933 
01934                 continue;
01935               }
01936              break;
01937 
01938            case 'U':
01939              /* Maybe 'u', maybe 'n'.  Only for LAPC/LAPCQ.  */
01940              if (cris_get_expression (&s, &out_insnp->expr))
01941               {
01942                 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET;
01943 
01944                 /* Define 1 as relaxing.  */
01945                 out_insnp->expr.X_md = 1;
01946                 continue;
01947               }
01948              break;
01949 
01950            case 'u':
01951              /* Four PC-relative bits in <3:0> representing <4:1>:0 of
01952                an offset relative to the beginning of the current
01953                insn.  */
01954              if (cris_get_expression (&s, &out_insnp->expr))
01955               {
01956                 out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET;
01957 
01958                 /* Define 0 as non-relaxing.  */
01959                 out_insnp->expr.X_md = 0;
01960 
01961                 /* We have to adjust the expression, because that
01962                    relocation is to the location *after* the
01963                    insn.  So add 2 for the insn.  */
01964                 out_insnp->expr.X_add_number += 2;
01965                 continue;
01966               }
01967              break;
01968 
01969            case 'x':
01970              /* Rs.m in bits <15:12> and <5:4>.  */
01971              if (! get_gen_reg (&s, &regno)
01972                 || ! get_bwd_size_modifier (&s, &size_bits))
01973               break;
01974              else
01975               {
01976                 out_insnp->opcode |= (regno << 12) | (size_bits << 4);
01977                 continue;
01978               }
01979 
01980            case 'y':
01981              /* Source operand in bits <10>, <3:0> and optionally a
01982                prefix; i.e. an indirect operand or an side-effect
01983                prefix.
01984 
01985                The difference to 's' is that this does not allow an
01986                "immediate" expression.  */
01987              if (! get_autoinc_prefix_or_indir_op (&s, prefixp,
01988                                               &mode, &regno,
01989                                               &imm_expr_found,
01990                                               &out_insnp->expr)
01991                 || imm_expr_found)
01992               break;
01993              else
01994               {
01995                 if (prefixp->kind != PREFIX_NONE)
01996                   {
01997                     /* A prefix, and those matched here always have
01998                       side-effects (see 's' case).  */
01999                     out_insnp->opcode |= (AUTOINCR_BIT << 8);
02000                   }
02001                 else
02002                   {
02003                     /* No prefix.  The "mode" variable contains bits
02004                       like whether or not this is autoincrement
02005                       mode.  */
02006                     out_insnp->opcode |= (mode << 10);
02007                   }
02008 
02009                 out_insnp->opcode |= regno /* << 0 */;
02010                 continue;
02011               }
02012 
02013            case 'z':
02014              /* Size modifier (B or W) in bit <4>.  */
02015              if (! get_bw_size_modifier (&s, &size_bits))
02016               break;
02017              else
02018               {
02019                 out_insnp->opcode |= size_bits << 4;
02020                 continue;
02021               }
02022 
02023            case 'T':
02024              if (cris_arch == arch_crisv32
02025                 && get_sup_reg (&s, &regno))
02026               {
02027                 out_insnp->opcode |= regno << 12;
02028                 continue;
02029               }
02030              break;
02031 
02032            default:
02033              BAD_CASE (*args);
02034            }
02035 
02036          /* We get here when we fail a match above or we found a
02037             complete match.  Break out of this loop.  */
02038          break;
02039        }
02040 
02041       /* Was it a match or a miss?  */
02042       if (match == 0)
02043        {
02044          /* If it's just that the args don't match, maybe the next
02045             item in the table is the same opcode but with
02046             matching operands.  First skip any invalid ones.  */
02047          while (instruction[1].name != NULL
02048                && strcmp (instruction->name, instruction[1].name) == 0
02049                && ! cris_insn_ver_valid_for_arch (instruction[1]
02050                                               .applicable_version,
02051                                               cris_arch))
02052            ++instruction;
02053 
02054          if (instruction[1].name != NULL
02055              && strcmp (instruction->name, instruction[1].name) == 0
02056              && cris_insn_ver_valid_for_arch (instruction[1]
02057                                           .applicable_version,
02058                                           cris_arch))
02059            {
02060              /* Yep.  Restart and try that one instead.  */
02061              ++instruction;
02062              s = operands;
02063              continue;
02064            }
02065          else
02066            {
02067              /* We've come to the end of instructions with this
02068                opcode, so it must be an error.  */
02069              as_bad (_("Illegal operands"));
02070 
02071              /* As discard_rest_of_line, but without continuing to the
02072                next line.  */
02073              while (!is_end_of_line[(unsigned char) *input_line_pointer])
02074               input_line_pointer++;
02075              return;
02076            }
02077        }
02078       else
02079        {
02080          /* We have a match.  Check if there's anything more to do.  */
02081          if (imm_expr_found)
02082            {
02083              /* There was an immediate mode operand, so we must check
02084                that it has an appropriate size.  */
02085              switch (instruction->imm_oprnd_size)
02086               {
02087               default:
02088               case SIZE_NONE:
02089                 /* Shouldn't happen; this one does not have immediate
02090                    operands with different sizes.  */
02091                 BAD_CASE (instruction->imm_oprnd_size);
02092                 break;
02093 
02094               case SIZE_FIX_32:
02095                 out_insnp->imm_oprnd_size = 4;
02096                 break;
02097 
02098               case SIZE_SPEC_REG:
02099                 if (cris_arch == arch_crisv32)
02100                   /* All immediate loads of special registers are
02101                      32-bit on CRISv32.  */
02102                   out_insnp->imm_oprnd_size = 4;
02103                 else
02104                   switch (out_insnp->spec_reg->reg_size)
02105                     {
02106                     case 1:
02107                      if (out_insnp->expr.X_op == O_constant
02108                          && (out_insnp->expr.X_add_number < -128
02109                             || out_insnp->expr.X_add_number > 255))
02110                        as_bad (_("Immediate value not in 8 bit range: %ld"),
02111                               out_insnp->expr.X_add_number);
02112                      /* Fall through.  */
02113                     case 2:
02114                      /* FIXME:  We need an indicator in the instruction
02115                         table to pass on, to indicate if we need to check
02116                         overflow for a signed or unsigned number.  */
02117                      if (out_insnp->expr.X_op == O_constant
02118                          && (out_insnp->expr.X_add_number < -32768
02119                             || out_insnp->expr.X_add_number > 65535))
02120                        as_bad (_("Immediate value not in 16 bit range: %ld"),
02121                               out_insnp->expr.X_add_number);
02122                      out_insnp->imm_oprnd_size = 2;
02123                      break;
02124 
02125                     case 4:
02126                      out_insnp->imm_oprnd_size = 4;
02127                      break;
02128 
02129                     default:
02130                      BAD_CASE (out_insnp->spec_reg->reg_size);
02131                     }
02132                 break;
02133 
02134               case SIZE_FIELD:
02135               case SIZE_FIELD_SIGNED:
02136               case SIZE_FIELD_UNSIGNED:
02137                 switch (size_bits)
02138                   {
02139                     /* FIXME: Find way to pass un/signedness to
02140                       caller, and set reloc type instead, postponing
02141                       this check until cris_number_to_imm.  That
02142                       necessarily corrects the reloc type for the
02143                       byte case, maybe requiring further changes.  */
02144                   case 0:
02145                     if (out_insnp->expr.X_op == O_constant)
02146                      {
02147                        if (instruction->imm_oprnd_size == SIZE_FIELD
02148                            && (out_insnp->expr.X_add_number < -128
02149                               || out_insnp->expr.X_add_number > 255))
02150                          as_bad (_("Immediate value not in 8 bit range: %ld"),
02151                                 out_insnp->expr.X_add_number);
02152                        else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED
02153                            && (out_insnp->expr.X_add_number < -128
02154                               || out_insnp->expr.X_add_number > 127))
02155                          as_bad (_("Immediate value not in 8 bit signed range: %ld"),
02156                                 out_insnp->expr.X_add_number);
02157                        else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED
02158                                && (out_insnp->expr.X_add_number < 0
02159                                    || out_insnp->expr.X_add_number > 255))
02160                          as_bad (_("Immediate value not in 8 bit unsigned range: %ld"),
02161                                 out_insnp->expr.X_add_number);
02162                      }
02163 
02164                     /* Fall through.  */
02165                   case 1:
02166                     if (out_insnp->expr.X_op == O_constant)
02167                      {
02168                        if (instruction->imm_oprnd_size == SIZE_FIELD
02169                            && (out_insnp->expr.X_add_number < -32768
02170                               || out_insnp->expr.X_add_number > 65535))
02171                          as_bad (_("Immediate value not in 16 bit range: %ld"),
02172                                 out_insnp->expr.X_add_number);
02173                        else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED
02174                            && (out_insnp->expr.X_add_number < -32768
02175                               || out_insnp->expr.X_add_number > 32767))
02176                          as_bad (_("Immediate value not in 16 bit signed range: %ld"),
02177                                 out_insnp->expr.X_add_number);
02178                        else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED
02179                            && (out_insnp->expr.X_add_number < 0
02180                               || out_insnp->expr.X_add_number > 65535))
02181                          as_bad (_("Immediate value not in 16 bit unsigned range: %ld"),
02182                                 out_insnp->expr.X_add_number);
02183                      }
02184                     out_insnp->imm_oprnd_size = 2;
02185                     break;
02186 
02187                   case 2:
02188                     out_insnp->imm_oprnd_size = 4;
02189                     break;
02190 
02191                   default:
02192                     BAD_CASE (out_insnp->spec_reg->reg_size);
02193                   }
02194               }
02195 
02196              /* If there was a relocation specified for the immediate
02197                expression (i.e. it had a PIC modifier) check that the
02198                size of the PIC relocation matches the size specified by
02199                the opcode.  */
02200              if (out_insnp->reloc != BFD_RELOC_NONE
02201                 && (cris_get_pic_reloc_size (out_insnp->reloc)
02202                     != (unsigned int) out_insnp->imm_oprnd_size))
02203               as_bad (_("PIC relocation size does not match operand size"));
02204            }
02205          else if (instruction->op == cris_muls_op
02206                  || instruction->op == cris_mulu_op)
02207            out_insnp->insn_type = CRIS_INSN_MUL;
02208        }
02209       break;
02210     }
02211 }
02212 
02213 /* Get a B, W, or D size modifier from the string pointed out by *cPP,
02214    which must point to a '.' in front of the modifier.  On successful
02215    return, *cPP is advanced to the character following the size
02216    modifier, and is undefined otherwise.
02217 
02218    cPP        Pointer to pointer to string starting
02219               with the size modifier.
02220 
02221    size_bitsp Pointer to variable to contain the size bits on
02222               successful return.
02223 
02224    Return 1 iff a correct size modifier is found, else 0.  */
02225 
02226 static int
02227 get_bwd_size_modifier (char **cPP, int *size_bitsp)
02228 {
02229   if (**cPP != '.')
02230     return 0;
02231   else
02232     {
02233       /* Consume the '.'.  */
02234       (*cPP)++;
02235 
02236       switch (**cPP)
02237        {
02238        case 'B':
02239        case 'b':
02240          *size_bitsp = 0;
02241          break;
02242 
02243        case 'W':
02244        case 'w':
02245          *size_bitsp = 1;
02246          break;
02247 
02248        case 'D':
02249        case 'd':
02250          *size_bitsp = 2;
02251          break;
02252 
02253        default:
02254          return 0;
02255        }
02256 
02257       /* Consume the size letter.  */
02258       (*cPP)++;
02259       return 1;
02260     }
02261 }
02262 
02263 /* Get a B or W size modifier from the string pointed out by *cPP,
02264    which must point to a '.' in front of the modifier.  On successful
02265    return, *cPP is advanced to the character following the size
02266    modifier, and is undefined otherwise.
02267 
02268    cPP        Pointer to pointer to string starting
02269               with the size modifier.
02270 
02271    size_bitsp Pointer to variable to contain the size bits on
02272               successful return.
02273 
02274    Return 1 iff a correct size modifier is found, else 0.  */
02275 
02276 static int
02277 get_bw_size_modifier (char **cPP, int *size_bitsp)
02278 {
02279   if (**cPP != '.')
02280     return 0;
02281   else
02282     {
02283       /* Consume the '.'.  */
02284       (*cPP)++;
02285 
02286       switch (**cPP)
02287        {
02288        case 'B':
02289        case 'b':
02290          *size_bitsp = 0;
02291          break;
02292 
02293        case 'W':
02294        case 'w':
02295          *size_bitsp = 1;
02296          break;
02297 
02298        default:
02299          return 0;
02300        }
02301 
02302       /* Consume the size letter.  */
02303       (*cPP)++;
02304       return 1;
02305     }
02306 }
02307 
02308 /* Get a general register from the string pointed out by *cPP.  The
02309    variable *cPP is advanced to the character following the general
02310    register name on a successful return, and has its initial position
02311    otherwise.
02312 
02313    cPP     Pointer to pointer to string, beginning with a general
02314            register name.
02315 
02316    regnop   Pointer to int containing the register number.
02317 
02318    Return 1 iff a correct general register designator is found,
02319            else 0.  */
02320 
02321 static int
02322 get_gen_reg (char **cPP, int *regnop)
02323 {
02324   char *oldp;
02325   oldp = *cPP;
02326 
02327   /* Handle a sometimes-mandatory dollar sign as register prefix.  */
02328   if (**cPP == REGISTER_PREFIX_CHAR)
02329     (*cPP)++;
02330   else if (demand_register_prefix)
02331     return 0;
02332 
02333   switch (**cPP)
02334     {
02335     case 'P':
02336     case 'p':
02337       /* "P" as in "PC"?  Consume the "P".  */
02338       (*cPP)++;
02339 
02340       if ((**cPP == 'C' || **cPP == 'c')
02341          && ! ISALNUM ((*cPP)[1])
02342          /* Here's a little twist: For v32 and the compatibility mode,
02343             we only recognize PC as a register number if there's '+]'
02344             after.  We don't consume that, but the presence can only be
02345             valid after a register in a post-increment context, which
02346             is also the only valid context for PC as a register for
02347             v32.  Not that it's used very often, but saying "MOVE.D
02348             [PC+],R5" should remain valid.  It's not supported for
02349             jump-type insns or other insns with no [Rn+] mode, though.  */
02350          && ((cris_arch != arch_crisv32
02351               && cris_arch != arch_cris_common_v10_v32)
02352              || ((*cPP)[1] == '+' && (*cPP)[2] == ']')))
02353        {
02354          /* It's "PC": consume the "c" and we're done.  */
02355          (*cPP)++;
02356          *regnop = REG_PC;
02357          return 1;
02358        }
02359       break;
02360 
02361       /* Like with PC, we recognize ACR, but only if it's *not* followed
02362         by '+', and only for v32.  */
02363     case 'A':
02364     case 'a':
02365       if (cris_arch != arch_crisv32
02366          || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C')
02367          || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R')
02368          || ISALNUM ((*cPP)[3])
02369          || (*cPP)[3] == '+')
02370        break;
02371       (*cPP) += 3;
02372       *regnop = 15;
02373       return 1;
02374 
02375     case 'R':
02376     case 'r':
02377       /* Hopefully r[0-9] or r1[0-5].  Consume 'R' or 'r'.  */
02378       (*cPP)++;
02379 
02380       if (ISDIGIT (**cPP))
02381        {
02382          /* It's r[0-9].  Consume and check the next digit.  */
02383          *regnop = **cPP - '0';
02384          (*cPP)++;
02385 
02386          if (! ISALNUM (**cPP))
02387            {
02388              /* No more digits, we're done.  */
02389              return 1;
02390            }
02391          else
02392            {
02393              /* One more digit.  Consume and add.  */
02394              *regnop = *regnop * 10 + (**cPP - '0');
02395 
02396              /* We need to check for a valid register number; Rn,
02397                0 <= n <= MAX_REG.  */
02398              if (*regnop <= MAX_REG)
02399               {
02400                 /* Consume second digit.  */
02401                 (*cPP)++;
02402                 return 1;
02403               }
02404            }
02405        }
02406       break;
02407 
02408     case 'S':
02409     case 's':
02410       /* "S" as in "SP"?  Consume the "S".  */
02411       (*cPP)++;
02412       if (**cPP == 'P' || **cPP == 'p')
02413        {
02414          /* It's "SP": consume the "p" and we're done.  */
02415          (*cPP)++;
02416          *regnop = REG_SP;
02417          return 1;
02418        }
02419       break;
02420 
02421     default:
02422       /* Just here to silence compilation warnings.  */
02423       ;
02424     }
02425 
02426   /* We get here if we fail.  Restore the pointer.  */
02427   *cPP = oldp;
02428   return 0;
02429 }
02430 
02431 /* Get a special register from the string pointed out by *cPP. The
02432    variable *cPP is advanced to the character following the special
02433    register name if one is found, and retains its original position
02434    otherwise.
02435 
02436    cPP     Pointer to pointer to string starting with a special register
02437            name.
02438 
02439    sregpp   Pointer to Pointer to struct spec_reg, where a pointer to the
02440            register description will be stored.
02441 
02442    Return 1 iff a correct special register name is found.  */
02443 
02444 static int
02445 get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp)
02446 {
02447   char *s1;
02448   const char *s2;
02449   char *name_begin = *cPP;
02450 
02451   const struct cris_spec_reg *sregp;
02452 
02453   /* Handle a sometimes-mandatory dollar sign as register prefix.  */
02454   if (*name_begin == REGISTER_PREFIX_CHAR)
02455     name_begin++;
02456   else if (demand_register_prefix)
02457     return 0;
02458 
02459   /* Loop over all special registers.  */
02460   for (sregp = cris_spec_regs; sregp->name != NULL; sregp++)
02461     {
02462       /* Start over from beginning of the supposed name.  */
02463       s1 = name_begin;
02464       s2 = sregp->name;
02465 
02466       while (*s2 != '\0' && TOLOWER (*s1) == *s2)
02467        {
02468          s1++;
02469          s2++;
02470        }
02471 
02472       /* For a match, we must have consumed the name in the table, and we
02473         must be outside what could be part of a name.   Assume here that a
02474         test for alphanumerics is sufficient for a name test.  */
02475       if (*s2 == 0 && ! ISALNUM (*s1)
02476          && cris_insn_ver_valid_for_arch (sregp->applicable_version,
02477                                       cris_arch))
02478        {
02479          /* We have a match.  Update the pointer and be done.  */
02480          *cPP = s1;
02481          *sregpp = sregp;
02482          return 1;
02483        }
02484     }
02485 
02486   /* If we got here, we did not find any name.  */
02487   return 0;
02488 }
02489 
02490 /* Get a support register from the string pointed out by *cPP. The
02491    variable *cPP is advanced to the character following the support-
02492    register name if one is found, and retains its original position
02493    otherwise.
02494 
02495    cPP     Pointer to pointer to string starting with a support-register
02496            name.
02497 
02498    sregpp   Pointer to int containing the register number.
02499 
02500    Return 1 iff a correct support-register name is found.  */
02501 
02502 static int
02503 get_sup_reg (char **cPP, int *regnop)
02504 {
02505   char *s1;
02506   const char *s2;
02507   char *name_begin = *cPP;
02508 
02509   const struct cris_support_reg *sregp;
02510 
02511   /* Handle a sometimes-mandatory dollar sign as register prefix.  */
02512   if (*name_begin == REGISTER_PREFIX_CHAR)
02513     name_begin++;
02514   else if (demand_register_prefix)
02515     return 0;
02516 
02517   /* Loop over all support-registers.  */
02518   for (sregp = cris_support_regs; sregp->name != NULL; sregp++)
02519     {
02520       /* Start over from beginning of the supposed name.  */
02521       s1 = name_begin;
02522       s2 = sregp->name;
02523 
02524       while (*s2 != '\0' && TOLOWER (*s1) == *s2)
02525        {
02526          s1++;
02527          s2++;
02528        }
02529 
02530       /* For a match, we must have consumed the name in the table, and we
02531         must be outside what could be part of a name.   Assume here that a
02532         test for alphanumerics is sufficient for a name test.  */
02533       if (*s2 == 0 && ! ISALNUM (*s1))
02534        {
02535          /* We have a match.  Update the pointer and be done.  */
02536          *cPP = s1;
02537          *regnop = sregp->number;
02538          return 1;
02539        }
02540     }
02541 
02542   /* If we got here, we did not find any name.  */
02543   return 0;
02544 }
02545 
02546 /* Get an unprefixed or side-effect-prefix operand from the string pointed
02547    out by *cPP.  The pointer *cPP is advanced to the character following
02548    the indirect operand if we have success, else it contains an undefined
02549    value.
02550 
02551    cPP         Pointer to pointer to string beginning with the first
02552                character of the supposed operand.
02553 
02554    prefixp     Pointer to structure containing an optional instruction
02555                prefix.
02556 
02557    is_autoincp        Pointer to int indicating the indirect or autoincrement
02558                bits.
02559 
02560    src_regnop  Pointer to int containing the source register number in
02561                the instruction.
02562 
02563    imm_foundp  Pointer to an int indicating if an immediate expression
02564                is found.
02565 
02566    imm_exprP   Pointer to a structure containing an immediate
02567                expression, if success and if *imm_foundp is nonzero.
02568 
02569    Return 1 iff a correct indirect operand is found.  */
02570 
02571 static int
02572 get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp,
02573                             int *is_autoincp, int *src_regnop,
02574                             int *imm_foundp, expressionS *imm_exprP)
02575 {
02576   /* Assume there was no immediate mode expression.  */
02577   *imm_foundp = 0;
02578 
02579   if (**cPP == '[')
02580     {
02581       /* So this operand is one of:
02582         Indirect: [rN]
02583         Autoincrement: [rN+]
02584         Indexed with assign: [rN=rM+rO.S]
02585         Offset with assign: [rN=rM+I], [rN=rM+[rO].s], [rN=rM+[rO+].s]
02586 
02587         Either way, consume the '['.  */
02588       (*cPP)++;
02589 
02590       /* Get the rN register.  */
02591       if (! get_gen_reg (cPP, src_regnop))
02592        /* If there was no register, then this cannot match.  */
02593        return 0;
02594       else
02595        {
02596          /* We got the register, now check the next character.  */
02597          switch (**cPP)
02598            {
02599            case ']':
02600              /* Indirect mode.  We're done here.  */
02601              prefixp->kind = PREFIX_NONE;
02602              *is_autoincp = 0;
02603              break;
02604 
02605            case '+':
02606              /* This must be an auto-increment mode, if there's a
02607                match.  */
02608              prefixp->kind = PREFIX_NONE;
02609              *is_autoincp = 1;
02610 
02611              /* We consume this character and break out to check the
02612                closing ']'.  */
02613              (*cPP)++;
02614              break;
02615 
02616            case '=':
02617              /* This must be indexed with assign, or offset with assign
02618                to match.  Not supported for crisv32 or in
02619                compatibility mode.  */
02620              if (cris_arch == arch_crisv32
02621                 || cris_arch == arch_cris_common_v10_v32)
02622               return 0;
02623 
02624              (*cPP)++;
02625 
02626              /* Either way, the next thing must be a register.  */
02627              if (! get_gen_reg (cPP, &prefixp->base_reg_number))
02628               /* No register, no match.  */
02629               return 0;
02630              else
02631               {
02632                 /* We've consumed "[rN=rM", so we must be looking at
02633                    "+rO.s]" or "+I]", or "-I]", or "+[rO].s]" or
02634                    "+[rO+].s]".  */
02635                 if (**cPP == '+')
02636                   {
02637                     int index_reg_number;
02638                     (*cPP)++;
02639 
02640                     if (**cPP == '[')
02641                      {
02642                        int size_bits;
02643                        /* This must be [rx=ry+[rz].s] or
02644                           [rx=ry+[rz+].s] or no match.  We must be
02645                           looking at rz after consuming the '['.  */
02646                        (*cPP)++;
02647 
02648                        if (!get_gen_reg (cPP, &index_reg_number))
02649                          return 0;
02650 
02651                        prefixp->kind = PREFIX_BDAP;
02652                        prefixp->opcode
02653                          = (BDAP_INDIR_OPCODE
02654                             + (prefixp->base_reg_number << 12)
02655                             + index_reg_number);
02656 
02657                        if (**cPP == '+')
02658                          {
02659                            /* We've seen "[rx=ry+[rz+" here, so now we
02660                              know that there must be "].s]" left to
02661                              check.  */
02662                            (*cPP)++;
02663                            prefixp->opcode |= AUTOINCR_BIT << 8;
02664                          }
02665 
02666                        /* If it wasn't autoincrement, we don't need to
02667                           add anything.  */
02668 
02669                        /* Check the next-to-last ']'.  */
02670                        if (**cPP != ']')
02671                          return 0;
02672 
02673                        (*cPP)++;
02674 
02675                        /* Check the ".s" modifier.  */
02676                        if (! get_bwd_size_modifier (cPP, &size_bits))
02677                          return 0;
02678 
02679                        prefixp->opcode |= size_bits << 4;
02680 
02681                        /* Now we got [rx=ry+[rz+].s or [rx=ry+[rz].s.
02682                           We break out to check the final ']'.  */
02683                        break;
02684                      }
02685                     /* It wasn't an indirection.  Check if it's a
02686                       register.  */
02687                     else if (get_gen_reg (cPP, &index_reg_number))
02688                      {
02689                        int size_bits;
02690 
02691                        /* Indexed with assign mode: "[rN+rM.S]".  */
02692                        prefixp->kind = PREFIX_BIAP;
02693                        prefixp->opcode
02694                          = (BIAP_OPCODE + (index_reg_number << 12)
02695                             + prefixp->base_reg_number /* << 0 */);
02696 
02697                        if (! get_bwd_size_modifier (cPP, &size_bits))
02698                          /* Size missing, this isn't a match.  */
02699                          return 0;
02700                        else
02701                          {
02702                            /* Size found, break out to check the
02703                              final ']'.  */
02704                            prefixp->opcode |= size_bits << 4;
02705                            break;
02706                          }
02707                      }
02708                     /* Not a register.  Then this must be "[rN+I]".  */
02709                     else if (cris_get_expression (cPP, &prefixp->expr))
02710                      {
02711                        /* We've got offset with assign mode.  Fill
02712                           in the blanks and break out to match the
02713                           final ']'.  */
02714                        prefixp->kind = PREFIX_BDAP_IMM;
02715 
02716                        /* We tentatively put an opcode corresponding to
02717                           a 32-bit operand here, although it may be
02718                           relaxed when there's no PIC specifier for the
02719                           operand.  */
02720                        prefixp->opcode
02721                          = (BDAP_INDIR_OPCODE
02722                             | (prefixp->base_reg_number << 12)
02723                             | (AUTOINCR_BIT << 8)
02724                             | (2 << 4)
02725                             | REG_PC /* << 0 */);
02726 
02727                        /* This can have a PIC suffix, specifying reloc
02728                           type to use.  */
02729                        if (pic && **cPP == PIC_SUFFIX_CHAR)
02730                          {
02731                            unsigned int relocsize;
02732 
02733                            cris_get_pic_suffix (cPP, &prefixp->reloc,
02734                                              &prefixp->expr);
02735 
02736                            /* Tweak the size of the immediate operand
02737                              in the prefix opcode if it isn't what we
02738                              set.  */
02739                            relocsize
02740                             = cris_get_pic_reloc_size (prefixp->reloc);
02741                            if (relocsize != 4)
02742                             prefixp->opcode
02743                               = ((prefixp->opcode & ~(3 << 4))
02744                                  | ((relocsize >> 1) << 4));
02745                          }
02746                        break;
02747                      }
02748                     else
02749                      /* Neither register nor expression found, so
02750                         this can't be a match.  */
02751                      return 0;
02752                   }
02753                 /* Not "[rN+" but perhaps "[rN-"?  */
02754                 else if (**cPP == '-')
02755                   {
02756                     /* We must have an offset with assign mode.  */
02757                     if (! cris_get_expression (cPP, &prefixp->expr))
02758                      /* No expression, no match.  */
02759                      return 0;
02760                     else
02761                      {
02762                        /* We've got offset with assign mode.  Fill
02763                           in the blanks and break out to match the
02764                           final ']'.
02765 
02766                           Note that we don't allow a PIC suffix for an
02767                           operand with a minus sign.  */
02768                        prefixp->kind = PREFIX_BDAP_IMM;
02769                        break;
02770                      }
02771                   }
02772                 else
02773                   /* Neither '+' nor '-' after "[rN=rM".  Lose.  */
02774                   return 0;
02775               }
02776            default:
02777              /* Neither ']' nor '+' nor '=' after "[rN".  Lose.  */
02778              return 0;
02779            }
02780        }
02781 
02782       /* When we get here, we have a match and will just check the closing
02783         ']'.  We can still fail though.  */
02784       if (**cPP != ']')
02785        return 0;
02786       else
02787        {
02788          /* Don't forget to consume the final ']'.
02789             Then return in glory.  */
02790          (*cPP)++;
02791          return 1;
02792        }
02793     }
02794   /* No indirection.  Perhaps a constant?  */
02795   else if (cris_get_expression (cPP, imm_exprP))
02796     {
02797       /* Expression found, this is immediate mode.  */
02798       prefixp->kind = PREFIX_NONE;
02799       *is_autoincp = 1;
02800       *src_regnop = REG_PC;
02801       *imm_foundp = 1;
02802 
02803       /* This can have a PIC suffix, specifying reloc type to use.  The
02804         caller must check that the reloc size matches the operand size.  */
02805       if (pic && **cPP == PIC_SUFFIX_CHAR)
02806        cris_get_pic_suffix (cPP, &prefixp->reloc, imm_exprP);
02807 
02808       return 1;
02809     }
02810 
02811   /* No luck today.  */
02812   return 0;
02813 }
02814 
02815 /* This function gets an indirect operand in a three-address operand
02816    combination from the string pointed out by *cPP.  The pointer *cPP is
02817    advanced to the character following the indirect operand on success, or
02818    has an unspecified value on failure.
02819 
02820    cPP      Pointer to pointer to string beginning
02821             with the operand
02822 
02823    prefixp   Pointer to structure containing an
02824             instruction prefix
02825 
02826    Returns 1 iff a correct indirect operand is found.  */
02827 
02828 static int
02829 get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp)
02830 {
02831   int reg_number;
02832 
02833   if (**cPP != '[')
02834     /* We must have a '[' or it's a clean failure.  */
02835     return 0;
02836 
02837   /* Eat the first '['.  */
02838   (*cPP)++;
02839 
02840   if (**cPP == '[')
02841     {
02842       /* A second '[', so this must be double-indirect mode.  */
02843       (*cPP)++;
02844       prefixp->kind = PREFIX_DIP;
02845       prefixp->opcode = DIP_OPCODE;
02846 
02847       /* Get the register or fail entirely.  */
02848       if (! get_gen_reg (cPP, &reg_number))
02849        return 0;
02850       else
02851        {
02852          prefixp->opcode |= reg_number /* << 0 */ ;
02853          if (**cPP == '+')
02854            {
02855              /* Since we found a '+', this must be double-indirect
02856                autoincrement mode.  */
02857              (*cPP)++;
02858              prefixp->opcode |= AUTOINCR_BIT << 8;
02859            }
02860 
02861          /* There's nothing particular to do, if this was a
02862             double-indirect *without* autoincrement.  */
02863        }
02864 
02865       /* Check the first ']'.  The second one is checked at the end.  */
02866       if (**cPP != ']')
02867        return 0;
02868 
02869       /* Eat the first ']', so we'll be looking at a second ']'.  */
02870       (*cPP)++;
02871     }
02872   /* No second '['.  Then we should have a register here, making
02873      it "[rN".  */
02874   else if (get_gen_reg (cPP, &prefixp->base_reg_number))
02875     {
02876       /* This must be indexed or offset mode: "[rN+I]" or
02877         "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]".  */
02878       if (**cPP == '+')
02879        {
02880          int index_reg_number;
02881 
02882          (*cPP)++;
02883 
02884          if (**cPP == '[')
02885            {
02886              /* This is "[rx+["...  Expect a register next.  */
02887              int size_bits;
02888              (*cPP)++;
02889 
02890              if (!get_gen_reg (cPP, &index_reg_number))
02891               return 0;
02892 
02893              prefixp->kind = PREFIX_BDAP;
02894              prefixp->opcode
02895               = (BDAP_INDIR_OPCODE
02896                  + (prefixp->base_reg_number << 12)
02897                  + index_reg_number);
02898 
02899              /* We've seen "[rx+[ry", so check if this is
02900                autoincrement.  */
02901              if (**cPP == '+')
02902               {
02903                 /* Yep, now at "[rx+[ry+".  */
02904                 (*cPP)++;
02905                 prefixp->opcode |= AUTOINCR_BIT << 8;
02906               }
02907              /* If it wasn't autoincrement, we don't need to
02908                add anything.  */
02909 
02910              /* Check a first closing ']': "[rx+[ry]" or
02911                "[rx+[ry+]".  */
02912              if (**cPP != ']')
02913               return 0;
02914              (*cPP)++;
02915 
02916              /* Now expect a size modifier ".S".  */
02917              if (! get_bwd_size_modifier (cPP, &size_bits))
02918               return 0;
02919 
02920              prefixp->opcode |= size_bits << 4;
02921 
02922              /* Ok, all interesting stuff has been seen:
02923                "[rx+[ry+].S" or "[rx+[ry].S".  We only need to
02924                expect a final ']', which we'll do in a common
02925                closing session.  */
02926            }
02927          /* Seen "[rN+", but not a '[', so check if we have a
02928             register.  */
02929          else if (get_gen_reg (cPP, &index_reg_number))
02930            {
02931              /* This is indexed mode: "[rN+rM.S]" or
02932                "[rN+rM.S+]".  */
02933              int size_bits;
02934              prefixp->kind = PREFIX_BIAP;
02935              prefixp->opcode
02936               = (BIAP_OPCODE
02937                  | prefixp->base_reg_number /* << 0 */
02938                  | (index_reg_number << 12));
02939 
02940              /* Consume the ".S".  */
02941              if (! get_bwd_size_modifier (cPP, &size_bits))
02942               /* Missing size, so fail.  */
02943               return 0;
02944              else
02945               /* Size found.  Add that piece and drop down to
02946                  the common checking of the closing ']'.  */
02947               prefixp->opcode |= size_bits << 4;
02948            }
02949          /* Seen "[rN+", but not a '[' or a register, so then
02950             it must be a constant "I".
02951 
02952             As a quality of implementation improvement, we check for a
02953             closing ']', like in an erroneous "[rN+]".  If we don't,
02954             the expression parser will emit a confusing "bad
02955             expression" when it sees the ']', probably because it
02956             doesn't like seeing no expression.  */
02957          else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr))
02958            {
02959              /* Expression found, so fill in the bits of offset
02960                mode and drop down to check the closing ']'.  */
02961              prefixp->kind = PREFIX_BDAP_IMM;
02962 
02963              /* We tentatively put an opcode corresponding to a 32-bit
02964                operand here, although it may be relaxed when there's no
02965                PIC specifier for the operand.  */
02966              prefixp->opcode
02967               = (BDAP_INDIR_OPCODE
02968                  | (prefixp->base_reg_number << 12)
02969                  | (AUTOINCR_BIT << 8)
02970                  | (2 << 4)
02971                  | REG_PC /* << 0 */);
02972 
02973              /* This can have a PIC suffix, specifying reloc type to use.  */
02974              if (pic && **cPP == PIC_SUFFIX_CHAR)
02975               {
02976                 unsigned int relocsize;
02977 
02978                 cris_get_pic_suffix (cPP, &prefixp->reloc, &prefixp->expr);
02979 
02980                 /* Tweak the size of the immediate operand in the prefix
02981                    opcode if it isn't what we set.  */
02982                 relocsize = cris_get_pic_reloc_size (prefixp->reloc);
02983                 if (relocsize != 4)
02984                   prefixp->opcode
02985                     = ((prefixp->opcode & ~(3 << 4))
02986                       | ((relocsize >> 1) << 4));
02987               }
02988            }
02989          else
02990            /* Nothing valid here: lose.  */
02991            return 0;
02992        }
02993       /* Seen "[rN" but no '+', so check if it's a '-'.  */
02994       else if (**cPP == '-')
02995        {
02996          /* Yep, we must have offset mode.  */
02997          if (! cris_get_expression (cPP, &prefixp->expr))
02998            /* No expression, so we lose.  */
02999            return 0;
03000          else
03001            {
03002              /* Expression found to make this offset mode, so
03003                fill those bits and drop down to check the
03004                closing ']'.
03005 
03006                Note that we don't allow a PIC suffix for
03007                an operand with a minus sign like this.  */
03008              prefixp->kind = PREFIX_BDAP_IMM;
03009            }
03010        }
03011       else
03012        {
03013          /* We've seen "[rN", but not '+' or '-'; rather a ']'.
03014             Hmm.  Normally this is a simple indirect mode that we
03015             shouldn't match, but if we expect ']', then we have a
03016             zero offset, so it can be a three-address-operand,
03017             like "[rN],rO,rP", thus offset mode.
03018 
03019             Don't eat the ']', that will be done in the closing
03020             ceremony.  */
03021          prefixp->expr.X_op = O_constant;
03022          prefixp->expr.X_add_number = 0;
03023          prefixp->expr.X_add_symbol = NULL;
03024          prefixp->expr.X_op_symbol = NULL;
03025          prefixp->kind = PREFIX_BDAP_IMM;
03026        }
03027     }
03028   /* A '[', but no second '[', and no register.  Check if we
03029      have an expression, making this "[I]" for a double-indirect
03030      prefix.  */
03031   else if (cris_get_expression (cPP, &prefixp->expr))
03032     {
03033       /* Expression found, the so called absolute mode for a
03034         double-indirect prefix on PC.  */
03035       prefixp->kind = PREFIX_DIP;
03036       prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC;
03037       prefixp->reloc = BFD_RELOC_32;
03038     }
03039   else
03040     /* Neither '[' nor register nor expression.  We lose.  */
03041     return 0;
03042 
03043   /* We get here as a closing ceremony to a successful match.  We just
03044      need to check the closing ']'.  */
03045   if (**cPP != ']')
03046     /* Oops.  Close but no air-polluter.  */
03047     return 0;
03048 
03049   /* Don't forget to consume that ']', before returning in glory.  */
03050   (*cPP)++;
03051   return 1;
03052 }
03053 
03054 /* Get an expression from the string pointed out by *cPP.
03055    The pointer *cPP is advanced to the character following the expression
03056    on a success, or retains its original value otherwise.
03057 
03058    cPP    Pointer to pointer to string beginning with the expression.
03059 
03060    exprP   Pointer to structure containing the expression.
03061 
03062    Return 1 iff a correct expression is found.  */
03063 
03064 static int
03065 cris_get_expression (char **cPP, expressionS *exprP)
03066 {
03067   char *saved_input_line_pointer;
03068   segT exp;
03069 
03070   /* The "expression" function expects to find an expression at the
03071      global variable input_line_pointer, so we have to save it to give
03072      the impression that we don't fiddle with global variables.  */
03073   saved_input_line_pointer = input_line_pointer;
03074   input_line_pointer = *cPP;
03075 
03076   /* Avoid a common error, confusing addressing modes.  Beware that the
03077      call to expression below does not signal that error; it treats []
03078      as parentheses, unless #define NEED_INDEX_OPERATOR in which case it
03079      gives them other confusing semantics rather than plain outlawing
03080      them, which is what we want.  */
03081   if (*input_line_pointer == '[')
03082     {
03083       input_line_pointer = saved_input_line_pointer;
03084       return 0;
03085     }
03086 
03087   exp = expression (exprP);
03088   if (exprP->X_op == O_illegal || exprP->X_op == O_absent)
03089     {
03090       input_line_pointer = saved_input_line_pointer;
03091       return 0;
03092     }
03093 
03094   /* Everything seems to be fine, just restore the global
03095      input_line_pointer and say we're successful.  */
03096   *cPP = input_line_pointer;
03097   input_line_pointer = saved_input_line_pointer;
03098   return 1;
03099 }
03100 
03101 /* Get a sequence of flag characters from *spp.  The pointer *cPP is
03102    advanced to the character following the expression.  The flag
03103    characters are consecutive, no commas or spaces.
03104 
03105    cPP      Pointer to pointer to string beginning with the expression.
03106 
03107    flagp     Pointer to int to return the flags expression.
03108 
03109    Return 1 iff a correct flags expression is found.  */
03110 
03111 static int
03112 get_flags (char **cPP, int *flagsp)
03113 {
03114   for (;;)
03115     {
03116       switch (**cPP)
03117        {
03118        case 'd':
03119        case 'D':
03120          if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3,
03121                                          cris_arch))
03122            return 0;
03123          *flagsp |= 0x80;
03124          break;
03125 
03126        case 'm':
03127        case 'M':
03128          if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10,
03129                                          cris_arch))
03130            return 0;
03131          *flagsp |= 0x80;
03132          break;
03133 
03134        case 'e':
03135        case 'E':
03136          if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3,
03137                                          cris_arch))
03138            return 0;
03139          *flagsp |= 0x40;
03140          break;
03141 
03142        case 'b':
03143        case 'B':
03144          if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10,
03145                                          cris_arch))
03146            return 0;
03147          *flagsp |= 0x40;
03148          break;
03149 
03150        case 'p':
03151        case 'P':
03152          if (! cris_insn_ver_valid_for_arch (cris_ver_v32p,
03153                                          cris_arch))
03154            return 0;
03155          *flagsp |= 0x80;
03156          break;
03157 
03158        case 'u':
03159        case 'U':
03160          if (! cris_insn_ver_valid_for_arch (cris_ver_v32p,
03161                                          cris_arch))
03162            return 0;
03163          *flagsp |= 0x40;
03164          break;
03165 
03166        case 'i':
03167        case 'I':
03168          *flagsp |= 0x20;
03169          break;
03170 
03171        case 'x':
03172        case 'X':
03173          *flagsp |= 0x10;
03174          break;
03175 
03176        case 'n':
03177        case 'N':
03178          *flagsp |= 0x8;
03179          break;
03180 
03181        case 'z':
03182        case 'Z':
03183          *flagsp |= 0x4;
03184          break;
03185 
03186        case 'v':
03187        case 'V':
03188          *flagsp |= 0x2;
03189          break;
03190 
03191        case 'c':
03192        case 'C':
03193          *flagsp |= 1;
03194          break;
03195 
03196        default:
03197          /* We consider this successful if we stop at a comma or
03198             whitespace.  Anything else, and we consider it a failure.  */
03199          if (**cPP != ','
03200              && **cPP != 0
03201              && ! ISSPACE (**cPP))
03202            return 0;
03203          else
03204            return 1;
03205        }
03206 
03207       /* Don't forget to consume each flag character.  */
03208       (*cPP)++;
03209     }
03210 }
03211 
03212 /* Generate code and fixes for a BDAP prefix.
03213    For v32, this handles ADDOQ because thankfully the opcodes are the
03214    same.
03215 
03216    base_regno Int containing the base register number.
03217 
03218    exprP      Pointer to structure containing the offset expression.  */
03219 
03220 static void
03221 gen_bdap (int base_regno, expressionS *exprP)
03222 {
03223   unsigned int opcode;
03224   char *opcodep;
03225 
03226   /* Put out the prefix opcode; assume quick immediate mode at first.  */
03227   opcode = BDAP_QUICK_OPCODE | (base_regno << 12);
03228   opcodep = cris_insn_first_word_frag ();
03229   md_number_to_chars (opcodep, opcode, 2);
03230 
03231   if (exprP->X_op == O_constant)
03232     {
03233       /* We have an absolute expression that we know the size of right
03234         now.  */
03235       long int value;
03236       int size;
03237 
03238       value = exprP->X_add_number;
03239       if (value < -32768 || value > 32767)
03240        /* Outside range for a "word", make it a dword.  */
03241        size = 2;
03242       else
03243        /* Assume "word" size.  */
03244        size = 1;
03245 
03246       /* If this is a signed-byte value, we can fit it into the prefix
03247         insn itself.  */
03248       if (value >= -128 && value <= 127)
03249        opcodep[0] = value;
03250       else
03251        {
03252          /* This is a word or dword displacement, which will be put in a
03253             word or dword after the prefix.  */
03254          char *p;
03255 
03256          opcodep[0] = BDAP_PC_LOW + (size << 4);
03257          opcodep[1] &= 0xF0;
03258          opcodep[1] |= BDAP_INCR_HIGH;
03259          p = frag_more (1 << size);
03260          md_number_to_chars (p, value, 1 << size);
03261        }
03262     }
03263   else
03264     {
03265       /* Handle complex expressions.  */
03266       valueT addvalue
03267        = SIMPLE_EXPR (exprP) ? exprP->X_add_number : 0;
03268       symbolS *sym
03269        = (SIMPLE_EXPR (exprP)
03270           ? exprP->X_add_symbol : make_expr_symbol (exprP));
03271 
03272       /* The expression is not defined yet but may become absolute.  We
03273         make it a relocation to be relaxed.  */
03274       frag_var (rs_machine_dependent, 4, 0,
03275               ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF),
03276               sym, addvalue, opcodep);
03277     }
03278 }
03279 
03280 /* Encode a branch displacement in the range -256..254 into the form used
03281    by CRIS conditional branch instructions.
03282 
03283    offset  The displacement value in bytes.  */
03284 
03285 static int
03286 branch_disp (int offset)
03287 {
03288   int disp;
03289 
03290   /* Adjust all short branch offsets here.  */
03291   if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32)
03292     offset += 2;
03293 
03294   disp = offset & 0xFE;
03295 
03296   if (offset < 0)
03297     disp |= 1;
03298 
03299   return disp;
03300 }
03301 
03302 /* Generate code and fixes for a 32-bit conditional branch instruction
03303    created by "extending" an existing 8-bit branch instruction.
03304 
03305    opcodep    Pointer to the word containing the original 8-bit branch
03306              instruction.
03307 
03308    writep     Pointer to "extension area" following the first instruction
03309              word.
03310 
03311    fragP      Pointer to the frag containing the instruction.
03312 
03313    add_symP,  Parts of the destination address expression.
03314    sub_symP,
03315    add_num.  */
03316 
03317 static void
03318 gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP,
03319                   symbolS *add_symP, symbolS *sub_symP, long int add_num)
03320 {
03321   int nop_opcode;
03322   int opc_offset;
03323   int branch_offset;
03324 
03325   if (cris_arch == arch_crisv32)
03326     {
03327       nop_opcode = NOP_OPCODE_V32;
03328       opc_offset = 10;
03329       branch_offset = -2 - 8;
03330     }
03331   else if (pic)
03332     {
03333       nop_opcode = NOP_OPCODE;
03334       opc_offset = 10;
03335       branch_offset = -2 - 8;
03336     }
03337   else
03338     {
03339       nop_opcode = NOP_OPCODE;
03340       opc_offset = 8;
03341       branch_offset = -2 - 6;
03342     }
03343 
03344   /* We should never get here for compatibility mode.  */
03345   if (cris_arch == arch_cris_common_v10_v32)
03346     as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n"));
03347 
03348   if (warn_for_branch_expansion)
03349     as_warn_where (fragP->fr_file, fragP->fr_line,
03350                  _("32-bit conditional branch generated"));
03351 
03352   /* Here, writep points to what will be opcodep + 2.  First, we change
03353      the actual branch in opcodep[0] and opcodep[1], so that in the
03354      final insn, it will look like:
03355        opcodep+10: Bcc .-6
03356 
03357      This means we don't have to worry about changing the opcode or
03358      messing with the delay-slot instruction.  So, we move it to last in
03359      the "extended" branch, and just change the displacement.  Admittedly,
03360      it's not the optimal extended construct, but we should get this
03361      rarely enough that it shouldn't matter.  */
03362 
03363   writep[opc_offset] = branch_disp (branch_offset);
03364   writep[opc_offset + 1] = opcodep[1];
03365 
03366   /* Then, we change the branch to an unconditional branch over the
03367      extended part, to the new location of the Bcc:
03368        opcodep:        BA .+10
03369        opcodep+2: NOP
03370 
03371      Note that these two writes are to currently different locations,
03372      merged later.  */
03373 
03374   md_number_to_chars (opcodep, BA_QUICK_OPCODE
03375                     + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)),
03376                     2);
03377   md_number_to_chars (writep, nop_opcode, 2);
03378 
03379   /* Then the extended thing, the 32-bit jump insn.
03380        opcodep+4: JUMP [PC+]
03381      or, in the PIC case,
03382        opcodep+4: MOVE [PC=PC+N],P0.  */
03383 
03384   md_number_to_chars (writep + 2,
03385                     cris_arch == arch_crisv32
03386                     ? BA_DWORD_OPCODE
03387                     : (pic ? MOVE_PC_INCR_OPCODE_PREFIX
03388                       : JUMP_PC_INCR_OPCODE), 2);
03389 
03390   /* We have to fill in the actual value too.
03391        opcodep+6: .DWORD
03392      This is most probably an expression, but we can cope with an absolute
03393      value too.  FIXME: Testcase needed with and without pic.  */
03394 
03395   if (add_symP == NULL && sub_symP == NULL)
03396     {
03397       /* An absolute address.  */
03398       if (pic || cris_arch == arch_crisv32)
03399        fix_new (fragP, writep + 4 - fragP->fr_literal, 4,
03400                section_symbol (absolute_section),
03401                add_num
03402                + (cris_arch == arch_crisv32 ? 6 : 0),
03403                1, BFD_RELOC_32_PCREL);
03404       else
03405        md_number_to_chars (writep + 4, add_num, 4);
03406     }
03407   else
03408     {
03409       if (sub_symP != NULL)
03410        as_bad_where (fragP->fr_file, fragP->fr_line,
03411                     _("Complex expression not supported"));
03412 
03413       /* Not absolute, we have to make it a frag for later evaluation.  */
03414       fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP,
03415               add_num + (cris_arch == arch_crisv32 ? 6 : 0),
03416               pic || cris_arch == arch_crisv32 ? 1 : 0,
03417               pic || cris_arch == arch_crisv32
03418               ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
03419     }
03420 
03421   if (cris_arch == arch_crisv32)
03422     /* Follow it with a "NOP" for CRISv32.  */
03423     md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2);
03424   else if (pic)
03425     /* ...and the rest of the move-opcode for pre-v32 PIC.  */
03426     md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2);
03427 }
03428 
03429 /* Get the size of an immediate-reloc in bytes.  Only valid for PIC
03430    relocs.  */
03431 
03432 static unsigned int
03433 cris_get_pic_reloc_size (bfd_reloc_code_real_type reloc)
03434 {
03435   return reloc == BFD_RELOC_CRIS_16_GOTPLT || reloc == BFD_RELOC_CRIS_16_GOT
03436     ? 2 : 4;
03437 }
03438 
03439 /* Store a reloc type at *RELOCP corresponding to the PIC suffix at *CPP.
03440    Adjust *EXPRP with any addend found after the PIC suffix.  */
03441 
03442 static void
03443 cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp,
03444                    expressionS *exprP)
03445 {
03446   char *s = *cPP;
03447   unsigned int i;
03448   expressionS const_expr;
03449 
03450   const struct pic_suffixes_struct
03451   {
03452     const char *const suffix;
03453     unsigned int len;
03454     bfd_reloc_code_real_type reloc;
03455   } pic_suffixes[] =
03456     {
03457 #undef PICMAP
03458 #define PICMAP(s, r) {s, sizeof (s) - 1, r}
03459       /* Keep this in order with longest unambiguous prefix first.  */
03460       PICMAP ("GOTPLT16", BFD_RELOC_CRIS_16_GOTPLT),
03461       PICMAP ("GOTPLT", BFD_RELOC_CRIS_32_GOTPLT),
03462       PICMAP ("PLTG", BFD_RELOC_CRIS_32_PLT_GOTREL),
03463       PICMAP ("PLT", BFD_RELOC_CRIS_32_PLT_PCREL),
03464       PICMAP ("GOTOFF", BFD_RELOC_CRIS_32_GOTREL),
03465       PICMAP ("GOT16", BFD_RELOC_CRIS_16_GOT),
03466       PICMAP ("GOT", BFD_RELOC_CRIS_32_GOT)
03467     };
03468 
03469   /* We've already seen the ':', so consume it.  */
03470   s++;
03471 
03472   for (i = 0; i < sizeof (pic_suffixes)/sizeof (pic_suffixes[0]); i++)
03473     {
03474       if (strncmp (s, pic_suffixes[i].suffix, pic_suffixes[i].len) == 0
03475          && ! is_part_of_name (s[pic_suffixes[i].len]))
03476        {
03477          /* We have a match.  Consume the suffix and set the relocation
03478             type.   */
03479          s += pic_suffixes[i].len;
03480 
03481          /* There can be a constant term appended.  If so, we will add it
03482             to *EXPRP.  */
03483          if (*s == '+' || *s == '-')
03484            {
03485              if (! cris_get_expression (&s, &const_expr))
03486               /* There was some kind of syntax error.  Bail out.  */
03487               break;
03488 
03489              /* Allow complex expressions as the constant part.  It still
03490                has to be an assembly-time constant or there will be an
03491                error emitting the reloc.  This makes the PIC qualifiers
03492                idempotent; foo:GOTOFF+32 == foo+32:GOTOFF.  The former we
03493                recognize here; the latter is parsed in the incoming
03494                expression.  */
03495              exprP->X_add_symbol = make_expr_symbol (exprP);
03496              exprP->X_op = O_add;
03497              exprP->X_add_number = 0;
03498              exprP->X_op_symbol = make_expr_symbol (&const_expr);
03499            }
03500 
03501          *relocp = pic_suffixes[i].reloc;
03502          *cPP = s;
03503          return;
03504        }
03505     }
03506 
03507   /* No match.  Don't consume anything; fall back and there will be a
03508      syntax error.  */
03509 }
03510 
03511 /* This *could* have been:
03512 
03513    Turn a string in input_line_pointer into a floating point constant
03514    of type TYPE, and store the appropriate bytes in *LITP.  The number
03515    of LITTLENUMS emitted is stored in *SIZEP.
03516 
03517    type         A character from FLTCHARS that describes what kind of
03518          floating-point number is wanted.
03519 
03520    litp         A pointer to an array that the result should be stored in.
03521 
03522    sizep  A pointer to an integer where the size of the result is stored.
03523 
03524    But we don't support floating point constants in assembly code *at all*,
03525    since it's suboptimal and just opens up bug opportunities.  GCC emits
03526    the bit patterns as hex.  All we could do here is to emit what GCC
03527    would have done in the first place.    *Nobody* writes floating-point
03528    code as assembly code, but if they do, they should be able enough to
03529    find out the correct bit patterns and use them.  */
03530 
03531 char *
03532 md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED,
03533         int *sizep ATTRIBUTE_UNUSED)
03534 {
03535   /* FIXME:  Is this function mentioned in the internals.texi manual?  If
03536      not, add it.  */
03537   return  _("Bad call to md_atof () - floating point formats are not supported");
03538 }
03539 
03540 /* Turn a number as a fixS * into a series of bytes that represents the
03541    number on the target machine.  The purpose of this procedure is the
03542    same as that of md_number_to_chars but this procedure is supposed to
03543    handle general bit field fixes and machine-dependent fixups.
03544 
03545    bufp              Pointer to an array where the result should be stored.
03546 
03547    val       The value to store.
03548 
03549    n         The number of bytes in "val" that should be stored.
03550 
03551    fixP             The fix to be applied to the bit field starting at bufp.
03552 
03553    seg       The segment containing this number.  */
03554 
03555 static void
03556 cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg)
03557 {
03558   segT sym_seg;
03559 
03560   know (n <= 4);
03561   know (fixP);
03562 
03563   /* We put the relative "vma" for the other segment for inter-segment
03564      relocations in the object data to stay binary "compatible" (with an
03565      uninteresting old version) for the relocation.
03566      Maybe delete some day.  */
03567   if (fixP->fx_addsy
03568       && (sym_seg = S_GET_SEGMENT (fixP->fx_addsy)) != seg)
03569     val += sym_seg->vma;
03570 
03571   if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
03572     switch (fixP->fx_r_type)
03573       {
03574        /* These must be fully resolved when getting here.  */
03575       case BFD_RELOC_16_PCREL:
03576       case BFD_RELOC_8_PCREL:
03577        as_bad_where (fixP->fx_file, fixP->fx_line,
03578                     _("PC-relative relocation must be trivially resolved"));
03579       default:
03580        ;
03581       }
03582 
03583   /* Only do this for old-arch binaries.  */
03584   if (cris_arch != arch_cris_any_v0_v10
03585       && (fixP->fx_addsy != NULL || fixP->fx_pcrel))
03586     return;
03587 
03588   switch (fixP->fx_r_type)
03589     {
03590       /* Ditto here, we put the addend into the object code as
03591         well as the reloc addend.  Keep it that way for now, to simplify
03592         regression tests on the object file contents.   FIXME: Seems
03593         uninteresting now that we have a test suite.  */
03594 
03595     case BFD_RELOC_CRIS_16_GOT:
03596     case BFD_RELOC_CRIS_32_GOT:
03597     case BFD_RELOC_CRIS_32_GOTREL:
03598     case BFD_RELOC_CRIS_16_GOTPLT:
03599     case BFD_RELOC_CRIS_32_GOTPLT:
03600     case BFD_RELOC_CRIS_32_PLT_GOTREL:
03601     case BFD_RELOC_CRIS_32_PLT_PCREL:
03602       /* We don't want to put in any kind of non-zero bits in the data
03603         being relocated for these.  */
03604       break;
03605 
03606     case BFD_RELOC_32_PCREL:
03607       /* If this one isn't fully resolved, we don't want to put anything
03608         in the object.  */
03609       if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
03610        break;
03611 
03612       /* Fall through.  */
03613     case BFD_RELOC_32:
03614       /* No use having warnings here, since most hosts have a 32-bit type
03615         for "long" (which will probably change soon, now that I wrote
03616         this).  */
03617       bufp[3] = (val >> 24) & 0xFF;
03618       bufp[2] = (val >> 16) & 0xFF;
03619       bufp[1] = (val >> 8) & 0xFF;
03620       bufp[0] = val & 0xFF;
03621       break;
03622 
03623       /* FIXME: The 16 and 8-bit cases should have a way to check
03624         whether a signed or unsigned (or any signedness) number is
03625         accepted.  */
03626 
03627     case BFD_RELOC_16:
03628     case BFD_RELOC_16_PCREL:
03629       if (val > 0xffff || val < -32768)
03630        as_bad_where (fixP->fx_file, fixP->fx_line,
03631                     _("Value not in 16 bit range: %ld"), val);
03632       if (! fixP->fx_addsy)
03633        {
03634          bufp[1] = (val >> 8) & 0xFF;
03635          bufp[0] = val & 0xFF;
03636        }
03637       break;
03638 
03639     case BFD_RELOC_CRIS_SIGNED_16:
03640       if (val > 32767 || val < -32768)
03641        as_bad_where (fixP->fx_file, fixP->fx_line,
03642                     _("Value not in 16 bit signed range: %ld"), val);
03643       if (! fixP->fx_addsy)
03644        {
03645          bufp[1] = (val >> 8) & 0xFF;
03646          bufp[0] = val & 0xFF;
03647        }
03648       break;
03649 
03650     case BFD_RELOC_8:
03651     case BFD_RELOC_8_PCREL:
03652       if (val > 255 || val < -128)
03653        as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val);
03654       if (! fixP->fx_addsy)
03655        bufp[0] = val & 0xFF;
03656       break;
03657 
03658     case BFD_RELOC_CRIS_SIGNED_8:
03659       if (val > 127 || val < -128)
03660        as_bad_where (fixP->fx_file, fixP->fx_line,
03661                     _("Value not in 8 bit signed range: %ld"), val);
03662       if (! fixP->fx_addsy)
03663        bufp[0] = val & 0xFF;
03664       break;
03665 
03666     case BFD_RELOC_CRIS_LAPCQ_OFFSET:
03667       /* FIXME: Test-cases for out-of-range values.  Probably also need
03668         to use as_bad_where.  */
03669     case BFD_RELOC_CRIS_UNSIGNED_4:
03670       if (val > 15 || val < 0)
03671        as_bad_where (fixP->fx_file, fixP->fx_line,
03672                     _("Value not in 4 bit unsigned range: %ld"), val);
03673       if (! fixP->fx_addsy)
03674        bufp[0] |= val & 0x0F;
03675       break;
03676 
03677     case BFD_RELOC_CRIS_UNSIGNED_5:
03678       if (val > 31 || val < 0)
03679        as_bad_where (fixP->fx_file, fixP->fx_line,
03680                     _("Value not in 5 bit unsigned range: %ld"), val);
03681       if (! fixP->fx_addsy)
03682        bufp[0] |= val & 0x1F;
03683       break;
03684 
03685     case BFD_RELOC_CRIS_SIGNED_6:
03686       if (val > 31 || val < -32)
03687        as_bad_where (fixP->fx_file, fixP->fx_line,
03688                     _("Value not in 6 bit range: %ld"), val);
03689       if (! fixP->fx_addsy)
03690        bufp[0] |= val & 0x3F;
03691       break;
03692 
03693     case BFD_RELOC_CRIS_UNSIGNED_6:
03694       if (val > 63 || val < 0)
03695        as_bad_where (fixP->fx_file, fixP->fx_line,
03696                     _("Value not in 6 bit unsigned range: %ld"), val);
03697       if (! fixP->fx_addsy)
03698        bufp[0] |= val & 0x3F;
03699       break;
03700 
03701     case BFD_RELOC_CRIS_BDISP8:
03702       if (! fixP->fx_addsy)
03703        bufp[0] = branch_disp (val);
03704       break;
03705 
03706     case BFD_RELOC_NONE:
03707       /* May actually happen automatically.  For example at broken
03708         words, if the word turns out not to be broken.
03709         FIXME: When?  Which testcase?  */
03710       if (! fixP->fx_addsy)
03711        md_number_to_chars (bufp, val, n);
03712       break;
03713 
03714     case BFD_RELOC_VTABLE_INHERIT:
03715       /* This borrowed from tc-ppc.c on a whim.  */
03716       if (fixP->fx_addsy
03717          && !S_IS_DEFINED (fixP->fx_addsy)
03718          && !S_IS_WEAK (fixP->fx_addsy))
03719        S_SET_WEAK (fixP->fx_addsy);
03720       /* Fall through.  */
03721 
03722     case BFD_RELOC_VTABLE_ENTRY:
03723       fixP->fx_done = 0;
03724       break;
03725 
03726     default:
03727       BAD_CASE (fixP->fx_r_type);
03728     }
03729 }
03730 
03731 /* Processes machine-dependent command line options.  Called once for
03732    each option on the command line that the machine-independent part of
03733    GAS does not understand.  */
03734 
03735 int
03736 md_parse_option (int arg, char *argp ATTRIBUTE_UNUSED)
03737 {
03738   switch (arg)
03739     {
03740     case 'H':
03741     case 'h':
03742       printf (_("Please use --help to see usage and options for this assembler.\n"));
03743       md_show_usage (stdout);
03744       exit (EXIT_SUCCESS);
03745 
03746     case 'N':
03747       warn_for_branch_expansion = 1;
03748       break;
03749 
03750     case OPTION_NO_US:
03751       demand_register_prefix = TRUE;
03752 
03753       if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
03754        as_bad (_("--no-underscore is invalid with a.out format"));
03755       else
03756        symbols_have_leading_underscore = FALSE;
03757       break;
03758 
03759     case OPTION_US:
03760       demand_register_prefix = FALSE;
03761       symbols_have_leading_underscore = TRUE;
03762       break;
03763 
03764     case OPTION_PIC:
03765       pic = TRUE;
03766       if (cris_arch != arch_crisv32)
03767        md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
03768       else
03769        md_long_jump_size = crisv32_long_jump_size;
03770       break;
03771 
03772     case OPTION_ARCH:
03773       {
03774        char *str = argp;
03775        enum cris_archs argarch = cris_arch_from_string (&str);
03776 
03777        if (argarch == arch_cris_unknown)
03778            as_bad (_("invalid <arch> in --march=<arch>: %s"), argp);
03779        else
03780          cris_arch = argarch;
03781 
03782        if (argarch == arch_crisv32)
03783          {
03784            err_for_dangerous_mul_placement = 0;
03785            md_long_jump_size = crisv32_long_jump_size;
03786          }
03787        else
03788          {
03789            if (pic)
03790              md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
03791            else
03792              md_long_jump_size = cris_any_v0_v10_long_jump_size;
03793          }
03794       }
03795       break;
03796 
03797     case OPTION_MULBUG_ABORT_OFF:
03798       err_for_dangerous_mul_placement = 0;
03799       break;
03800 
03801     case OPTION_MULBUG_ABORT_ON:
03802       err_for_dangerous_mul_placement = 1;
03803       break;
03804 
03805     default:
03806       return 0;
03807     }
03808 
03809   return 1;
03810 }
03811 
03812 /* Round up a section size to the appropriate boundary.  */
03813 valueT
03814 md_section_align (segT segment, valueT size)
03815 {
03816   /* Round all sects to multiple of 4, except the bss section, which
03817      we'll round to word-size.
03818 
03819      FIXME: Check if this really matters.  All sections should be
03820      rounded up, and all sections should (optionally) be assumed to be
03821      dword-aligned, it's just that there is actual usage of linking to a
03822      multiple of two.  */
03823   if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
03824     {
03825       if (segment == bss_section)
03826        return (size + 1) & ~1;
03827       return (size + 3) & ~3;
03828     }
03829   else
03830     {
03831       /* FIXME: Is this wanted?  It matches the testsuite, but that's not
03832         really a valid reason.  */
03833       if (segment == text_section)
03834        return (size + 3) & ~3;
03835     }
03836 
03837   return size;
03838 }
03839 
03840 /* Generate a machine-dependent relocation.  */
03841 arelent *
03842 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
03843 {
03844   arelent *relP;
03845   bfd_reloc_code_real_type code;
03846 
03847   switch (fixP->fx_r_type)
03848     {
03849     case BFD_RELOC_CRIS_SIGNED_8:
03850       code = BFD_RELOC_8;
03851       break;
03852 
03853     case BFD_RELOC_CRIS_SIGNED_16:
03854       code = BFD_RELOC_16;
03855       break;
03856 
03857     case BFD_RELOC_CRIS_16_GOT:
03858     case BFD_RELOC_CRIS_32_GOT:
03859     case BFD_RELOC_CRIS_16_GOTPLT:
03860     case BFD_RELOC_CRIS_32_GOTPLT:
03861     case BFD_RELOC_CRIS_32_GOTREL:
03862     case BFD_RELOC_CRIS_32_PLT_GOTREL:
03863     case BFD_RELOC_CRIS_32_PLT_PCREL:
03864     case BFD_RELOC_32:
03865     case BFD_RELOC_32_PCREL:
03866     case BFD_RELOC_16:
03867     case BFD_RELOC_8:
03868     case BFD_RELOC_VTABLE_INHERIT:
03869     case BFD_RELOC_VTABLE_ENTRY:
03870     case BFD_RELOC_CRIS_UNSIGNED_8:
03871     case BFD_RELOC_CRIS_UNSIGNED_16:
03872     case BFD_RELOC_CRIS_LAPCQ_OFFSET:
03873       code = fixP->fx_r_type;
03874       break;
03875     default:
03876       as_bad_where (fixP->fx_file, fixP->fx_line,
03877                   _("Semantics error.  This type of operand can not be relocated, it must be an assembly-time constant"));
03878       return 0;
03879     }
03880 
03881   relP = (arelent *) xmalloc (sizeof (arelent));
03882   assert (relP != 0);
03883   relP->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
03884   *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
03885   relP->address = fixP->fx_frag->fr_address + fixP->fx_where;
03886 
03887   relP->addend = fixP->fx_offset;
03888 
03889   /* This is the standard place for KLUDGEs to work around bugs in
03890      bfd_install_relocation (first such note in the documentation
03891      appears with binutils-2.8).
03892 
03893      That function bfd_install_relocation does the wrong thing with
03894      putting stuff into the addend of a reloc (it should stay out) for a
03895      weak symbol.  The really bad thing is that it adds the
03896      "segment-relative offset" of the symbol into the reloc.  In this
03897      case, the reloc should instead be relative to the symbol with no
03898      other offset than the assembly code shows; and since the symbol is
03899      weak, any local definition should be ignored until link time (or
03900      thereafter).
03901      To wit:  weaksym+42  should be weaksym+42 in the reloc,
03902      not weaksym+(offset_from_segment_of_local_weaksym_definition)
03903 
03904      To "work around" this, we subtract the segment-relative offset of
03905      "known" weak symbols.  This evens out the extra offset.
03906 
03907      That happens for a.out but not for ELF, since for ELF,
03908      bfd_install_relocation uses the "special function" field of the
03909      howto, and does not execute the code that needs to be undone.  */
03910 
03911   if (OUTPUT_FLAVOR == bfd_target_aout_flavour
03912       && fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy)
03913       && ! bfd_is_und_section (S_GET_SEGMENT (fixP->fx_addsy)))
03914     {
03915       relP->addend -= S_GET_VALUE (fixP->fx_addsy);
03916     }
03917 
03918   relP->howto = bfd_reloc_type_lookup (stdoutput, code);
03919   if (! relP->howto)
03920     {
03921       const char *name;
03922 
03923       name = S_GET_NAME (fixP->fx_addsy);
03924       if (name == NULL)
03925        name = _("<unknown>");
03926       as_fatal (_("Cannot generate relocation type for symbol %s, code %s"),
03927               name, bfd_get_reloc_code_name (code));
03928     }
03929 
03930   return relP;
03931 }
03932 
03933 /* Machine-dependent usage-output.  */
03934 
03935 void
03936 md_show_usage (FILE *stream)
03937 {
03938   /* The messages are formatted to line up with the generic options.  */
03939   fprintf (stream, _("CRIS-specific options:\n"));
03940   fprintf (stream, "%s",
03941           _("  -h, -H                  Don't execute, print this help text.  Deprecated.\n"));
03942   fprintf (stream, "%s",
03943           _("  -N                      Warn when branches are expanded to jumps.\n"));
03944   fprintf (stream, "%s",
03945           _("  --underscore            User symbols are normally prepended with underscore.\n"));
03946   fprintf (stream, "%s",
03947           _("                          Registers will not need any prefix.\n"));
03948   fprintf (stream, "%s",
03949           _("  --no-underscore         User symbols do not have any prefix.\n"));
03950   fprintf (stream, "%s",
03951           _("                          Registers will require a `$'-prefix.\n"));
03952   fprintf (stream, "%s",
03953           _("  --pic               Enable generation of position-independent code.\n"));
03954   fprintf (stream, "%s",
03955           _("  --march=<arch>             Generate code for <arch>.  Valid choices for <arch>\n\
03956                             are v0_v10, v10, v32 and common_v10_v32.\n"));
03957 }
03958 
03959 /* Apply a fixS (fixup of an instruction or data that we didn't have
03960    enough info to complete immediately) to the data in a frag.  */
03961 
03962 void
03963 md_apply_fix (fixS *fixP, valueT *valP, segT seg)
03964 {
03965   /* This assignment truncates upper bits if valueT is 64 bits (as with
03966      --enable-64-bit-bfd), which is fine here, though we cast to avoid
03967      any compiler warnings.  */
03968   long val = (long) *valP;
03969   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
03970 
03971   if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
03972     fixP->fx_done = 1;
03973 
03974   if (fixP->fx_bit_fixP || fixP->fx_im_disp != 0)
03975     {
03976       as_bad_where (fixP->fx_file, fixP->fx_line, _("Invalid relocation"));
03977       fixP->fx_done = 1;
03978     }
03979   else
03980     {
03981       /* We can't actually support subtracting a symbol.  */
03982       if (fixP->fx_subsy != (symbolS *) NULL)
03983        as_bad_where (fixP->fx_file, fixP->fx_line,
03984                     _("expression too complex"));
03985 
03986       /* This operand-type is scaled.  */
03987       if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET)
03988        val /= 2;
03989       cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg);
03990     }
03991 }
03992 
03993 /* All relocations are relative to the location just after the fixup;
03994    the address of the fixup plus its size.  */
03995 
03996 long
03997 md_pcrel_from (fixS *fixP)
03998 {
03999   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
04000 
04001   /* FIXME:  We get here only at the end of assembly, when X in ".-X" is
04002      still unknown.  Since we don't have pc-relative relocations in a.out,
04003      this is invalid.  What to do if anything for a.out, is to add
04004      pc-relative relocations everywhere including the elinux program
04005      loader.  For ELF, allow straight-forward PC-relative relocations,
04006      which are always relative to the location after the relocation.  */
04007   if (OUTPUT_FLAVOR != bfd_target_elf_flavour
04008       || (fixP->fx_r_type != BFD_RELOC_8_PCREL
04009          && fixP->fx_r_type != BFD_RELOC_16_PCREL
04010          && fixP->fx_r_type != BFD_RELOC_32_PCREL
04011          && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET))
04012     as_bad_where (fixP->fx_file, fixP->fx_line,
04013                 _("Invalid pc-relative relocation"));
04014   return fixP->fx_size + addr;
04015 }
04016 
04017 /* We have no need to give defaults for symbol-values.  */
04018 symbolS *
04019 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
04020 {
04021   return 0;
04022 }
04023 
04024 /* If this function returns non-zero, it prevents the relocation
04025    against symbol(s) in the FIXP from being replaced with relocations
04026    against section symbols, and guarantees that a relocation will be
04027    emitted even when the value can be resolved locally.  */
04028 int
04029 md_cris_force_relocation (struct fix *fixp)
04030 {
04031   switch (fixp->fx_r_type)
04032     {
04033     case BFD_RELOC_CRIS_16_GOT:
04034     case BFD_RELOC_CRIS_32_GOT:
04035     case BFD_RELOC_CRIS_16_GOTPLT:
04036     case BFD_RELOC_CRIS_32_GOTPLT:
04037     case BFD_RELOC_CRIS_32_GOTREL:
04038     case BFD_RELOC_CRIS_32_PLT_GOTREL:
04039     case BFD_RELOC_CRIS_32_PLT_PCREL:
04040       return 1;
04041     default:
04042       ;
04043     }
04044 
04045   return generic_force_reloc (fixp);
04046 }
04047 
04048 /* Check and emit error if broken-word handling has failed to fix up a
04049    case-table.       This is called from write.c, after doing everything it
04050    knows about how to handle broken words.  */
04051 
04052 void
04053 tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
04054 {
04055   if (new_offset > 32767 || new_offset < -32768)
04056     /* We really want a genuine error, not a warning, so make it one.  */
04057     as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
04058                 _("Adjusted signed .word (%ld) overflows: `switch'-statement too large."),
04059                 (long) new_offset);
04060 }
04061 
04062 /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers.  */
04063 
04064 static void
04065 cris_force_reg_prefix (void)
04066 {
04067   demand_register_prefix = TRUE;
04068 }
04069 
04070 /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers.  */
04071 
04072 static void
04073 cris_relax_reg_prefix (void)
04074 {
04075   demand_register_prefix = FALSE;
04076 }
04077 
04078 /* Adjust for having a leading '_' on all user symbols.  */
04079 
04080 static void
04081 cris_sym_leading_underscore (void)
04082 {
04083   /* We can't really do anything more than assert that what the program
04084      thinks symbol starts with agrees with the command-line options, since
04085      the bfd is already created.  */
04086 
04087   if (!symbols_have_leading_underscore)
04088     as_bad (_(".syntax %s requires command-line option `--underscore'"),
04089            SYNTAX_USER_SYM_LEADING_UNDERSCORE);
04090 }
04091 
04092 /* Adjust for not having any particular prefix on user symbols.  */
04093 
04094 static void cris_sym_no_leading_underscore (void)
04095 {
04096   if (symbols_have_leading_underscore)
04097     as_bad (_(".syntax %s requires command-line option `--no-underscore'"),
04098            SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE);
04099 }
04100 
04101 /* Handle the .syntax pseudo, which takes an argument that decides what
04102    syntax the assembly code has.  */
04103 
04104 static void
04105 s_syntax (int ignore ATTRIBUTE_UNUSED)
04106 {
04107   static const struct syntaxes
04108   {
04109     const char *const operand;
04110     void (*fn) (void);
04111   } syntax_table[] =
04112     {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix},
04113      {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix},
04114      {SYNTAX_USER_SYM_LEADING_UNDERSCORE, cris_sym_leading_underscore},
04115      {SYNTAX_USER_SYM_NO_LEADING_UNDERSCORE, cris_sym_no_leading_underscore}};
04116 
04117   const struct syntaxes *sp;
04118 
04119   for (sp = syntax_table;
04120        sp < syntax_table + sizeof (syntax_table) / sizeof (syntax_table[0]);
04121        sp++)
04122     {
04123       if (strncmp (input_line_pointer, sp->operand,
04124                  strlen (sp->operand)) == 0)
04125        {
04126          (sp->fn) ();
04127 
04128          input_line_pointer += strlen (sp->operand);
04129          demand_empty_rest_of_line ();
04130          return;
04131        }
04132     }
04133 
04134   as_bad (_("Unknown .syntax operand"));
04135 }
04136 
04137 /* Wrapper for dwarf2_directive_file to emit error if this is seen when
04138    not emitting ELF.  */
04139 
04140 static void
04141 s_cris_file (int dummy)
04142 {
04143   if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
04144     as_bad (_("Pseudodirective .file is only valid when generating ELF"));
04145   else
04146     dwarf2_directive_file (dummy);
04147 }
04148 
04149 /* Wrapper for dwarf2_directive_loc to emit error if this is seen when not
04150    emitting ELF.  */
04151 
04152 static void
04153 s_cris_loc (int dummy)
04154 {
04155   if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
04156     as_bad (_("Pseudodirective .loc is only valid when generating ELF"));
04157   else
04158     dwarf2_directive_loc (dummy);
04159 }
04160 
04161 /* Translate a <arch> string (as common to --march=<arch> and .arch <arch>)
04162    into an enum.  If the string *STR is recognized, *STR is updated to point
04163    to the end of the string.  If the string is not recognized,
04164    arch_cris_unknown is returned.  */
04165 
04166 static enum cris_archs
04167 cris_arch_from_string (char **str)
04168 {
04169   static const struct cris_arch_struct
04170   {
04171     const char *const name;
04172     enum cris_archs arch;
04173   } arch_table[] =
04174       /* Keep in order longest-first for choices where one is a prefix
04175         of another.  */
04176     {{"v0_v10", arch_cris_any_v0_v10},
04177      {"v10", arch_crisv10},
04178      {"v32", arch_crisv32},
04179      {"common_v10_v32", arch_cris_common_v10_v32}};
04180 
04181   const struct cris_arch_struct *ap;
04182 
04183   for (ap = arch_table;
04184        ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]);
04185        ap++)
04186     {
04187       int len = strlen (ap->name);
04188 
04189       if (strncmp (*str, ap->name, len) == 0
04190          && (str[0][len] == 0 || ISSPACE (str[0][len])))
04191        {
04192          *str += strlen (ap->name);
04193          return ap->arch;
04194        }
04195     }
04196 
04197   return arch_cris_unknown;
04198 }
04199 
04200 /* Return nonzero if architecture version ARCH matches version range in
04201    IVER.  */
04202 
04203 static int
04204 cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver,
04205                            enum cris_archs arch)
04206 {
04207   switch (arch)
04208     {
04209     case arch_cris_any_v0_v10:
04210       return
04211        (iver == cris_ver_version_all
04212         || iver == cris_ver_warning
04213         || iver == cris_ver_v0_3
04214         || iver == cris_ver_v3p
04215         || iver == cris_ver_v0_10
04216         || iver == cris_ver_sim_v0_10
04217         || iver == cris_ver_v3_10
04218         || iver == cris_ver_v8
04219         || iver == cris_ver_v8p
04220         || iver == cris_ver_v8_10
04221         || iver == cris_ver_v10
04222         || iver == cris_ver_v10p);
04223       
04224     case arch_crisv32:
04225       return
04226        (iver == cris_ver_version_all
04227         || iver == cris_ver_v3p
04228         || iver == cris_ver_v8p
04229         || iver == cris_ver_v10p
04230         || iver == cris_ver_v32p);
04231 
04232     case arch_cris_common_v10_v32:
04233       return
04234        (iver == cris_ver_version_all
04235         || iver == cris_ver_v3p
04236         || iver == cris_ver_v8p
04237         || iver == cris_ver_v10p);
04238 
04239     case arch_crisv0:
04240       return
04241        (iver == cris_ver_version_all
04242         || iver == cris_ver_v0_3
04243         || iver == cris_ver_v0_10
04244         || iver == cris_ver_sim_v0_10);
04245 
04246     case arch_crisv3:
04247       return
04248        (iver == cris_ver_version_all
04249         || iver == cris_ver_v0_3
04250         || iver == cris_ver_v3p
04251         || iver == cris_ver_v0_10
04252         || iver == cris_ver_sim_v0_10
04253         || iver == cris_ver_v3_10);
04254 
04255     case arch_crisv8:
04256       return
04257        (iver == cris_ver_version_all
04258         || iver == cris_ver_v3p
04259         || iver == cris_ver_v0_10
04260         || iver == cris_ver_sim_v0_10
04261         || iver == cris_ver_v3_10
04262         || iver == cris_ver_v8
04263         || iver == cris_ver_v8p
04264         || iver == cris_ver_v8_10);
04265 
04266     case arch_crisv10:
04267       return
04268        (iver == cris_ver_version_all
04269         || iver == cris_ver_v3p
04270         || iver == cris_ver_v0_10
04271         || iver == cris_ver_sim_v0_10
04272         || iver == cris_ver_v3_10
04273         || iver == cris_ver_v8p
04274         || iver == cris_ver_v8_10
04275         || iver == cris_ver_v10
04276         || iver == cris_ver_v10p);
04277 
04278     default:
04279       BAD_CASE (arch);
04280    }
04281 }
04282 
04283 /* Assert that the .arch ARCHCHOICE1 is compatible with the specified or
04284    default --march=<ARCHCHOICE2> option.  */
04285 
04286 static void
04287 s_cris_arch (int dummy ATTRIBUTE_UNUSED)
04288 {
04289   /* Right now we take the easy route and check for sameness.  It's not
04290      obvious that allowing e.g. --march=v32 and .arch common_v0_v32
04291      would be more useful than confusing, implementation-wise and
04292      user-wise.  */
04293 
04294   char *str = input_line_pointer;
04295   enum cris_archs arch = cris_arch_from_string (&str);
04296 
04297   if (arch == arch_cris_unknown)
04298     {
04299       as_bad (_("unknown operand to .arch"));
04300 
04301       /* For this one, str does not reflect the end of the operand,
04302         since there was no matching arch.  Skip it manually; skip
04303         things that can be part of a word (a name).  */
04304       while (is_part_of_name (*str))
04305        str++;
04306     }
04307   else if (arch != cris_arch)
04308     as_bad (_(".arch <arch> requires a matching --march=... option"));
04309 
04310   input_line_pointer = str;
04311   demand_empty_rest_of_line ();
04312   return;
04313 }
04314 
04315 /*
04316  * Local variables:
04317  * eval: (c-set-style "gnu")
04318  * indent-tabs-mode: t
04319  * End:
04320  */