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tc-arm.c
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00001 /* tc-arm.c -- Assemble for the ARM
00002    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
00003    2004, 2005, 2006
00004    Free Software Foundation, Inc.
00005    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
00006        Modified by David Taylor (dtaylor@armltd.co.uk)
00007        Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
00008        Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
00009        Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
00010 
00011    This file is part of GAS, the GNU Assembler.
00012 
00013    GAS is free software; you can redistribute it and/or modify
00014    it under the terms of the GNU General Public License as published by
00015    the Free Software Foundation; either version 2, or (at your option)
00016    any later version.
00017 
00018    GAS is distributed in the hope that it will be useful,
00019    but WITHOUT ANY WARRANTY; without even the implied warranty of
00020    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00021    GNU General Public License for more details.
00022 
00023    You should have received a copy of the GNU General Public License
00024    along with GAS; see the file COPYING.  If not, write to the Free
00025    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00026    02110-1301, USA.  */
00027 
00028 #include <limits.h>
00029 #include <stdarg.h>
00030 #define        NO_RELOC 0
00031 #include "as.h"
00032 #include "safe-ctype.h"
00033 #include "subsegs.h"
00034 #include "obstack.h"
00035 
00036 #include "opcode/arm.h"
00037 
00038 #ifdef OBJ_ELF
00039 #include "elf/arm.h"
00040 #include "dw2gencfi.h"
00041 #endif
00042 
00043 #include "dwarf2dbg.h"
00044 
00045 #define WARN_DEPRECATED 1
00046 
00047 #ifdef OBJ_ELF
00048 /* Must be at least the size of the largest unwind opcode (currently two).  */
00049 #define ARM_OPCODE_CHUNK_SIZE 8
00050 
00051 /* This structure holds the unwinding state.  */
00052 
00053 static struct
00054 {
00055   symbolS *     proc_start;
00056   symbolS *     table_entry;
00057   symbolS *     personality_routine;
00058   int           personality_index;
00059   /* The segment containing the function.  */
00060   segT          saved_seg;
00061   subsegT       saved_subseg;
00062   /* Opcodes generated from this function.  */
00063   unsigned char * opcodes;
00064   int           opcode_count;
00065   int           opcode_alloc;
00066   /* The number of bytes pushed to the stack.  */
00067   offsetT       frame_size;
00068   /* We don't add stack adjustment opcodes immediately so that we can merge
00069      multiple adjustments.  We can also omit the final adjustment
00070      when using a frame pointer.  */
00071   offsetT       pending_offset;
00072   /* These two fields are set by both unwind_movsp and unwind_setfp.  They
00073      hold the reg+offset to use when restoring sp from a frame pointer.       */
00074   offsetT       fp_offset;
00075   int           fp_reg;
00076   /* Nonzero if an unwind_setfp directive has been seen.  */
00077   unsigned      fp_used:1;
00078   /* Nonzero if the last opcode restores sp from fp_reg.  */
00079   unsigned      sp_restored:1;
00080 } unwind;
00081 
00082 /* Bit N indicates that an R_ARM_NONE relocation has been output for
00083    __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
00084    emitted only once per section, to save unnecessary bloat.  */
00085 static unsigned int marked_pr_dependency = 0;
00086 
00087 #endif /* OBJ_ELF */
00088 
00089 /* Results from operand parsing worker functions.  */
00090 
00091 typedef enum
00092 {
00093   PARSE_OPERAND_SUCCESS,
00094   PARSE_OPERAND_FAIL,
00095   PARSE_OPERAND_FAIL_NO_BACKTRACK
00096 } parse_operand_result;
00097 
00098 enum arm_float_abi
00099 {
00100   ARM_FLOAT_ABI_HARD,
00101   ARM_FLOAT_ABI_SOFTFP,
00102   ARM_FLOAT_ABI_SOFT
00103 };
00104 
00105 /* Types of processor to assemble for.    */
00106 #ifndef CPU_DEFAULT
00107 #if defined __XSCALE__
00108 #define CPU_DEFAULT  ARM_ARCH_XSCALE
00109 #else
00110 #if defined __thumb__
00111 #define CPU_DEFAULT  ARM_ARCH_V5T
00112 #endif
00113 #endif
00114 #endif
00115 
00116 #ifndef FPU_DEFAULT
00117 # ifdef TE_LINUX
00118 #  define FPU_DEFAULT FPU_ARCH_FPA
00119 # elif defined (TE_NetBSD)
00120 #  ifdef OBJ_ELF
00121 #   define FPU_DEFAULT FPU_ARCH_VFP       /* Soft-float, but VFP order.  */
00122 #  else
00123     /* Legacy a.out format.  */
00124 #   define FPU_DEFAULT FPU_ARCH_FPA       /* Soft-float, but FPA order.  */
00125 #  endif
00126 # elif defined (TE_VXWORKS)
00127 #  define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order.  */
00128 # else
00129    /* For backwards compatibility, default to FPA.  */
00130 #  define FPU_DEFAULT FPU_ARCH_FPA
00131 # endif
00132 #endif /* ifndef FPU_DEFAULT */
00133 
00134 #define streq(a, b)        (strcmp (a, b) == 0)
00135 
00136 static arm_feature_set cpu_variant;
00137 static arm_feature_set arm_arch_used;
00138 static arm_feature_set thumb_arch_used;
00139 
00140 /* Flags stored in private area of BFD structure.  */
00141 static int uses_apcs_26          = FALSE;
00142 static int atpcs          = FALSE;
00143 static int support_interwork = FALSE;
00144 static int uses_apcs_float   = FALSE;
00145 static int pic_code       = FALSE;
00146 
00147 /* Variables that we set while parsing command-line options.  Once all
00148    options have been read we re-process these values to set the real
00149    assembly flags.  */
00150 static const arm_feature_set *legacy_cpu = NULL;
00151 static const arm_feature_set *legacy_fpu = NULL;
00152 
00153 static const arm_feature_set *mcpu_cpu_opt = NULL;
00154 static const arm_feature_set *mcpu_fpu_opt = NULL;
00155 static const arm_feature_set *march_cpu_opt = NULL;
00156 static const arm_feature_set *march_fpu_opt = NULL;
00157 static const arm_feature_set *mfpu_opt = NULL;
00158 static const arm_feature_set *object_arch = NULL;
00159 
00160 /* Constants for known architecture features.  */
00161 static const arm_feature_set fpu_default = FPU_DEFAULT;
00162 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
00163 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
00164 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
00165 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
00166 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
00167 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
00168 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
00169 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
00170 
00171 #ifdef CPU_DEFAULT
00172 static const arm_feature_set cpu_default = CPU_DEFAULT;
00173 #endif
00174 
00175 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
00176 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
00177 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
00178 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
00179 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
00180 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
00181 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
00182 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
00183 static const arm_feature_set arm_ext_v4t_5 =
00184   ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
00185 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
00186 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
00187 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
00188 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
00189 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
00190 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
00191 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
00192 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
00193 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
00194 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
00195 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
00196 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
00197 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
00198 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
00199 
00200 static const arm_feature_set arm_arch_any = ARM_ANY;
00201 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
00202 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
00203 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
00204 
00205 static const arm_feature_set arm_cext_iwmmxt2 =
00206   ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
00207 static const arm_feature_set arm_cext_iwmmxt =
00208   ARM_FEATURE (0, ARM_CEXT_IWMMXT);
00209 static const arm_feature_set arm_cext_xscale =
00210   ARM_FEATURE (0, ARM_CEXT_XSCALE);
00211 static const arm_feature_set arm_cext_maverick =
00212   ARM_FEATURE (0, ARM_CEXT_MAVERICK);
00213 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
00214 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
00215 static const arm_feature_set fpu_vfp_ext_v1xd =
00216   ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
00217 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
00218 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
00219 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
00220 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
00221 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
00222   ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
00223 
00224 static int mfloat_abi_opt = -1;
00225 /* Record user cpu selection for object attributes.  */
00226 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
00227 /* Must be long enough to hold any of the names in arm_cpus.  */
00228 static char selected_cpu_name[16];
00229 #ifdef OBJ_ELF
00230 # ifdef EABI_DEFAULT
00231 static int meabi_flags = EABI_DEFAULT;
00232 # else
00233 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
00234 # endif
00235 
00236 bfd_boolean
00237 arm_is_eabi(void)
00238 {
00239   return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
00240 }
00241 #endif
00242 
00243 #ifdef OBJ_ELF
00244 /* Pre-defined "_GLOBAL_OFFSET_TABLE_"    */
00245 symbolS * GOT_symbol;
00246 #endif
00247 
00248 /* 0: assemble for ARM,
00249    1: assemble for Thumb,
00250    2: assemble for Thumb even though target CPU does not support thumb
00251       instructions.  */
00252 static int thumb_mode = 0;
00253 
00254 /* If unified_syntax is true, we are processing the new unified
00255    ARM/Thumb syntax.  Important differences from the old ARM mode:
00256 
00257      - Immediate operands do not require a # prefix.
00258      - Conditional affixes always appear at the end of the
00259        instruction.  (For backward compatibility, those instructions
00260        that formerly had them in the middle, continue to accept them
00261        there.)
00262      - The IT instruction may appear, and if it does is validated
00263        against subsequent conditional affixes.  It does not generate
00264        machine code.
00265 
00266    Important differences from the old Thumb mode:
00267 
00268      - Immediate operands do not require a # prefix.
00269      - Most of the V6T2 instructions are only available in unified mode.
00270      - The .N and .W suffixes are recognized and honored (it is an error
00271        if they cannot be honored).
00272      - All instructions set the flags if and only if they have an 's' affix.
00273      - Conditional affixes may be used.  They are validated against
00274        preceding IT instructions.  Unlike ARM mode, you cannot use a
00275        conditional affix except in the scope of an IT instruction.  */
00276 
00277 static bfd_boolean unified_syntax = FALSE;
00278 
00279 enum neon_el_type
00280 {
00281   NT_invtype,
00282   NT_untyped,
00283   NT_integer,
00284   NT_float,
00285   NT_poly,
00286   NT_signed,
00287   NT_unsigned
00288 };
00289 
00290 struct neon_type_el
00291 {
00292   enum neon_el_type type;
00293   unsigned size;
00294 };
00295 
00296 #define NEON_MAX_TYPE_ELS 4
00297 
00298 struct neon_type
00299 {
00300   struct neon_type_el el[NEON_MAX_TYPE_ELS];
00301   unsigned elems;
00302 };
00303 
00304 struct arm_it
00305 {
00306   const char *       error;
00307   unsigned long instruction;
00308   int         size;
00309   int         size_req;
00310   int         cond;
00311   /* "uncond_value" is set to the value in place of the conditional field in
00312      unconditional versions of the instruction, or -1 if nothing is
00313      appropriate.  */
00314   int         uncond_value;
00315   struct neon_type vectype;
00316   /* Set to the opcode if the instruction needs relaxation.
00317      Zero if the instruction is not relaxed.  */
00318   unsigned long      relax;
00319   struct
00320   {
00321     bfd_reloc_code_real_type type;
00322     expressionS                  exp;
00323     int                          pc_rel;
00324   } reloc;
00325 
00326   struct
00327   {
00328     unsigned reg;
00329     signed int imm;
00330     struct neon_type_el vectype;
00331     unsigned present : 1;  /* Operand present.  */
00332     unsigned isreg   : 1;  /* Operand was a register.  */
00333     unsigned immisreg       : 1;  /* .imm field is a second register.  */
00334     unsigned isscalar   : 1;  /* Operand is a (Neon) scalar.  */
00335     unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */
00336     unsigned immisfloat : 1;  /* Immediate was parsed as a float.  */
00337     /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
00338        instructions. This allows us to disambiguate ARM <-> vector insns.  */
00339     unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
00340     unsigned isvec      : 1;  /* Is a single, double or quad VFP/Neon reg.  */
00341     unsigned isquad     : 1;  /* Operand is Neon quad-precision register.  */
00342     unsigned issingle   : 1;  /* Operand is VFP single-precision register.  */
00343     unsigned hasreloc       : 1;  /* Operand has relocation suffix.  */
00344     unsigned writeback      : 1;  /* Operand has trailing !  */
00345     unsigned preind  : 1;  /* Preindexed address.  */
00346     unsigned postind : 1;  /* Postindexed address.  */
00347     unsigned negative       : 1;  /* Index register was negated.  */
00348     unsigned shifted : 1;  /* Shift applied to operation.  */
00349     unsigned shift_kind : 3;  /* Shift operation (enum shift_kind).  */
00350   } operands[6];
00351 };
00352 
00353 static struct arm_it inst;
00354 
00355 #define NUM_FLOAT_VALS 8
00356 
00357 const char * fp_const[] =
00358 {
00359   "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
00360 };
00361 
00362 /* Number of littlenums required to hold an extended precision number.       */
00363 #define MAX_LITTLENUMS 6
00364 
00365 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
00366 
00367 #define FAIL  (-1)
00368 #define SUCCESS (0)
00369 
00370 #define SUFF_S 1
00371 #define SUFF_D 2
00372 #define SUFF_E 3
00373 #define SUFF_P 4
00374 
00375 #define CP_T_X        0x00008000
00376 #define CP_T_Y        0x00400000
00377 
00378 #define CONDS_BIT     0x00100000
00379 #define LOAD_BIT      0x00100000
00380 
00381 #define DOUBLE_LOAD_FLAG 0x00000001
00382 
00383 struct asm_cond
00384 {
00385   const char *       template;
00386   unsigned long value;
00387 };
00388 
00389 #define COND_ALWAYS 0xE
00390 
00391 struct asm_psr
00392 {
00393   const char *template;
00394   unsigned long field;
00395 };
00396 
00397 struct asm_barrier_opt
00398 {
00399   const char *template;
00400   unsigned long value;
00401 };
00402 
00403 /* The bit that distinguishes CPSR and SPSR.  */
00404 #define SPSR_BIT   (1 << 22)
00405 
00406 /* The individual PSR flag bits.  */
00407 #define PSR_c (1 << 16)
00408 #define PSR_x (1 << 17)
00409 #define PSR_s (1 << 18)
00410 #define PSR_f (1 << 19)
00411 
00412 struct reloc_entry
00413 {
00414   char *name;
00415   bfd_reloc_code_real_type reloc;
00416 };
00417 
00418 enum vfp_reg_pos
00419 {
00420   VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
00421   VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
00422 };
00423 
00424 enum vfp_ldstm_type
00425 {
00426   VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
00427 };
00428 
00429 /* Bits for DEFINED field in neon_typed_alias.  */
00430 #define NTA_HASTYPE  1
00431 #define NTA_HASINDEX 2
00432 
00433 struct neon_typed_alias
00434 {
00435   unsigned char defined;
00436   unsigned char index;
00437   struct neon_type_el eltype;
00438 };
00439 
00440 /* ARM register categories.  This includes coprocessor numbers and various
00441    architecture extensions' registers.    */
00442 enum arm_reg_type
00443 {
00444   REG_TYPE_RN,
00445   REG_TYPE_CP,
00446   REG_TYPE_CN,
00447   REG_TYPE_FN,
00448   REG_TYPE_VFS,
00449   REG_TYPE_VFD,
00450   REG_TYPE_NQ,
00451   REG_TYPE_VFSD,
00452   REG_TYPE_NDQ,
00453   REG_TYPE_NSDQ,
00454   REG_TYPE_VFC,
00455   REG_TYPE_MVF,
00456   REG_TYPE_MVD,
00457   REG_TYPE_MVFX,
00458   REG_TYPE_MVDX,
00459   REG_TYPE_MVAX,
00460   REG_TYPE_DSPSC,
00461   REG_TYPE_MMXWR,
00462   REG_TYPE_MMXWC,
00463   REG_TYPE_MMXWCG,
00464   REG_TYPE_XSCALE,
00465 };
00466 
00467 /* Structure for a hash table entry for a register.
00468    If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
00469    information which states whether a vector type or index is specified (for a
00470    register alias created with .dn or .qn). Otherwise NEON should be NULL.  */
00471 struct reg_entry
00472 {
00473   const char        *name;
00474   unsigned char      number;
00475   unsigned char      type;
00476   unsigned char      builtin;
00477   struct neon_typed_alias *neon;
00478 };
00479 
00480 /* Diagnostics used when we don't get a register of the expected type.       */
00481 const char *const reg_expected_msgs[] =
00482 {
00483   N_("ARM register expected"),
00484   N_("bad or missing co-processor number"),
00485   N_("co-processor register expected"),
00486   N_("FPA register expected"),
00487   N_("VFP single precision register expected"),
00488   N_("VFP/Neon double precision register expected"),
00489   N_("Neon quad precision register expected"),
00490   N_("VFP single or double precision register expected"),
00491   N_("Neon double or quad precision register expected"),
00492   N_("VFP single, double or Neon quad precision register expected"),
00493   N_("VFP system register expected"),
00494   N_("Maverick MVF register expected"),
00495   N_("Maverick MVD register expected"),
00496   N_("Maverick MVFX register expected"),
00497   N_("Maverick MVDX register expected"),
00498   N_("Maverick MVAX register expected"),
00499   N_("Maverick DSPSC register expected"),
00500   N_("iWMMXt data register expected"),
00501   N_("iWMMXt control register expected"),
00502   N_("iWMMXt scalar register expected"),
00503   N_("XScale accumulator register expected"),
00504 };
00505 
00506 /* Some well known registers that we refer to directly elsewhere.  */
00507 #define REG_SP       13
00508 #define REG_LR       14
00509 #define REG_PC       15
00510 
00511 /* ARM instructions take 4bytes in the object file, Thumb instructions
00512    take 2:  */
00513 #define INSN_SIZE    4
00514 
00515 struct asm_opcode
00516 {
00517   /* Basic string to match.  */
00518   const char *template;
00519 
00520   /* Parameters to instruction.     */
00521   unsigned char operands[8];
00522 
00523   /* Conditional tag - see opcode_lookup.  */
00524   unsigned int tag : 4;
00525 
00526   /* Basic instruction code.  */
00527   unsigned int avalue : 28;
00528 
00529   /* Thumb-format instruction code.  */
00530   unsigned int tvalue;
00531 
00532   /* Which architecture variant provides this instruction.  */
00533   const arm_feature_set *avariant;
00534   const arm_feature_set *tvariant;
00535 
00536   /* Function to call to encode instruction in ARM format.  */
00537   void (* aencode) (void);
00538 
00539   /* Function to call to encode instruction in Thumb format.  */
00540   void (* tencode) (void);
00541 };
00542 
00543 /* Defines for various bits that we will want to toggle.  */
00544 #define INST_IMMEDIATE      0x02000000
00545 #define OFFSET_REG   0x02000000
00546 #define HWOFFSET_IMM 0x00400000
00547 #define SHIFT_BY_REG 0x00000010
00548 #define PRE_INDEX    0x01000000
00549 #define INDEX_UP     0x00800000
00550 #define WRITE_BACK   0x00200000
00551 #define LDM_TYPE_2_OR_3     0x00400000
00552 #define CPSI_MMOD    0x00020000
00553 
00554 #define LITERAL_MASK 0xf000f000
00555 #define OPCODE_MASK  0xfe1fffff
00556 #define V4_STR_BIT   0x00000020
00557 
00558 #define DATA_OP_SHIFT       21
00559 
00560 #define T2_OPCODE_MASK      0xfe1fffff
00561 #define T2_DATA_OP_SHIFT 21
00562 
00563 /* Codes to distinguish the arithmetic instructions.  */
00564 #define OPCODE_AND   0
00565 #define OPCODE_EOR   1
00566 #define OPCODE_SUB   2
00567 #define OPCODE_RSB   3
00568 #define OPCODE_ADD   4
00569 #define OPCODE_ADC   5
00570 #define OPCODE_SBC   6
00571 #define OPCODE_RSC   7
00572 #define OPCODE_TST   8
00573 #define OPCODE_TEQ   9
00574 #define OPCODE_CMP   10
00575 #define OPCODE_CMN   11
00576 #define OPCODE_ORR   12
00577 #define OPCODE_MOV   13
00578 #define OPCODE_BIC   14
00579 #define OPCODE_MVN   15
00580 
00581 #define T2_OPCODE_AND       0
00582 #define T2_OPCODE_BIC       1
00583 #define T2_OPCODE_ORR       2
00584 #define T2_OPCODE_ORN       3
00585 #define T2_OPCODE_EOR       4
00586 #define T2_OPCODE_ADD       8
00587 #define T2_OPCODE_ADC       10
00588 #define T2_OPCODE_SBC       11
00589 #define T2_OPCODE_SUB       13
00590 #define T2_OPCODE_RSB       14
00591 
00592 #define T_OPCODE_MUL 0x4340
00593 #define T_OPCODE_TST 0x4200
00594 #define T_OPCODE_CMN 0x42c0
00595 #define T_OPCODE_NEG 0x4240
00596 #define T_OPCODE_MVN 0x43c0
00597 
00598 #define T_OPCODE_ADD_R3     0x1800
00599 #define T_OPCODE_SUB_R3 0x1a00
00600 #define T_OPCODE_ADD_HI 0x4400
00601 #define T_OPCODE_ADD_ST 0xb000
00602 #define T_OPCODE_SUB_ST 0xb080
00603 #define T_OPCODE_ADD_SP 0xa800
00604 #define T_OPCODE_ADD_PC 0xa000
00605 #define T_OPCODE_ADD_I8 0x3000
00606 #define T_OPCODE_SUB_I8 0x3800
00607 #define T_OPCODE_ADD_I3 0x1c00
00608 #define T_OPCODE_SUB_I3 0x1e00
00609 
00610 #define T_OPCODE_ASR_R      0x4100
00611 #define T_OPCODE_LSL_R      0x4080
00612 #define T_OPCODE_LSR_R      0x40c0
00613 #define T_OPCODE_ROR_R      0x41c0
00614 #define T_OPCODE_ASR_I      0x1000
00615 #define T_OPCODE_LSL_I      0x0000
00616 #define T_OPCODE_LSR_I      0x0800
00617 
00618 #define T_OPCODE_MOV_I8     0x2000
00619 #define T_OPCODE_CMP_I8 0x2800
00620 #define T_OPCODE_CMP_LR 0x4280
00621 #define T_OPCODE_MOV_HR 0x4600
00622 #define T_OPCODE_CMP_HR 0x4500
00623 
00624 #define T_OPCODE_LDR_PC 0x4800
00625 #define T_OPCODE_LDR_SP 0x9800
00626 #define T_OPCODE_STR_SP 0x9000
00627 #define T_OPCODE_LDR_IW 0x6800
00628 #define T_OPCODE_STR_IW 0x6000
00629 #define T_OPCODE_LDR_IH 0x8800
00630 #define T_OPCODE_STR_IH 0x8000
00631 #define T_OPCODE_LDR_IB 0x7800
00632 #define T_OPCODE_STR_IB 0x7000
00633 #define T_OPCODE_LDR_RW 0x5800
00634 #define T_OPCODE_STR_RW 0x5000
00635 #define T_OPCODE_LDR_RH 0x5a00
00636 #define T_OPCODE_STR_RH 0x5200
00637 #define T_OPCODE_LDR_RB 0x5c00
00638 #define T_OPCODE_STR_RB 0x5400
00639 
00640 #define T_OPCODE_PUSH       0xb400
00641 #define T_OPCODE_POP 0xbc00
00642 
00643 #define T_OPCODE_BRANCH 0xe000
00644 
00645 #define THUMB_SIZE   2      /* Size of thumb instruction.  */
00646 #define THUMB_PP_PC_LR 0x0100
00647 #define THUMB_LOAD_BIT 0x0800
00648 #define THUMB2_LOAD_BIT 0x00100000
00649 
00650 #define BAD_ARGS     _("bad arguments to instruction")
00651 #define BAD_PC              _("r15 not allowed here")
00652 #define BAD_COND     _("instruction cannot be conditional")
00653 #define BAD_OVERLAP  _("registers may not be the same")
00654 #define BAD_HIREG    _("lo register required")
00655 #define BAD_THUMB32  _("instruction not supported in Thumb16 mode")
00656 #define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
00657 #define BAD_BRANCH   _("branch must be last instruction in IT block")
00658 #define BAD_NOT_IT   _("instruction not allowed in IT block")
00659 #define BAD_FPU             _("selected FPU does not support instruction")
00660 
00661 static struct hash_control *arm_ops_hsh;
00662 static struct hash_control *arm_cond_hsh;
00663 static struct hash_control *arm_shift_hsh;
00664 static struct hash_control *arm_psr_hsh;
00665 static struct hash_control *arm_v7m_psr_hsh;
00666 static struct hash_control *arm_reg_hsh;
00667 static struct hash_control *arm_reloc_hsh;
00668 static struct hash_control *arm_barrier_opt_hsh;
00669 
00670 /* Stuff needed to resolve the label ambiguity
00671    As:
00672      ...
00673      label:   <insn>
00674    may differ from:
00675      ...
00676      label:
00677              <insn>
00678 */
00679 
00680 symbolS *  last_label_seen;
00681 static int label_is_thumb_function_name = FALSE;
00682 
00683 /* Literal pool structure.  Held on a per-section
00684    and per-sub-section basis.  */
00685 
00686 #define MAX_LITERAL_POOL_SIZE 1024
00687 typedef struct literal_pool
00688 {
00689   expressionS  literals [MAX_LITERAL_POOL_SIZE];
00690   unsigned int        next_free_entry;
00691   unsigned int        id;
00692   symbolS *    symbol;
00693   segT         section;
00694   subsegT      sub_section;
00695   struct literal_pool * next;
00696 } literal_pool;
00697 
00698 /* Pointer to a linked list of literal pools.  */
00699 literal_pool * list_of_pools = NULL;
00700 
00701 /* State variables for IT block handling.  */
00702 static bfd_boolean current_it_mask = 0;
00703 static int current_cc;
00704 
00705 
00706 /* Pure syntax.       */
00707 
00708 /* This array holds the chars that always start a comment.  If the
00709    pre-processor is disabled, these aren't very useful.  */
00710 const char comment_chars[] = "@";
00711 
00712 /* This array holds the chars that only start a comment at the beginning of
00713    a line.  If the line seems to have the form '# 123 filename'
00714    .line and .file directives will appear in the pre-processed output.       */
00715 /* Note that input_file.c hand checks for '#' at the beginning of the
00716    first line of the input file.  This is because the compiler outputs
00717    #NO_APP at the beginning of its output.  */
00718 /* Also note that comments like this one will always work.  */
00719 const char line_comment_chars[] = "#";
00720 
00721 const char line_separator_chars[] = ";";
00722 
00723 /* Chars that can be used to separate mant
00724    from exp in floating point numbers.    */
00725 const char EXP_CHARS[] = "eE";
00726 
00727 /* Chars that mean this number is a floating point constant.  */
00728 /* As in 0f12.456  */
00729 /* or   0d1.2345e12  */
00730 
00731 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
00732 
00733 /* Prefix characters that indicate the start of an immediate
00734    value.  */
00735 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
00736 
00737 /* Separator character handling.  */
00738 
00739 #define skip_whitespace(str)  do { if (*(str) == ' ') ++(str); } while (0)
00740 
00741 static inline int
00742 skip_past_char (char ** str, char c)
00743 {
00744   if (**str == c)
00745     {
00746       (*str)++;
00747       return SUCCESS;
00748     }
00749   else
00750     return FAIL;
00751 }
00752 #define skip_past_comma(str) skip_past_char (str, ',')
00753 
00754 /* Arithmetic expressions (possibly involving symbols).  */
00755 
00756 /* Return TRUE if anything in the expression is a bignum.  */
00757 
00758 static int
00759 walk_no_bignums (symbolS * sp)
00760 {
00761   if (symbol_get_value_expression (sp)->X_op == O_big)
00762     return 1;
00763 
00764   if (symbol_get_value_expression (sp)->X_add_symbol)
00765     {
00766       return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
00767              || (symbol_get_value_expression (sp)->X_op_symbol
00768                 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
00769     }
00770 
00771   return 0;
00772 }
00773 
00774 static int in_my_get_expression = 0;
00775 
00776 /* Third argument to my_get_expression.    */
00777 #define GE_NO_PREFIX 0
00778 #define GE_IMM_PREFIX 1
00779 #define GE_OPT_PREFIX 2
00780 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
00781    immediates, as can be used in Neon VMVN and VMOV immediate instructions.  */
00782 #define GE_OPT_PREFIX_BIG 3
00783 
00784 static int
00785 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
00786 {
00787   char * save_in;
00788   segT  seg;
00789 
00790   /* In unified syntax, all prefixes are optional.  */
00791   if (unified_syntax)
00792     prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
00793                   : GE_OPT_PREFIX;
00794 
00795   switch (prefix_mode)
00796     {
00797     case GE_NO_PREFIX: break;
00798     case GE_IMM_PREFIX:
00799       if (!is_immediate_prefix (**str))
00800        {
00801          inst.error = _("immediate expression requires a # prefix");
00802          return FAIL;
00803        }
00804       (*str)++;
00805       break;
00806     case GE_OPT_PREFIX:
00807     case GE_OPT_PREFIX_BIG:
00808       if (is_immediate_prefix (**str))
00809        (*str)++;
00810       break;
00811     default: abort ();
00812     }
00813 
00814   memset (ep, 0, sizeof (expressionS));
00815 
00816   save_in = input_line_pointer;
00817   input_line_pointer = *str;
00818   in_my_get_expression = 1;
00819   seg = expression (ep);
00820   in_my_get_expression = 0;
00821 
00822   if (ep->X_op == O_illegal)
00823     {
00824       /* We found a bad expression in md_operand().  */
00825       *str = input_line_pointer;
00826       input_line_pointer = save_in;
00827       if (inst.error == NULL)
00828        inst.error = _("bad expression");
00829       return 1;
00830     }
00831 
00832 #ifdef OBJ_AOUT
00833   if (seg != absolute_section
00834       && seg != text_section
00835       && seg != data_section
00836       && seg != bss_section
00837       && seg != undefined_section)
00838     {
00839       inst.error = _("bad segment");
00840       *str = input_line_pointer;
00841       input_line_pointer = save_in;
00842       return 1;
00843     }
00844 #endif
00845 
00846   /* Get rid of any bignums now, so that we don't generate an error for which
00847      we can't establish a line number later on.   Big numbers are never valid
00848      in instructions, which is where this routine is always called.  */
00849   if (prefix_mode != GE_OPT_PREFIX_BIG
00850       && (ep->X_op == O_big
00851           || (ep->X_add_symbol
00852              && (walk_no_bignums (ep->X_add_symbol)
00853                  || (ep->X_op_symbol
00854                     && walk_no_bignums (ep->X_op_symbol))))))
00855     {
00856       inst.error = _("invalid constant");
00857       *str = input_line_pointer;
00858       input_line_pointer = save_in;
00859       return 1;
00860     }
00861 
00862   *str = input_line_pointer;
00863   input_line_pointer = save_in;
00864   return 0;
00865 }
00866 
00867 /* Turn a string in input_line_pointer into a floating point constant
00868    of type TYPE, and store the appropriate bytes in *LITP.  The number
00869    of LITTLENUMS emitted is stored in *SIZEP.  An error message is
00870    returned, or NULL on OK.
00871 
00872    Note that fp constants aren't represent in the normal way on the ARM.
00873    In big endian mode, things are as expected.   However, in little endian
00874    mode fp constants are big-endian word-wise, and little-endian byte-wise
00875    within the words.  For example, (double) 1.1 in big endian mode is
00876    the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
00877    the byte sequence 99 99 f1 3f 9a 99 99 99.
00878 
00879    ??? The format of 12 byte floats is uncertain according to gcc's arm.h.  */
00880 
00881 char *
00882 md_atof (int type, char * litP, int * sizeP)
00883 {
00884   int prec;
00885   LITTLENUM_TYPE words[MAX_LITTLENUMS];
00886   char *t;
00887   int i;
00888 
00889   switch (type)
00890     {
00891     case 'f':
00892     case 'F':
00893     case 's':
00894     case 'S':
00895       prec = 2;
00896       break;
00897 
00898     case 'd':
00899     case 'D':
00900     case 'r':
00901     case 'R':
00902       prec = 4;
00903       break;
00904 
00905     case 'x':
00906     case 'X':
00907       prec = 6;
00908       break;
00909 
00910     case 'p':
00911     case 'P':
00912       prec = 6;
00913       break;
00914 
00915     default:
00916       *sizeP = 0;
00917       return _("bad call to MD_ATOF()");
00918     }
00919 
00920   t = atof_ieee (input_line_pointer, type, words);
00921   if (t)
00922     input_line_pointer = t;
00923   *sizeP = prec * 2;
00924 
00925   if (target_big_endian)
00926     {
00927       for (i = 0; i < prec; i++)
00928        {
00929          md_number_to_chars (litP, (valueT) words[i], 2);
00930          litP += 2;
00931        }
00932     }
00933   else
00934     {
00935       if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
00936        for (i = prec - 1; i >= 0; i--)
00937          {
00938            md_number_to_chars (litP, (valueT) words[i], 2);
00939            litP += 2;
00940          }
00941       else
00942        /* For a 4 byte float the order of elements in `words' is 1 0.
00943           For an 8 byte float the order is 1 0 3 2.  */
00944        for (i = 0; i < prec; i += 2)
00945          {
00946            md_number_to_chars (litP, (valueT) words[i + 1], 2);
00947            md_number_to_chars (litP + 2, (valueT) words[i], 2);
00948            litP += 4;
00949          }
00950     }
00951 
00952   return 0;
00953 }
00954 
00955 /* We handle all bad expressions here, so that we can report the faulty
00956    instruction in the error message.  */
00957 void
00958 md_operand (expressionS * expr)
00959 {
00960   if (in_my_get_expression)
00961     expr->X_op = O_illegal;
00962 }
00963 
00964 /* Immediate values.  */
00965 
00966 /* Generic immediate-value read function for use in directives.
00967    Accepts anything that 'expression' can fold to a constant.
00968    *val receives the number.  */
00969 #ifdef OBJ_ELF
00970 static int
00971 immediate_for_directive (int *val)
00972 {
00973   expressionS exp;
00974   exp.X_op = O_illegal;
00975 
00976   if (is_immediate_prefix (*input_line_pointer))
00977     {
00978       input_line_pointer++;
00979       expression (&exp);
00980     }
00981 
00982   if (exp.X_op != O_constant)
00983     {
00984       as_bad (_("expected #constant"));
00985       ignore_rest_of_line ();
00986       return FAIL;
00987     }
00988   *val = exp.X_add_number;
00989   return SUCCESS;
00990 }
00991 #endif
00992 
00993 /* Register parsing.  */
00994 
00995 /* Generic register parser.  CCP points to what should be the
00996    beginning of a register name.  If it is indeed a valid register
00997    name, advance CCP over it and return the reg_entry structure;
00998    otherwise return NULL.  Does not issue diagnostics.  */
00999 
01000 static struct reg_entry *
01001 arm_reg_parse_multi (char **ccp)
01002 {
01003   char *start = *ccp;
01004   char *p;
01005   struct reg_entry *reg;
01006 
01007 #ifdef REGISTER_PREFIX
01008   if (*start != REGISTER_PREFIX)
01009     return NULL;
01010   start++;
01011 #endif
01012 #ifdef OPTIONAL_REGISTER_PREFIX
01013   if (*start == OPTIONAL_REGISTER_PREFIX)
01014     start++;
01015 #endif
01016 
01017   p = start;
01018   if (!ISALPHA (*p) || !is_name_beginner (*p))
01019     return NULL;
01020 
01021   do
01022     p++;
01023   while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
01024 
01025   reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
01026 
01027   if (!reg)
01028     return NULL;
01029 
01030   *ccp = p;
01031   return reg;
01032 }
01033 
01034 static int
01035 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
01036                     enum arm_reg_type type)
01037 {
01038   /* Alternative syntaxes are accepted for a few register classes.  */
01039   switch (type)
01040     {
01041     case REG_TYPE_MVF:
01042     case REG_TYPE_MVD:
01043     case REG_TYPE_MVFX:
01044     case REG_TYPE_MVDX:
01045       /* Generic coprocessor register names are allowed for these.  */
01046       if (reg && reg->type == REG_TYPE_CN)
01047        return reg->number;
01048       break;
01049 
01050     case REG_TYPE_CP:
01051       /* For backward compatibility, a bare number is valid here.  */
01052       {
01053        unsigned long processor = strtoul (start, ccp, 10);
01054        if (*ccp != start && processor <= 15)
01055          return processor;
01056       }
01057 
01058     case REG_TYPE_MMXWC:
01059       /* WC includes WCG.  ??? I'm not sure this is true for all
01060         instructions that take WC registers.  */
01061       if (reg && reg->type == REG_TYPE_MMXWCG)
01062        return reg->number;
01063       break;
01064 
01065     default:
01066       break;
01067     }
01068 
01069   return FAIL;
01070 }
01071 
01072 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
01073    return value is the register number or FAIL.  */
01074 
01075 static int
01076 arm_reg_parse (char **ccp, enum arm_reg_type type)
01077 {
01078   char *start = *ccp;
01079   struct reg_entry *reg = arm_reg_parse_multi (ccp);
01080   int ret;
01081 
01082   /* Do not allow a scalar (reg+index) to parse as a register.  */
01083   if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
01084     return FAIL;
01085 
01086   if (reg && reg->type == type)
01087     return reg->number;
01088 
01089   if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
01090     return ret;
01091 
01092   *ccp = start;
01093   return FAIL;
01094 }
01095 
01096 /* Parse a Neon type specifier. *STR should point at the leading '.'
01097    character. Does no verification at this stage that the type fits the opcode
01098    properly. E.g.,
01099 
01100      .i32.i32.s16
01101      .s32.f32
01102      .u16
01103 
01104    Can all be legally parsed by this function.
01105 
01106    Fills in neon_type struct pointer with parsed information, and updates STR
01107    to point after the parsed type specifier. Returns SUCCESS if this was a legal
01108    type, FAIL if not.  */
01109 
01110 static int
01111 parse_neon_type (struct neon_type *type, char **str)
01112 {
01113   char *ptr = *str;
01114 
01115   if (type)
01116     type->elems = 0;
01117 
01118   while (type->elems < NEON_MAX_TYPE_ELS)
01119     {
01120       enum neon_el_type thistype = NT_untyped;
01121       unsigned thissize = -1u;
01122 
01123       if (*ptr != '.')
01124        break;
01125 
01126       ptr++;
01127 
01128       /* Just a size without an explicit type.  */
01129       if (ISDIGIT (*ptr))
01130        goto parsesize;
01131 
01132       switch (TOLOWER (*ptr))
01133        {
01134        case 'i': thistype = NT_integer; break;
01135        case 'f': thistype = NT_float; break;
01136        case 'p': thistype = NT_poly; break;
01137        case 's': thistype = NT_signed; break;
01138        case 'u': thistype = NT_unsigned; break;
01139         case 'd':
01140           thistype = NT_float;
01141           thissize = 64;
01142           ptr++;
01143           goto done;
01144        default:
01145          as_bad (_("unexpected character `%c' in type specifier"), *ptr);
01146          return FAIL;
01147        }
01148 
01149       ptr++;
01150 
01151       /* .f is an abbreviation for .f32.  */
01152       if (thistype == NT_float && !ISDIGIT (*ptr))
01153        thissize = 32;
01154       else
01155        {
01156        parsesize:
01157          thissize = strtoul (ptr, &ptr, 10);
01158 
01159          if (thissize != 8 && thissize != 16 && thissize != 32
01160               && thissize != 64)
01161             {
01162               as_bad (_("bad size %d in type specifier"), thissize);
01163              return FAIL;
01164            }
01165        }
01166 
01167       done:
01168       if (type)
01169         {
01170           type->el[type->elems].type = thistype;
01171          type->el[type->elems].size = thissize;
01172          type->elems++;
01173        }
01174     }
01175 
01176   /* Empty/missing type is not a successful parse.  */
01177   if (type->elems == 0)
01178     return FAIL;
01179 
01180   *str = ptr;
01181 
01182   return SUCCESS;
01183 }
01184 
01185 /* Errors may be set multiple times during parsing or bit encoding
01186    (particularly in the Neon bits), but usually the earliest error which is set
01187    will be the most meaningful. Avoid overwriting it with later (cascading)
01188    errors by calling this function.  */
01189 
01190 static void
01191 first_error (const char *err)
01192 {
01193   if (!inst.error)
01194     inst.error = err;
01195 }
01196 
01197 /* Parse a single type, e.g. ".s32", leading period included.  */
01198 static int
01199 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
01200 {
01201   char *str = *ccp;
01202   struct neon_type optype;
01203 
01204   if (*str == '.')
01205     {
01206       if (parse_neon_type (&optype, &str) == SUCCESS)
01207         {
01208           if (optype.elems == 1)
01209             *vectype = optype.el[0];
01210           else
01211             {
01212               first_error (_("only one type should be specified for operand"));
01213               return FAIL;
01214             }
01215         }
01216       else
01217         {
01218           first_error (_("vector type expected"));
01219           return FAIL;
01220         }
01221     }
01222   else
01223     return FAIL;
01224   
01225   *ccp = str;
01226   
01227   return SUCCESS;
01228 }
01229 
01230 /* Special meanings for indices (which have a range of 0-7), which will fit into
01231    a 4-bit integer.  */
01232 
01233 #define NEON_ALL_LANES             15
01234 #define NEON_INTERLEAVE_LANES      14
01235 
01236 /* Parse either a register or a scalar, with an optional type. Return the
01237    register number, and optionally fill in the actual type of the register
01238    when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
01239    type/index information in *TYPEINFO.  */
01240 
01241 static int
01242 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
01243                            enum arm_reg_type *rtype,
01244                            struct neon_typed_alias *typeinfo)
01245 {
01246   char *str = *ccp;
01247   struct reg_entry *reg = arm_reg_parse_multi (&str);
01248   struct neon_typed_alias atype;
01249   struct neon_type_el parsetype;
01250 
01251   atype.defined = 0;
01252   atype.index = -1;
01253   atype.eltype.type = NT_invtype;
01254   atype.eltype.size = -1;
01255 
01256   /* Try alternate syntax for some types of register. Note these are mutually
01257      exclusive with the Neon syntax extensions.  */
01258   if (reg == NULL)
01259     {
01260       int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
01261       if (altreg != FAIL)
01262         *ccp = str;
01263       if (typeinfo)
01264         *typeinfo = atype;
01265       return altreg;
01266     }
01267 
01268   /* Undo polymorphism when a set of register types may be accepted.  */
01269   if ((type == REG_TYPE_NDQ
01270        && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
01271       || (type == REG_TYPE_VFSD
01272           && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
01273       || (type == REG_TYPE_NSDQ
01274           && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
01275               || reg->type == REG_TYPE_NQ))
01276       || (type == REG_TYPE_MMXWC
01277          && (reg->type == REG_TYPE_MMXWCG)))
01278     type = reg->type;
01279 
01280   if (type != reg->type)
01281     return FAIL;
01282 
01283   if (reg->neon)
01284     atype = *reg->neon;
01285   
01286   if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
01287     {
01288       if ((atype.defined & NTA_HASTYPE) != 0)
01289         {
01290           first_error (_("can't redefine type for operand"));
01291           return FAIL;
01292         }
01293       atype.defined |= NTA_HASTYPE;
01294       atype.eltype = parsetype;
01295     }
01296     
01297   if (skip_past_char (&str, '[') == SUCCESS)
01298     {
01299       if (type != REG_TYPE_VFD)
01300         {
01301           first_error (_("only D registers may be indexed"));
01302           return FAIL;
01303         }
01304     
01305       if ((atype.defined & NTA_HASINDEX) != 0)
01306         {
01307           first_error (_("can't change index for operand"));
01308           return FAIL;
01309         }
01310 
01311       atype.defined |= NTA_HASINDEX;
01312 
01313       if (skip_past_char (&str, ']') == SUCCESS)
01314         atype.index = NEON_ALL_LANES;
01315       else
01316         {
01317           expressionS exp;
01318 
01319           my_get_expression (&exp, &str, GE_NO_PREFIX);
01320 
01321           if (exp.X_op != O_constant)
01322             {
01323               first_error (_("constant expression required"));
01324               return FAIL;
01325             }
01326 
01327           if (skip_past_char (&str, ']') == FAIL)
01328             return FAIL;
01329 
01330           atype.index = exp.X_add_number;
01331         }
01332     }
01333   
01334   if (typeinfo)
01335     *typeinfo = atype;
01336   
01337   if (rtype)
01338     *rtype = type;
01339   
01340   *ccp = str;
01341   
01342   return reg->number;
01343 }
01344 
01345 /* Like arm_reg_parse, but allow allow the following extra features:
01346     - If RTYPE is non-zero, return the (possibly restricted) type of the
01347       register (e.g. Neon double or quad reg when either has been requested).
01348     - If this is a Neon vector type with additional type information, fill
01349       in the struct pointed to by VECTYPE (if non-NULL).
01350    This function will fault on encountering a scalar.
01351 */
01352 
01353 static int
01354 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
01355                      enum arm_reg_type *rtype, struct neon_type_el *vectype)
01356 {
01357   struct neon_typed_alias atype;
01358   char *str = *ccp;
01359   int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
01360 
01361   if (reg == FAIL)
01362     return FAIL;
01363 
01364   /* Do not allow a scalar (reg+index) to parse as a register.  */
01365   if ((atype.defined & NTA_HASINDEX) != 0)
01366     {
01367       first_error (_("register operand expected, but got scalar"));
01368       return FAIL;
01369     }
01370 
01371   if (vectype)
01372     *vectype = atype.eltype;
01373 
01374   *ccp = str;
01375 
01376   return reg;
01377 }
01378 
01379 #define NEON_SCALAR_REG(X)  ((X) >> 4)
01380 #define NEON_SCALAR_INDEX(X)       ((X) & 15)
01381 
01382 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
01383    have enough information to be able to do a good job bounds-checking. So, we
01384    just do easy checks here, and do further checks later.  */
01385 
01386 static int
01387 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
01388 {
01389   int reg;
01390   char *str = *ccp;
01391   struct neon_typed_alias atype;
01392   
01393   reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
01394   
01395   if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
01396     return FAIL;
01397   
01398   if (atype.index == NEON_ALL_LANES)
01399     {
01400       first_error (_("scalar must have an index"));
01401       return FAIL;
01402     }
01403   else if (atype.index >= 64 / elsize)
01404     {
01405       first_error (_("scalar index out of range"));
01406       return FAIL;
01407     }
01408   
01409   if (type)
01410     *type = atype.eltype;
01411   
01412   *ccp = str;
01413   
01414   return reg * 16 + atype.index;
01415 }
01416 
01417 /* Parse an ARM register list.  Returns the bitmask, or FAIL.  */
01418 static long
01419 parse_reg_list (char ** strp)
01420 {
01421   char * str = * strp;
01422   long  range = 0;
01423   int   another_range;
01424 
01425   /* We come back here if we get ranges concatenated by '+' or '|'.  */
01426   do
01427     {
01428       another_range = 0;
01429 
01430       if (*str == '{')
01431        {
01432          int in_range = 0;
01433          int cur_reg = -1;
01434 
01435          str++;
01436          do
01437            {
01438              int reg;
01439 
01440              if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
01441               {
01442                 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
01443                 return FAIL;
01444               }
01445 
01446              if (in_range)
01447               {
01448                 int i;
01449 
01450                 if (reg <= cur_reg)
01451                   {
01452                     first_error (_("bad range in register list"));
01453                     return FAIL;
01454                   }
01455 
01456                 for (i = cur_reg + 1; i < reg; i++)
01457                   {
01458                     if (range & (1 << i))
01459                      as_tsktsk
01460                        (_("Warning: duplicated register (r%d) in register list"),
01461                         i);
01462                     else
01463                      range |= 1 << i;
01464                   }
01465                 in_range = 0;
01466               }
01467 
01468              if (range & (1 << reg))
01469               as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
01470                         reg);
01471              else if (reg <= cur_reg)
01472               as_tsktsk (_("Warning: register range not in ascending order"));
01473 
01474              range |= 1 << reg;
01475              cur_reg = reg;
01476            }
01477          while (skip_past_comma (&str) != FAIL
01478                || (in_range = 1, *str++ == '-'));
01479          str--;
01480 
01481          if (*str++ != '}')
01482            {
01483              first_error (_("missing `}'"));
01484              return FAIL;
01485            }
01486        }
01487       else
01488        {
01489          expressionS expr;
01490 
01491          if (my_get_expression (&expr, &str, GE_NO_PREFIX))
01492            return FAIL;
01493 
01494          if (expr.X_op == O_constant)
01495            {
01496              if (expr.X_add_number
01497                 != (expr.X_add_number & 0x0000ffff))
01498               {
01499                 inst.error = _("invalid register mask");
01500                 return FAIL;
01501               }
01502 
01503              if ((range & expr.X_add_number) != 0)
01504               {
01505                 int regno = range & expr.X_add_number;
01506 
01507                 regno &= -regno;
01508                 regno = (1 << regno) - 1;
01509                 as_tsktsk
01510                   (_("Warning: duplicated register (r%d) in register list"),
01511                    regno);
01512               }
01513 
01514              range |= expr.X_add_number;
01515            }
01516          else
01517            {
01518              if (inst.reloc.type != 0)
01519               {
01520                 inst.error = _("expression too complex");
01521                 return FAIL;
01522               }
01523 
01524              memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
01525              inst.reloc.type = BFD_RELOC_ARM_MULTI;
01526              inst.reloc.pc_rel = 0;
01527            }
01528        }
01529 
01530       if (*str == '|' || *str == '+')
01531        {
01532          str++;
01533          another_range = 1;
01534        }
01535     }
01536   while (another_range);
01537 
01538   *strp = str;
01539   return range;
01540 }
01541 
01542 /* Types of registers in a list.  */
01543 
01544 enum reg_list_els
01545 {
01546   REGLIST_VFP_S,
01547   REGLIST_VFP_D,
01548   REGLIST_NEON_D
01549 };
01550 
01551 /* Parse a VFP register list.  If the string is invalid return FAIL.
01552    Otherwise return the number of registers, and set PBASE to the first
01553    register.  Parses registers of type ETYPE.
01554    If REGLIST_NEON_D is used, several syntax enhancements are enabled:
01555      - Q registers can be used to specify pairs of D registers
01556      - { } can be omitted from around a singleton register list
01557          FIXME: This is not implemented, as it would require backtracking in
01558          some cases, e.g.:
01559            vtbl.8 d3,d4,d5
01560          This could be done (the meaning isn't really ambiguous), but doesn't
01561          fit in well with the current parsing framework.
01562      - 32 D registers may be used (also true for VFPv3).
01563    FIXME: Types are ignored in these register lists, which is probably a
01564    bug.  */
01565 
01566 static int
01567 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
01568 {
01569   char *str = *ccp;
01570   int base_reg;
01571   int new_base;
01572   enum arm_reg_type regtype = 0;
01573   int max_regs = 0;
01574   int count = 0;
01575   int warned = 0;
01576   unsigned long mask = 0;
01577   int i;
01578 
01579   if (*str != '{')
01580     {
01581       inst.error = _("expecting {");
01582       return FAIL;
01583     }
01584 
01585   str++;
01586 
01587   switch (etype)
01588     {
01589     case REGLIST_VFP_S:
01590       regtype = REG_TYPE_VFS;
01591       max_regs = 32;
01592       break;
01593     
01594     case REGLIST_VFP_D:
01595       regtype = REG_TYPE_VFD;
01596       break;
01597     
01598     case REGLIST_NEON_D:
01599       regtype = REG_TYPE_NDQ;
01600       break;
01601     }
01602 
01603   if (etype != REGLIST_VFP_S)
01604     {
01605       /* VFPv3 allows 32 D registers.  */
01606       if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
01607         {
01608           max_regs = 32;
01609           if (thumb_mode)
01610             ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
01611                                     fpu_vfp_ext_v3);
01612           else
01613             ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
01614                                     fpu_vfp_ext_v3);
01615         }
01616       else
01617         max_regs = 16;
01618     }
01619 
01620   base_reg = max_regs;
01621 
01622   do
01623     {
01624       int setmask = 1, addregs = 1;
01625 
01626       new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
01627 
01628       if (new_base == FAIL)
01629        {
01630          first_error (_(reg_expected_msgs[regtype]));
01631          return FAIL;
01632        }
01633  
01634       if (new_base >= max_regs)
01635         {
01636           first_error (_("register out of range in list"));
01637           return FAIL;
01638         }
01639  
01640       /* Note: a value of 2 * n is returned for the register Q<n>.  */
01641       if (regtype == REG_TYPE_NQ)
01642         {
01643           setmask = 3;
01644           addregs = 2;
01645         }
01646 
01647       if (new_base < base_reg)
01648        base_reg = new_base;
01649 
01650       if (mask & (setmask << new_base))
01651        {
01652          first_error (_("invalid register list"));
01653          return FAIL;
01654        }
01655 
01656       if ((mask >> new_base) != 0 && ! warned)
01657        {
01658          as_tsktsk (_("register list not in ascending order"));
01659          warned = 1;
01660        }
01661 
01662       mask |= setmask << new_base;
01663       count += addregs;
01664 
01665       if (*str == '-') /* We have the start of a range expression */
01666        {
01667          int high_range;
01668 
01669          str++;
01670 
01671          if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
01672               == FAIL)
01673            {
01674              inst.error = gettext (reg_expected_msgs[regtype]);
01675              return FAIL;
01676            }
01677 
01678           if (high_range >= max_regs)
01679             {
01680               first_error (_("register out of range in list"));
01681               return FAIL;
01682             }
01683 
01684           if (regtype == REG_TYPE_NQ)
01685             high_range = high_range + 1;
01686 
01687          if (high_range <= new_base)
01688            {
01689              inst.error = _("register range not in ascending order");
01690              return FAIL;
01691            }
01692 
01693          for (new_base += addregs; new_base <= high_range; new_base += addregs)
01694            {
01695              if (mask & (setmask << new_base))
01696               {
01697                 inst.error = _("invalid register list");
01698                 return FAIL;
01699               }
01700 
01701              mask |= setmask << new_base;
01702              count += addregs;
01703            }
01704        }
01705     }
01706   while (skip_past_comma (&str) != FAIL);
01707 
01708   str++;
01709 
01710   /* Sanity check -- should have raised a parse error above.  */
01711   if (count == 0 || count > max_regs)
01712     abort ();
01713 
01714   *pbase = base_reg;
01715 
01716   /* Final test -- the registers must be consecutive.  */
01717   mask >>= base_reg;
01718   for (i = 0; i < count; i++)
01719     {
01720       if ((mask & (1u << i)) == 0)
01721        {
01722          inst.error = _("non-contiguous register range");
01723          return FAIL;
01724        }
01725     }
01726 
01727   *ccp = str;
01728 
01729   return count;
01730 }
01731 
01732 /* True if two alias types are the same.  */
01733 
01734 static int
01735 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
01736 {
01737   if (!a && !b)
01738     return 1;
01739     
01740   if (!a || !b)
01741     return 0;
01742 
01743   if (a->defined != b->defined)
01744     return 0;
01745   
01746   if ((a->defined & NTA_HASTYPE) != 0
01747       && (a->eltype.type != b->eltype.type
01748           || a->eltype.size != b->eltype.size))
01749     return 0;
01750 
01751   if ((a->defined & NTA_HASINDEX) != 0
01752       && (a->index != b->index))
01753     return 0;
01754   
01755   return 1;
01756 }
01757 
01758 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
01759    The base register is put in *PBASE.
01760    The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
01761    the return value.
01762    The register stride (minus one) is put in bit 4 of the return value.
01763    Bits [6:5] encode the list length (minus one).
01764    The type of the list elements is put in *ELTYPE, if non-NULL.  */
01765 
01766 #define NEON_LANE(X)        ((X) & 0xf)
01767 #define NEON_REG_STRIDE(X)  ((((X) >> 4) & 1) + 1)
01768 #define NEON_REGLIST_LENGTH(X)     ((((X) >> 5) & 3) + 1)
01769 
01770 static int
01771 parse_neon_el_struct_list (char **str, unsigned *pbase,
01772                            struct neon_type_el *eltype)
01773 {
01774   char *ptr = *str;
01775   int base_reg = -1;
01776   int reg_incr = -1;
01777   int count = 0;
01778   int lane = -1;
01779   int leading_brace = 0;
01780   enum arm_reg_type rtype = REG_TYPE_NDQ;
01781   int addregs = 1;
01782   const char *const incr_error = "register stride must be 1 or 2";
01783   const char *const type_error = "mismatched element/structure types in list";
01784   struct neon_typed_alias firsttype;
01785   
01786   if (skip_past_char (&ptr, '{') == SUCCESS)
01787     leading_brace = 1;
01788   
01789   do
01790     {
01791       struct neon_typed_alias atype;
01792       int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
01793 
01794       if (getreg == FAIL)
01795         {
01796           first_error (_(reg_expected_msgs[rtype]));
01797           return FAIL;
01798         }
01799       
01800       if (base_reg == -1)
01801         {
01802           base_reg = getreg;
01803           if (rtype == REG_TYPE_NQ)
01804             {
01805               reg_incr = 1;
01806               addregs = 2;
01807             }
01808           firsttype = atype;
01809         }
01810       else if (reg_incr == -1)
01811         {
01812           reg_incr = getreg - base_reg;
01813           if (reg_incr < 1 || reg_incr > 2)
01814             {
01815               first_error (_(incr_error));
01816               return FAIL;
01817             }
01818         }
01819       else if (getreg != base_reg + reg_incr * count)
01820         {
01821           first_error (_(incr_error));
01822           return FAIL;
01823         }
01824 
01825       if (!neon_alias_types_same (&atype, &firsttype))
01826         {
01827           first_error (_(type_error));
01828           return FAIL;
01829         }
01830       
01831       /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
01832          modes.  */
01833       if (ptr[0] == '-')
01834         {
01835           struct neon_typed_alias htype;
01836           int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
01837           if (lane == -1)
01838             lane = NEON_INTERLEAVE_LANES;
01839           else if (lane != NEON_INTERLEAVE_LANES)
01840             {
01841               first_error (_(type_error));
01842               return FAIL;
01843             }
01844           if (reg_incr == -1)
01845             reg_incr = 1;
01846           else if (reg_incr != 1)
01847             {
01848               first_error (_("don't use Rn-Rm syntax with non-unit stride"));
01849               return FAIL;
01850             }
01851           ptr++;
01852           hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
01853           if (hireg == FAIL)
01854             {
01855               first_error (_(reg_expected_msgs[rtype]));
01856               return FAIL;
01857             }
01858           if (!neon_alias_types_same (&htype, &firsttype))
01859             {
01860               first_error (_(type_error));
01861               return FAIL;
01862             }
01863           count += hireg + dregs - getreg;
01864           continue;
01865         }
01866       
01867       /* If we're using Q registers, we can't use [] or [n] syntax.  */
01868       if (rtype == REG_TYPE_NQ)
01869         {
01870           count += 2;
01871           continue;
01872         }
01873       
01874       if ((atype.defined & NTA_HASINDEX) != 0)
01875         {
01876           if (lane == -1)
01877             lane = atype.index;
01878           else if (lane != atype.index)
01879             {
01880               first_error (_(type_error));
01881               return FAIL;
01882             }
01883         }
01884       else if (lane == -1)
01885         lane = NEON_INTERLEAVE_LANES;
01886       else if (lane != NEON_INTERLEAVE_LANES)
01887         {
01888           first_error (_(type_error));
01889           return FAIL;
01890         }
01891       count++;
01892     }
01893   while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
01894   
01895   /* No lane set by [x]. We must be interleaving structures.  */
01896   if (lane == -1)
01897     lane = NEON_INTERLEAVE_LANES;
01898   
01899   /* Sanity check.  */
01900   if (lane == -1 || base_reg == -1 || count < 1 || count > 4
01901       || (count > 1 && reg_incr == -1))
01902     {
01903       first_error (_("error parsing element/structure list"));
01904       return FAIL;
01905     }
01906 
01907   if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
01908     {
01909       first_error (_("expected }"));
01910       return FAIL;
01911     }
01912   
01913   if (reg_incr == -1)
01914     reg_incr = 1;
01915 
01916   if (eltype)
01917     *eltype = firsttype.eltype;
01918 
01919   *pbase = base_reg;
01920   *str = ptr;
01921   
01922   return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
01923 }
01924 
01925 /* Parse an explicit relocation suffix on an expression.  This is
01926    either nothing, or a word in parentheses.  Note that if !OBJ_ELF,
01927    arm_reloc_hsh contains no entries, so this function can only
01928    succeed if there is no () after the word.  Returns -1 on error,
01929    BFD_RELOC_UNUSED if there wasn't any suffix.   */
01930 static int
01931 parse_reloc (char **str)
01932 {
01933   struct reloc_entry *r;
01934   char *p, *q;
01935 
01936   if (**str != '(')
01937     return BFD_RELOC_UNUSED;
01938 
01939   p = *str + 1;
01940   q = p;
01941 
01942   while (*q && *q != ')' && *q != ',')
01943     q++;
01944   if (*q != ')')
01945     return -1;
01946 
01947   if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
01948     return -1;
01949 
01950   *str = q + 1;
01951   return r->reloc;
01952 }
01953 
01954 /* Directives: register aliases.  */
01955 
01956 static struct reg_entry *
01957 insert_reg_alias (char *str, int number, int type)
01958 {
01959   struct reg_entry *new;
01960   const char *name;
01961 
01962   if ((new = hash_find (arm_reg_hsh, str)) != 0)
01963     {
01964       if (new->builtin)
01965        as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
01966 
01967       /* Only warn about a redefinition if it's not defined as the
01968         same register.       */
01969       else if (new->number != number || new->type != type)
01970        as_warn (_("ignoring redefinition of register alias '%s'"), str);
01971 
01972       return 0;
01973     }
01974 
01975   name = xstrdup (str);
01976   new = xmalloc (sizeof (struct reg_entry));
01977 
01978   new->name = name;
01979   new->number = number;
01980   new->type = type;
01981   new->builtin = FALSE;
01982   new->neon = NULL;
01983 
01984   if (hash_insert (arm_reg_hsh, name, (PTR) new))
01985     abort ();
01986   
01987   return new;
01988 }
01989 
01990 static void
01991 insert_neon_reg_alias (char *str, int number, int type,
01992                        struct neon_typed_alias *atype)
01993 {
01994   struct reg_entry *reg = insert_reg_alias (str, number, type);
01995   
01996   if (!reg)
01997     {
01998       first_error (_("attempt to redefine typed alias"));
01999       return;
02000     }
02001   
02002   if (atype)
02003     {
02004       reg->neon = xmalloc (sizeof (struct neon_typed_alias));
02005       *reg->neon = *atype;
02006     }
02007 }
02008 
02009 /* Look for the .req directive.     This is of the form:
02010 
02011        new_register_name .req existing_register_name
02012 
02013    If we find one, or if it looks sufficiently like one that we want to
02014    handle any error here, return non-zero.  Otherwise return zero.  */
02015 
02016 static int
02017 create_register_alias (char * newname, char *p)
02018 {
02019   struct reg_entry *old;
02020   char *oldname, *nbuf;
02021   size_t nlen;
02022 
02023   /* The input scrubber ensures that whitespace after the mnemonic is
02024      collapsed to single spaces.  */
02025   oldname = p;
02026   if (strncmp (oldname, " .req ", 6) != 0)
02027     return 0;
02028 
02029   oldname += 6;
02030   if (*oldname == '\0')
02031     return 0;
02032 
02033   old = hash_find (arm_reg_hsh, oldname);
02034   if (!old)
02035     {
02036       as_warn (_("unknown register '%s' -- .req ignored"), oldname);
02037       return 1;
02038     }
02039 
02040   /* If TC_CASE_SENSITIVE is defined, then newname already points to
02041      the desired alias name, and p points to its end.  If not, then
02042      the desired alias name is in the global original_case_string.  */
02043 #ifdef TC_CASE_SENSITIVE
02044   nlen = p - newname;
02045 #else
02046   newname = original_case_string;
02047   nlen = strlen (newname);
02048 #endif
02049 
02050   nbuf = alloca (nlen + 1);
02051   memcpy (nbuf, newname, nlen);
02052   nbuf[nlen] = '\0';
02053 
02054   /* Create aliases under the new name as stated; an all-lowercase
02055      version of the new name; and an all-uppercase version of the new
02056      name.  */
02057   insert_reg_alias (nbuf, old->number, old->type);
02058 
02059   for (p = nbuf; *p; p++)
02060     *p = TOUPPER (*p);
02061 
02062   if (strncmp (nbuf, newname, nlen))
02063     insert_reg_alias (nbuf, old->number, old->type);
02064 
02065   for (p = nbuf; *p; p++)
02066     *p = TOLOWER (*p);
02067 
02068   if (strncmp (nbuf, newname, nlen))
02069     insert_reg_alias (nbuf, old->number, old->type);
02070 
02071   return 1;
02072 }
02073 
02074 /* Create a Neon typed/indexed register alias using directives, e.g.:
02075      X .dn d5.s32[1]
02076      Y .qn 6.s16
02077      Z .dn d7
02078      T .dn Z[0]
02079    These typed registers can be used instead of the types specified after the
02080    Neon mnemonic, so long as all operands given have types. Types can also be
02081    specified directly, e.g.:
02082      vadd d0.s32, d1.s32, d2.s32
02083 */
02084 
02085 static int
02086 create_neon_reg_alias (char *newname, char *p)
02087 {
02088   enum arm_reg_type basetype;
02089   struct reg_entry *basereg;
02090   struct reg_entry mybasereg;
02091   struct neon_type ntype;
02092   struct neon_typed_alias typeinfo;
02093   char *namebuf, *nameend;
02094   int namelen;
02095   
02096   typeinfo.defined = 0;
02097   typeinfo.eltype.type = NT_invtype;
02098   typeinfo.eltype.size = -1;
02099   typeinfo.index = -1;
02100   
02101   nameend = p;
02102   
02103   if (strncmp (p, " .dn ", 5) == 0)
02104     basetype = REG_TYPE_VFD;
02105   else if (strncmp (p, " .qn ", 5) == 0)
02106     basetype = REG_TYPE_NQ;
02107   else
02108     return 0;
02109   
02110   p += 5;
02111   
02112   if (*p == '\0')
02113     return 0;
02114   
02115   basereg = arm_reg_parse_multi (&p);
02116 
02117   if (basereg && basereg->type != basetype)
02118     {
02119       as_bad (_("bad type for register"));
02120       return 0;
02121     }
02122 
02123   if (basereg == NULL)
02124     {
02125       expressionS exp;
02126       /* Try parsing as an integer.  */
02127       my_get_expression (&exp, &p, GE_NO_PREFIX);
02128       if (exp.X_op != O_constant)
02129         {
02130           as_bad (_("expression must be constant"));
02131           return 0;
02132         }
02133       basereg = &mybasereg;
02134       basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
02135                                                   : exp.X_add_number;
02136       basereg->neon = 0;
02137     }
02138 
02139   if (basereg->neon)
02140     typeinfo = *basereg->neon;
02141 
02142   if (parse_neon_type (&ntype, &p) == SUCCESS)
02143     {
02144       /* We got a type.  */
02145       if (typeinfo.defined & NTA_HASTYPE)
02146         {
02147           as_bad (_("can't redefine the type of a register alias"));
02148           return 0;
02149         }
02150       
02151       typeinfo.defined |= NTA_HASTYPE;
02152       if (ntype.elems != 1)
02153         {
02154           as_bad (_("you must specify a single type only"));
02155           return 0;
02156         }
02157       typeinfo.eltype = ntype.el[0];
02158     }
02159   
02160   if (skip_past_char (&p, '[') == SUCCESS)
02161     {
02162       expressionS exp;
02163       /* We got a scalar index.  */
02164     
02165       if (typeinfo.defined & NTA_HASINDEX)
02166         {
02167           as_bad (_("can't redefine the index of a scalar alias"));
02168           return 0;
02169         }
02170     
02171       my_get_expression (&exp, &p, GE_NO_PREFIX);
02172     
02173       if (exp.X_op != O_constant)
02174         {
02175           as_bad (_("scalar index must be constant"));
02176           return 0;
02177         }
02178       
02179       typeinfo.defined |= NTA_HASINDEX;
02180       typeinfo.index = exp.X_add_number;
02181     
02182       if (skip_past_char (&p, ']') == FAIL)
02183         {
02184           as_bad (_("expecting ]"));
02185           return 0;
02186         }
02187     }
02188 
02189   namelen = nameend - newname;
02190   namebuf = alloca (namelen + 1);
02191   strncpy (namebuf, newname, namelen);
02192   namebuf[namelen] = '\0';
02193   
02194   insert_neon_reg_alias (namebuf, basereg->number, basetype,
02195                          typeinfo.defined != 0 ? &typeinfo : NULL);
02196     
02197   /* Insert name in all uppercase.  */
02198   for (p = namebuf; *p; p++)
02199     *p = TOUPPER (*p);
02200   
02201   if (strncmp (namebuf, newname, namelen))
02202     insert_neon_reg_alias (namebuf, basereg->number, basetype,
02203                            typeinfo.defined != 0 ? &typeinfo : NULL);
02204   
02205   /* Insert name in all lowercase.  */
02206   for (p = namebuf; *p; p++)
02207     *p = TOLOWER (*p);
02208   
02209   if (strncmp (namebuf, newname, namelen))
02210     insert_neon_reg_alias (namebuf, basereg->number, basetype,
02211                            typeinfo.defined != 0 ? &typeinfo : NULL);
02212   
02213   return 1;
02214 }
02215 
02216 /* Should never be called, as .req goes between the alias and the
02217    register name, not at the beginning of the line.  */
02218 static void
02219 s_req (int a ATTRIBUTE_UNUSED)
02220 {
02221   as_bad (_("invalid syntax for .req directive"));
02222 }
02223 
02224 static void
02225 s_dn (int a ATTRIBUTE_UNUSED)
02226 {
02227   as_bad (_("invalid syntax for .dn directive"));
02228 }
02229 
02230 static void
02231 s_qn (int a ATTRIBUTE_UNUSED)
02232 {
02233   as_bad (_("invalid syntax for .qn directive"));
02234 }
02235 
02236 /* The .unreq directive deletes an alias which was previously defined
02237    by .req.  For example:
02238 
02239        my_alias .req r11
02240        .unreq my_alias        */
02241 
02242 static void
02243 s_unreq (int a ATTRIBUTE_UNUSED)
02244 {
02245   char * name;
02246   char saved_char;
02247 
02248   name = input_line_pointer;
02249 
02250   while (*input_line_pointer != 0
02251         && *input_line_pointer != ' '
02252         && *input_line_pointer != '\n')
02253     ++input_line_pointer;
02254 
02255   saved_char = *input_line_pointer;
02256   *input_line_pointer = 0;
02257 
02258   if (!*name)
02259     as_bad (_("invalid syntax for .unreq directive"));
02260   else
02261     {
02262       struct reg_entry *reg = hash_find (arm_reg_hsh, name);
02263 
02264       if (!reg)
02265        as_bad (_("unknown register alias '%s'"), name);
02266       else if (reg->builtin)
02267        as_warn (_("ignoring attempt to undefine built-in register '%s'"),
02268                name);
02269       else
02270        {
02271          hash_delete (arm_reg_hsh, name);
02272          free ((char *) reg->name);
02273           if (reg->neon)
02274             free (reg->neon);
02275          free (reg);
02276        }
02277     }
02278 
02279   *input_line_pointer = saved_char;
02280   demand_empty_rest_of_line ();
02281 }
02282 
02283 /* Directives: Instruction set selection.  */
02284 
02285 #ifdef OBJ_ELF
02286 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
02287    (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
02288    Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
02289    and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped.  */
02290 
02291 static enum mstate mapstate = MAP_UNDEFINED;
02292 
02293 void
02294 mapping_state (enum mstate state)
02295 {
02296   symbolS * symbolP;
02297   const char * symname;
02298   int type;
02299 
02300   if (mapstate == state)
02301     /* The mapping symbol has already been emitted.
02302        There is nothing else to do.  */
02303     return;
02304 
02305   mapstate = state;
02306 
02307   switch (state)
02308     {
02309     case MAP_DATA:
02310       symname = "$d";
02311       type = BSF_NO_FLAGS;
02312       break;
02313     case MAP_ARM:
02314       symname = "$a";
02315       type = BSF_NO_FLAGS;
02316       break;
02317     case MAP_THUMB:
02318       symname = "$t";
02319       type = BSF_NO_FLAGS;
02320       break;
02321     case MAP_UNDEFINED:
02322       return;
02323     default:
02324       abort ();
02325     }
02326 
02327   seg_info (now_seg)->tc_segment_info_data.mapstate = state;
02328 
02329   symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
02330   symbol_table_insert (symbolP);
02331   symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
02332 
02333   switch (state)
02334     {
02335     case MAP_ARM:
02336       THUMB_SET_FUNC (symbolP, 0);
02337       ARM_SET_THUMB (symbolP, 0);
02338       ARM_SET_INTERWORK (symbolP, support_interwork);
02339       break;
02340 
02341     case MAP_THUMB:
02342       THUMB_SET_FUNC (symbolP, 1);
02343       ARM_SET_THUMB (symbolP, 1);
02344       ARM_SET_INTERWORK (symbolP, support_interwork);
02345       break;
02346 
02347     case MAP_DATA:
02348     default:
02349       return;
02350     }
02351 }
02352 #else
02353 #define mapping_state(x) /* nothing */
02354 #endif
02355 
02356 /* Find the real, Thumb encoded start of a Thumb function.  */
02357 
02358 static symbolS *
02359 find_real_start (symbolS * symbolP)
02360 {
02361   char *       real_start;
02362   const char * name = S_GET_NAME (symbolP);
02363   symbolS *    new_target;
02364 
02365   /* This definition must agree with the one in gcc/config/arm/thumb.c.       */
02366 #define STUB_NAME ".real_start_of"
02367 
02368   if (name == NULL)
02369     abort ();
02370 
02371   /* The compiler may generate BL instructions to local labels because
02372      it needs to perform a branch to a far away location. These labels
02373      do not have a corresponding ".real_start_of" label.  We check
02374      both for S_IS_LOCAL and for a leading dot, to give a way to bypass
02375      the ".real_start_of" convention for nonlocal branches.  */
02376   if (S_IS_LOCAL (symbolP) || name[0] == '.')
02377     return symbolP;
02378 
02379   real_start = ACONCAT ((STUB_NAME, name, NULL));
02380   new_target = symbol_find (real_start);
02381 
02382   if (new_target == NULL)
02383     {
02384       as_warn ("Failed to find real start of function: %s\n", name);
02385       new_target = symbolP;
02386     }
02387 
02388   return new_target;
02389 }
02390 
02391 static void
02392 opcode_select (int width)
02393 {
02394   switch (width)
02395     {
02396     case 16:
02397       if (! thumb_mode)
02398        {
02399          if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
02400            as_bad (_("selected processor does not support THUMB opcodes"));
02401 
02402          thumb_mode = 1;
02403          /* No need to force the alignment, since we will have been
02404             coming from ARM mode, which is word-aligned.  */
02405          record_alignment (now_seg, 1);
02406        }
02407       mapping_state (MAP_THUMB);
02408       break;
02409 
02410     case 32:
02411       if (thumb_mode)
02412        {
02413          if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
02414            as_bad (_("selected processor does not support ARM opcodes"));
02415 
02416          thumb_mode = 0;
02417 
02418          if (!need_pass_2)
02419            frag_align (2, 0, 0);
02420 
02421          record_alignment (now_seg, 1);
02422        }
02423       mapping_state (MAP_ARM);
02424       break;
02425 
02426     default:
02427       as_bad (_("invalid instruction size selected (%d)"), width);
02428     }
02429 }
02430 
02431 static void
02432 s_arm (int ignore ATTRIBUTE_UNUSED)
02433 {
02434   opcode_select (32);
02435   demand_empty_rest_of_line ();
02436 }
02437 
02438 static void
02439 s_thumb (int ignore ATTRIBUTE_UNUSED)
02440 {
02441   opcode_select (16);
02442   demand_empty_rest_of_line ();
02443 }
02444 
02445 static void
02446 s_code (int unused ATTRIBUTE_UNUSED)
02447 {
02448   int temp;
02449 
02450   temp = get_absolute_expression ();
02451   switch (temp)
02452     {
02453     case 16:
02454     case 32:
02455       opcode_select (temp);
02456       break;
02457 
02458     default:
02459       as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
02460     }
02461 }
02462 
02463 static void
02464 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
02465 {
02466   /* If we are not already in thumb mode go into it, EVEN if
02467      the target processor does not support thumb instructions.
02468      This is used by gcc/config/arm/lib1funcs.asm for example
02469      to compile interworking support functions even if the
02470      target processor should not support interworking.  */
02471   if (! thumb_mode)
02472     {
02473       thumb_mode = 2;
02474       record_alignment (now_seg, 1);
02475     }
02476 
02477   demand_empty_rest_of_line ();
02478 }
02479 
02480 static void
02481 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
02482 {
02483   s_thumb (0);
02484 
02485   /* The following label is the name/address of the start of a Thumb function.
02486      We need to know this for the interworking support.  */
02487   label_is_thumb_function_name = TRUE;
02488 }
02489 
02490 /* Perform a .set directive, but also mark the alias as
02491    being a thumb function.  */
02492 
02493 static void
02494 s_thumb_set (int equiv)
02495 {
02496   /* XXX the following is a duplicate of the code for s_set() in read.c
02497      We cannot just call that code as we need to get at the symbol that
02498      is created.  */
02499   char *    name;
02500   char     delim;
02501   char *    end_name;
02502   symbolS * symbolP;
02503 
02504   /* Especial apologies for the random logic:
02505      This just grew, and could be parsed much more simply!
02506      Dean - in haste.  */
02507   name     = input_line_pointer;
02508   delim           = get_symbol_end ();
02509   end_name  = input_line_pointer;
02510   *end_name = delim;
02511 
02512   if (*input_line_pointer != ',')
02513     {
02514       *end_name = 0;
02515       as_bad (_("expected comma after name \"%s\""), name);
02516       *end_name = delim;
02517       ignore_rest_of_line ();
02518       return;
02519     }
02520 
02521   input_line_pointer++;
02522   *end_name = 0;
02523 
02524   if (name[0] == '.' && name[1] == '\0')
02525     {
02526       /* XXX - this should not happen to .thumb_set.  */
02527       abort ();
02528     }
02529 
02530   if ((symbolP = symbol_find (name)) == NULL
02531       && (symbolP = md_undefined_symbol (name)) == NULL)
02532     {
02533 #ifndef NO_LISTING
02534       /* When doing symbol listings, play games with dummy fragments living
02535         outside the normal fragment chain to record the file and line info
02536         for this symbol.  */
02537       if (listing & LISTING_SYMBOLS)
02538        {
02539          extern struct list_info_struct * listing_tail;
02540          fragS * dummy_frag = xmalloc (sizeof (fragS));
02541 
02542          memset (dummy_frag, 0, sizeof (fragS));
02543          dummy_frag->fr_type = rs_fill;
02544          dummy_frag->line = listing_tail;
02545          symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
02546          dummy_frag->fr_symbol = symbolP;
02547        }
02548       else
02549 #endif
02550        symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
02551 
02552 #ifdef OBJ_COFF
02553       /* "set" symbols are local unless otherwise specified.  */
02554       SF_SET_LOCAL (symbolP);
02555 #endif /* OBJ_COFF  */
02556     }                       /* Make a new symbol.  */
02557 
02558   symbol_table_insert (symbolP);
02559 
02560   * end_name = delim;
02561 
02562   if (equiv
02563       && S_IS_DEFINED (symbolP)
02564       && S_GET_SEGMENT (symbolP) != reg_section)
02565     as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
02566 
02567   pseudo_set (symbolP);
02568 
02569   demand_empty_rest_of_line ();
02570 
02571   /* XXX Now we come to the Thumb specific bit of code.  */
02572 
02573   THUMB_SET_FUNC (symbolP, 1);
02574   ARM_SET_THUMB (symbolP, 1);
02575 #if defined OBJ_ELF || defined OBJ_COFF
02576   ARM_SET_INTERWORK (symbolP, support_interwork);
02577 #endif
02578 }
02579 
02580 /* Directives: Mode selection.  */
02581 
02582 /* .syntax [unified|divided] - choose the new unified syntax
02583    (same for Arm and Thumb encoding, modulo slight differences in what
02584    can be represented) or the old divergent syntax for each mode.  */
02585 static void
02586 s_syntax (int unused ATTRIBUTE_UNUSED)
02587 {
02588   char *name, delim;
02589 
02590   name = input_line_pointer;
02591   delim = get_symbol_end ();
02592 
02593   if (!strcasecmp (name, "unified"))
02594     unified_syntax = TRUE;
02595   else if (!strcasecmp (name, "divided"))
02596     unified_syntax = FALSE;
02597   else
02598     {
02599       as_bad (_("unrecognized syntax mode \"%s\""), name);
02600       return;
02601     }
02602   *input_line_pointer = delim;
02603   demand_empty_rest_of_line ();
02604 }
02605 
02606 /* Directives: sectioning and alignment.  */
02607 
02608 /* Same as s_align_ptwo but align 0 => align 2.   */
02609 
02610 static void
02611 s_align (int unused ATTRIBUTE_UNUSED)
02612 {
02613   int temp;
02614   long temp_fill;
02615   long max_alignment = 15;
02616 
02617   temp = get_absolute_expression ();
02618   if (temp > max_alignment)
02619     as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
02620   else if (temp < 0)
02621     {
02622       as_bad (_("alignment negative. 0 assumed."));
02623       temp = 0;
02624     }
02625 
02626   if (*input_line_pointer == ',')
02627     {
02628       input_line_pointer++;
02629       temp_fill = get_absolute_expression ();
02630     }
02631   else
02632     temp_fill = 0;
02633 
02634   if (!temp)
02635     temp = 2;
02636 
02637   /* Only make a frag if we HAVE to.  */
02638   if (temp && !need_pass_2)
02639     frag_align (temp, (int) temp_fill, 0);
02640   demand_empty_rest_of_line ();
02641 
02642   record_alignment (now_seg, temp);
02643 }
02644 
02645 static void
02646 s_bss (int ignore ATTRIBUTE_UNUSED)
02647 {
02648   /* We don't support putting frags in the BSS segment, we fake it by
02649      marking in_bss, then looking at s_skip for clues.  */
02650   subseg_set (bss_section, 0);
02651   demand_empty_rest_of_line ();
02652   mapping_state (MAP_DATA);
02653 }
02654 
02655 static void
02656 s_even (int ignore ATTRIBUTE_UNUSED)
02657 {
02658   /* Never make frag if expect extra pass.  */
02659   if (!need_pass_2)
02660     frag_align (1, 0, 0);
02661 
02662   record_alignment (now_seg, 1);
02663 
02664   demand_empty_rest_of_line ();
02665 }
02666 
02667 /* Directives: Literal pools.  */
02668 
02669 static literal_pool *
02670 find_literal_pool (void)
02671 {
02672   literal_pool * pool;
02673 
02674   for (pool = list_of_pools; pool != NULL; pool = pool->next)
02675     {
02676       if (pool->section == now_seg
02677          && pool->sub_section == now_subseg)
02678        break;
02679     }
02680 
02681   return pool;
02682 }
02683 
02684 static literal_pool *
02685 find_or_make_literal_pool (void)
02686 {
02687   /* Next literal pool ID number.  */
02688   static unsigned int latest_pool_num = 1;
02689   literal_pool *      pool;
02690 
02691   pool = find_literal_pool ();
02692 
02693   if (pool == NULL)
02694     {
02695       /* Create a new pool.  */
02696       pool = xmalloc (sizeof (* pool));
02697       if (! pool)
02698        return NULL;
02699 
02700       pool->next_free_entry = 0;
02701       pool->section      = now_seg;
02702       pool->sub_section         = now_subseg;
02703       pool->next         = list_of_pools;
02704       pool->symbol       = NULL;
02705 
02706       /* Add it to the list.  */
02707       list_of_pools = pool;
02708     }
02709 
02710   /* New pools, and emptied pools, will have a NULL symbol.  */
02711   if (pool->symbol == NULL)
02712     {
02713       pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
02714                                 (valueT) 0, &zero_address_frag);
02715       pool->id = latest_pool_num ++;
02716     }
02717 
02718   /* Done.  */
02719   return pool;
02720 }
02721 
02722 /* Add the literal in the global 'inst'
02723    structure to the relevent literal pool.  */
02724 
02725 static int
02726 add_to_lit_pool (void)
02727 {
02728   literal_pool * pool;
02729   unsigned int entry;
02730 
02731   pool = find_or_make_literal_pool ();
02732 
02733   /* Check if this literal value is already in the pool.  */
02734   for (entry = 0; entry < pool->next_free_entry; entry ++)
02735     {
02736       if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
02737          && (inst.reloc.exp.X_op == O_constant)
02738          && (pool->literals[entry].X_add_number
02739              == inst.reloc.exp.X_add_number)
02740          && (pool->literals[entry].X_unsigned
02741              == inst.reloc.exp.X_unsigned))
02742        break;
02743 
02744       if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
02745          && (inst.reloc.exp.X_op == O_symbol)
02746          && (pool->literals[entry].X_add_number
02747              == inst.reloc.exp.X_add_number)
02748          && (pool->literals[entry].X_add_symbol
02749              == inst.reloc.exp.X_add_symbol)
02750          && (pool->literals[entry].X_op_symbol
02751              == inst.reloc.exp.X_op_symbol))
02752        break;
02753     }
02754 
02755   /* Do we need to create a new entry?    */
02756   if (entry == pool->next_free_entry)
02757     {
02758       if (entry >= MAX_LITERAL_POOL_SIZE)
02759        {
02760          inst.error = _("literal pool overflow");
02761          return FAIL;
02762        }
02763 
02764       pool->literals[entry] = inst.reloc.exp;
02765       pool->next_free_entry += 1;
02766     }
02767 
02768   inst.reloc.exp.X_op             = O_symbol;
02769   inst.reloc.exp.X_add_number = ((int) entry) * 4;
02770   inst.reloc.exp.X_add_symbol = pool->symbol;
02771 
02772   return SUCCESS;
02773 }
02774 
02775 /* Can't use symbol_new here, so have to create a symbol and then at
02776    a later date assign it a value. Thats what these functions do.  */
02777 
02778 static void
02779 symbol_locate (symbolS *    symbolP,
02780               const char * name,   /* It is copied, the caller can modify.    */
02781               segT       segment,  /* Segment identifier (SEG_<something>).  */
02782               valueT     valu,     /* Symbol value.  */
02783               fragS *           frag)     /* Associated fragment.      */
02784 {
02785   unsigned int name_length;
02786   char * preserved_copy_of_name;
02787 
02788   name_length = strlen (name) + 1;   /* +1 for \0.  */
02789   obstack_grow (&notes, name, name_length);
02790   preserved_copy_of_name = obstack_finish (&notes);
02791 
02792 #ifdef tc_canonicalize_symbol_name
02793   preserved_copy_of_name =
02794     tc_canonicalize_symbol_name (preserved_copy_of_name);
02795 #endif
02796 
02797   S_SET_NAME (symbolP, preserved_copy_of_name);
02798 
02799   S_SET_SEGMENT (symbolP, segment);
02800   S_SET_VALUE (symbolP, valu);
02801   symbol_clear_list_pointers (symbolP);
02802 
02803   symbol_set_frag (symbolP, frag);
02804 
02805   /* Link to end of symbol chain.  */
02806   {
02807     extern int symbol_table_frozen;
02808 
02809     if (symbol_table_frozen)
02810       abort ();
02811   }
02812 
02813   symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
02814 
02815   obj_symbol_new_hook (symbolP);
02816 
02817 #ifdef tc_symbol_new_hook
02818   tc_symbol_new_hook (symbolP);
02819 #endif
02820 
02821 #ifdef DEBUG_SYMS
02822   verify_symbol_chain (symbol_rootP, symbol_lastP);
02823 #endif /* DEBUG_SYMS  */
02824 }
02825 
02826 
02827 static void
02828 s_ltorg (int ignored ATTRIBUTE_UNUSED)
02829 {
02830   unsigned int entry;
02831   literal_pool * pool;
02832   char sym_name[20];
02833 
02834   pool = find_literal_pool ();
02835   if (pool == NULL
02836       || pool->symbol == NULL
02837       || pool->next_free_entry == 0)
02838     return;
02839 
02840   mapping_state (MAP_DATA);
02841 
02842   /* Align pool as you have word accesses.
02843      Only make a frag if we have to.  */
02844   if (!need_pass_2)
02845     frag_align (2, 0, 0);
02846 
02847   record_alignment (now_seg, 2);
02848 
02849   sprintf (sym_name, "$$lit_\002%x", pool->id);
02850 
02851   symbol_locate (pool->symbol, sym_name, now_seg,
02852                (valueT) frag_now_fix (), frag_now);
02853   symbol_table_insert (pool->symbol);
02854 
02855   ARM_SET_THUMB (pool->symbol, thumb_mode);
02856 
02857 #if defined OBJ_COFF || defined OBJ_ELF
02858   ARM_SET_INTERWORK (pool->symbol, support_interwork);
02859 #endif
02860 
02861   for (entry = 0; entry < pool->next_free_entry; entry ++)
02862     /* First output the expression in the instruction to the pool.  */
02863     emit_expr (&(pool->literals[entry]), 4); /* .word  */
02864 
02865   /* Mark the pool as empty.  */
02866   pool->next_free_entry = 0;
02867   pool->symbol = NULL;
02868 }
02869 
02870 #ifdef OBJ_ELF
02871 /* Forward declarations for functions below, in the MD interface
02872    section.  */
02873 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
02874 static valueT create_unwind_entry (int);
02875 static void start_unwind_section (const segT, int);
02876 static void add_unwind_opcode (valueT, int);
02877 static void flush_pending_unwind (void);
02878 
02879 /* Directives: Data.  */
02880 
02881 static void
02882 s_arm_elf_cons (int nbytes)
02883 {
02884   expressionS exp;
02885 
02886 #ifdef md_flush_pending_output
02887   md_flush_pending_output ();
02888 #endif
02889 
02890   if (is_it_end_of_statement ())
02891     {
02892       demand_empty_rest_of_line ();
02893       return;
02894     }
02895 
02896 #ifdef md_cons_align
02897   md_cons_align (nbytes);
02898 #endif
02899 
02900   mapping_state (MAP_DATA);
02901   do
02902     {
02903       int reloc;
02904       char *base = input_line_pointer;
02905 
02906       expression (& exp);
02907 
02908       if (exp.X_op != O_symbol)
02909        emit_expr (&exp, (unsigned int) nbytes);
02910       else
02911        {
02912          char *before_reloc = input_line_pointer;
02913          reloc = parse_reloc (&input_line_pointer);
02914          if (reloc == -1)
02915            {
02916              as_bad (_("unrecognized relocation suffix"));
02917              ignore_rest_of_line ();
02918              return;
02919            }
02920          else if (reloc == BFD_RELOC_UNUSED)
02921            emit_expr (&exp, (unsigned int) nbytes);
02922          else
02923            {
02924              reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
02925              int size = bfd_get_reloc_size (howto);
02926 
02927              if (reloc == BFD_RELOC_ARM_PLT32)
02928               {
02929                 as_bad (_("(plt) is only valid on branch targets"));
02930                 reloc = BFD_RELOC_UNUSED;
02931                 size = 0;
02932               }
02933 
02934              if (size > nbytes)
02935               as_bad (_("%s relocations do not fit in %d bytes"),
02936                      howto->name, nbytes);
02937              else
02938               {
02939                 /* We've parsed an expression stopping at O_symbol.
02940                    But there may be more expression left now that we
02941                    have parsed the relocation marker.  Parse it again.
02942                    XXX Surely there is a cleaner way to do this.  */
02943                 char *p = input_line_pointer;
02944                 int offset;
02945                 char *save_buf = alloca (input_line_pointer - base);
02946                 memcpy (save_buf, base, input_line_pointer - base);
02947                 memmove (base + (input_line_pointer - before_reloc),
02948                         base, before_reloc - base);
02949 
02950                 input_line_pointer = base + (input_line_pointer-before_reloc);
02951                 expression (&exp);
02952                 memcpy (base, save_buf, p - base);
02953 
02954                 offset = nbytes - size;
02955                 p = frag_more ((int) nbytes);
02956                 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
02957                             size, &exp, 0, reloc);
02958               }
02959            }
02960        }
02961     }
02962   while (*input_line_pointer++ == ',');
02963 
02964   /* Put terminator back into stream.  */
02965   input_line_pointer --;
02966   demand_empty_rest_of_line ();
02967 }
02968 
02969 
02970 /* Parse a .rel31 directive.  */
02971 
02972 static void
02973 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
02974 {
02975   expressionS exp;
02976   char *p;
02977   valueT highbit;
02978 
02979   highbit = 0;
02980   if (*input_line_pointer == '1')
02981     highbit = 0x80000000;
02982   else if (*input_line_pointer != '0')
02983     as_bad (_("expected 0 or 1"));
02984 
02985   input_line_pointer++;
02986   if (*input_line_pointer != ',')
02987     as_bad (_("missing comma"));
02988   input_line_pointer++;
02989 
02990 #ifdef md_flush_pending_output
02991   md_flush_pending_output ();
02992 #endif
02993 
02994 #ifdef md_cons_align
02995   md_cons_align (4);
02996 #endif
02997 
02998   mapping_state (MAP_DATA);
02999 
03000   expression (&exp);
03001 
03002   p = frag_more (4);
03003   md_number_to_chars (p, highbit, 4);
03004   fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
03005               BFD_RELOC_ARM_PREL31);
03006 
03007   demand_empty_rest_of_line ();
03008 }
03009 
03010 /* Directives: AEABI stack-unwind tables.  */
03011 
03012 /* Parse an unwind_fnstart directive.  Simply records the current location.  */
03013 
03014 static void
03015 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
03016 {
03017   demand_empty_rest_of_line ();
03018   /* Mark the start of the function.  */
03019   unwind.proc_start = expr_build_dot ();
03020 
03021   /* Reset the rest of the unwind info.    */
03022   unwind.opcode_count = 0;
03023   unwind.table_entry = NULL;
03024   unwind.personality_routine = NULL;
03025   unwind.personality_index = -1;
03026   unwind.frame_size = 0;
03027   unwind.fp_offset = 0;
03028   unwind.fp_reg = 13;
03029   unwind.fp_used = 0;
03030   unwind.sp_restored = 0;
03031 }
03032 
03033 
03034 /* Parse a handlerdata directive.  Creates the exception handling table entry
03035    for the function.  */
03036 
03037 static void
03038 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
03039 {
03040   demand_empty_rest_of_line ();
03041   if (unwind.table_entry)
03042     as_bad (_("dupicate .handlerdata directive"));
03043 
03044   create_unwind_entry (1);
03045 }
03046 
03047 /* Parse an unwind_fnend directive.  Generates the index table entry.  */
03048 
03049 static void
03050 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
03051 {
03052   long where;
03053   char *ptr;
03054   valueT val;
03055 
03056   demand_empty_rest_of_line ();
03057 
03058   /* Add eh table entry.  */
03059   if (unwind.table_entry == NULL)
03060     val = create_unwind_entry (0);
03061   else
03062     val = 0;
03063 
03064   /* Add index table entry.  This is two words.   */
03065   start_unwind_section (unwind.saved_seg, 1);
03066   frag_align (2, 0, 0);
03067   record_alignment (now_seg, 2);
03068 
03069   ptr = frag_more (8);
03070   where = frag_now_fix () - 8;
03071 
03072   /* Self relative offset of the function start.  */
03073   fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
03074           BFD_RELOC_ARM_PREL31);
03075 
03076   /* Indicate dependency on EHABI-defined personality routines to the
03077      linker, if it hasn't been done already.  */
03078   if (unwind.personality_index >= 0 && unwind.personality_index < 3
03079       && !(marked_pr_dependency & (1 << unwind.personality_index)))
03080     {
03081       static const char *const name[] = {
03082        "__aeabi_unwind_cpp_pr0",
03083        "__aeabi_unwind_cpp_pr1",
03084        "__aeabi_unwind_cpp_pr2"
03085       };
03086       symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
03087       fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
03088       marked_pr_dependency |= 1 << unwind.personality_index;
03089       seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
03090        = marked_pr_dependency;
03091     }
03092 
03093   if (val)
03094     /* Inline exception table entry.  */
03095     md_number_to_chars (ptr + 4, val, 4);
03096   else
03097     /* Self relative offset of the table entry.   */
03098     fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
03099             BFD_RELOC_ARM_PREL31);
03100 
03101   /* Restore the original section.  */
03102   subseg_set (unwind.saved_seg, unwind.saved_subseg);
03103 }
03104 
03105 
03106 /* Parse an unwind_cantunwind directive.  */
03107 
03108 static void
03109 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
03110 {
03111   demand_empty_rest_of_line ();
03112   if (unwind.personality_routine || unwind.personality_index != -1)
03113     as_bad (_("personality routine specified for cantunwind frame"));
03114 
03115   unwind.personality_index = -2;
03116 }
03117 
03118 
03119 /* Parse a personalityindex directive.    */
03120 
03121 static void
03122 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
03123 {
03124   expressionS exp;
03125 
03126   if (unwind.personality_routine || unwind.personality_index != -1)
03127     as_bad (_("duplicate .personalityindex directive"));
03128 
03129   expression (&exp);
03130 
03131   if (exp.X_op != O_constant
03132       || exp.X_add_number < 0 || exp.X_add_number > 15)
03133     {
03134       as_bad (_("bad personality routine number"));
03135       ignore_rest_of_line ();
03136       return;
03137     }
03138 
03139   unwind.personality_index = exp.X_add_number;
03140 
03141   demand_empty_rest_of_line ();
03142 }
03143 
03144 
03145 /* Parse a personality directive.  */
03146 
03147 static void
03148 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
03149 {
03150   char *name, *p, c;
03151 
03152   if (unwind.personality_routine || unwind.personality_index != -1)
03153     as_bad (_("duplicate .personality directive"));
03154 
03155   name = input_line_pointer;
03156   c = get_symbol_end ();
03157   p = input_line_pointer;
03158   unwind.personality_routine = symbol_find_or_make (name);
03159   *p = c;
03160   demand_empty_rest_of_line ();
03161 }
03162 
03163 
03164 /* Parse a directive saving core registers.  */
03165 
03166 static void
03167 s_arm_unwind_save_core (void)
03168 {
03169   valueT op;
03170   long range;
03171   int n;
03172 
03173   range = parse_reg_list (&input_line_pointer);
03174   if (range == FAIL)
03175     {
03176       as_bad (_("expected register list"));
03177       ignore_rest_of_line ();
03178       return;
03179     }
03180 
03181   demand_empty_rest_of_line ();
03182 
03183   /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
03184      into .unwind_save {..., sp...}.  We aren't bothered about the value of
03185      ip because it is clobbered by calls.  */
03186   if (unwind.sp_restored && unwind.fp_reg == 12
03187       && (range & 0x3000) == 0x1000)
03188     {
03189       unwind.opcode_count--;
03190       unwind.sp_restored = 0;
03191       range = (range | 0x2000) & ~0x1000;
03192       unwind.pending_offset = 0;
03193     }
03194 
03195   /* Pop r4-r15.  */
03196   if (range & 0xfff0)
03197     {
03198       /* See if we can use the short opcodes.  These pop a block of up to 8
03199         registers starting with r4, plus maybe r14.  */
03200       for (n = 0; n < 8; n++)
03201        {
03202          /* Break at the first non-saved register.       */
03203          if ((range & (1 << (n + 4))) == 0)
03204            break;
03205        }
03206       /* See if there are any other bits set.  */
03207       if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
03208        {
03209          /* Use the long form.  */
03210          op = 0x8000 | ((range >> 4) & 0xfff);
03211          add_unwind_opcode (op, 2);
03212        }
03213       else
03214        {
03215          /* Use the short form.  */
03216          if (range & 0x4000)
03217            op = 0xa8; /* Pop r14.  */
03218          else
03219            op = 0xa0; /* Do not pop r14.  */
03220          op |= (n - 1);
03221          add_unwind_opcode (op, 1);
03222        }
03223     }
03224 
03225   /* Pop r0-r3.       */
03226   if (range & 0xf)
03227     {
03228       op = 0xb100 | (range & 0xf);
03229       add_unwind_opcode (op, 2);
03230     }
03231 
03232   /* Record the number of bytes pushed.    */
03233   for (n = 0; n < 16; n++)
03234     {
03235       if (range & (1 << n))
03236        unwind.frame_size += 4;
03237     }
03238 }
03239 
03240 
03241 /* Parse a directive saving FPA registers.  */
03242 
03243 static void
03244 s_arm_unwind_save_fpa (int reg)
03245 {
03246   expressionS exp;
03247   int num_regs;
03248   valueT op;
03249 
03250   /* Get Number of registers to transfer.  */
03251   if (skip_past_comma (&input_line_pointer) != FAIL)
03252     expression (&exp);
03253   else
03254     exp.X_op = O_illegal;
03255 
03256   if (exp.X_op != O_constant)
03257     {
03258       as_bad (_("expected , <constant>"));
03259       ignore_rest_of_line ();
03260       return;
03261     }
03262 
03263   num_regs = exp.X_add_number;
03264 
03265   if (num_regs < 1 || num_regs > 4)
03266     {
03267       as_bad (_("number of registers must be in the range [1:4]"));
03268       ignore_rest_of_line ();
03269       return;
03270     }
03271 
03272   demand_empty_rest_of_line ();
03273 
03274   if (reg == 4)
03275     {
03276       /* Short form.  */
03277       op = 0xb4 | (num_regs - 1);
03278       add_unwind_opcode (op, 1);
03279     }
03280   else
03281     {
03282       /* Long form.  */
03283       op = 0xc800 | (reg << 4) | (num_regs - 1);
03284       add_unwind_opcode (op, 2);
03285     }
03286   unwind.frame_size += num_regs * 12;
03287 }
03288 
03289 
03290 /* Parse a directive saving VFP registers for ARMv6 and above.  */
03291 
03292 static void
03293 s_arm_unwind_save_vfp_armv6 (void)
03294 {
03295   int count;
03296   unsigned int start;
03297   valueT op;
03298   int num_vfpv3_regs = 0;
03299   int num_regs_below_16;
03300 
03301   count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
03302   if (count == FAIL)
03303     {
03304       as_bad (_("expected register list"));
03305       ignore_rest_of_line ();
03306       return;
03307     }
03308 
03309   demand_empty_rest_of_line ();
03310 
03311   /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
03312      than FSTMX/FLDMX-style ones).  */
03313 
03314   /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31.  */
03315   if (start >= 16)
03316     num_vfpv3_regs = count;
03317   else if (start + count > 16)
03318     num_vfpv3_regs = start + count - 16;
03319 
03320   if (num_vfpv3_regs > 0)
03321     {
03322       int start_offset = start > 16 ? start - 16 : 0;
03323       op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
03324       add_unwind_opcode (op, 2);
03325     }
03326 
03327   /* Generate opcode for registers numbered in the range 0 .. 15.  */
03328   num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
03329   assert (num_regs_below_16 + num_vfpv3_regs == count);
03330   if (num_regs_below_16 > 0)
03331     {
03332       op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
03333       add_unwind_opcode (op, 2);
03334     }
03335 
03336   unwind.frame_size += count * 8;
03337 }
03338 
03339 
03340 /* Parse a directive saving VFP registers for pre-ARMv6.  */
03341 
03342 static void
03343 s_arm_unwind_save_vfp (void)
03344 {
03345   int count;
03346   unsigned int reg;
03347   valueT op;
03348 
03349   count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
03350   if (count == FAIL)
03351     {
03352       as_bad (_("expected register list"));
03353       ignore_rest_of_line ();
03354       return;
03355     }
03356 
03357   demand_empty_rest_of_line ();
03358 
03359   if (reg == 8)
03360     {
03361       /* Short form.  */
03362       op = 0xb8 | (count - 1);
03363       add_unwind_opcode (op, 1);
03364     }
03365   else
03366     {
03367       /* Long form.  */
03368       op = 0xb300 | (reg << 4) | (count - 1);
03369       add_unwind_opcode (op, 2);
03370     }
03371   unwind.frame_size += count * 8 + 4;
03372 }
03373 
03374 
03375 /* Parse a directive saving iWMMXt data registers.  */
03376 
03377 static void
03378 s_arm_unwind_save_mmxwr (void)
03379 {
03380   int reg;
03381   int hi_reg;
03382   int i;
03383   unsigned mask = 0;
03384   valueT op;
03385 
03386   if (*input_line_pointer == '{')
03387     input_line_pointer++;
03388 
03389   do
03390     {
03391       reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
03392 
03393       if (reg == FAIL)
03394        {
03395          as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
03396          goto error;
03397        }
03398 
03399       if (mask >> reg)
03400        as_tsktsk (_("register list not in ascending order"));
03401       mask |= 1 << reg;
03402 
03403       if (*input_line_pointer == '-')
03404        {
03405          input_line_pointer++;
03406          hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
03407          if (hi_reg == FAIL)
03408            {
03409              as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
03410              goto error;
03411            }
03412          else if (reg >= hi_reg)
03413            {
03414              as_bad (_("bad register range"));
03415              goto error;
03416            }
03417          for (; reg < hi_reg; reg++)
03418            mask |= 1 << reg;
03419        }
03420     }
03421   while (skip_past_comma (&input_line_pointer) != FAIL);
03422 
03423   if (*input_line_pointer == '}')
03424     input_line_pointer++;
03425 
03426   demand_empty_rest_of_line ();
03427 
03428   /* Generate any deferred opcodes because we're going to be looking at
03429      the list.       */
03430   flush_pending_unwind ();
03431 
03432   for (i = 0; i < 16; i++)
03433     {
03434       if (mask & (1 << i))
03435        unwind.frame_size += 8;
03436     }
03437 
03438   /* Attempt to combine with a previous opcode.   We do this because gcc
03439      likes to output separate unwind directives for a single block of
03440      registers.       */
03441   if (unwind.opcode_count > 0)
03442     {
03443       i = unwind.opcodes[unwind.opcode_count - 1];
03444       if ((i & 0xf8) == 0xc0)
03445        {
03446          i &= 7;
03447          /* Only merge if the blocks are contiguous.  */
03448          if (i < 6)
03449            {
03450              if ((mask & 0xfe00) == (1 << 9))
03451               {
03452                 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
03453                 unwind.opcode_count--;
03454               }
03455            }
03456          else if (i == 6 && unwind.opcode_count >= 2)
03457            {
03458              i = unwind.opcodes[unwind.opcode_count - 2];
03459              reg = i >> 4;
03460              i &= 0xf;
03461 
03462              op = 0xffff << (reg - 1);
03463              if (reg > 0
03464                 && ((mask & op) == (1u << (reg - 1))))
03465               {
03466                 op = (1 << (reg + i + 1)) - 1;
03467                 op &= ~((1 << reg) - 1);
03468                 mask |= op;
03469                 unwind.opcode_count -= 2;
03470               }
03471            }
03472        }
03473     }
03474 
03475   hi_reg = 15;
03476   /* We want to generate opcodes in the order the registers have been
03477      saved, ie. descending order.  */
03478   for (reg = 15; reg >= -1; reg--)
03479     {
03480       /* Save registers in blocks.  */
03481       if (reg < 0
03482          || !(mask & (1 << reg)))
03483        {
03484          /* We found an unsaved reg.  Generate opcodes to save the
03485             preceeding block.      */
03486          if (reg != hi_reg)
03487            {
03488              if (reg == 9)
03489               {
03490                 /* Short form.  */
03491                 op = 0xc0 | (hi_reg - 10);
03492                 add_unwind_opcode (op, 1);
03493               }
03494              else
03495               {
03496                 /* Long form.       */
03497                 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
03498                 add_unwind_opcode (op, 2);
03499               }
03500            }
03501          hi_reg = reg - 1;
03502        }
03503     }
03504 
03505   return;
03506 error:
03507   ignore_rest_of_line ();
03508 }
03509 
03510 static void
03511 s_arm_unwind_save_mmxwcg (void)
03512 {
03513   int reg;
03514   int hi_reg;
03515   unsigned mask = 0;
03516   valueT op;
03517 
03518   if (*input_line_pointer == '{')
03519     input_line_pointer++;
03520 
03521   do
03522     {
03523       reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
03524 
03525       if (reg == FAIL)
03526        {
03527          as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
03528          goto error;
03529        }
03530 
03531       reg -= 8;
03532       if (mask >> reg)
03533        as_tsktsk (_("register list not in ascending order"));
03534       mask |= 1 << reg;
03535 
03536       if (*input_line_pointer == '-')
03537        {
03538          input_line_pointer++;
03539          hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
03540          if (hi_reg == FAIL)
03541            {
03542              as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
03543              goto error;
03544            }
03545          else if (reg >= hi_reg)
03546            {
03547              as_bad (_("bad register range"));
03548              goto error;
03549            }
03550          for (; reg < hi_reg; reg++)
03551            mask |= 1 << reg;
03552        }
03553     }
03554   while (skip_past_comma (&input_line_pointer) != FAIL);
03555 
03556   if (*input_line_pointer == '}')
03557     input_line_pointer++;
03558 
03559   demand_empty_rest_of_line ();
03560 
03561   /* Generate any deferred opcodes because we're going to be looking at
03562      the list.       */
03563   flush_pending_unwind ();
03564 
03565   for (reg = 0; reg < 16; reg++)
03566     {
03567       if (mask & (1 << reg))
03568        unwind.frame_size += 4;
03569     }
03570   op = 0xc700 | mask;
03571   add_unwind_opcode (op, 2);
03572   return;
03573 error:
03574   ignore_rest_of_line ();
03575 }
03576 
03577 
03578 /* Parse an unwind_save directive.
03579    If the argument is non-zero, this is a .vsave directive.  */
03580 
03581 static void
03582 s_arm_unwind_save (int arch_v6)
03583 {
03584   char *peek;
03585   struct reg_entry *reg;
03586   bfd_boolean had_brace = FALSE;
03587 
03588   /* Figure out what sort of save we have.  */
03589   peek = input_line_pointer;
03590 
03591   if (*peek == '{')
03592     {
03593       had_brace = TRUE;
03594       peek++;
03595     }
03596 
03597   reg = arm_reg_parse_multi (&peek);
03598 
03599   if (!reg)
03600     {
03601       as_bad (_("register expected"));
03602       ignore_rest_of_line ();
03603       return;
03604     }
03605 
03606   switch (reg->type)
03607     {
03608     case REG_TYPE_FN:
03609       if (had_brace)
03610        {
03611          as_bad (_("FPA .unwind_save does not take a register list"));
03612          ignore_rest_of_line ();
03613          return;
03614        }
03615       s_arm_unwind_save_fpa (reg->number);
03616       return;
03617 
03618     case REG_TYPE_RN:         s_arm_unwind_save_core ();   return;
03619     case REG_TYPE_VFD:
03620       if (arch_v6)
03621         s_arm_unwind_save_vfp_armv6 ();
03622       else
03623         s_arm_unwind_save_vfp ();
03624       return;
03625     case REG_TYPE_MMXWR:  s_arm_unwind_save_mmxwr ();  return;
03626     case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
03627 
03628     default:
03629       as_bad (_(".unwind_save does not support this kind of register"));
03630       ignore_rest_of_line ();
03631     }
03632 }
03633 
03634 
03635 /* Parse an unwind_movsp directive.  */
03636 
03637 static void
03638 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
03639 {
03640   int reg;
03641   valueT op;
03642   int offset;
03643 
03644   reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
03645   if (reg == FAIL)
03646     {
03647       as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
03648       ignore_rest_of_line ();
03649       return;
03650     }
03651 
03652   /* Optional constant.      */
03653   if (skip_past_comma (&input_line_pointer) != FAIL)
03654     {
03655       if (immediate_for_directive (&offset) == FAIL)
03656        return;
03657     }
03658   else
03659     offset = 0;
03660 
03661   demand_empty_rest_of_line ();
03662 
03663   if (reg == REG_SP || reg == REG_PC)
03664     {
03665       as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
03666       return;
03667     }
03668 
03669   if (unwind.fp_reg != REG_SP)
03670     as_bad (_("unexpected .unwind_movsp directive"));
03671 
03672   /* Generate opcode to restore the value.  */
03673   op = 0x90 | reg;
03674   add_unwind_opcode (op, 1);
03675 
03676   /* Record the information for later.    */
03677   unwind.fp_reg = reg;
03678   unwind.fp_offset = unwind.frame_size - offset;
03679   unwind.sp_restored = 1;
03680 }
03681 
03682 /* Parse an unwind_pad directive.  */
03683 
03684 static void
03685 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
03686 {
03687   int offset;
03688 
03689   if (immediate_for_directive (&offset) == FAIL)
03690     return;
03691 
03692   if (offset & 3)
03693     {
03694       as_bad (_("stack increment must be multiple of 4"));
03695       ignore_rest_of_line ();
03696       return;
03697     }
03698 
03699   /* Don't generate any opcodes, just record the details for later.  */
03700   unwind.frame_size += offset;
03701   unwind.pending_offset += offset;
03702 
03703   demand_empty_rest_of_line ();
03704 }
03705 
03706 /* Parse an unwind_setfp directive.  */
03707 
03708 static void
03709 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
03710 {
03711   int sp_reg;
03712   int fp_reg;
03713   int offset;
03714 
03715   fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
03716   if (skip_past_comma (&input_line_pointer) == FAIL)
03717     sp_reg = FAIL;
03718   else
03719     sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
03720 
03721   if (fp_reg == FAIL || sp_reg == FAIL)
03722     {
03723       as_bad (_("expected <reg>, <reg>"));
03724       ignore_rest_of_line ();
03725       return;
03726     }
03727 
03728   /* Optional constant.      */
03729   if (skip_past_comma (&input_line_pointer) != FAIL)
03730     {
03731       if (immediate_for_directive (&offset) == FAIL)
03732        return;
03733     }
03734   else
03735     offset = 0;
03736 
03737   demand_empty_rest_of_line ();
03738 
03739   if (sp_reg != 13 && sp_reg != unwind.fp_reg)
03740     {
03741       as_bad (_("register must be either sp or set by a previous"
03742               "unwind_movsp directive"));
03743       return;
03744     }
03745 
03746   /* Don't generate any opcodes, just record the information for later.       */
03747   unwind.fp_reg = fp_reg;
03748   unwind.fp_used = 1;
03749   if (sp_reg == 13)
03750     unwind.fp_offset = unwind.frame_size - offset;
03751   else
03752     unwind.fp_offset -= offset;
03753 }
03754 
03755 /* Parse an unwind_raw directive.  */
03756 
03757 static void
03758 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
03759 {
03760   expressionS exp;
03761   /* This is an arbitrary limit.    */
03762   unsigned char op[16];
03763   int count;
03764 
03765   expression (&exp);
03766   if (exp.X_op == O_constant
03767       && skip_past_comma (&input_line_pointer) != FAIL)
03768     {
03769       unwind.frame_size += exp.X_add_number;
03770       expression (&exp);
03771     }
03772   else
03773     exp.X_op = O_illegal;
03774 
03775   if (exp.X_op != O_constant)
03776     {
03777       as_bad (_("expected <offset>, <opcode>"));
03778       ignore_rest_of_line ();
03779       return;
03780     }
03781 
03782   count = 0;
03783 
03784   /* Parse the opcode.      */
03785   for (;;)
03786     {
03787       if (count >= 16)
03788        {
03789          as_bad (_("unwind opcode too long"));
03790          ignore_rest_of_line ();
03791        }
03792       if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
03793        {
03794          as_bad (_("invalid unwind opcode"));
03795          ignore_rest_of_line ();
03796          return;
03797        }
03798       op[count++] = exp.X_add_number;
03799 
03800       /* Parse the next byte.  */
03801       if (skip_past_comma (&input_line_pointer) == FAIL)
03802        break;
03803 
03804       expression (&exp);
03805     }
03806 
03807   /* Add the opcode bytes in reverse order.  */
03808   while (count--)
03809     add_unwind_opcode (op[count], 1);
03810 
03811   demand_empty_rest_of_line ();
03812 }
03813 
03814 
03815 /* Parse a .eabi_attribute directive.  */
03816 
03817 static void
03818 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
03819 {
03820   expressionS exp;
03821   bfd_boolean is_string;
03822   int tag;
03823   unsigned int i = 0;
03824   char *s = NULL;
03825   char saved_char;
03826 
03827   expression (& exp);
03828   if (exp.X_op != O_constant)
03829     goto bad;
03830 
03831   tag = exp.X_add_number;
03832   if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
03833     is_string = 1;
03834   else
03835     is_string = 0;
03836 
03837   if (skip_past_comma (&input_line_pointer) == FAIL)
03838     goto bad;
03839   if (tag == 32 || !is_string)
03840     {
03841       expression (& exp);
03842       if (exp.X_op != O_constant)
03843        {
03844          as_bad (_("expected numeric constant"));
03845          ignore_rest_of_line ();
03846          return;
03847        }
03848       i = exp.X_add_number;
03849     }
03850   if (tag == Tag_compatibility
03851       && skip_past_comma (&input_line_pointer) == FAIL)
03852     {
03853       as_bad (_("expected comma"));
03854       ignore_rest_of_line ();
03855       return;
03856     }
03857   if (is_string)
03858     {
03859       skip_whitespace(input_line_pointer);
03860       if (*input_line_pointer != '"')
03861        goto bad_string;
03862       input_line_pointer++;
03863       s = input_line_pointer;
03864       while (*input_line_pointer && *input_line_pointer != '"')
03865        input_line_pointer++;
03866       if (*input_line_pointer != '"')
03867        goto bad_string;
03868       saved_char = *input_line_pointer;
03869       *input_line_pointer = 0;
03870     }
03871   else
03872     {
03873       s = NULL;
03874       saved_char = 0;
03875     }
03876   
03877   if (tag == Tag_compatibility)
03878     elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
03879   else if (is_string)
03880     elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
03881   else
03882     elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
03883 
03884   if (s)
03885     {
03886       *input_line_pointer = saved_char;
03887       input_line_pointer++;
03888     }
03889   demand_empty_rest_of_line ();
03890   return;
03891 bad_string:
03892   as_bad (_("bad string constant"));
03893   ignore_rest_of_line ();
03894   return;
03895 bad:
03896   as_bad (_("expected <tag> , <value>"));
03897   ignore_rest_of_line ();
03898 }
03899 #endif /* OBJ_ELF */
03900 
03901 static void s_arm_arch (int);
03902 static void s_arm_object_arch (int);
03903 static void s_arm_cpu (int);
03904 static void s_arm_fpu (int);
03905 
03906 #ifdef TE_PE
03907 
03908 static void
03909 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) 
03910 {
03911   expressionS exp;
03912 
03913   do
03914     {
03915       expression (&exp);
03916       if (exp.X_op == O_symbol)
03917        exp.X_op = O_secrel;
03918 
03919       emit_expr (&exp, 4);
03920     }
03921   while (*input_line_pointer++ == ',');
03922 
03923   input_line_pointer--;
03924   demand_empty_rest_of_line ();
03925 }
03926 #endif /* TE_PE */
03927 
03928 /* This table describes all the machine specific pseudo-ops the assembler
03929    has to support.  The fields are:
03930      pseudo-op name without dot
03931      function to call to execute this pseudo-op
03932      Integer arg to pass to the function.  */
03933 
03934 const pseudo_typeS md_pseudo_table[] =
03935 {
03936   /* Never called because '.req' does not start a line.  */
03937   { "req",       s_req,       0 },
03938   /* Following two are likewise never called.  */
03939   { "dn",        s_dn,          0 },
03940   { "qn",          s_qn,          0 },
03941   { "unreq",     s_unreq,     0 },
03942   { "bss",       s_bss,       0 },
03943   { "align",     s_align,     0 },
03944   { "arm",       s_arm,       0 },
03945   { "thumb",     s_thumb,     0 },
03946   { "code",      s_code,      0 },
03947   { "force_thumb", s_force_thumb, 0 },
03948   { "thumb_func",  s_thumb_func,  0 },
03949   { "thumb_set",   s_thumb_set,      0 },
03950   { "even",      s_even,      0 },
03951   { "ltorg",     s_ltorg,     0 },
03952   { "pool",      s_ltorg,     0 },
03953   { "syntax",    s_syntax,    0 },
03954   { "cpu",       s_arm_cpu,   0 },
03955   { "arch",      s_arm_arch,         0 },
03956   { "object_arch", s_arm_object_arch,     0 },
03957   { "fpu",       s_arm_fpu,   0 },
03958 #ifdef OBJ_ELF
03959   { "word",      s_arm_elf_cons, 4 },
03960   { "long",      s_arm_elf_cons, 4 },
03961   { "rel31",     s_arm_rel31,        0 },
03962   { "fnstart",              s_arm_unwind_fnstart,       0 },
03963   { "fnend",         s_arm_unwind_fnend,  0 },
03964   { "cantunwind",    s_arm_unwind_cantunwind, 0 },
03965   { "personality",   s_arm_unwind_personality, 0 },
03966   { "personalityindex",     s_arm_unwind_personalityindex, 0 },
03967   { "handlerdata",   s_arm_unwind_handlerdata, 0 },
03968   { "save",          s_arm_unwind_save,   0 },
03969   { "vsave",         s_arm_unwind_save,   1 },
03970   { "movsp",         s_arm_unwind_movsp,  0 },
03971   { "pad",           s_arm_unwind_pad,    0 },
03972   { "setfp",         s_arm_unwind_setfp,  0 },
03973   { "unwind_raw",    s_arm_unwind_raw,    0 },
03974   { "eabi_attribute",       s_arm_eabi_attribute,       0 },
03975 #else
03976   { "word",      cons, 4},
03977 
03978   /* These are used for dwarf.  */
03979   {"2byte", cons, 2},
03980   {"4byte", cons, 4},
03981   {"8byte", cons, 8},
03982   /* These are used for dwarf2.  */
03983   { "file", (void (*) (int)) dwarf2_directive_file, 0 },
03984   { "loc",  dwarf2_directive_loc,  0 },
03985   { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
03986 #endif
03987   { "extend",    float_cons, 'x' },
03988   { "ldouble",          float_cons, 'x' },
03989   { "packed",    float_cons, 'p' },
03990 #ifdef TE_PE
03991   {"secrel32", pe_directive_secrel, 0},
03992 #endif
03993   { 0, 0, 0 }
03994 };
03995 
03996 /* Parser functions used exclusively in instruction operands.  */
03997 
03998 /* Generic immediate-value read function for use in insn parsing.
03999    STR points to the beginning of the immediate (the leading #);
04000    VAL receives the value; if the value is outside [MIN, MAX]
04001    issue an error.  PREFIX_OPT is true if the immediate prefix is
04002    optional.  */
04003 
04004 static int
04005 parse_immediate (char **str, int *val, int min, int max,
04006                bfd_boolean prefix_opt)
04007 {
04008   expressionS exp;
04009   my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
04010   if (exp.X_op != O_constant)
04011     {
04012       inst.error = _("constant expression required");
04013       return FAIL;
04014     }
04015 
04016   if (exp.X_add_number < min || exp.X_add_number > max)
04017     {
04018       inst.error = _("immediate value out of range");
04019       return FAIL;
04020     }
04021 
04022   *val = exp.X_add_number;
04023   return SUCCESS;
04024 }
04025 
04026 /* Less-generic immediate-value read function with the possibility of loading a
04027    big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
04028    instructions. Puts the result directly in inst.operands[i].  */
04029 
04030 static int
04031 parse_big_immediate (char **str, int i)
04032 {
04033   expressionS exp;
04034   char *ptr = *str;
04035 
04036   my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
04037 
04038   if (exp.X_op == O_constant)
04039     {
04040       inst.operands[i].imm = exp.X_add_number & 0xffffffff;
04041       /* If we're on a 64-bit host, then a 64-bit number can be returned using
04042         O_constant.  We have to be careful not to break compilation for
04043         32-bit X_add_number, though.  */
04044       if ((exp.X_add_number & ~0xffffffffl) != 0)
04045        {
04046           /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4.  */
04047          inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
04048          inst.operands[i].regisimm = 1;
04049        }
04050     }
04051   else if (exp.X_op == O_big
04052            && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32
04053            && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number <= 64)
04054     {
04055       unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
04056       /* Bignums have their least significant bits in
04057          generic_bignum[0]. Make sure we put 32 bits in imm and
04058          32 bits in reg,  in a (hopefully) portable way.  */
04059       assert (parts != 0);
04060       inst.operands[i].imm = 0;
04061       for (j = 0; j < parts; j++, idx++)
04062         inst.operands[i].imm |= generic_bignum[idx]
04063                                 << (LITTLENUM_NUMBER_OF_BITS * j);
04064       inst.operands[i].reg = 0;
04065       for (j = 0; j < parts; j++, idx++)
04066         inst.operands[i].reg |= generic_bignum[idx]
04067                                 << (LITTLENUM_NUMBER_OF_BITS * j);
04068       inst.operands[i].regisimm = 1;
04069     }
04070   else
04071     return FAIL;
04072   
04073   *str = ptr;
04074 
04075   return SUCCESS;
04076 }
04077 
04078 /* Returns the pseudo-register number of an FPA immediate constant,
04079    or FAIL if there isn't a valid constant here.  */
04080 
04081 static int
04082 parse_fpa_immediate (char ** str)
04083 {
04084   LITTLENUM_TYPE words[MAX_LITTLENUMS];
04085   char *       save_in;
04086   expressionS  exp;
04087   int          i;
04088   int          j;
04089 
04090   /* First try and match exact strings, this is to guarantee
04091      that some formats will work even for cross assembly.  */
04092 
04093   for (i = 0; fp_const[i]; i++)
04094     {
04095       if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
04096        {
04097          char *start = *str;
04098 
04099          *str += strlen (fp_const[i]);
04100          if (is_end_of_line[(unsigned char) **str])
04101            return i + 8;
04102          *str = start;
04103        }
04104     }
04105 
04106   /* Just because we didn't get a match doesn't mean that the constant
04107      isn't valid, just that it is in a format that we don't
04108      automatically recognize.  Try parsing it with the standard
04109      expression routines.  */
04110 
04111   memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
04112 
04113   /* Look for a raw floating point number.  */
04114   if ((save_in = atof_ieee (*str, 'x', words)) != NULL
04115       && is_end_of_line[(unsigned char) *save_in])
04116     {
04117       for (i = 0; i < NUM_FLOAT_VALS; i++)
04118        {
04119          for (j = 0; j < MAX_LITTLENUMS; j++)
04120            {
04121              if (words[j] != fp_values[i][j])
04122               break;
04123            }
04124 
04125          if (j == MAX_LITTLENUMS)
04126            {
04127              *str = save_in;
04128              return i + 8;
04129            }
04130        }
04131     }
04132 
04133   /* Try and parse a more complex expression, this will probably fail
04134      unless the code uses a floating point prefix (eg "0f").  */
04135   save_in = input_line_pointer;
04136   input_line_pointer = *str;
04137   if (expression (&exp) == absolute_section
04138       && exp.X_op == O_big
04139       && exp.X_add_number < 0)
04140     {
04141       /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
04142         Ditto for 15.       */
04143       if (gen_to_words (words, 5, (long) 15) == 0)
04144        {
04145          for (i = 0; i < NUM_FLOAT_VALS; i++)
04146            {
04147              for (j = 0; j < MAX_LITTLENUMS; j++)
04148               {
04149                 if (words[j] != fp_values[i][j])
04150                   break;
04151               }
04152 
04153              if (j == MAX_LITTLENUMS)
04154               {
04155                 *str = input_line_pointer;
04156                 input_line_pointer = save_in;
04157                 return i + 8;
04158               }
04159            }
04160        }
04161     }
04162 
04163   *str = input_line_pointer;
04164   input_line_pointer = save_in;
04165   inst.error = _("invalid FPA immediate expression");
04166   return FAIL;
04167 }
04168 
04169 /* Returns 1 if a number has "quarter-precision" float format
04170    0baBbbbbbc defgh000 00000000 00000000.  */
04171 
04172 static int
04173 is_quarter_float (unsigned imm)
04174 {
04175   int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
04176   return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
04177 }
04178 
04179 /* Parse an 8-bit "quarter-precision" floating point number of the form:
04180    0baBbbbbbc defgh000 00000000 00000000.
04181    The zero and minus-zero cases need special handling, since they can't be
04182    encoded in the "quarter-precision" float format, but can nonetheless be
04183    loaded as integer constants.  */
04184 
04185 static unsigned
04186 parse_qfloat_immediate (char **ccp, int *immed)
04187 {
04188   char *str = *ccp;
04189   char *fpnum;
04190   LITTLENUM_TYPE words[MAX_LITTLENUMS];
04191   int found_fpchar = 0;
04192   
04193   skip_past_char (&str, '#');
04194   
04195   /* We must not accidentally parse an integer as a floating-point number. Make
04196      sure that the value we parse is not an integer by checking for special
04197      characters '.' or 'e'.
04198      FIXME: This is a horrible hack, but doing better is tricky because type
04199      information isn't in a very usable state at parse time.  */
04200   fpnum = str;
04201   skip_whitespace (fpnum);
04202 
04203   if (strncmp (fpnum, "0x", 2) == 0)
04204     return FAIL;
04205   else
04206     {
04207       for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
04208         if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
04209           {
04210             found_fpchar = 1;
04211             break;
04212           }
04213 
04214       if (!found_fpchar)
04215         return FAIL;
04216     }
04217   
04218   if ((str = atof_ieee (str, 's', words)) != NULL)
04219     {
04220       unsigned fpword = 0;
04221       int i;
04222       
04223       /* Our FP word must be 32 bits (single-precision FP).  */
04224       for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
04225         {
04226           fpword <<= LITTLENUM_NUMBER_OF_BITS;
04227           fpword |= words[i];
04228         }
04229       
04230       if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
04231         *immed = fpword;
04232       else
04233         return FAIL;
04234 
04235       *ccp = str;
04236       
04237       return SUCCESS;
04238     }
04239   
04240   return FAIL;
04241 }
04242 
04243 /* Shift operands.  */
04244 enum shift_kind
04245 {
04246   SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
04247 };
04248 
04249 struct asm_shift_name
04250 {
04251   const char    *name;
04252   enum shift_kind  kind;
04253 };
04254 
04255 /* Third argument to parse_shift.  */
04256 enum parse_shift_mode
04257 {
04258   NO_SHIFT_RESTRICT,        /* Any kind of shift is accepted.  */
04259   SHIFT_IMMEDIATE,          /* Shift operand must be an immediate.    */
04260   SHIFT_LSL_OR_ASR_IMMEDIATE,      /* Shift must be LSL or ASR immediate.    */
04261   SHIFT_ASR_IMMEDIATE,             /* Shift must be ASR immediate.     */
04262   SHIFT_LSL_IMMEDIATE,             /* Shift must be LSL immediate.     */
04263 };
04264 
04265 /* Parse a <shift> specifier on an ARM data processing instruction.
04266    This has three forms:
04267 
04268      (LSL|LSR|ASL|ASR|ROR) Rs
04269      (LSL|LSR|ASL|ASR|ROR) #imm
04270      RRX
04271 
04272    Note that ASL is assimilated to LSL in the instruction encoding, and
04273    RRX to ROR #0 (which cannot be written as such).  */
04274 
04275 static int
04276 parse_shift (char **str, int i, enum parse_shift_mode mode)
04277 {
04278   const struct asm_shift_name *shift_name;
04279   enum shift_kind shift;
04280   char *s = *str;
04281   char *p = s;
04282   int reg;
04283 
04284   for (p = *str; ISALPHA (*p); p++)
04285     ;
04286 
04287   if (p == *str)
04288     {
04289       inst.error = _("shift expression expected");
04290       return FAIL;
04291     }
04292 
04293   shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
04294 
04295   if (shift_name == NULL)
04296     {
04297       inst.error = _("shift expression expected");
04298       return FAIL;
04299     }
04300 
04301   shift = shift_name->kind;
04302 
04303   switch (mode)
04304     {
04305     case NO_SHIFT_RESTRICT:
04306     case SHIFT_IMMEDIATE:   break;
04307 
04308     case SHIFT_LSL_OR_ASR_IMMEDIATE:
04309       if (shift != SHIFT_LSL && shift != SHIFT_ASR)
04310        {
04311          inst.error = _("'LSL' or 'ASR' required");
04312          return FAIL;
04313        }
04314       break;
04315 
04316     case SHIFT_LSL_IMMEDIATE:
04317       if (shift != SHIFT_LSL)
04318        {
04319          inst.error = _("'LSL' required");
04320          return FAIL;
04321        }
04322       break;
04323 
04324     case SHIFT_ASR_IMMEDIATE:
04325       if (shift != SHIFT_ASR)
04326        {
04327          inst.error = _("'ASR' required");
04328          return FAIL;
04329        }
04330       break;
04331 
04332     default: abort ();
04333     }
04334 
04335   if (shift != SHIFT_RRX)
04336     {
04337       /* Whitespace can appear here if the next thing is a bare digit.       */
04338       skip_whitespace (p);
04339 
04340       if (mode == NO_SHIFT_RESTRICT
04341          && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
04342        {
04343          inst.operands[i].imm = reg;
04344          inst.operands[i].immisreg = 1;
04345        }
04346       else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
04347        return FAIL;
04348     }
04349   inst.operands[i].shift_kind = shift;
04350   inst.operands[i].shifted = 1;
04351   *str = p;
04352   return SUCCESS;
04353 }
04354 
04355 /* Parse a <shifter_operand> for an ARM data processing instruction:
04356 
04357       #<immediate>
04358       #<immediate>, <rotate>
04359       <Rm>
04360       <Rm>, <shift>
04361 
04362    where <shift> is defined by parse_shift above, and <rotate> is a
04363    multiple of 2 between 0 and 30.  Validation of immediate operands
04364    is deferred to md_apply_fix.  */
04365 
04366 static int
04367 parse_shifter_operand (char **str, int i)
04368 {
04369   int value;
04370   expressionS expr;
04371 
04372   if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
04373     {
04374       inst.operands[i].reg = value;
04375       inst.operands[i].isreg = 1;
04376 
04377       /* parse_shift will override this if appropriate */
04378       inst.reloc.exp.X_op = O_constant;
04379       inst.reloc.exp.X_add_number = 0;
04380 
04381       if (skip_past_comma (str) == FAIL)
04382        return SUCCESS;
04383 
04384       /* Shift operation on register.  */
04385       return parse_shift (str, i, NO_SHIFT_RESTRICT);
04386     }
04387 
04388   if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
04389     return FAIL;
04390 
04391   if (skip_past_comma (str) == SUCCESS)
04392     {
04393       /* #x, y -- ie explicit rotation by Y.  */
04394       if (my_get_expression (&expr, str, GE_NO_PREFIX))
04395        return FAIL;
04396 
04397       if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
04398        {
04399          inst.error = _("constant expression expected");
04400          return FAIL;
04401        }
04402 
04403       value = expr.X_add_number;
04404       if (value < 0 || value > 30 || value % 2 != 0)
04405        {
04406          inst.error = _("invalid rotation");
04407          return FAIL;
04408        }
04409       if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
04410        {
04411          inst.error = _("invalid constant");
04412          return FAIL;
04413        }
04414 
04415       /* Convert to decoded value.  md_apply_fix will put it back.  */
04416       inst.reloc.exp.X_add_number
04417        = (((inst.reloc.exp.X_add_number << (32 - value))
04418            | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
04419     }
04420 
04421   inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
04422   inst.reloc.pc_rel = 0;
04423   return SUCCESS;
04424 }
04425 
04426 /* Group relocation information.  Each entry in the table contains the
04427    textual name of the relocation as may appear in assembler source
04428    and must end with a colon.
04429    Along with this textual name are the relocation codes to be used if
04430    the corresponding instruction is an ALU instruction (ADD or SUB only),
04431    an LDR, an LDRS, or an LDC.  */
04432 
04433 struct group_reloc_table_entry
04434 {
04435   const char *name;
04436   int alu_code;
04437   int ldr_code;
04438   int ldrs_code;
04439   int ldc_code;
04440 };
04441 
04442 typedef enum
04443 {
04444   /* Varieties of non-ALU group relocation.  */
04445 
04446   GROUP_LDR,
04447   GROUP_LDRS,
04448   GROUP_LDC
04449 } group_reloc_type;
04450 
04451 static struct group_reloc_table_entry group_reloc_table[] =
04452   { /* Program counter relative: */
04453     { "pc_g0_nc",
04454       BFD_RELOC_ARM_ALU_PC_G0_NC,  /* ALU */
04455       0,                           /* LDR */
04456       0,                           /* LDRS */
04457       0 },                         /* LDC */
04458     { "pc_g0",
04459       BFD_RELOC_ARM_ALU_PC_G0,            /* ALU */
04460       BFD_RELOC_ARM_LDR_PC_G0,            /* LDR */
04461       BFD_RELOC_ARM_LDRS_PC_G0,           /* LDRS */
04462       BFD_RELOC_ARM_LDC_PC_G0 },   /* LDC */
04463     { "pc_g1_nc",
04464       BFD_RELOC_ARM_ALU_PC_G1_NC,  /* ALU */
04465       0,                           /* LDR */
04466       0,                           /* LDRS */
04467       0 },                         /* LDC */
04468     { "pc_g1",
04469       BFD_RELOC_ARM_ALU_PC_G1,            /* ALU */
04470       BFD_RELOC_ARM_LDR_PC_G1,            /* LDR */
04471       BFD_RELOC_ARM_LDRS_PC_G1,           /* LDRS */
04472       BFD_RELOC_ARM_LDC_PC_G1 },   /* LDC */
04473     { "pc_g2",
04474       BFD_RELOC_ARM_ALU_PC_G2,            /* ALU */
04475       BFD_RELOC_ARM_LDR_PC_G2,            /* LDR */
04476       BFD_RELOC_ARM_LDRS_PC_G2,           /* LDRS */
04477       BFD_RELOC_ARM_LDC_PC_G2 },   /* LDC */
04478     /* Section base relative */
04479     { "sb_g0_nc",
04480       BFD_RELOC_ARM_ALU_SB_G0_NC,  /* ALU */
04481       0,                           /* LDR */
04482       0,                           /* LDRS */
04483       0 },                         /* LDC */
04484     { "sb_g0",
04485       BFD_RELOC_ARM_ALU_SB_G0,            /* ALU */
04486       BFD_RELOC_ARM_LDR_SB_G0,            /* LDR */
04487       BFD_RELOC_ARM_LDRS_SB_G0,           /* LDRS */
04488       BFD_RELOC_ARM_LDC_SB_G0 },   /* LDC */
04489     { "sb_g1_nc",
04490       BFD_RELOC_ARM_ALU_SB_G1_NC,  /* ALU */
04491       0,                           /* LDR */
04492       0,                           /* LDRS */
04493       0 },                         /* LDC */
04494     { "sb_g1",
04495       BFD_RELOC_ARM_ALU_SB_G1,            /* ALU */
04496       BFD_RELOC_ARM_LDR_SB_G1,            /* LDR */
04497       BFD_RELOC_ARM_LDRS_SB_G1,           /* LDRS */
04498       BFD_RELOC_ARM_LDC_SB_G1 },   /* LDC */
04499     { "sb_g2",
04500       BFD_RELOC_ARM_ALU_SB_G2,            /* ALU */
04501       BFD_RELOC_ARM_LDR_SB_G2,            /* LDR */
04502       BFD_RELOC_ARM_LDRS_SB_G2,           /* LDRS */
04503       BFD_RELOC_ARM_LDC_SB_G2 }    };     /* LDC */
04504 
04505 /* Given the address of a pointer pointing to the textual name of a group
04506    relocation as may appear in assembler source, attempt to find its details
04507    in group_reloc_table.  The pointer will be updated to the character after
04508    the trailing colon.  On failure, FAIL will be returned; SUCCESS
04509    otherwise.  On success, *entry will be updated to point at the relevant
04510    group_reloc_table entry. */
04511 
04512 static int
04513 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
04514 {
04515   unsigned int i;
04516   for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
04517     {
04518       int length = strlen (group_reloc_table[i].name);
04519 
04520       if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
04521           (*str)[length] == ':')
04522         {
04523           *out = &group_reloc_table[i];
04524           *str += (length + 1);
04525           return SUCCESS;
04526         }
04527     }
04528 
04529   return FAIL;
04530 }
04531 
04532 /* Parse a <shifter_operand> for an ARM data processing instruction
04533    (as for parse_shifter_operand) where group relocations are allowed:
04534 
04535       #<immediate>
04536       #<immediate>, <rotate>
04537       #:<group_reloc>:<expression>
04538       <Rm>
04539       <Rm>, <shift>
04540 
04541    where <group_reloc> is one of the strings defined in group_reloc_table.
04542    The hashes are optional.
04543 
04544    Everything else is as for parse_shifter_operand.  */
04545 
04546 static parse_operand_result
04547 parse_shifter_operand_group_reloc (char **str, int i)
04548 {
04549   /* Determine if we have the sequence of characters #: or just :
04550      coming next.  If we do, then we check for a group relocation.
04551      If we don't, punt the whole lot to parse_shifter_operand.  */
04552 
04553   if (((*str)[0] == '#' && (*str)[1] == ':')
04554       || (*str)[0] == ':')
04555     {
04556       struct group_reloc_table_entry *entry;
04557 
04558       if ((*str)[0] == '#')
04559         (*str) += 2;
04560       else
04561         (*str)++;
04562 
04563       /* Try to parse a group relocation.  Anything else is an error.  */
04564       if (find_group_reloc_table_entry (str, &entry) == FAIL)
04565         {
04566           inst.error = _("unknown group relocation");
04567           return PARSE_OPERAND_FAIL_NO_BACKTRACK;
04568         }
04569 
04570       /* We now have the group relocation table entry corresponding to
04571          the name in the assembler source.  Next, we parse the expression.  */
04572       if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
04573         return PARSE_OPERAND_FAIL_NO_BACKTRACK;
04574 
04575       /* Record the relocation type (always the ALU variant here).  */
04576       inst.reloc.type = entry->alu_code;
04577       assert (inst.reloc.type != 0);
04578 
04579       return PARSE_OPERAND_SUCCESS;
04580     }
04581   else
04582     return parse_shifter_operand (str, i) == SUCCESS
04583            ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
04584 
04585   /* Never reached.  */
04586 }
04587 
04588 /* Parse all forms of an ARM address expression.  Information is written
04589    to inst.operands[i] and/or inst.reloc.
04590 
04591    Preindexed addressing (.preind=1):
04592 
04593    [Rn, #offset]       .reg=Rn .reloc.exp=offset
04594    [Rn, +/-Rm]              .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
04595    [Rn, +/-Rm, shift]  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
04596                      .shift_kind=shift .reloc.exp=shift_imm
04597 
04598    These three may have a trailing ! which causes .writeback to be set also.
04599 
04600    Postindexed addressing (.postind=1, .writeback=1):
04601 
04602    [Rn], #offset       .reg=Rn .reloc.exp=offset
04603    [Rn], +/-Rm              .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
04604    [Rn], +/-Rm, shift  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
04605                      .shift_kind=shift .reloc.exp=shift_imm
04606 
04607    Unindexed addressing (.preind=0, .postind=0):
04608 
04609    [Rn], {option}      .reg=Rn .imm=option .immisreg=0
04610 
04611    Other:
04612 
04613    [Rn]{!}           shorthand for [Rn,#0]{!}
04614    =immediate        .isreg=0 .reloc.exp=immediate
04615    label             .reg=PC .reloc.pc_rel=1 .reloc.exp=label
04616 
04617   It is the caller's responsibility to check for addressing modes not
04618   supported by the instruction, and to set inst.reloc.type.  */
04619 
04620 static parse_operand_result
04621 parse_address_main (char **str, int i, int group_relocations,
04622                     group_reloc_type group_type)
04623 {
04624   char *p = *str;
04625   int reg;
04626 
04627   if (skip_past_char (&p, '[') == FAIL)
04628     {
04629       if (skip_past_char (&p, '=') == FAIL)
04630        {
04631          /* bare address - translate to PC-relative offset */
04632          inst.reloc.pc_rel = 1;
04633          inst.operands[i].reg = REG_PC;
04634          inst.operands[i].isreg = 1;
04635          inst.operands[i].preind = 1;
04636        }
04637       /* else a load-constant pseudo op, no special treatment needed here */
04638 
04639       if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
04640        return PARSE_OPERAND_FAIL;
04641 
04642       *str = p;
04643       return PARSE_OPERAND_SUCCESS;
04644     }
04645 
04646   if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
04647     {
04648       inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
04649       return PARSE_OPERAND_FAIL;
04650     }
04651   inst.operands[i].reg = reg;
04652   inst.operands[i].isreg = 1;
04653 
04654   if (skip_past_comma (&p) == SUCCESS)
04655     {
04656       inst.operands[i].preind = 1;
04657 
04658       if (*p == '+') p++;
04659       else if (*p == '-') p++, inst.operands[i].negative = 1;
04660 
04661       if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
04662        {
04663          inst.operands[i].imm = reg;
04664          inst.operands[i].immisreg = 1;
04665 
04666          if (skip_past_comma (&p) == SUCCESS)
04667            if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
04668              return PARSE_OPERAND_FAIL;
04669        }
04670       else if (skip_past_char (&p, ':') == SUCCESS)
04671         {
04672           /* FIXME: '@' should be used here, but it's filtered out by generic
04673              code before we get to see it here. This may be subject to
04674              change.  */
04675           expressionS exp;
04676           my_get_expression (&exp, &p, GE_NO_PREFIX);
04677           if (exp.X_op != O_constant)
04678             {
04679               inst.error = _("alignment must be constant");
04680               return PARSE_OPERAND_FAIL;
04681             }
04682           inst.operands[i].imm = exp.X_add_number << 8;
04683           inst.operands[i].immisalign = 1;
04684           /* Alignments are not pre-indexes.  */
04685           inst.operands[i].preind = 0;
04686         }
04687       else
04688        {
04689          if (inst.operands[i].negative)
04690            {
04691              inst.operands[i].negative = 0;
04692              p--;
04693            }
04694 
04695          if (group_relocations &&
04696               ((*p == '#' && *(p + 1) == ':') || *p == ':'))
04697 
04698            {
04699              struct group_reloc_table_entry *entry;
04700 
04701               /* Skip over the #: or : sequence.  */
04702               if (*p == '#')
04703                 p += 2;
04704               else
04705                 p++;
04706 
04707              /* Try to parse a group relocation.  Anything else is an
04708                  error.  */
04709              if (find_group_reloc_table_entry (&p, &entry) == FAIL)
04710               {
04711                 inst.error = _("unknown group relocation");
04712                 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
04713               }
04714 
04715              /* We now have the group relocation table entry corresponding to
04716                the name in the assembler source.  Next, we parse the
04717                  expression.  */
04718              if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
04719               return PARSE_OPERAND_FAIL_NO_BACKTRACK;
04720 
04721              /* Record the relocation type.  */
04722               switch (group_type)
04723                 {
04724                   case GROUP_LDR:
04725                    inst.reloc.type = entry->ldr_code;
04726                     break;
04727 
04728                   case GROUP_LDRS:
04729                    inst.reloc.type = entry->ldrs_code;
04730                     break;
04731 
04732                   case GROUP_LDC:
04733                    inst.reloc.type = entry->ldc_code;
04734                     break;
04735 
04736                   default:
04737                     assert (0);
04738                 }
04739 
04740               if (inst.reloc.type == 0)
04741               {
04742                 inst.error = _("this group relocation is not allowed on this instruction");
04743                 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
04744               }
04745             }
04746           else
04747            if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
04748              return PARSE_OPERAND_FAIL;
04749        }
04750     }
04751 
04752   if (skip_past_char (&p, ']') == FAIL)
04753     {
04754       inst.error = _("']' expected");
04755       return PARSE_OPERAND_FAIL;
04756     }
04757 
04758   if (skip_past_char (&p, '!') == SUCCESS)
04759     inst.operands[i].writeback = 1;
04760 
04761   else if (skip_past_comma (&p) == SUCCESS)
04762     {
04763       if (skip_past_char (&p, '{') == SUCCESS)
04764        {
04765          /* [Rn], {expr} - unindexed, with option */
04766          if (parse_immediate (&p, &inst.operands[i].imm,
04767                             0, 255, TRUE) == FAIL)
04768            return PARSE_OPERAND_FAIL;
04769 
04770          if (skip_past_char (&p, '}') == FAIL)
04771            {
04772              inst.error = _("'}' expected at end of 'option' field");
04773              return PARSE_OPERAND_FAIL;
04774            }
04775          if (inst.operands[i].preind)
04776            {
04777              inst.error = _("cannot combine index with option");
04778              return PARSE_OPERAND_FAIL;
04779            }
04780          *str = p;
04781          return PARSE_OPERAND_SUCCESS;
04782        }
04783       else
04784        {
04785          inst.operands[i].postind = 1;
04786          inst.operands[i].writeback = 1;
04787 
04788          if (inst.operands[i].preind)
04789            {
04790              inst.error = _("cannot combine pre- and post-indexing");
04791              return PARSE_OPERAND_FAIL;
04792            }
04793 
04794          if (*p == '+') p++;
04795          else if (*p == '-') p++, inst.operands[i].negative = 1;
04796 
04797          if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
04798            {
04799               /* We might be using the immediate for alignment already. If we
04800                  are, OR the register number into the low-order bits.  */
04801               if (inst.operands[i].immisalign)
04802                inst.operands[i].imm |= reg;
04803               else
04804                 inst.operands[i].imm = reg;
04805              inst.operands[i].immisreg = 1;
04806 
04807              if (skip_past_comma (&p) == SUCCESS)
04808               if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
04809                 return PARSE_OPERAND_FAIL;
04810            }
04811          else
04812            {
04813              if (inst.operands[i].negative)
04814               {
04815                 inst.operands[i].negative = 0;
04816                 p--;
04817               }
04818              if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
04819               return PARSE_OPERAND_FAIL;
04820            }
04821        }
04822     }
04823 
04824   /* If at this point neither .preind nor .postind is set, we have a
04825      bare [Rn]{!}, which is shorthand for [Rn,#0]{!}.  */
04826   if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
04827     {
04828       inst.operands[i].preind = 1;
04829       inst.reloc.exp.X_op = O_constant;
04830       inst.reloc.exp.X_add_number = 0;
04831     }
04832   *str = p;
04833   return PARSE_OPERAND_SUCCESS;
04834 }
04835 
04836 static int
04837 parse_address (char **str, int i)
04838 {
04839   return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
04840          ? SUCCESS : FAIL;
04841 }
04842 
04843 static parse_operand_result
04844 parse_address_group_reloc (char **str, int i, group_reloc_type type)
04845 {
04846   return parse_address_main (str, i, 1, type);
04847 }
04848 
04849 /* Parse an operand for a MOVW or MOVT instruction.  */
04850 static int
04851 parse_half (char **str)
04852 {
04853   char * p;
04854   
04855   p = *str;
04856   skip_past_char (&p, '#');
04857   if (strncasecmp (p, ":lower16:", 9) == 0) 
04858     inst.reloc.type = BFD_RELOC_ARM_MOVW;
04859   else if (strncasecmp (p, ":upper16:", 9) == 0)
04860     inst.reloc.type = BFD_RELOC_ARM_MOVT;
04861 
04862   if (inst.reloc.type != BFD_RELOC_UNUSED)
04863     {
04864       p += 9;
04865       skip_whitespace(p);
04866     }
04867 
04868   if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
04869     return FAIL;
04870 
04871   if (inst.reloc.type == BFD_RELOC_UNUSED)
04872     {
04873       if (inst.reloc.exp.X_op != O_constant)
04874        {
04875          inst.error = _("constant expression expected");
04876          return FAIL;
04877        }
04878       if (inst.reloc.exp.X_add_number < 0
04879          || inst.reloc.exp.X_add_number > 0xffff)
04880        {
04881          inst.error = _("immediate value out of range");
04882          return FAIL;
04883        }
04884     }
04885   *str = p;
04886   return SUCCESS;
04887 }
04888 
04889 /* Miscellaneous. */
04890 
04891 /* Parse a PSR flag operand.  The value returned is FAIL on syntax error,
04892    or a bitmask suitable to be or-ed into the ARM msr instruction.  */
04893 static int
04894 parse_psr (char **str)
04895 {
04896   char *p;
04897   unsigned long psr_field;
04898   const struct asm_psr *psr;
04899   char *start;
04900 
04901   /* CPSR's and SPSR's can now be lowercase.  This is just a convenience
04902      feature for ease of use and backwards compatibility.  */
04903   p = *str;
04904   if (strncasecmp (p, "SPSR", 4) == 0)
04905     psr_field = SPSR_BIT;
04906   else if (strncasecmp (p, "CPSR", 4) == 0)
04907     psr_field = 0;
04908   else
04909     {
04910       start = p;
04911       do
04912        p++;
04913       while (ISALNUM (*p) || *p == '_');
04914 
04915       psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
04916       if (!psr)
04917        return FAIL;
04918 
04919       *str = p;
04920       return psr->field;
04921     }
04922 
04923   p += 4;
04924   if (*p == '_')
04925     {
04926       /* A suffix follows.  */
04927       p++;
04928       start = p;
04929 
04930       do
04931        p++;
04932       while (ISALNUM (*p) || *p == '_');
04933 
04934       psr = hash_find_n (arm_psr_hsh, start, p - start);
04935       if (!psr)
04936        goto error;
04937 
04938       psr_field |= psr->field;
04939     }
04940   else
04941     {
04942       if (ISALNUM (*p))
04943        goto error;    /* Garbage after "[CS]PSR".  */
04944 
04945       psr_field |= (PSR_c | PSR_f);
04946     }
04947   *str = p;
04948   return psr_field;
04949 
04950  error:
04951   inst.error = _("flag for {c}psr instruction expected");
04952   return FAIL;
04953 }
04954 
04955 /* Parse the flags argument to CPSI[ED].  Returns FAIL on error, or a
04956    value suitable for splatting into the AIF field of the instruction.       */
04957 
04958 static int
04959 parse_cps_flags (char **str)
04960 {
04961   int val = 0;
04962   int saw_a_flag = 0;
04963   char *s = *str;
04964 
04965   for (;;)
04966     switch (*s++)
04967       {
04968       case '\0': case ',':
04969        goto done;
04970 
04971       case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
04972       case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
04973       case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
04974 
04975       default:
04976        inst.error = _("unrecognized CPS flag");
04977        return FAIL;
04978       }
04979 
04980  done:
04981   if (saw_a_flag == 0)
04982     {
04983       inst.error = _("missing CPS flags");
04984       return FAIL;
04985     }
04986 
04987   *str = s - 1;
04988   return val;
04989 }
04990 
04991 /* Parse an endian specifier ("BE" or "LE", case insensitive);
04992    returns 0 for big-endian, 1 for little-endian, FAIL for an error.  */
04993 
04994 static int
04995 parse_endian_specifier (char **str)
04996 {
04997   int little_endian;
04998   char *s = *str;
04999 
05000   if (strncasecmp (s, "BE", 2))
05001     little_endian = 0;
05002   else if (strncasecmp (s, "LE", 2))
05003     little_endian = 1;
05004   else
05005     {
05006       inst.error = _("valid endian specifiers are be or le");
05007       return FAIL;
05008     }
05009 
05010   if (ISALNUM (s[2]) || s[2] == '_')
05011     {
05012       inst.error = _("valid endian specifiers are be or le");
05013       return FAIL;
05014     }
05015 
05016   *str = s + 2;
05017   return little_endian;
05018 }
05019 
05020 /* Parse a rotation specifier: ROR #0, #8, #16, #24.  *val receives a
05021    value suitable for poking into the rotate field of an sxt or sxta
05022    instruction, or FAIL on error.  */
05023 
05024 static int
05025 parse_ror (char **str)
05026 {
05027   int rot;
05028   char *s = *str;
05029 
05030   if (strncasecmp (s, "ROR", 3) == 0)
05031     s += 3;
05032   else
05033     {
05034       inst.error = _("missing rotation field after comma");
05035       return FAIL;
05036     }
05037 
05038   if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
05039     return FAIL;
05040 
05041   switch (rot)
05042     {
05043     case  0: *str = s; return 0x0;
05044     case  8: *str = s; return 0x1;
05045     case 16: *str = s; return 0x2;
05046     case 24: *str = s; return 0x3;
05047 
05048     default:
05049       inst.error = _("rotation can only be 0, 8, 16, or 24");
05050       return FAIL;
05051     }
05052 }
05053 
05054 /* Parse a conditional code (from conds[] below).  The value returned is in the
05055    range 0 .. 14, or FAIL.  */
05056 static int
05057 parse_cond (char **str)
05058 {
05059   char *p, *q;
05060   const struct asm_cond *c;
05061 
05062   p = q = *str;
05063   while (ISALPHA (*q))
05064     q++;
05065 
05066   c = hash_find_n (arm_cond_hsh, p, q - p);
05067   if (!c)
05068     {
05069       inst.error = _("condition required");
05070       return FAIL;
05071     }
05072 
05073   *str = q;
05074   return c->value;
05075 }
05076 
05077 /* Parse an option for a barrier instruction.  Returns the encoding for the
05078    option, or FAIL.  */
05079 static int
05080 parse_barrier (char **str)
05081 {
05082   char *p, *q;
05083   const struct asm_barrier_opt *o;
05084 
05085   p = q = *str;
05086   while (ISALPHA (*q))
05087     q++;
05088 
05089   o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
05090   if (!o)
05091     return FAIL;
05092 
05093   *str = q;
05094   return o->value;
05095 }
05096 
05097 /* Parse the operands of a table branch instruction.  Similar to a memory
05098    operand.  */
05099 static int
05100 parse_tb (char **str)
05101 {
05102   char * p = *str;
05103   int reg;
05104 
05105   if (skip_past_char (&p, '[') == FAIL)
05106     {
05107       inst.error = _("'[' expected");
05108       return FAIL;
05109     }
05110 
05111   if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
05112     {
05113       inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
05114       return FAIL;
05115     }
05116   inst.operands[0].reg = reg;
05117 
05118   if (skip_past_comma (&p) == FAIL)
05119     {
05120       inst.error = _("',' expected");
05121       return FAIL;
05122     }
05123   
05124   if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
05125     {
05126       inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
05127       return FAIL;
05128     }
05129   inst.operands[0].imm = reg;
05130 
05131   if (skip_past_comma (&p) == SUCCESS)
05132     {
05133       if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
05134        return FAIL;
05135       if (inst.reloc.exp.X_add_number != 1)
05136        {
05137          inst.error = _("invalid shift");
05138          return FAIL;
05139        }
05140       inst.operands[0].shifted = 1;
05141     }
05142 
05143   if (skip_past_char (&p, ']') == FAIL)
05144     {
05145       inst.error = _("']' expected");
05146       return FAIL;
05147     }
05148   *str = p;
05149   return SUCCESS;
05150 }
05151 
05152 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
05153    information on the types the operands can take and how they are encoded.
05154    Up to four operands may be read; this function handles setting the
05155    ".present" field for each read operand itself.
05156    Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
05157    else returns FAIL.  */
05158 
05159 static int
05160 parse_neon_mov (char **str, int *which_operand)
05161 {
05162   int i = *which_operand, val;
05163   enum arm_reg_type rtype;
05164   char *ptr = *str;
05165   struct neon_type_el optype;
05166   
05167   if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
05168     {
05169       /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>.  */
05170       inst.operands[i].reg = val;
05171       inst.operands[i].isscalar = 1;
05172       inst.operands[i].vectype = optype;
05173       inst.operands[i++].present = 1;
05174 
05175       if (skip_past_comma (&ptr) == FAIL)
05176         goto wanted_comma;
05177       
05178       if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
05179         goto wanted_arm;
05180       
05181       inst.operands[i].reg = val;
05182       inst.operands[i].isreg = 1;
05183       inst.operands[i].present = 1;
05184     }
05185   else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
05186            != FAIL)
05187     {
05188       /* Cases 0, 1, 2, 3, 5 (D only).  */
05189       if (skip_past_comma (&ptr) == FAIL)
05190         goto wanted_comma;
05191       
05192       inst.operands[i].reg = val;
05193       inst.operands[i].isreg = 1;
05194       inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
05195       inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
05196       inst.operands[i].isvec = 1;
05197       inst.operands[i].vectype = optype;
05198       inst.operands[i++].present = 1;
05199 
05200       if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
05201         {
05202           /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
05203              Case 13: VMOV <Sd>, <Rm>  */
05204           inst.operands[i].reg = val;
05205           inst.operands[i].isreg = 1;
05206           inst.operands[i].present = 1;
05207 
05208           if (rtype == REG_TYPE_NQ)
05209             {
05210               first_error (_("can't use Neon quad register here"));
05211               return FAIL;
05212             }
05213           else if (rtype != REG_TYPE_VFS)
05214             {
05215               i++;
05216               if (skip_past_comma (&ptr) == FAIL)
05217                 goto wanted_comma;
05218               if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
05219                 goto wanted_arm;
05220               inst.operands[i].reg = val;
05221               inst.operands[i].isreg = 1;
05222               inst.operands[i].present = 1;
05223             }
05224         }
05225       else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
05226           /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
05227              Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
05228              Case 10: VMOV.F32 <Sd>, #<imm>
05229              Case 11: VMOV.F64 <Dd>, #<imm>  */
05230         inst.operands[i].immisfloat = 1;
05231       else if (parse_big_immediate (&ptr, i) == SUCCESS)
05232           /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
05233              Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */
05234         ;
05235       else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
05236                                            &optype)) != FAIL)
05237         {
05238           /* Case 0: VMOV<c><q> <Qd>, <Qm>
05239              Case 1: VMOV<c><q> <Dd>, <Dm>
05240              Case 8: VMOV.F32 <Sd>, <Sm>
05241              Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm>  */
05242 
05243           inst.operands[i].reg = val;
05244           inst.operands[i].isreg = 1;
05245           inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
05246           inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
05247           inst.operands[i].isvec = 1;
05248           inst.operands[i].vectype = optype;
05249           inst.operands[i].present = 1;
05250           
05251           if (skip_past_comma (&ptr) == SUCCESS)
05252             {
05253               /* Case 15.  */
05254               i++;
05255 
05256               if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
05257                 goto wanted_arm;
05258 
05259               inst.operands[i].reg = val;
05260               inst.operands[i].isreg = 1;
05261               inst.operands[i++].present = 1;
05262               
05263               if (skip_past_comma (&ptr) == FAIL)
05264                 goto wanted_comma;
05265               
05266               if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
05267                 goto wanted_arm;
05268               
05269               inst.operands[i].reg = val;
05270               inst.operands[i].isreg = 1;
05271               inst.operands[i++].present = 1;
05272             }
05273         }
05274       else
05275         {
05276           first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
05277           return FAIL;
05278         }
05279     }
05280   else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
05281     {
05282       /* Cases 6, 7.  */
05283       inst.operands[i].reg = val;
05284       inst.operands[i].isreg = 1;
05285       inst.operands[i++].present = 1;
05286       
05287       if (skip_past_comma (&ptr) == FAIL)
05288         goto wanted_comma;
05289       
05290       if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
05291         {
05292           /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]>  */
05293           inst.operands[i].reg = val;
05294           inst.operands[i].isscalar = 1;
05295           inst.operands[i].present = 1;
05296           inst.operands[i].vectype = optype;
05297         }
05298       else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
05299         {
05300           /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm>  */
05301           inst.operands[i].reg = val;
05302           inst.operands[i].isreg = 1;
05303           inst.operands[i++].present = 1;
05304           
05305           if (skip_past_comma (&ptr) == FAIL)
05306             goto wanted_comma;
05307           
05308           if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
05309               == FAIL)
05310             {
05311               first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
05312               return FAIL;
05313             }
05314 
05315           inst.operands[i].reg = val;
05316           inst.operands[i].isreg = 1;
05317           inst.operands[i].isvec = 1;
05318           inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
05319           inst.operands[i].vectype = optype;
05320           inst.operands[i].present = 1;
05321           
05322           if (rtype == REG_TYPE_VFS)
05323             {
05324               /* Case 14.  */
05325               i++;
05326               if (skip_past_comma (&ptr) == FAIL)
05327                 goto wanted_comma;
05328               if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
05329                                               &optype)) == FAIL)
05330                 {
05331                   first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
05332                   return FAIL;
05333                 }
05334               inst.operands[i].reg = val;
05335               inst.operands[i].isreg = 1;
05336               inst.operands[i].isvec = 1;
05337               inst.operands[i].issingle = 1;
05338               inst.operands[i].vectype = optype;
05339               inst.operands[i].present = 1;
05340             }
05341         }
05342       else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
05343                != FAIL)
05344         {
05345           /* Case 13.  */
05346           inst.operands[i].reg = val;
05347           inst.operands[i].isreg = 1;
05348           inst.operands[i].isvec = 1;
05349           inst.operands[i].issingle = 1;
05350           inst.operands[i].vectype = optype;
05351           inst.operands[i++].present = 1;
05352         }
05353     }
05354   else
05355     {
05356       first_error (_("parse error"));
05357       return FAIL;
05358     }
05359 
05360   /* Successfully parsed the operands. Update args.  */
05361   *which_operand = i;
05362   *str = ptr;
05363   return SUCCESS;
05364 
05365   wanted_comma:
05366   first_error (_("expected comma"));
05367   return FAIL;
05368   
05369   wanted_arm:
05370   first_error (_(reg_expected_msgs[REG_TYPE_RN]));
05371   return FAIL;
05372 }
05373 
05374 /* Matcher codes for parse_operands.  */
05375 enum operand_parse_code
05376 {
05377   OP_stop,    /* end of line */
05378 
05379   OP_RR,      /* ARM register */
05380   OP_RRnpc,   /* ARM register, not r15 */
05381   OP_RRnpcb,  /* ARM register, not r15, in square brackets */
05382   OP_RRw,     /* ARM register, not r15, optional trailing ! */
05383   OP_RCP,     /* Coprocessor number */
05384   OP_RCN,     /* Coprocessor register */
05385   OP_RF,      /* FPA register */
05386   OP_RVS,     /* VFP single precision register */
05387   OP_RVD,     /* VFP double precision register (0..15) */
05388   OP_RND,       /* Neon double precision register (0..31) */
05389   OP_RNQ,     /* Neon quad precision register */
05390   OP_RVSD,    /* VFP single or double precision register */
05391   OP_RNDQ,      /* Neon double or quad precision register */
05392   OP_RNSDQ,   /* Neon single, double or quad precision register */
05393   OP_RNSC,      /* Neon scalar D[X] */
05394   OP_RVC,     /* VFP control register */
05395   OP_RMF,     /* Maverick F register */
05396   OP_RMD,     /* Maverick D register */
05397   OP_RMFX,    /* Maverick FX register */
05398   OP_RMDX,    /* Maverick DX register */
05399   OP_RMAX,    /* Maverick AX register */
05400   OP_RMDS,    /* Maverick DSPSC register */
05401   OP_RIWR,    /* iWMMXt wR register */
05402   OP_RIWC,    /* iWMMXt wC register */
05403   OP_RIWG,    /* iWMMXt wCG register */
05404   OP_RXA,     /* XScale accumulator register */
05405 
05406   OP_REGLST,  /* ARM register list */
05407   OP_VRSLST,  /* VFP single-precision register list */
05408   OP_VRDLST,  /* VFP double-precision register list */
05409   OP_VRSDLST,   /* VFP single or double-precision register list (& quad) */
05410   OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
05411   OP_NSTRLST,   /* Neon element/structure list */
05412 
05413   OP_NILO,      /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...)  */
05414   OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
05415   OP_RVSD_I0, /* VFP S or D reg, or immediate zero.  */
05416   OP_RR_RNSC,   /* ARM reg or Neon scalar.  */
05417   OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar.  */
05418   OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar.  */
05419   OP_RND_RNSC,  /* Neon D reg, or Neon scalar.  */
05420   OP_VMOV,      /* Neon VMOV operands.  */
05421   OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN.  */
05422   OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
05423   OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */
05424 
05425   OP_I0,        /* immediate zero */
05426   OP_I7,      /* immediate value 0 .. 7 */
05427   OP_I15,     /*               0 .. 15 */
05428   OP_I16,     /*               1 .. 16 */
05429   OP_I16z,      /*                 0 .. 16 */
05430   OP_I31,     /*               0 .. 31 */
05431   OP_I31w,    /*               0 .. 31, optional trailing ! */
05432   OP_I32,     /*               1 .. 32 */
05433   OP_I32z,    /*               0 .. 32 */
05434   OP_I63,     /*               0 .. 63 */
05435   OP_I63s,    /*             -64 .. 63 */
05436   OP_I64,     /*               1 .. 64 */
05437   OP_I64z,    /*               0 .. 64 */
05438   OP_I255,    /*               0 .. 255 */
05439 
05440   OP_I4b,     /* immediate, prefix optional, 1 .. 4 */
05441   OP_I7b,     /*                          0 .. 7 */
05442   OP_I15b,    /*                          0 .. 15 */
05443   OP_I31b,    /*                          0 .. 31 */
05444 
05445   OP_SH,      /* shifter operand */
05446   OP_SHG,     /* shifter operand with possible group relocation */
05447   OP_ADDR,    /* Memory address expression (any mode) */
05448   OP_ADDRGLDR,       /* Mem addr expr (any mode) with possible LDR group reloc */
05449   OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
05450   OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
05451   OP_EXP,     /* arbitrary expression */
05452   OP_EXPi,    /* same, with optional immediate prefix */
05453   OP_EXPr,    /* same, with optional relocation suffix */
05454   OP_HALF,    /* 0 .. 65535 or low/high reloc.  */
05455 
05456   OP_CPSF,    /* CPS flags */
05457   OP_ENDI,    /* Endianness specifier */
05458   OP_PSR,     /* CPSR/SPSR mask for msr */
05459   OP_COND,    /* conditional code */
05460   OP_TB,      /* Table branch.  */
05461 
05462   OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register.  */
05463   OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */
05464 
05465   OP_RRnpc_I0,       /* ARM register or literal 0 */
05466   OP_RR_EXr,  /* ARM register or expression with opt. reloc suff. */
05467   OP_RR_EXi,  /* ARM register or expression with imm prefix */
05468   OP_RF_IF,   /* FPA register or immediate */
05469   OP_RIWR_RIWC, /* iWMMXt R or C reg */
05470   OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
05471 
05472   /* Optional operands.      */
05473   OP_oI7b,     /* immediate, prefix optional, 0 .. 7 */
05474   OP_oI31b,    /*                         0 .. 31 */
05475   OP_oI32b,      /*                             1 .. 32 */
05476   OP_oIffffb,  /*                         0 .. 65535 */
05477   OP_oI255c,   /*      curly-brace enclosed, 0 .. 255 */
05478 
05479   OP_oRR,      /* ARM register */
05480   OP_oRRnpc,   /* ARM register, not the PC */
05481   OP_oRRw,     /* ARM register, not r15, optional trailing ! */
05482   OP_oRND,       /* Optional Neon double precision register */
05483   OP_oRNQ,       /* Optional Neon quad precision register */
05484   OP_oRNDQ,      /* Optional Neon double or quad precision register */
05485   OP_oRNSDQ,   /* Optional single, double or quad precision vector register */
05486   OP_oSHll,    /* LSL immediate */
05487   OP_oSHar,    /* ASR immediate */
05488   OP_oSHllar,  /* LSL or ASR immediate */
05489   OP_oROR,     /* ROR 0/8/16/24 */
05490   OP_oBARRIER,        /* Option argument for a barrier instruction.  */
05491 
05492   OP_FIRST_OPTIONAL = OP_oI7b
05493 };
05494 
05495 /* Generic instruction operand parser.    This does no encoding and no
05496    semantic validation; it merely squirrels values away in the inst
05497    structure.  Returns SUCCESS or FAIL depending on whether the
05498    specified grammar matched.  */
05499 static int
05500 parse_operands (char *str, const unsigned char *pattern)
05501 {
05502   unsigned const char *upat = pattern;
05503   char *backtrack_pos = 0;
05504   const char *backtrack_error = 0;
05505   int i, val, backtrack_index = 0;
05506   enum arm_reg_type rtype;
05507   parse_operand_result result;
05508 
05509 #define po_char_or_fail(chr) do {         \
05510   if (skip_past_char (&str, chr) == FAIL) \
05511     goto bad_args;                        \
05512 } while (0)
05513 
05514 #define po_reg_or_fail(regtype) do {                           \
05515   val = arm_typed_reg_parse (&str, regtype, &rtype,            \
05516                           &inst.operands[i].vectype);   \
05517   if (val == FAIL)                                      \
05518     {                                                   \
05519       first_error (_(reg_expected_msgs[regtype]));             \
05520       goto failure;                                     \
05521     }                                                   \
05522   inst.operands[i].reg = val;                                  \
05523   inst.operands[i].isreg = 1;                                  \
05524   inst.operands[i].isquad = (rtype == REG_TYPE_NQ);            \
05525   inst.operands[i].issingle = (rtype == REG_TYPE_VFS);         \
05526   inst.operands[i].isvec = (rtype == REG_TYPE_VFS              \
05527                             || rtype == REG_TYPE_VFD           \
05528                             || rtype == REG_TYPE_NQ);          \
05529 } while (0)
05530 
05531 #define po_reg_or_goto(regtype, label) do {                    \
05532   val = arm_typed_reg_parse (&str, regtype, &rtype,            \
05533                              &inst.operands[i].vectype);       \
05534   if (val == FAIL)                                      \
05535     goto label;                                                \
05536                                                         \
05537   inst.operands[i].reg = val;                                  \
05538   inst.operands[i].isreg = 1;                                  \
05539   inst.operands[i].isquad = (rtype == REG_TYPE_NQ);            \
05540   inst.operands[i].issingle = (rtype == REG_TYPE_VFS);         \
05541   inst.operands[i].isvec = (rtype == REG_TYPE_VFS              \
05542                             || rtype == REG_TYPE_VFD           \
05543                             || rtype == REG_TYPE_NQ);          \
05544 } while (0)
05545 
05546 #define po_imm_or_fail(min, max, popt) do {                    \
05547   if (parse_immediate (&str, &val, min, max, popt) == FAIL)    \
05548     goto failure;                                       \
05549   inst.operands[i].imm = val;                                  \
05550 } while (0)
05551 
05552 #define po_scalar_or_goto(elsz, label) do {                    \
05553   val = parse_scalar (&str, elsz, &inst.operands[i].vectype);  \
05554   if (val == FAIL)                                      \
05555     goto label;                                                \
05556   inst.operands[i].reg = val;                                  \
05557   inst.operands[i].isscalar = 1;                        \
05558 } while (0)
05559 
05560 #define po_misc_or_fail(expr) do {        \
05561   if (expr)                               \
05562     goto failure;                         \
05563 } while (0)
05564 
05565 #define po_misc_or_fail_no_backtrack(expr) do {  \
05566   result = expr;                          \
05567   if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
05568     backtrack_pos = 0;                           \
05569   if (result != PARSE_OPERAND_SUCCESS)           \
05570     goto failure;                         \
05571 } while (0)
05572 
05573   skip_whitespace (str);
05574 
05575   for (i = 0; upat[i] != OP_stop; i++)
05576     {
05577       if (upat[i] >= OP_FIRST_OPTIONAL)
05578        {
05579          /* Remember where we are in case we need to backtrack.  */
05580          assert (!backtrack_pos);
05581          backtrack_pos = str;
05582          backtrack_error = inst.error;
05583          backtrack_index = i;
05584        }
05585 
05586       if (i > 0 && (i > 1 || inst.operands[0].present))
05587        po_char_or_fail (',');
05588 
05589       switch (upat[i])
05590        {
05591          /* Registers */
05592        case OP_oRRnpc:
05593        case OP_RRnpc:
05594        case OP_oRR:
05595        case OP_RR:    po_reg_or_fail (REG_TYPE_RN);       break;
05596        case OP_RCP:   po_reg_or_fail (REG_TYPE_CP);       break;
05597        case OP_RCN:   po_reg_or_fail (REG_TYPE_CN);       break;
05598        case OP_RF:    po_reg_or_fail (REG_TYPE_FN);       break;
05599        case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);      break;
05600        case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);      break;
05601         case OP_oRND:
05602        case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);      break;
05603        case OP_RVC:   po_reg_or_fail (REG_TYPE_VFC);      break;
05604        case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);      break;
05605        case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);      break;
05606        case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);     break;
05607        case OP_RMDX:  po_reg_or_fail (REG_TYPE_MVDX);     break;
05608        case OP_RMAX:  po_reg_or_fail (REG_TYPE_MVAX);     break;
05609        case OP_RMDS:  po_reg_or_fail (REG_TYPE_DSPSC);    break;
05610        case OP_RIWR:  po_reg_or_fail (REG_TYPE_MMXWR);    break;
05611        case OP_RIWC:  po_reg_or_fail (REG_TYPE_MMXWC);    break;
05612        case OP_RIWG:  po_reg_or_fail (REG_TYPE_MMXWCG);  break;
05613        case OP_RXA:   po_reg_or_fail (REG_TYPE_XSCALE);  break;
05614         case OP_oRNQ:
05615        case OP_RNQ:   po_reg_or_fail (REG_TYPE_NQ);      break;
05616         case OP_oRNDQ:
05617        case OP_RNDQ:  po_reg_or_fail (REG_TYPE_NDQ);     break;
05618         case OP_RVSD:  po_reg_or_fail (REG_TYPE_VFSD);    break;
05619         case OP_oRNSDQ:
05620         case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
05621 
05622         /* Neon scalar. Using an element size of 8 means that some invalid
05623            scalars are accepted here, so deal with those in later code.  */
05624         case OP_RNSC:  po_scalar_or_goto (8, failure);    break;
05625 
05626         /* WARNING: We can expand to two operands here. This has the potential
05627            to totally confuse the backtracking mechanism! It will be OK at
05628            least as long as we don't try to use optional args as well,
05629            though.  */
05630         case OP_NILO:
05631           {
05632             po_reg_or_goto (REG_TYPE_NDQ, try_imm);
05633            inst.operands[i].present = 1;
05634             i++;
05635             skip_past_comma (&str);
05636             po_reg_or_goto (REG_TYPE_NDQ, one_reg_only);
05637             break;
05638             one_reg_only:
05639             /* Optional register operand was omitted. Unfortunately, it's in
05640                operands[i-1] and we need it to be in inst.operands[i]. Fix that
05641                here (this is a bit grotty).  */
05642             inst.operands[i] = inst.operands[i-1];
05643             inst.operands[i-1].present = 0;
05644             break;
05645             try_imm:
05646            /* There's a possibility of getting a 64-bit immediate here, so
05647               we need special handling.  */
05648            if (parse_big_immediate (&str, i) == FAIL)
05649              {
05650               inst.error = _("immediate value is out of range");
05651               goto failure;
05652              }
05653           }
05654           break;
05655 
05656         case OP_RNDQ_I0:
05657           {
05658             po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
05659             break;
05660             try_imm0:
05661             po_imm_or_fail (0, 0, TRUE);
05662           }
05663           break;
05664 
05665         case OP_RVSD_I0:
05666           po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
05667           break;
05668 
05669         case OP_RR_RNSC:
05670           {
05671             po_scalar_or_goto (8, try_rr);
05672             break;
05673             try_rr:
05674             po_reg_or_fail (REG_TYPE_RN);
05675           }
05676           break;
05677 
05678         case OP_RNSDQ_RNSC:
05679           {
05680             po_scalar_or_goto (8, try_nsdq);
05681             break;
05682             try_nsdq:
05683             po_reg_or_fail (REG_TYPE_NSDQ);
05684           }
05685           break;
05686 
05687         case OP_RNDQ_RNSC:
05688           {
05689             po_scalar_or_goto (8, try_ndq);
05690             break;
05691             try_ndq:
05692             po_reg_or_fail (REG_TYPE_NDQ);
05693           }
05694           break;
05695 
05696         case OP_RND_RNSC:
05697           {
05698             po_scalar_or_goto (8, try_vfd);
05699             break;
05700             try_vfd:
05701             po_reg_or_fail (REG_TYPE_VFD);
05702           }
05703           break;
05704 
05705         case OP_VMOV:
05706           /* WARNING: parse_neon_mov can move the operand counter, i. If we're
05707              not careful then bad things might happen.  */
05708           po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
05709           break;
05710 
05711         case OP_RNDQ_IMVNb:
05712           {
05713             po_reg_or_goto (REG_TYPE_NDQ, try_mvnimm);
05714             break;
05715             try_mvnimm:
05716             /* There's a possibility of getting a 64-bit immediate here, so
05717                we need special handling.  */
05718             if (parse_big_immediate (&str, i) == FAIL)
05719               {
05720                 inst.error = _("immediate value is out of range");
05721                 goto failure;
05722               }
05723           }
05724           break;
05725 
05726         case OP_RNDQ_I63b:
05727           {
05728             po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
05729             break;
05730             try_shimm:
05731             po_imm_or_fail (0, 63, TRUE);
05732           }
05733           break;
05734 
05735        case OP_RRnpcb:
05736          po_char_or_fail ('[');
05737          po_reg_or_fail  (REG_TYPE_RN);
05738          po_char_or_fail (']');
05739          break;
05740 
05741        case OP_RRw:
05742        case OP_oRRw:
05743          po_reg_or_fail (REG_TYPE_RN);
05744          if (skip_past_char (&str, '!') == SUCCESS)
05745            inst.operands[i].writeback = 1;
05746          break;
05747 
05748          /* Immediates */
05749        case OP_I7:    po_imm_or_fail (  0,          7, FALSE); break;
05750        case OP_I15:   po_imm_or_fail (  0,         15, FALSE); break;
05751        case OP_I16:   po_imm_or_fail (  1,         16, FALSE); break;
05752         case OP_I16z:        po_imm_or_fail (  0,     16, FALSE);   break;
05753        case OP_I31:   po_imm_or_fail (  0,         31, FALSE); break;
05754        case OP_I32:   po_imm_or_fail (  1,         32, FALSE); break;
05755         case OP_I32z:        po_imm_or_fail (  0,     32, FALSE);   break;
05756        case OP_I63s:  po_imm_or_fail (-64,         63, FALSE); break;
05757         case OP_I63:  po_imm_or_fail (  0,     63, FALSE);   break;
05758         case OP_I64:  po_imm_or_fail (  1,     64, FALSE);   break;
05759         case OP_I64z:        po_imm_or_fail (  0,     64, FALSE);   break;
05760        case OP_I255:  po_imm_or_fail (  0,        255, FALSE); break;
05761 
05762        case OP_I4b:   po_imm_or_fail (  1,          4, TRUE);  break;
05763        case OP_oI7b:
05764        case OP_I7b:   po_imm_or_fail (  0,          7, TRUE);  break;
05765        case OP_I15b:  po_imm_or_fail (  0,         15, TRUE);  break;
05766        case OP_oI31b:
05767        case OP_I31b:  po_imm_or_fail (  0,         31, TRUE);  break;
05768         case OP_oI32b:   po_imm_or_fail (  1,     32, TRUE);    break;
05769        case OP_oIffffb: po_imm_or_fail (  0, 0xffff, TRUE);    break;
05770 
05771          /* Immediate variants */
05772        case OP_oI255c:
05773          po_char_or_fail ('{');
05774          po_imm_or_fail (0, 255, TRUE);
05775          po_char_or_fail ('}');
05776          break;
05777 
05778        case OP_I31w:
05779          /* The expression parser chokes on a trailing !, so we have
05780             to find it first and zap it.  */
05781          {
05782            char *s = str;
05783            while (*s && *s != ',')
05784              s++;
05785            if (s[-1] == '!')
05786              {
05787               s[-1] = '\0';
05788               inst.operands[i].writeback = 1;
05789              }
05790            po_imm_or_fail (0, 31, TRUE);
05791            if (str == s - 1)
05792              str = s;
05793          }
05794          break;
05795 
05796          /* Expressions */
05797        case OP_EXPi: EXPi:
05798          po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
05799                                          GE_OPT_PREFIX));
05800          break;
05801 
05802        case OP_EXP:
05803          po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
05804                                          GE_NO_PREFIX));
05805          break;
05806 
05807        case OP_EXPr: EXPr:
05808          po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
05809                                          GE_NO_PREFIX));
05810          if (inst.reloc.exp.X_op == O_symbol)
05811            {
05812              val = parse_reloc (&str);
05813              if (val == -1)
05814               {
05815                 inst.error = _("unrecognized relocation suffix");
05816                 goto failure;
05817               }
05818              else if (val != BFD_RELOC_UNUSED)
05819               {
05820                 inst.operands[i].imm = val;
05821                 inst.operands[i].hasreloc = 1;
05822               }
05823            }
05824          break;
05825 
05826          /* Operand for MOVW or MOVT.  */
05827        case OP_HALF:
05828          po_misc_or_fail (parse_half (&str));
05829          break;
05830 
05831          /* Register or expression */
05832        case OP_RR_EXr:        po_reg_or_goto (REG_TYPE_RN, EXPr); break;
05833        case OP_RR_EXi:        po_reg_or_goto (REG_TYPE_RN, EXPi); break;
05834 
05835          /* Register or immediate */
05836        case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0);   break;
05837        I0:             po_imm_or_fail (0, 0, FALSE);          break;
05838 
05839        case OP_RF_IF:    po_reg_or_goto (REG_TYPE_FN, IF);   break;
05840        IF:
05841          if (!is_immediate_prefix (*str))
05842            goto bad_args;
05843          str++;
05844          val = parse_fpa_immediate (&str);
05845          if (val == FAIL)
05846            goto failure;
05847          /* FPA immediates are encoded as registers 8-15.
05848             parse_fpa_immediate has already applied the offset.  */
05849          inst.operands[i].reg = val;
05850          inst.operands[i].isreg = 1;
05851          break;
05852 
05853        case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
05854        I32z:           po_imm_or_fail (0, 32, FALSE);     break;
05855 
05856          /* Two kinds of register */
05857        case OP_RIWR_RIWC:
05858          {
05859            struct reg_entry *rege = arm_reg_parse_multi (&str);
05860            if (!rege
05861               || (rege->type != REG_TYPE_MMXWR
05862                   && rege->type != REG_TYPE_MMXWC
05863                   && rege->type != REG_TYPE_MMXWCG))
05864              {
05865               inst.error = _("iWMMXt data or control register expected");
05866               goto failure;
05867              }
05868            inst.operands[i].reg = rege->number;
05869            inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
05870          }
05871          break;
05872 
05873        case OP_RIWC_RIWG:
05874          {
05875            struct reg_entry *rege = arm_reg_parse_multi (&str);
05876            if (!rege
05877               || (rege->type != REG_TYPE_MMXWC
05878                   && rege->type != REG_TYPE_MMXWCG))
05879              {
05880               inst.error = _("iWMMXt control register expected");
05881               goto failure;
05882              }
05883            inst.operands[i].reg = rege->number;
05884            inst.operands[i].isreg = 1;
05885          }
05886          break;
05887 
05888          /* Misc */
05889        case OP_CPSF:  val = parse_cps_flags (&str);            break;
05890        case OP_ENDI:  val = parse_endian_specifier (&str);     break;
05891        case OP_oROR:  val = parse_ror (&str);           break;
05892        case OP_PSR:   val = parse_psr (&str);           break;
05893        case OP_COND:  val = parse_cond (&str);          break;
05894        case OP_oBARRIER:val = parse_barrier (&str);            break;
05895 
05896         case OP_RVC_PSR:
05897           po_reg_or_goto (REG_TYPE_VFC, try_psr);
05898           inst.operands[i].isvec = 1;  /* Mark VFP control reg as vector.  */
05899           break;
05900           try_psr:
05901           val = parse_psr (&str);
05902           break;
05903 
05904         case OP_APSR_RR:
05905           po_reg_or_goto (REG_TYPE_RN, try_apsr);
05906           break;
05907           try_apsr:
05908           /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
05909              instruction).  */
05910           if (strncasecmp (str, "APSR_", 5) == 0)
05911             {
05912               unsigned found = 0;
05913               str += 5;
05914               while (found < 15)
05915                 switch (*str++)
05916                   {
05917                   case 'c': found = (found & 1) ? 16 : found | 1; break;
05918                   case 'n': found = (found & 2) ? 16 : found | 2; break;
05919                   case 'z': found = (found & 4) ? 16 : found | 4; break;
05920                   case 'v': found = (found & 8) ? 16 : found | 8; break;
05921                   default: found = 16;
05922                   }
05923               if (found != 15)
05924                 goto failure;
05925               inst.operands[i].isvec = 1;
05926             }
05927           else
05928             goto failure;
05929           break;
05930 
05931        case OP_TB:
05932          po_misc_or_fail (parse_tb (&str));
05933          break;
05934 
05935          /* Register lists */
05936        case OP_REGLST:
05937          val = parse_reg_list (&str);
05938          if (*str == '^')
05939            {
05940              inst.operands[1].writeback = 1;
05941              str++;
05942            }
05943          break;
05944 
05945        case OP_VRSLST:
05946          val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
05947          break;
05948 
05949        case OP_VRDLST:
05950          val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
05951          break;
05952 
05953         case OP_VRSDLST:
05954           /* Allow Q registers too.  */
05955           val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
05956                                     REGLIST_NEON_D);
05957           if (val == FAIL)
05958             {
05959               inst.error = NULL;
05960               val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
05961                                         REGLIST_VFP_S);
05962               inst.operands[i].issingle = 1;
05963             }
05964           break;
05965 
05966         case OP_NRDLST:
05967           val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
05968                                     REGLIST_NEON_D);
05969           break;
05970 
05971        case OP_NSTRLST:
05972           val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
05973                                            &inst.operands[i].vectype);
05974           break;
05975 
05976          /* Addressing modes */
05977        case OP_ADDR:
05978          po_misc_or_fail (parse_address (&str, i));
05979          break;
05980 
05981        case OP_ADDRGLDR:
05982          po_misc_or_fail_no_backtrack (
05983             parse_address_group_reloc (&str, i, GROUP_LDR));
05984          break;
05985 
05986        case OP_ADDRGLDRS:
05987          po_misc_or_fail_no_backtrack (
05988             parse_address_group_reloc (&str, i, GROUP_LDRS));
05989          break;
05990 
05991        case OP_ADDRGLDC:
05992          po_misc_or_fail_no_backtrack (
05993             parse_address_group_reloc (&str, i, GROUP_LDC));
05994          break;
05995 
05996        case OP_SH:
05997          po_misc_or_fail (parse_shifter_operand (&str, i));
05998          break;
05999 
06000        case OP_SHG:
06001          po_misc_or_fail_no_backtrack (
06002             parse_shifter_operand_group_reloc (&str, i));
06003          break;
06004 
06005        case OP_oSHll:
06006          po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
06007          break;
06008 
06009        case OP_oSHar:
06010          po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
06011          break;
06012 
06013        case OP_oSHllar:
06014          po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
06015          break;
06016 
06017        default:
06018          as_fatal ("unhandled operand code %d", upat[i]);
06019        }
06020 
06021       /* Various value-based sanity checks and shared operations.  We
06022         do not signal immediate failures for the register constraints;
06023         this allows a syntax error to take precedence.   */
06024       switch (upat[i])
06025        {
06026        case OP_oRRnpc:
06027        case OP_RRnpc:
06028        case OP_RRnpcb:
06029        case OP_RRw:
06030        case OP_oRRw:
06031        case OP_RRnpc_I0:
06032          if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
06033            inst.error = BAD_PC;
06034          break;
06035 
06036        case OP_CPSF:
06037        case OP_ENDI:
06038        case OP_oROR:
06039        case OP_PSR:
06040         case OP_RVC_PSR:
06041        case OP_COND:
06042        case OP_oBARRIER:
06043        case OP_REGLST:
06044        case OP_VRSLST:
06045        case OP_VRDLST:
06046         case OP_VRSDLST:
06047         case OP_NRDLST:
06048         case OP_NSTRLST:
06049          if (val == FAIL)
06050            goto failure;
06051          inst.operands[i].imm = val;
06052          break;
06053 
06054        default:
06055          break;
06056        }
06057 
06058       /* If we get here, this operand was successfully parsed. */
06059       inst.operands[i].present = 1;
06060       continue;
06061 
06062     bad_args:
06063       inst.error = BAD_ARGS;
06064 
06065     failure:
06066       if (!backtrack_pos)
06067        {
06068          /* The parse routine should already have set inst.error, but set a
06069             defaut here just in case.  */
06070          if (!inst.error)
06071            inst.error = _("syntax error");
06072          return FAIL;
06073        }
06074 
06075       /* Do not backtrack over a trailing optional argument that
06076         absorbed some text.  We will only fail again, with the
06077         'garbage following instruction' error message, which is
06078         probably less helpful than the current one.  */
06079       if (backtrack_index == i && backtrack_pos != str
06080          && upat[i+1] == OP_stop)
06081        {
06082          if (!inst.error)
06083            inst.error = _("syntax error");
06084          return FAIL;
06085        }
06086 
06087       /* Try again, skipping the optional argument at backtrack_pos.  */
06088       str = backtrack_pos;
06089       inst.error = backtrack_error;
06090       inst.operands[backtrack_index].present = 0;
06091       i = backtrack_index;
06092       backtrack_pos = 0;
06093     }
06094 
06095   /* Check that we have parsed all the arguments.  */
06096   if (*str != '\0' && !inst.error)
06097     inst.error = _("garbage following instruction");
06098 
06099   return inst.error ? FAIL : SUCCESS;
06100 }
06101 
06102 #undef po_char_or_fail
06103 #undef po_reg_or_fail
06104 #undef po_reg_or_goto
06105 #undef po_imm_or_fail
06106 #undef po_scalar_or_fail
06107 
06108 /* Shorthand macro for instruction encoding functions issuing errors.  */
06109 #define constraint(expr, err) do {        \
06110   if (expr)                               \
06111     {                                     \
06112       inst.error = err;                          \
06113       return;                             \
06114     }                                     \
06115 } while (0)
06116 
06117 /* Functions for operand encoding.  ARM, then Thumb.  */
06118 
06119 #define rotate_left(v, n) (v << n | v >> (32 - n))
06120 
06121 /* If VAL can be encoded in the immediate field of an ARM instruction,
06122    return the encoded form.  Otherwise, return FAIL.  */
06123 
06124 static unsigned int
06125 encode_arm_immediate (unsigned int val)
06126 {
06127   unsigned int a, i;
06128 
06129   for (i = 0; i < 32; i += 2)
06130     if ((a = rotate_left (val, i)) <= 0xff)
06131       return a | (i << 7); /* 12-bit pack: [shift-cnt,const].  */
06132 
06133   return FAIL;
06134 }
06135 
06136 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
06137    return the encoded form.  Otherwise, return FAIL.  */
06138 static unsigned int
06139 encode_thumb32_immediate (unsigned int val)
06140 {
06141   unsigned int a, i;
06142 
06143   if (val <= 0xff)
06144     return val;
06145 
06146   for (i = 1; i <= 24; i++)
06147     {
06148       a = val >> i;
06149       if ((val & ~(0xff << i)) == 0)
06150        return ((val >> i) & 0x7f) | ((32 - i) << 7);
06151     }
06152 
06153   a = val & 0xff;
06154   if (val == ((a << 16) | a))
06155     return 0x100 | a;
06156   if (val == ((a << 24) | (a << 16) | (a << 8) | a))
06157     return 0x300 | a;
06158 
06159   a = val & 0xff00;
06160   if (val == ((a << 16) | a))
06161     return 0x200 | (a >> 8);
06162 
06163   return FAIL;
06164 }
06165 /* Encode a VFP SP or DP register number into inst.instruction.  */
06166 
06167 static void
06168 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
06169 {
06170   if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
06171       && reg > 15)
06172     {
06173       if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
06174         {
06175           if (thumb_mode)
06176             ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
06177                                     fpu_vfp_ext_v3);
06178           else
06179             ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
06180                                     fpu_vfp_ext_v3);
06181         }
06182       else
06183         {
06184           first_error (_("D register out of range for selected VFP version"));
06185           return;
06186         }
06187     }
06188 
06189   switch (pos)
06190     {
06191     case VFP_REG_Sd:
06192       inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
06193       break;
06194 
06195     case VFP_REG_Sn:
06196       inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
06197       break;
06198 
06199     case VFP_REG_Sm:
06200       inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
06201       break;
06202 
06203     case VFP_REG_Dd:
06204       inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
06205       break;
06206     
06207     case VFP_REG_Dn:
06208       inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
06209       break;
06210     
06211     case VFP_REG_Dm:
06212       inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
06213       break;
06214 
06215     default:
06216       abort ();
06217     }
06218 }
06219 
06220 /* Encode a <shift> in an ARM-format instruction.  The immediate,
06221    if any, is handled by md_apply_fix.     */
06222 static void
06223 encode_arm_shift (int i)
06224 {
06225   if (inst.operands[i].shift_kind == SHIFT_RRX)
06226     inst.instruction |= SHIFT_ROR << 5;
06227   else
06228     {
06229       inst.instruction |= inst.operands[i].shift_kind << 5;
06230       if (inst.operands[i].immisreg)
06231        {
06232          inst.instruction |= SHIFT_BY_REG;
06233          inst.instruction |= inst.operands[i].imm << 8;
06234        }
06235       else
06236        inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
06237     }
06238 }
06239 
06240 static void
06241 encode_arm_shifter_operand (int i)
06242 {
06243   if (inst.operands[i].isreg)
06244     {
06245       inst.instruction |= inst.operands[i].reg;
06246       encode_arm_shift (i);
06247     }
06248   else
06249     inst.instruction |= INST_IMMEDIATE;
06250 }
06251 
06252 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3.  */
06253 static void
06254 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
06255 {
06256   assert (inst.operands[i].isreg);
06257   inst.instruction |= inst.operands[i].reg << 16;
06258 
06259   if (inst.operands[i].preind)
06260     {
06261       if (is_t)
06262        {
06263          inst.error = _("instruction does not accept preindexed addressing");
06264          return;
06265        }
06266       inst.instruction |= PRE_INDEX;
06267       if (inst.operands[i].writeback)
06268        inst.instruction |= WRITE_BACK;
06269 
06270     }
06271   else if (inst.operands[i].postind)
06272     {
06273       assert (inst.operands[i].writeback);
06274       if (is_t)
06275        inst.instruction |= WRITE_BACK;
06276     }
06277   else /* unindexed - only for coprocessor */
06278     {
06279       inst.error = _("instruction does not accept unindexed addressing");
06280       return;
06281     }
06282 
06283   if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
06284       && (((inst.instruction & 0x000f0000) >> 16)
06285          == ((inst.instruction & 0x0000f000) >> 12)))
06286     as_warn ((inst.instruction & LOAD_BIT)
06287             ? _("destination register same as write-back base")
06288             : _("source register same as write-back base"));
06289 }
06290 
06291 /* inst.operands[i] was set up by parse_address.  Encode it into an
06292    ARM-format mode 2 load or store instruction.   If is_t is true,
06293    reject forms that cannot be used with a T instruction (i.e. not
06294    post-indexed).  */
06295 static void
06296 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
06297 {
06298   encode_arm_addr_mode_common (i, is_t);
06299 
06300   if (inst.operands[i].immisreg)
06301     {
06302       inst.instruction |= INST_IMMEDIATE;  /* yes, this is backwards */
06303       inst.instruction |= inst.operands[i].imm;
06304       if (!inst.operands[i].negative)
06305        inst.instruction |= INDEX_UP;
06306       if (inst.operands[i].shifted)
06307        {
06308          if (inst.operands[i].shift_kind == SHIFT_RRX)
06309            inst.instruction |= SHIFT_ROR << 5;
06310          else
06311            {
06312              inst.instruction |= inst.operands[i].shift_kind << 5;
06313              inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
06314            }
06315        }
06316     }
06317   else /* immediate offset in inst.reloc */
06318     {
06319       if (inst.reloc.type == BFD_RELOC_UNUSED)
06320        inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
06321     }
06322 }
06323 
06324 /* inst.operands[i] was set up by parse_address.  Encode it into an
06325    ARM-format mode 3 load or store instruction.   Reject forms that
06326    cannot be used with such instructions.  If is_t is true, reject
06327    forms that cannot be used with a T instruction (i.e. not
06328    post-indexed).  */
06329 static void
06330 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
06331 {
06332   if (inst.operands[i].immisreg && inst.operands[i].shifted)
06333     {
06334       inst.error = _("instruction does not accept scaled register index");
06335       return;
06336     }
06337 
06338   encode_arm_addr_mode_common (i, is_t);
06339 
06340   if (inst.operands[i].immisreg)
06341     {
06342       inst.instruction |= inst.operands[i].imm;
06343       if (!inst.operands[i].negative)
06344        inst.instruction |= INDEX_UP;
06345     }
06346   else /* immediate offset in inst.reloc */
06347     {
06348       inst.instruction |= HWOFFSET_IMM;
06349       if (inst.reloc.type == BFD_RELOC_UNUSED)
06350        inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
06351     }
06352 }
06353 
06354 /* inst.operands[i] was set up by parse_address.  Encode it into an
06355    ARM-format instruction.  Reject all forms which cannot be encoded
06356    into a coprocessor load/store instruction.  If wb_ok is false,
06357    reject use of writeback; if unind_ok is false, reject use of
06358    unindexed addressing.  If reloc_override is not 0, use it instead
06359    of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
06360    (in which case it is preserved).  */
06361 
06362 static int
06363 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
06364 {
06365   inst.instruction |= inst.operands[i].reg << 16;
06366 
06367   assert (!(inst.operands[i].preind && inst.operands[i].postind));
06368 
06369   if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
06370     {
06371       assert (!inst.operands[i].writeback);
06372       if (!unind_ok)
06373        {
06374          inst.error = _("instruction does not support unindexed addressing");
06375          return FAIL;
06376        }
06377       inst.instruction |= inst.operands[i].imm;
06378       inst.instruction |= INDEX_UP;
06379       return SUCCESS;
06380     }
06381 
06382   if (inst.operands[i].preind)
06383     inst.instruction |= PRE_INDEX;
06384 
06385   if (inst.operands[i].writeback)
06386     {
06387       if (inst.operands[i].reg == REG_PC)
06388        {
06389          inst.error = _("pc may not be used with write-back");
06390          return FAIL;
06391        }
06392       if (!wb_ok)
06393        {
06394          inst.error = _("instruction does not support writeback");
06395          return FAIL;
06396        }
06397       inst.instruction |= WRITE_BACK;
06398     }
06399 
06400   if (reloc_override)
06401     inst.reloc.type = reloc_override;
06402   else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
06403             || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
06404            && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
06405     {
06406       if (thumb_mode)
06407         inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
06408       else
06409         inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
06410     }
06411 
06412   return SUCCESS;
06413 }
06414 
06415 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
06416    Determine whether it can be performed with a move instruction; if
06417    it can, convert inst.instruction to that move instruction and
06418    return 1; if it can't, convert inst.instruction to a literal-pool
06419    load and return 0.  If this is not a valid thing to do in the
06420    current context, set inst.error and return 1.
06421 
06422    inst.operands[i] describes the destination register.  */
06423 
06424 static int
06425 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
06426 {
06427   unsigned long tbit;
06428 
06429   if (thumb_p)
06430     tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
06431   else
06432     tbit = LOAD_BIT;
06433 
06434   if ((inst.instruction & tbit) == 0)
06435     {
06436       inst.error = _("invalid pseudo operation");
06437       return 1;
06438     }
06439   if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
06440     {
06441       inst.error = _("constant expression expected");
06442       return 1;
06443     }
06444   if (inst.reloc.exp.X_op == O_constant)
06445     {
06446       if (thumb_p)
06447        {
06448          if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
06449            {
06450              /* This can be done with a mov(1) instruction.  */
06451              inst.instruction      = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
06452              inst.instruction |= inst.reloc.exp.X_add_number;
06453              return 1;
06454            }
06455        }
06456       else
06457        {
06458          int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
06459          if (value != FAIL)
06460            {
06461              /* This can be done with a mov instruction.  */
06462              inst.instruction &= LITERAL_MASK;
06463              inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
06464              inst.instruction |= value & 0xfff;
06465              return 1;
06466            }
06467 
06468          value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
06469          if (value != FAIL)
06470            {
06471              /* This can be done with a mvn instruction.  */
06472              inst.instruction &= LITERAL_MASK;
06473              inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
06474              inst.instruction |= value & 0xfff;
06475              return 1;
06476            }
06477        }
06478     }
06479 
06480   if (add_to_lit_pool () == FAIL)
06481     {
06482       inst.error = _("literal pool insertion failed");
06483       return 1;
06484     }
06485   inst.operands[1].reg = REG_PC;
06486   inst.operands[1].isreg = 1;
06487   inst.operands[1].preind = 1;
06488   inst.reloc.pc_rel = 1;
06489   inst.reloc.type = (thumb_p
06490                    ? BFD_RELOC_ARM_THUMB_OFFSET
06491                    : (mode_3
06492                      ? BFD_RELOC_ARM_HWLITERAL
06493                      : BFD_RELOC_ARM_LITERAL));
06494   return 0;
06495 }
06496 
06497 /* Functions for instruction encoding, sorted by subarchitecture.
06498    First some generics; their names are taken from the conventional
06499    bit positions for register arguments in ARM format instructions.  */
06500 
06501 static void
06502 do_noargs (void)
06503 {
06504 }
06505 
06506 static void
06507 do_rd (void)
06508 {
06509   inst.instruction |= inst.operands[0].reg << 12;
06510 }
06511 
06512 static void
06513 do_rd_rm (void)
06514 {
06515   inst.instruction |= inst.operands[0].reg << 12;
06516   inst.instruction |= inst.operands[1].reg;
06517 }
06518 
06519 static void
06520 do_rd_rn (void)
06521 {
06522   inst.instruction |= inst.operands[0].reg << 12;
06523   inst.instruction |= inst.operands[1].reg << 16;
06524 }
06525 
06526 static void
06527 do_rn_rd (void)
06528 {
06529   inst.instruction |= inst.operands[0].reg << 16;
06530   inst.instruction |= inst.operands[1].reg << 12;
06531 }
06532 
06533 static void
06534 do_rd_rm_rn (void)
06535 {
06536   unsigned Rn = inst.operands[2].reg;
06537   /* Enforce restrictions on SWP instruction.  */
06538   if ((inst.instruction & 0x0fbfffff) == 0x01000090)
06539     constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
06540               _("Rn must not overlap other operands"));
06541   inst.instruction |= inst.operands[0].reg << 12;
06542   inst.instruction |= inst.operands[1].reg;
06543   inst.instruction |= Rn << 16;
06544 }
06545 
06546 static void
06547 do_rd_rn_rm (void)
06548 {
06549   inst.instruction |= inst.operands[0].reg << 12;
06550   inst.instruction |= inst.operands[1].reg << 16;
06551   inst.instruction |= inst.operands[2].reg;
06552 }
06553 
06554 static void
06555 do_rm_rd_rn (void)
06556 {
06557   inst.instruction |= inst.operands[0].reg;
06558   inst.instruction |= inst.operands[1].reg << 12;
06559   inst.instruction |= inst.operands[2].reg << 16;
06560 }
06561 
06562 static void
06563 do_imm0 (void)
06564 {
06565   inst.instruction |= inst.operands[0].imm;
06566 }
06567 
06568 static void
06569 do_rd_cpaddr (void)
06570 {
06571   inst.instruction |= inst.operands[0].reg << 12;
06572   encode_arm_cp_address (1, TRUE, TRUE, 0);
06573 }
06574 
06575 /* ARM instructions, in alphabetical order by function name (except
06576    that wrapper functions appear immediately after the function they
06577    wrap).  */
06578 
06579 /* This is a pseudo-op of the form "adr rd, label" to be converted
06580    into a relative address of the form "add rd, pc, #label-.-8".  */
06581 
06582 static void
06583 do_adr (void)
06584 {
06585   inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
06586 
06587   /* Frag hacking will turn this into a sub instruction if the offset turns
06588      out to be negative.  */
06589   inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
06590   inst.reloc.pc_rel = 1;
06591   inst.reloc.exp.X_add_number -= 8;
06592 }
06593 
06594 /* This is a pseudo-op of the form "adrl rd, label" to be converted
06595    into a relative address of the form:
06596    add rd, pc, #low(label-.-8)"
06597    add rd, rd, #high(label-.-8)"  */
06598 
06599 static void
06600 do_adrl (void)
06601 {
06602   inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
06603 
06604   /* Frag hacking will turn this into a sub instruction if the offset turns
06605      out to be negative.  */
06606   inst.reloc.type           = BFD_RELOC_ARM_ADRL_IMMEDIATE;
06607   inst.reloc.pc_rel         = 1;
06608   inst.size                 = INSN_SIZE * 2;
06609   inst.reloc.exp.X_add_number -= 8;
06610 }
06611 
06612 static void
06613 do_arit (void)
06614 {
06615   if (!inst.operands[1].present)
06616     inst.operands[1].reg = inst.operands[0].reg;
06617   inst.instruction |= inst.operands[0].reg << 12;
06618   inst.instruction |= inst.operands[1].reg << 16;
06619   encode_arm_shifter_operand (2);
06620 }
06621 
06622 static void
06623 do_barrier (void)
06624 {
06625   if (inst.operands[0].present)
06626     {
06627       constraint ((inst.instruction & 0xf0) != 0x40
06628                 && inst.operands[0].imm != 0xf,
06629                 "bad barrier type");
06630       inst.instruction |= inst.operands[0].imm;
06631     }
06632   else
06633     inst.instruction |= 0xf;
06634 }
06635 
06636 static void
06637 do_bfc (void)
06638 {
06639   unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
06640   constraint (msb > 32, _("bit-field extends past end of register"));
06641   /* The instruction encoding stores the LSB and MSB,
06642      not the LSB and width.  */
06643   inst.instruction |= inst.operands[0].reg << 12;
06644   inst.instruction |= inst.operands[1].imm << 7;
06645   inst.instruction |= (msb - 1) << 16;
06646 }
06647 
06648 static void
06649 do_bfi (void)
06650 {
06651   unsigned int msb;
06652 
06653   /* #0 in second position is alternative syntax for bfc, which is
06654      the same instruction but with REG_PC in the Rm field.  */
06655   if (!inst.operands[1].isreg)
06656     inst.operands[1].reg = REG_PC;
06657 
06658   msb = inst.operands[2].imm + inst.operands[3].imm;
06659   constraint (msb > 32, _("bit-field extends past end of register"));
06660   /* The instruction encoding stores the LSB and MSB,
06661      not the LSB and width.  */
06662   inst.instruction |= inst.operands[0].reg << 12;
06663   inst.instruction |= inst.operands[1].reg;
06664   inst.instruction |= inst.operands[2].imm << 7;
06665   inst.instruction |= (msb - 1) << 16;
06666 }
06667 
06668 static void
06669 do_bfx (void)
06670 {
06671   constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
06672              _("bit-field extends past end of register"));
06673   inst.instruction |= inst.operands[0].reg << 12;
06674   inst.instruction |= inst.operands[1].reg;
06675   inst.instruction |= inst.operands[2].imm << 7;
06676   inst.instruction |= (inst.operands[3].imm - 1) << 16;
06677 }
06678 
06679 /* ARM V5 breakpoint instruction (argument parse)
06680      BKPT <16 bit unsigned immediate>
06681      Instruction is not conditional.
06682        The bit pattern given in insns[] has the COND_ALWAYS condition,
06683        and it is an error if the caller tried to override that.  */
06684 
06685 static void
06686 do_bkpt (void)
06687 {
06688   /* Top 12 of 16 bits to bits 19:8.  */
06689   inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
06690 
06691   /* Bottom 4 of 16 bits to bits 3:0.  */
06692   inst.instruction |= inst.operands[0].imm & 0xf;
06693 }
06694 
06695 static void
06696 encode_branch (int default_reloc)
06697 {
06698   if (inst.operands[0].hasreloc)
06699     {
06700       constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
06701                 _("the only suffix valid here is '(plt)'"));
06702       inst.reloc.type       = BFD_RELOC_ARM_PLT32;
06703     }
06704   else
06705     {
06706       inst.reloc.type = default_reloc;
06707     }
06708   inst.reloc.pc_rel = 1;
06709 }
06710 
06711 static void
06712 do_branch (void)
06713 {
06714 #ifdef OBJ_ELF
06715   if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
06716     encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
06717   else
06718 #endif
06719     encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
06720 }
06721 
06722 static void
06723 do_bl (void)
06724 {
06725 #ifdef OBJ_ELF
06726   if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
06727     {
06728       if (inst.cond == COND_ALWAYS)
06729        encode_branch (BFD_RELOC_ARM_PCREL_CALL);
06730       else
06731        encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
06732     }
06733   else
06734 #endif
06735     encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
06736 }
06737 
06738 /* ARM V5 branch-link-exchange instruction (argument parse)
06739      BLX <target_addr>             ie BLX(1)
06740      BLX{<condition>} <Rm>  ie BLX(2)
06741    Unfortunately, there are two different opcodes for this mnemonic.
06742    So, the insns[].value is not used, and the code here zaps values
06743        into inst.instruction.
06744    Also, the <target_addr> can be 25 bits, hence has its own reloc.  */
06745 
06746 static void
06747 do_blx (void)
06748 {
06749   if (inst.operands[0].isreg)
06750     {
06751       /* Arg is a register; the opcode provided by insns[] is correct.
06752         It is not illegal to do "blx pc", just useless.  */
06753       if (inst.operands[0].reg == REG_PC)
06754        as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
06755 
06756       inst.instruction |= inst.operands[0].reg;
06757     }
06758   else
06759     {
06760       /* Arg is an address; this instruction cannot be executed
06761         conditionally, and the opcode must be adjusted.  */
06762       constraint (inst.cond != COND_ALWAYS, BAD_COND);
06763       inst.instruction = 0xfa000000;
06764 #ifdef OBJ_ELF
06765       if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
06766        encode_branch (BFD_RELOC_ARM_PCREL_CALL);
06767       else
06768 #endif
06769        encode_branch (BFD_RELOC_ARM_PCREL_BLX);
06770     }
06771 }
06772 
06773 static void
06774 do_bx (void)
06775 {
06776   if (inst.operands[0].reg == REG_PC)
06777     as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
06778 
06779   inst.instruction |= inst.operands[0].reg;
06780 }
06781 
06782 
06783 /* ARM v5TEJ.  Jump to Jazelle code.  */
06784 
06785 static void
06786 do_bxj (void)
06787 {
06788   if (inst.operands[0].reg == REG_PC)
06789     as_tsktsk (_("use of r15 in bxj is not really useful"));
06790 
06791   inst.instruction |= inst.operands[0].reg;
06792 }
06793 
06794 /* Co-processor data operation:
06795       CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
06796       CDP2    <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}  */
06797 static void
06798 do_cdp (void)
06799 {
06800   inst.instruction |= inst.operands[0].reg << 8;
06801   inst.instruction |= inst.operands[1].imm << 20;
06802   inst.instruction |= inst.operands[2].reg << 12;
06803   inst.instruction |= inst.operands[3].reg << 16;
06804   inst.instruction |= inst.operands[4].reg;
06805   inst.instruction |= inst.operands[5].imm << 5;
06806 }
06807 
06808 static void
06809 do_cmp (void)
06810 {
06811   inst.instruction |= inst.operands[0].reg << 16;
06812   encode_arm_shifter_operand (1);
06813 }
06814 
06815 /* Transfer between coprocessor and ARM registers.
06816    MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
06817    MRC2
06818    MCR{cond}
06819    MCR2
06820 
06821    No special properties.  */
06822 
06823 static void
06824 do_co_reg (void)
06825 {
06826   inst.instruction |= inst.operands[0].reg << 8;
06827   inst.instruction |= inst.operands[1].imm << 21;
06828   inst.instruction |= inst.operands[2].reg << 12;
06829   inst.instruction |= inst.operands[3].reg << 16;
06830   inst.instruction |= inst.operands[4].reg;
06831   inst.instruction |= inst.operands[5].imm << 5;
06832 }
06833 
06834 /* Transfer between coprocessor register and pair of ARM registers.
06835    MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
06836    MCRR2
06837    MRRC{cond}
06838    MRRC2
06839 
06840    Two XScale instructions are special cases of these:
06841 
06842      MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
06843      MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
06844 
06845    Result unpredicatable if Rd or Rn is R15.  */
06846 
06847 static void
06848 do_co_reg2c (void)
06849 {
06850   inst.instruction |= inst.operands[0].reg << 8;
06851   inst.instruction |= inst.operands[1].imm << 4;
06852   inst.instruction |= inst.operands[2].reg << 12;
06853   inst.instruction |= inst.operands[3].reg << 16;
06854   inst.instruction |= inst.operands[4].reg;
06855 }
06856 
06857 static void
06858 do_cpsi (void)
06859 {
06860   inst.instruction |= inst.operands[0].imm << 6;
06861   if (inst.operands[1].present)
06862     {
06863       inst.instruction |= CPSI_MMOD;
06864       inst.instruction |= inst.operands[1].imm;
06865     }
06866 }
06867 
06868 static void
06869 do_dbg (void)
06870 {
06871   inst.instruction |= inst.operands[0].imm;
06872 }
06873 
06874 static void
06875 do_it (void)
06876 {
06877   /* There is no IT instruction in ARM mode.  We
06878      process it but do not generate code for it.  */
06879   inst.size = 0;
06880 }
06881 
06882 static void
06883 do_ldmstm (void)
06884 {
06885   int base_reg = inst.operands[0].reg;
06886   int range = inst.operands[1].imm;
06887 
06888   inst.instruction |= base_reg << 16;
06889   inst.instruction |= range;
06890 
06891   if (inst.operands[1].writeback)
06892     inst.instruction |= LDM_TYPE_2_OR_3;
06893 
06894   if (inst.operands[0].writeback)
06895     {
06896       inst.instruction |= WRITE_BACK;
06897       /* Check for unpredictable uses of writeback.  */
06898       if (inst.instruction & LOAD_BIT)
06899        {
06900          /* Not allowed in LDM type 2.     */
06901          if ((inst.instruction & LDM_TYPE_2_OR_3)
06902              && ((range & (1 << REG_PC)) == 0))
06903            as_warn (_("writeback of base register is UNPREDICTABLE"));
06904          /* Only allowed if base reg not in list for other types.  */
06905          else if (range & (1 << base_reg))
06906            as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
06907        }
06908       else /* STM.  */
06909        {
06910          /* Not allowed for type 2.  */
06911          if (inst.instruction & LDM_TYPE_2_OR_3)
06912            as_warn (_("writeback of base register is UNPREDICTABLE"));
06913          /* Only allowed if base reg not in list, or first in list.  */
06914          else if ((range & (1 << base_reg))
06915                  && (range & ((1 << base_reg) - 1)))
06916            as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
06917        }
06918     }
06919 }
06920 
06921 /* ARMv5TE load-consecutive (argument parse)
06922    Mode is like LDRH.
06923 
06924      LDRccD R, mode
06925      STRccD R, mode.  */
06926 
06927 static void
06928 do_ldrd (void)
06929 {
06930   constraint (inst.operands[0].reg % 2 != 0,
06931              _("first destination register must be even"));
06932   constraint (inst.operands[1].present
06933              && inst.operands[1].reg != inst.operands[0].reg + 1,
06934              _("can only load two consecutive registers"));
06935   constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
06936   constraint (!inst.operands[2].isreg, _("'[' expected"));
06937 
06938   if (!inst.operands[1].present)
06939     inst.operands[1].reg = inst.operands[0].reg + 1;
06940   
06941   if (inst.instruction & LOAD_BIT)
06942     {
06943       /* encode_arm_addr_mode_3 will diagnose overlap between the base
06944         register and the first register written; we have to diagnose
06945         overlap between the base and the second register written here.        */
06946 
06947       if (inst.operands[2].reg == inst.operands[1].reg
06948          && (inst.operands[2].writeback || inst.operands[2].postind))
06949        as_warn (_("base register written back, and overlaps "
06950                  "second destination register"));
06951 
06952       /* For an index-register load, the index register must not overlap the
06953         destination (even if not write-back).    */
06954       else if (inst.operands[2].immisreg
06955               && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
06956                  || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
06957        as_warn (_("index register overlaps destination register"));
06958     }
06959 
06960   inst.instruction |= inst.operands[0].reg << 12;
06961   encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
06962 }
06963 
06964 static void
06965 do_ldrex (void)
06966 {
06967   constraint (!inst.operands[1].isreg || !inst.operands[1].preind
06968              || inst.operands[1].postind || inst.operands[1].writeback
06969              || inst.operands[1].immisreg || inst.operands[1].shifted
06970              || inst.operands[1].negative
06971              /* This can arise if the programmer has written
06972                  strex rN, rM, foo
06973                or if they have mistakenly used a register name as the last
06974                operand,  eg:
06975                  strex rN, rM, rX
06976                It is very difficult to distinguish between these two cases
06977                because "rX" might actually be a label. ie the register
06978                name has been occluded by a symbol of the same name. So we
06979                just generate a general 'bad addressing mode' type error
06980                message and leave it up to the programmer to discover the
06981                true cause and fix their mistake.  */
06982              || (inst.operands[1].reg == REG_PC),
06983              BAD_ADDR_MODE);
06984 
06985   constraint (inst.reloc.exp.X_op != O_constant
06986              || inst.reloc.exp.X_add_number != 0,
06987              _("offset must be zero in ARM encoding"));
06988 
06989   inst.instruction |= inst.operands[0].reg << 12;
06990   inst.instruction |= inst.operands[1].reg << 16;
06991   inst.reloc.type = BFD_RELOC_UNUSED;
06992 }
06993 
06994 static void
06995 do_ldrexd (void)
06996 {
06997   constraint (inst.operands[0].reg % 2 != 0,
06998              _("even register required"));
06999   constraint (inst.operands[1].present
07000              && inst.operands[1].reg != inst.operands[0].reg + 1,
07001              _("can only load two consecutive registers"));
07002   /* If op 1 were present and equal to PC, this function wouldn't
07003      have been called in the first place.  */
07004   constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
07005 
07006   inst.instruction |= inst.operands[0].reg << 12;
07007   inst.instruction |= inst.operands[2].reg << 16;
07008 }
07009 
07010 static void
07011 do_ldst (void)
07012 {
07013   inst.instruction |= inst.operands[0].reg << 12;
07014   if (!inst.operands[1].isreg)
07015     if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
07016       return;
07017   encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
07018 }
07019 
07020 static void
07021 do_ldstt (void)
07022 {
07023   /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
07024      reject [Rn,...].  */
07025   if (inst.operands[1].preind)
07026     {
07027       constraint (inst.reloc.exp.X_op != O_constant ||
07028                 inst.reloc.exp.X_add_number != 0,
07029                 _("this instruction requires a post-indexed address"));
07030 
07031       inst.operands[1].preind = 0;
07032       inst.operands[1].postind = 1;
07033       inst.operands[1].writeback = 1;
07034     }
07035   inst.instruction |= inst.operands[0].reg << 12;
07036   encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
07037 }
07038 
07039 /* Halfword and signed-byte load/store operations.  */
07040 
07041 static void
07042 do_ldstv4 (void)
07043 {
07044   inst.instruction |= inst.operands[0].reg << 12;
07045   if (!inst.operands[1].isreg)
07046     if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
07047       return;
07048   encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
07049 }
07050 
07051 static void
07052 do_ldsttv4 (void)
07053 {
07054   /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
07055      reject [Rn,...].  */
07056   if (inst.operands[1].preind)
07057     {
07058       constraint (inst.reloc.exp.X_op != O_constant ||
07059                 inst.reloc.exp.X_add_number != 0,
07060                 _("this instruction requires a post-indexed address"));
07061 
07062       inst.operands[1].preind = 0;
07063       inst.operands[1].postind = 1;
07064       inst.operands[1].writeback = 1;
07065     }
07066   inst.instruction |= inst.operands[0].reg << 12;
07067   encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
07068 }
07069 
07070 /* Co-processor register load/store.
07071    Format: <LDC|STC>{cond}[L] CP#,CRd,<address>   */
07072 static void
07073 do_lstc (void)
07074 {
07075   inst.instruction |= inst.operands[0].reg << 8;
07076   inst.instruction |= inst.operands[1].reg << 12;
07077   encode_arm_cp_address (2, TRUE, TRUE, 0);
07078 }
07079 
07080 static void
07081 do_mlas (void)
07082 {
07083   /* This restriction does not apply to mls (nor to mla in v6 or later).  */
07084   if (inst.operands[0].reg == inst.operands[1].reg
07085       && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
07086       && !(inst.instruction & 0x00400000))
07087     as_tsktsk (_("Rd and Rm should be different in mla"));
07088 
07089   inst.instruction |= inst.operands[0].reg << 16;
07090   inst.instruction |= inst.operands[1].reg;
07091   inst.instruction |= inst.operands[2].reg << 8;
07092   inst.instruction |= inst.operands[3].reg << 12;
07093 }
07094 
07095 static void
07096 do_mov (void)
07097 {
07098   inst.instruction |= inst.operands[0].reg << 12;
07099   encode_arm_shifter_operand (1);
07100 }
07101 
07102 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>.       */
07103 static void
07104 do_mov16 (void)
07105 {
07106   bfd_vma imm;
07107   bfd_boolean top;
07108 
07109   top = (inst.instruction & 0x00400000) != 0;
07110   constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
07111              _(":lower16: not allowed this instruction"));
07112   constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
07113              _(":upper16: not allowed instruction"));
07114   inst.instruction |= inst.operands[0].reg << 12;
07115   if (inst.reloc.type == BFD_RELOC_UNUSED)
07116     {
07117       imm = inst.reloc.exp.X_add_number;
07118       /* The value is in two pieces: 0:11, 16:19.  */
07119       inst.instruction |= (imm & 0x00000fff);
07120       inst.instruction |= (imm & 0x0000f000) << 4;
07121     }
07122 }
07123 
07124 static void do_vfp_nsyn_opcode (const char *);
07125 
07126 static int
07127 do_vfp_nsyn_mrs (void)
07128 {
07129   if (inst.operands[0].isvec)
07130     {
07131       if (inst.operands[1].reg != 1)
07132         first_error (_("operand 1 must be FPSCR"));
07133       memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
07134       memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
07135       do_vfp_nsyn_opcode ("fmstat");
07136     }
07137   else if (inst.operands[1].isvec)
07138     do_vfp_nsyn_opcode ("fmrx");
07139   else
07140     return FAIL;
07141     
07142   return SUCCESS;
07143 }
07144 
07145 static int
07146 do_vfp_nsyn_msr (void)
07147 {
07148   if (inst.operands[0].isvec)
07149     do_vfp_nsyn_opcode ("fmxr");
07150   else
07151     return FAIL;
07152 
07153   return SUCCESS;
07154 }
07155 
07156 static void
07157 do_mrs (void)
07158 {
07159   if (do_vfp_nsyn_mrs () == SUCCESS)
07160     return;
07161 
07162   /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
07163   constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
07164              != (PSR_c|PSR_f),
07165              _("'CPSR' or 'SPSR' expected"));
07166   inst.instruction |= inst.operands[0].reg << 12;
07167   inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
07168 }
07169 
07170 /* Two possible forms:
07171       "{C|S}PSR_<field>, Rm",
07172       "{C|S}PSR_f, #expression".  */
07173 
07174 static void
07175 do_msr (void)
07176 {
07177   if (do_vfp_nsyn_msr () == SUCCESS)
07178     return;
07179 
07180   inst.instruction |= inst.operands[0].imm;
07181   if (inst.operands[1].isreg)
07182     inst.instruction |= inst.operands[1].reg;
07183   else
07184     {
07185       inst.instruction |= INST_IMMEDIATE;
07186       inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
07187       inst.reloc.pc_rel = 0;
07188     }
07189 }
07190 
07191 static void
07192 do_mul (void)
07193 {
07194   if (!inst.operands[2].present)
07195     inst.operands[2].reg = inst.operands[0].reg;
07196   inst.instruction |= inst.operands[0].reg << 16;
07197   inst.instruction |= inst.operands[1].reg;
07198   inst.instruction |= inst.operands[2].reg << 8;
07199 
07200   if (inst.operands[0].reg == inst.operands[1].reg
07201       && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
07202     as_tsktsk (_("Rd and Rm should be different in mul"));
07203 }
07204 
07205 /* Long Multiply Parser
07206    UMULL RdLo, RdHi, Rm, Rs
07207    SMULL RdLo, RdHi, Rm, Rs
07208    UMLAL RdLo, RdHi, Rm, Rs
07209    SMLAL RdLo, RdHi, Rm, Rs.  */
07210 
07211 static void
07212 do_mull (void)
07213 {
07214   inst.instruction |= inst.operands[0].reg << 12;
07215   inst.instruction |= inst.operands[1].reg << 16;
07216   inst.instruction |= inst.operands[2].reg;
07217   inst.instruction |= inst.operands[3].reg << 8;
07218 
07219   /* rdhi, rdlo and rm must all be different.  */
07220   if (inst.operands[0].reg == inst.operands[1].reg
07221       || inst.operands[0].reg == inst.operands[2].reg
07222       || inst.operands[1].reg == inst.operands[2].reg)
07223     as_tsktsk (_("rdhi, rdlo and rm must all be different"));
07224 }
07225 
07226 static void
07227 do_nop (void)
07228 {
07229   if (inst.operands[0].present)
07230     {
07231       /* Architectural NOP hints are CPSR sets with no bits selected.  */
07232       inst.instruction &= 0xf0000000;
07233       inst.instruction |= 0x0320f000 + inst.operands[0].imm;
07234     }
07235 }
07236 
07237 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
07238    PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
07239    Condition defaults to COND_ALWAYS.
07240    Error if Rd, Rn or Rm are R15.  */
07241 
07242 static void
07243 do_pkhbt (void)
07244 {
07245   inst.instruction |= inst.operands[0].reg << 12;
07246   inst.instruction |= inst.operands[1].reg << 16;
07247   inst.instruction |= inst.operands[2].reg;
07248   if (inst.operands[3].present)
07249     encode_arm_shift (3);
07250 }
07251 
07252 /* ARM V6 PKHTB (Argument Parse).  */
07253 
07254 static void
07255 do_pkhtb (void)
07256 {
07257   if (!inst.operands[3].present)
07258     {
07259       /* If the shift specifier is omitted, turn the instruction
07260         into pkhbt rd, rm, rn. */
07261       inst.instruction &= 0xfff00010;
07262       inst.instruction |= inst.operands[0].reg << 12;
07263       inst.instruction |= inst.operands[1].reg;
07264       inst.instruction |= inst.operands[2].reg << 16;
07265     }
07266   else
07267     {
07268       inst.instruction |= inst.operands[0].reg << 12;
07269       inst.instruction |= inst.operands[1].reg << 16;
07270       inst.instruction |= inst.operands[2].reg;
07271       encode_arm_shift (3);
07272     }
07273 }
07274 
07275 /* ARMv5TE: Preload-Cache
07276 
07277     PLD <addr_mode>
07278 
07279   Syntactically, like LDR with B=1, W=0, L=1.  */
07280 
07281 static void
07282 do_pld (void)
07283 {
07284   constraint (!inst.operands[0].isreg,
07285              _("'[' expected after PLD mnemonic"));
07286   constraint (inst.operands[0].postind,
07287              _("post-indexed expression used in preload instruction"));
07288   constraint (inst.operands[0].writeback,
07289              _("writeback used in preload instruction"));
07290   constraint (!inst.operands[0].preind,
07291              _("unindexed addressing used in preload instruction"));
07292   encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
07293 }
07294 
07295 /* ARMv7: PLI <addr_mode>  */
07296 static void
07297 do_pli (void)
07298 {
07299   constraint (!inst.operands[0].isreg,
07300              _("'[' expected after PLI mnemonic"));
07301   constraint (inst.operands[0].postind,
07302              _("post-indexed expression used in preload instruction"));
07303   constraint (inst.operands[0].writeback,
07304              _("writeback used in preload instruction"));
07305   constraint (!inst.operands[0].preind,
07306              _("unindexed addressing used in preload instruction"));
07307   encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
07308   inst.instruction &= ~PRE_INDEX;
07309 }
07310 
07311 static void
07312 do_push_pop (void)
07313 {
07314   inst.operands[1] = inst.operands[0];
07315   memset (&inst.operands[0], 0, sizeof inst.operands[0]);
07316   inst.operands[0].isreg = 1;
07317   inst.operands[0].writeback = 1;
07318   inst.operands[0].reg = REG_SP;
07319   do_ldmstm ();
07320 }
07321 
07322 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
07323    word at the specified address and the following word
07324    respectively.
07325    Unconditionally executed.
07326    Error if Rn is R15.      */
07327 
07328 static void
07329 do_rfe (void)
07330 {
07331   inst.instruction |= inst.operands[0].reg << 16;
07332   if (inst.operands[0].writeback)
07333     inst.instruction |= WRITE_BACK;
07334 }
07335 
07336 /* ARM V6 ssat (argument parse).  */
07337 
07338 static void
07339 do_ssat (void)
07340 {
07341   inst.instruction |= inst.operands[0].reg << 12;
07342   inst.instruction |= (inst.operands[1].imm - 1) << 16;
07343   inst.instruction |= inst.operands[2].reg;
07344 
07345   if (inst.operands[3].present)
07346     encode_arm_shift (3);
07347 }
07348 
07349 /* ARM V6 usat (argument parse).  */
07350 
07351 static void
07352 do_usat (void)
07353 {
07354   inst.instruction |= inst.operands[0].reg << 12;
07355   inst.instruction |= inst.operands[1].imm << 16;
07356   inst.instruction |= inst.operands[2].reg;
07357 
07358   if (inst.operands[3].present)
07359     encode_arm_shift (3);
07360 }
07361 
07362 /* ARM V6 ssat16 (argument parse).  */
07363 
07364 static void
07365 do_ssat16 (void)
07366 {
07367   inst.instruction |= inst.operands[0].reg << 12;
07368   inst.instruction |= ((inst.operands[1].imm - 1) << 16);
07369   inst.instruction |= inst.operands[2].reg;
07370 }
07371 
07372 static void
07373 do_usat16 (void)
07374 {
07375   inst.instruction |= inst.operands[0].reg << 12;
07376   inst.instruction |= inst.operands[1].imm << 16;
07377   inst.instruction |= inst.operands[2].reg;
07378 }
07379 
07380 /* ARM V6 SETEND (argument parse).  Sets the E bit in the CPSR while
07381    preserving the other bits.
07382 
07383    setend <endian_specifier>, where <endian_specifier> is either
07384    BE or LE.  */
07385 
07386 static void
07387 do_setend (void)
07388 {
07389   if (inst.operands[0].imm)
07390     inst.instruction |= 0x200;
07391 }
07392 
07393 static void
07394 do_shift (void)
07395 {
07396   unsigned int Rm = (inst.operands[1].present
07397                    ? inst.operands[1].reg
07398                    : inst.operands[0].reg);
07399 
07400   inst.instruction |= inst.operands[0].reg << 12;
07401   inst.instruction |= Rm;
07402   if (inst.operands[2].isreg)  /* Rd, {Rm,} Rs */
07403     {
07404       inst.instruction |= inst.operands[2].reg << 8;
07405       inst.instruction |= SHIFT_BY_REG;
07406     }
07407   else
07408     inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
07409 }
07410 
07411 static void
07412 do_smc (void)
07413 {
07414   inst.reloc.type = BFD_RELOC_ARM_SMC;
07415   inst.reloc.pc_rel = 0;
07416 }
07417 
07418 static void
07419 do_swi (void)
07420 {
07421   inst.reloc.type = BFD_RELOC_ARM_SWI;
07422   inst.reloc.pc_rel = 0;
07423 }
07424 
07425 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
07426    SMLAxy{cond} Rd,Rm,Rs,Rn
07427    SMLAWy{cond} Rd,Rm,Rs,Rn
07428    Error if any register is R15.  */
07429 
07430 static void
07431 do_smla (void)
07432 {
07433   inst.instruction |= inst.operands[0].reg << 16;
07434   inst.instruction |= inst.operands[1].reg;
07435   inst.instruction |= inst.operands[2].reg << 8;
07436   inst.instruction |= inst.operands[3].reg << 12;
07437 }
07438 
07439 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
07440    SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
07441    Error if any register is R15.
07442    Warning if Rdlo == Rdhi.  */
07443 
07444 static void
07445 do_smlal (void)
07446 {
07447   inst.instruction |= inst.operands[0].reg << 12;
07448   inst.instruction |= inst.operands[1].reg << 16;
07449   inst.instruction |= inst.operands[2].reg;
07450   inst.instruction |= inst.operands[3].reg << 8;
07451 
07452   if (inst.operands[0].reg == inst.operands[1].reg)
07453     as_tsktsk (_("rdhi and rdlo must be different"));
07454 }
07455 
07456 /* ARM V5E (El Segundo) signed-multiply (argument parse)
07457    SMULxy{cond} Rd,Rm,Rs
07458    Error if any register is R15.  */
07459 
07460 static void
07461 do_smul (void)
07462 {
07463   inst.instruction |= inst.operands[0].reg << 16;
07464   inst.instruction |= inst.operands[1].reg;
07465   inst.instruction |= inst.operands[2].reg << 8;
07466 }
07467 
07468 /* ARM V6 srs (argument parse).  The variable fields in the encoding are
07469    the same for both ARM and Thumb-2.  */
07470 
07471 static void
07472 do_srs (void)
07473 {
07474   int reg;
07475 
07476   if (inst.operands[0].present)
07477     {
07478       reg = inst.operands[0].reg;
07479       constraint (reg != 13, _("SRS base register must be r13"));
07480     }
07481   else
07482     reg = 13;
07483 
07484   inst.instruction |= reg << 16;
07485   inst.instruction |= inst.operands[1].imm;
07486   if (inst.operands[0].writeback || inst.operands[1].writeback)
07487     inst.instruction |= WRITE_BACK;
07488 }
07489 
07490 /* ARM V6 strex (argument parse).  */
07491 
07492 static void
07493 do_strex (void)
07494 {
07495   constraint (!inst.operands[2].isreg || !inst.operands[2].preind
07496              || inst.operands[2].postind || inst.operands[2].writeback
07497              || inst.operands[2].immisreg || inst.operands[2].shifted
07498              || inst.operands[2].negative
07499              /* See comment in do_ldrex().  */
07500              || (inst.operands[2].reg == REG_PC),
07501              BAD_ADDR_MODE);
07502 
07503   constraint (inst.operands[0].reg == inst.operands[1].reg
07504              || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
07505 
07506   constraint (inst.reloc.exp.X_op != O_constant
07507              || inst.reloc.exp.X_add_number != 0,
07508              _("offset must be zero in ARM encoding"));
07509 
07510   inst.instruction |= inst.operands[0].reg << 12;
07511   inst.instruction |= inst.operands[1].reg;
07512   inst.instruction |= inst.operands[2].reg << 16;
07513   inst.reloc.type = BFD_RELOC_UNUSED;
07514 }
07515 
07516 static void
07517 do_strexd (void)
07518 {
07519   constraint (inst.operands[1].reg % 2 != 0,
07520              _("even register required"));
07521   constraint (inst.operands[2].present
07522              && inst.operands[2].reg != inst.operands[1].reg + 1,
07523              _("can only store two consecutive registers"));
07524   /* If op 2 were present and equal to PC, this function wouldn't
07525      have been called in the first place.  */
07526   constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
07527 
07528   constraint (inst.operands[0].reg == inst.operands[1].reg
07529              || inst.operands[0].reg == inst.operands[1].reg + 1
07530              || inst.operands[0].reg == inst.operands[3].reg,
07531              BAD_OVERLAP);
07532 
07533   inst.instruction |= inst.operands[0].reg << 12;
07534   inst.instruction |= inst.operands[1].reg;
07535   inst.instruction |= inst.operands[3].reg << 16;
07536 }
07537 
07538 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
07539    extends it to 32-bits, and adds the result to a value in another
07540    register.  You can specify a rotation by 0, 8, 16, or 24 bits
07541    before extracting the 16-bit value.
07542    SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
07543    Condition defaults to COND_ALWAYS.
07544    Error if any register uses R15.  */
07545 
07546 static void
07547 do_sxtah (void)
07548 {
07549   inst.instruction |= inst.operands[0].reg << 12;
07550   inst.instruction |= inst.operands[1].reg << 16;
07551   inst.instruction |= inst.operands[2].reg;
07552   inst.instruction |= inst.operands[3].imm << 10;
07553 }
07554 
07555 /* ARM V6 SXTH.
07556 
07557    SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
07558    Condition defaults to COND_ALWAYS.
07559    Error if any register uses R15.  */
07560 
07561 static void
07562 do_sxth (void)
07563 {
07564   inst.instruction |= inst.operands[0].reg << 12;
07565   inst.instruction |= inst.operands[1].reg;
07566   inst.instruction |= inst.operands[2].imm << 10;
07567 }
07568 
07569 /* VFP instructions.  In a logical order: SP variant first, monad
07570    before dyad, arithmetic then move then load/store.  */
07571 
07572 static void
07573 do_vfp_sp_monadic (void)
07574 {
07575   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
07576   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
07577 }
07578 
07579 static void
07580 do_vfp_sp_dyadic (void)
07581 {
07582   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
07583   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
07584   encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
07585 }
07586 
07587 static void
07588 do_vfp_sp_compare_z (void)
07589 {
07590   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
07591 }
07592 
07593 static void
07594 do_vfp_dp_sp_cvt (void)
07595 {
07596   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
07597   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
07598 }
07599 
07600 static void
07601 do_vfp_sp_dp_cvt (void)
07602 {
07603   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
07604   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
07605 }
07606 
07607 static void
07608 do_vfp_reg_from_sp (void)
07609 {
07610   inst.instruction |= inst.operands[0].reg << 12;
07611   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
07612 }
07613 
07614 static void
07615 do_vfp_reg2_from_sp2 (void)
07616 {
07617   constraint (inst.operands[2].imm != 2,
07618              _("only two consecutive VFP SP registers allowed here"));
07619   inst.instruction |= inst.operands[0].reg << 12;
07620   inst.instruction |= inst.operands[1].reg << 16;
07621   encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
07622 }
07623 
07624 static void
07625 do_vfp_sp_from_reg (void)
07626 {
07627   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
07628   inst.instruction |= inst.operands[1].reg << 12;
07629 }
07630 
07631 static void
07632 do_vfp_sp2_from_reg2 (void)
07633 {
07634   constraint (inst.operands[0].imm != 2,
07635              _("only two consecutive VFP SP registers allowed here"));
07636   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
07637   inst.instruction |= inst.operands[1].reg << 12;
07638   inst.instruction |= inst.operands[2].reg << 16;
07639 }
07640 
07641 static void
07642 do_vfp_sp_ldst (void)
07643 {
07644   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
07645   encode_arm_cp_address (1, FALSE, TRUE, 0);
07646 }
07647 
07648 static void
07649 do_vfp_dp_ldst (void)
07650 {
07651   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
07652   encode_arm_cp_address (1, FALSE, TRUE, 0);
07653 }
07654 
07655 
07656 static void
07657 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
07658 {
07659   if (inst.operands[0].writeback)
07660     inst.instruction |= WRITE_BACK;
07661   else
07662     constraint (ldstm_type != VFP_LDSTMIA,
07663               _("this addressing mode requires base-register writeback"));
07664   inst.instruction |= inst.operands[0].reg << 16;
07665   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
07666   inst.instruction |= inst.operands[1].imm;
07667 }
07668 
07669 static void
07670 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
07671 {
07672   int count;
07673 
07674   if (inst.operands[0].writeback)
07675     inst.instruction |= WRITE_BACK;
07676   else
07677     constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
07678               _("this addressing mode requires base-register writeback"));
07679 
07680   inst.instruction |= inst.operands[0].reg << 16;
07681   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
07682 
07683   count = inst.operands[1].imm << 1;
07684   if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
07685     count += 1;
07686 
07687   inst.instruction |= count;
07688 }
07689 
07690 static void
07691 do_vfp_sp_ldstmia (void)
07692 {
07693   vfp_sp_ldstm (VFP_LDSTMIA);
07694 }
07695 
07696 static void
07697 do_vfp_sp_ldstmdb (void)
07698 {
07699   vfp_sp_ldstm (VFP_LDSTMDB);
07700 }
07701 
07702 static void
07703 do_vfp_dp_ldstmia (void)
07704 {
07705   vfp_dp_ldstm (VFP_LDSTMIA);
07706 }
07707 
07708 static void
07709 do_vfp_dp_ldstmdb (void)
07710 {
07711   vfp_dp_ldstm (VFP_LDSTMDB);
07712 }
07713 
07714 static void
07715 do_vfp_xp_ldstmia (void)
07716 {
07717   vfp_dp_ldstm (VFP_LDSTMIAX);
07718 }
07719 
07720 static void
07721 do_vfp_xp_ldstmdb (void)
07722 {
07723   vfp_dp_ldstm (VFP_LDSTMDBX);
07724 }
07725 
07726 static