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cell-binutils  2.17cvs20070401
Classes | Defines | Typedefs | Enumerations | Functions | Variables
tc-arm.c File Reference
#include <limits.h>
#include <stdarg.h>
#include "as.h"
#include "safe-ctype.h"
#include "subsegs.h"
#include "obstack.h"
#include "opcode/arm.h"
#include "dwarf2dbg.h"

Go to the source code of this file.

Classes

struct  neon_type_el
struct  neon_type
struct  arm_it
struct  asm_cond
struct  asm_psr
struct  asm_barrier_opt
struct  reloc_entry
struct  neon_typed_alias
struct  reg_entry
struct  asm_opcode
struct  literal_pool
struct  asm_shift_name
struct  group_reloc_table_entry
struct  neon_tab_entry
struct  arm_it.reloc
struct  arm_it.operands

Defines

#define NO_RELOC   0
#define WARN_DEPRECATED   1
#define FPU_DEFAULT   FPU_ARCH_FPA
#define streq(a, b)   (strcmp (a, b) == 0)
#define NEON_MAX_TYPE_ELS   4
#define NUM_FLOAT_VALS   8
#define MAX_LITTLENUMS   6
#define FAIL   (-1)
#define SUCCESS   (0)
#define SUFF_S   1
#define SUFF_D   2
#define SUFF_E   3
#define SUFF_P   4
#define CP_T_X   0x00008000
#define CP_T_Y   0x00400000
#define CONDS_BIT   0x00100000
#define LOAD_BIT   0x00100000
#define DOUBLE_LOAD_FLAG   0x00000001
#define COND_ALWAYS   0xE
#define SPSR_BIT   (1 << 22)
#define PSR_c   (1 << 16)
#define PSR_x   (1 << 17)
#define PSR_s   (1 << 18)
#define PSR_f   (1 << 19)
#define NTA_HASTYPE   1
#define NTA_HASINDEX   2
#define REG_SP   13
#define REG_LR   14
#define REG_PC   15
#define INSN_SIZE   4
#define INST_IMMEDIATE   0x02000000
#define OFFSET_REG   0x02000000
#define HWOFFSET_IMM   0x00400000
#define SHIFT_BY_REG   0x00000010
#define PRE_INDEX   0x01000000
#define INDEX_UP   0x00800000
#define WRITE_BACK   0x00200000
#define LDM_TYPE_2_OR_3   0x00400000
#define CPSI_MMOD   0x00020000
#define LITERAL_MASK   0xf000f000
#define OPCODE_MASK   0xfe1fffff
#define V4_STR_BIT   0x00000020
#define DATA_OP_SHIFT   21
#define T2_OPCODE_MASK   0xfe1fffff
#define T2_DATA_OP_SHIFT   21
#define OPCODE_AND   0
#define OPCODE_EOR   1
#define OPCODE_SUB   2
#define OPCODE_RSB   3
#define OPCODE_ADD   4
#define OPCODE_ADC   5
#define OPCODE_SBC   6
#define OPCODE_RSC   7
#define OPCODE_TST   8
#define OPCODE_TEQ   9
#define OPCODE_CMP   10
#define OPCODE_CMN   11
#define OPCODE_ORR   12
#define OPCODE_MOV   13
#define OPCODE_BIC   14
#define OPCODE_MVN   15
#define T2_OPCODE_AND   0
#define T2_OPCODE_BIC   1
#define T2_OPCODE_ORR   2
#define T2_OPCODE_ORN   3
#define T2_OPCODE_EOR   4
#define T2_OPCODE_ADD   8
#define T2_OPCODE_ADC   10
#define T2_OPCODE_SBC   11
#define T2_OPCODE_SUB   13
#define T2_OPCODE_RSB   14
#define T_OPCODE_MUL   0x4340
#define T_OPCODE_TST   0x4200
#define T_OPCODE_CMN   0x42c0
#define T_OPCODE_NEG   0x4240
#define T_OPCODE_MVN   0x43c0
#define T_OPCODE_ADD_R3   0x1800
#define T_OPCODE_SUB_R3   0x1a00
#define T_OPCODE_ADD_HI   0x4400
#define T_OPCODE_ADD_ST   0xb000
#define T_OPCODE_SUB_ST   0xb080
#define T_OPCODE_ADD_SP   0xa800
#define T_OPCODE_ADD_PC   0xa000
#define T_OPCODE_ADD_I8   0x3000
#define T_OPCODE_SUB_I8   0x3800
#define T_OPCODE_ADD_I3   0x1c00
#define T_OPCODE_SUB_I3   0x1e00
#define T_OPCODE_ASR_R   0x4100
#define T_OPCODE_LSL_R   0x4080
#define T_OPCODE_LSR_R   0x40c0
#define T_OPCODE_ROR_R   0x41c0
#define T_OPCODE_ASR_I   0x1000
#define T_OPCODE_LSL_I   0x0000
#define T_OPCODE_LSR_I   0x0800
#define T_OPCODE_MOV_I8   0x2000
#define T_OPCODE_CMP_I8   0x2800
#define T_OPCODE_CMP_LR   0x4280
#define T_OPCODE_MOV_HR   0x4600
#define T_OPCODE_CMP_HR   0x4500
#define T_OPCODE_LDR_PC   0x4800
#define T_OPCODE_LDR_SP   0x9800
#define T_OPCODE_STR_SP   0x9000
#define T_OPCODE_LDR_IW   0x6800
#define T_OPCODE_STR_IW   0x6000
#define T_OPCODE_LDR_IH   0x8800
#define T_OPCODE_STR_IH   0x8000
#define T_OPCODE_LDR_IB   0x7800
#define T_OPCODE_STR_IB   0x7000
#define T_OPCODE_LDR_RW   0x5800
#define T_OPCODE_STR_RW   0x5000
#define T_OPCODE_LDR_RH   0x5a00
#define T_OPCODE_STR_RH   0x5200
#define T_OPCODE_LDR_RB   0x5c00
#define T_OPCODE_STR_RB   0x5400
#define T_OPCODE_PUSH   0xb400
#define T_OPCODE_POP   0xbc00
#define T_OPCODE_BRANCH   0xe000
#define THUMB_SIZE   2 /* Size of thumb instruction. */
#define THUMB_PP_PC_LR   0x0100
#define THUMB_LOAD_BIT   0x0800
#define THUMB2_LOAD_BIT   0x00100000
#define BAD_ARGS   _("bad arguments to instruction")
#define BAD_PC   _("r15 not allowed here")
#define BAD_COND   _("instruction cannot be conditional")
#define BAD_OVERLAP   _("registers may not be the same")
#define BAD_HIREG   _("lo register required")
#define BAD_THUMB32   _("instruction not supported in Thumb16 mode")
#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
#define BAD_BRANCH   _("branch must be last instruction in IT block")
#define BAD_NOT_IT   _("instruction not allowed in IT block")
#define BAD_FPU   _("selected FPU does not support instruction")
#define MAX_LITERAL_POOL_SIZE   1024
#define is_immediate_prefix(C)   ((C) == '#' || (C) == '$')
#define skip_whitespace(str)   do { if (*(str) == ' ') ++(str); } while (0)
#define skip_past_comma(str)   skip_past_char (str, ',')
#define GE_NO_PREFIX   0
#define GE_IMM_PREFIX   1
#define GE_OPT_PREFIX   2
#define GE_OPT_PREFIX_BIG   3
#define NEON_ALL_LANES   15
#define NEON_INTERLEAVE_LANES   14
#define NEON_SCALAR_REG(X)   ((X) >> 4)
#define NEON_SCALAR_INDEX(X)   ((X) & 15)
#define NEON_LANE(X)   ((X) & 0xf)
#define NEON_REG_STRIDE(X)   ((((X) >> 4) & 1) + 1)
#define NEON_REGLIST_LENGTH(X)   ((((X) >> 5) & 3) + 1)
#define mapping_state(x)   /* nothing */
#define STUB_NAME   ".real_start_of"
#define po_char_or_fail(chr)
#define po_reg_or_fail(regtype)
#define po_reg_or_goto(regtype, label)
#define po_imm_or_fail(min, max, popt)
#define po_scalar_or_goto(elsz, label)
#define po_misc_or_fail(expr)
#define po_misc_or_fail_no_backtrack(expr)
#define constraint(expr, err)
#define rotate_left(v, n)   (v << n | v >> (32 - n))
#define T16_32_TAB
#define X(a, b, c)   T_MNEM_##a
#define X(a, b, c)   0x##b
#define THUMB_OP16(n)   (thumb_op16[(n) - (T16_32_OFFSET + 1)])
#define X(a, b, c)   0x##c
#define THUMB_OP32(n)   (thumb_op32[(n) - (T16_32_OFFSET + 1)])
#define THUMB_SETS_FLAGS(n)   (THUMB_OP32 (n) & 0x00100000)
#define N_INV   -1u
#define NEON_ENC_TAB
#define X(OPC, I, F, S)   N_MNEM_##OPC
#define X(OPC, I, F, S)   { (I), (F), (S) }
#define NEON_ENC_INTEGER(X)   (neon_enc_tab[(X) & 0x0fffffff].integer)
#define NEON_ENC_ARMREG(X)   (neon_enc_tab[(X) & 0x0fffffff].integer)
#define NEON_ENC_POLY(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
#define NEON_ENC_FLOAT(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
#define NEON_ENC_SCALAR(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
#define NEON_ENC_IMMED(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
#define NEON_ENC_INTERLV(X)   (neon_enc_tab[(X) & 0x0fffffff].integer)
#define NEON_ENC_LANE(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
#define NEON_ENC_DUP(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
#define NEON_ENC_SINGLE(X)   ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
#define NEON_ENC_DOUBLE(X)   ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
#define NEON_SHAPE_DEF
#define S2(A, B)   NS_##A##B
#define S3(A, B, C)   NS_##A##B##C
#define S4(A, B, C, D)   NS_##A##B##C##D
#define X(N, L, C)   S##N L
#define X(N, L, C)   SC_##C
#define S2(A, B)   { SE_##A, SE_##B }
#define S3(A, B, C)   { SE_##A, SE_##B, SE_##C }
#define S4(A, B, C, D)   { SE_##A, SE_##B, SE_##C, SE_##D }
#define X(N, L, C)   { N, S##N L }
#define N_ALLMODS   (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
#define N_SU_ALL   (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
#define N_SU_32   (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
#define N_SU_16_64   (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
#define N_SUF_32   (N_SU_32 | N_F32)
#define N_I_ALL   (N_I8 | N_I16 | N_I32 | N_I64)
#define N_IF_32   (N_I8 | N_I16 | N_I32 | N_F32)
#define N_IGNORE_TYPE   (N_KEY | N_EQK)
#define LOW4(R)   ((R) & 0xf)
#define HI1(R)   (((R) >> 4) & 1)
#define CVT_VAR(C, X, Y)
#define REGDEF(s, n, t)   { #s, n, REG_TYPE_##t, TRUE, 0 }
#define REGNUM(p, n, t)   REGDEF(p##n, n, t)
#define REGNUM2(p, n, t)   REGDEF(p##n, 2 * n, t)
#define REGSET(p, t)
#define REGSETH(p, t)
#define REGSET2(p, t)
#define OPS0()   { OP_stop, }
#define OPS1(a)   { OP_##a, }
#define OPS2(a, b)   { OP_##a,OP_##b, }
#define OPS3(a, b, c)   { OP_##a,OP_##b,OP_##c, }
#define OPS4(a, b, c, d)   { OP_##a,OP_##b,OP_##c,OP_##d, }
#define OPS5(a, b, c, d, e)   { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
#define OPS6(a, b, c, d, e, f)   { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
#define TxCE(mnem, op, top, nops, ops, ae, te)
#define TCE(mnem, aop, top, nops, ops, ae, te)   TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
#define tCE(mnem, aop, top, nops, ops, ae, te)   TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
#define TxC3(mnem, op, top, nops, ops, ae, te)
#define TxC3w(mnem, op, top, nops, ops, ae, te)
#define TC3(mnem, aop, top, nops, ops, ae, te)   TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
#define TC3w(mnem, aop, top, nops, ops, ae, te)   TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
#define tC3(mnem, aop, top, nops, ops, ae, te)   TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
#define tC3w(mnem, aop, top, nops, ops, ae, te)   TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te)
#define TxCM(m1, m2, op, top, nops, ops, ae, te)
#define TCM(m1, m2, aop, top, nops, ops, ae, te)   TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
#define tCM(m1, m2, aop, top, nops, ops, ae, te)   TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
#define TUE(mnem, op, top, nops, ops, ae, te)
#define TUF(mnem, op, top, nops, ops, ae, te)
#define CE(mnem,op, nops, ops, ae)   { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
#define C3(mnem, op, nops, ops, ae)   { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
#define CL(mnem, op, nops, ops, ae)
#define cCE(mnem,op, nops, ops, ae)   { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
#define cCL(mnem, op, nops, ops, ae)
#define C3E(mnem, op, nops, ops, ae)
#define xCM_(m1, m2, m3, op, nops, ops, ae)
#define CM(m1, m2, op, nops, ops, ae)
#define UE(mnem, op, nops, ops, ae)   { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
#define UF(mnem, op, nops, ops, ae)   { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
#define NUF(mnem, op, nops, ops, enc)
#define nUF(mnem, op, nops, ops, enc)
#define NCE_tag(mnem, op, nops, ops, enc, tag)
#define NCE(mnem, op, nops, ops, enc)   NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
#define NCEF(mnem, op, nops, ops, enc)   NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
#define nCE_tag(mnem, op, nops, ops, enc, tag)
#define nCE(mnem, op, nops, ops, enc)   nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
#define nCEF(mnem, op, nops, ops, enc)   nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
#define do_0   0
#define UT(mnem,op, nops, ops, te)   TUE(mnem, 0, op, nops, ops, 0, te)
#define ARM_VARIANT   &arm_ext_v1 /* Core ARM Instructions. */
#define THUMB_VARIANT   &arm_ext_v4t
#define THUMB_VARIANT   &arm_ext_v6
#define THUMB_VARIANT   &arm_ext_v6t2
#define ARM_VARIANT   &arm_ext_v2 /* ARM 2 - multiplies. */
#define THUMB_VARIANT   &arm_ext_v4t
#define THUMB_VARIANT   &arm_ext_v6t2
#define ARM_VARIANT   &arm_ext_v2s /* ARM 3 - swp instructions. */
#define ARM_VARIANT   &arm_ext_v3 /* ARM 6 Status register instructions. */
#define ARM_VARIANT   &arm_ext_v3m /* ARM 7M long multiplies. */
#define ARM_VARIANT   &arm_ext_v4 /* ARM Architecture 4. */
#define THUMB_VARIANT   &arm_ext_v4t
#define ARM_VARIANT   &arm_ext_v4t_5
#define ARM_VARIANT   &arm_ext_v5 /* ARM Architecture 5T. */
#define THUMB_VARIANT   &arm_ext_v5t
#define THUMB_VARIANT   &arm_ext_v6t2
#define ARM_VARIANT   &arm_ext_v5exp /* ARM Architecture 5TExP. */
#define ARM_VARIANT   &arm_ext_v5e /* ARM Architecture 5TE. */
#define ARM_VARIANT   &arm_ext_v5j /* ARM Architecture 5TEJ. */
#define ARM_VARIANT   &arm_ext_v6 /* ARM V6. */
#define THUMB_VARIANT   &arm_ext_v6
#define THUMB_VARIANT   &arm_ext_v6t2
#define THUMB_VARIANT   &arm_ext_v6_notm
#define ARM_VARIANT   &arm_ext_v6k
#define THUMB_VARIANT   &arm_ext_v6k
#define THUMB_VARIANT   &arm_ext_v6_notm
#define THUMB_VARIANT   &arm_ext_v6t2
#define ARM_VARIANT   &arm_ext_v6z
#define ARM_VARIANT   &arm_ext_v6t2
#define ARM_VARIANT   &arm_ext_v1
#define ARM_VARIANT   NULL
#define THUMB_VARIANT   &arm_ext_div
#define ARM_VARIANT   &arm_ext_v7
#define THUMB_VARIANT   &arm_ext_v7
#define ARM_VARIANT   &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#define ARM_VARIANT   &fpu_fpa_ext_v2
#define ARM_VARIANT   &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
#define ARM_VARIANT   &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
#define ARM_VARIANT   &fpu_vfp_ext_v2
#define ARM_VARIANT   &fpu_vfp_ext_v1xd
#define THUMB_VARIANT   &fpu_vfp_ext_v1xd
#define THUMB_VARIANT   &fpu_neon_ext_v1
#define ARM_VARIANT   &fpu_neon_ext_v1
#define THUMB_VARIANT   &fpu_vfp_v3_or_neon_ext
#define ARM_VARIANT   &fpu_vfp_v3_or_neon_ext
#define THUMB_VARIANT   &fpu_vfp_ext_v3
#define ARM_VARIANT   &fpu_vfp_ext_v3
#define ARM_VARIANT   &arm_cext_xscale /* Intel XScale extensions. */
#define ARM_VARIANT   &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
#define ARM_VARIANT   &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
#define ARM_VARIANT   &arm_cext_maverick /* Cirrus Maverick instructions. */
#define OPTION_EL   (OPTION_MD_BASE + 1)

Typedefs

typedef struct literal_pool literal_pool

Enumerations

enum  parse_operand_result { PARSE_OPERAND_SUCCESS, PARSE_OPERAND_FAIL, PARSE_OPERAND_FAIL_NO_BACKTRACK }
enum  arm_float_abi { ARM_FLOAT_ABI_HARD, ARM_FLOAT_ABI_SOFTFP, ARM_FLOAT_ABI_SOFT }
enum  neon_el_type {
  NT_invtype, NT_untyped, NT_integer, NT_float,
  NT_poly, NT_signed, NT_unsigned
}
enum  vfp_reg_pos {
  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn, VFP_REG_Dd,
  VFP_REG_Dm, VFP_REG_Dn
}
enum  vfp_ldstm_type { VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX }
enum  arm_reg_type {
  REG_TYPE_RN, REG_TYPE_CP, REG_TYPE_CN, REG_TYPE_FN,
  REG_TYPE_VFS, REG_TYPE_VFD, REG_TYPE_NQ, REG_TYPE_VFSD,
  REG_TYPE_NDQ, REG_TYPE_NSDQ, REG_TYPE_VFC, REG_TYPE_MVF,
  REG_TYPE_MVD, REG_TYPE_MVFX, REG_TYPE_MVDX, REG_TYPE_MVAX,
  REG_TYPE_DSPSC, REG_TYPE_MMXWR, REG_TYPE_MMXWC, REG_TYPE_MMXWCG,
  REG_TYPE_XSCALE
}
enum  reg_list_els { REGLIST_VFP_S, REGLIST_VFP_D, REGLIST_NEON_D }
enum  shift_kind {
  SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR,
  SHIFT_RRX
}
enum  parse_shift_mode {
  NO_SHIFT_RESTRICT, SHIFT_IMMEDIATE, SHIFT_LSL_OR_ASR_IMMEDIATE, SHIFT_ASR_IMMEDIATE,
  SHIFT_LSL_IMMEDIATE
}
enum  group_reloc_type { GROUP_LDR, GROUP_LDRS, GROUP_LDC }
enum  operand_parse_code {
  OP_stop, OP_RR, OP_RRnpc, OP_RRnpcb,
  OP_RRw, OP_RCP, OP_RCN, OP_RF,
  OP_RVS, OP_RVD, OP_RND, OP_RNQ,
  OP_RVSD, OP_RNDQ, OP_RNSDQ, OP_RNSC,
  OP_RVC, OP_RMF, OP_RMD, OP_RMFX,
  OP_RMDX, OP_RMAX, OP_RMDS, OP_RIWR,
  OP_RIWC, OP_RIWG, OP_RXA, OP_REGLST,
  OP_VRSLST, OP_VRDLST, OP_VRSDLST, OP_NRDLST,
  OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RVSD_I0,
  OP_RR_RNSC, OP_RNSDQ_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC,
  OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_RIWR_I32z,
  OP_I0, OP_I7, OP_I15, OP_I16,
  OP_I16z, OP_I31, OP_I31w, OP_I32,
  OP_I32z, OP_I63, OP_I63s, OP_I64,
  OP_I64z, OP_I255, OP_I4b, OP_I7b,
  OP_I15b, OP_I31b, OP_SH, OP_SHG,
  OP_ADDR, OP_ADDRGLDR, OP_ADDRGLDRS, OP_ADDRGLDC,
  OP_EXP, OP_EXPi, OP_EXPr, OP_HALF,
  OP_CPSF, OP_ENDI, OP_PSR, OP_COND,
  OP_TB, OP_RVC_PSR, OP_APSR_RR, OP_RRnpc_I0,
  OP_RR_EXr, OP_RR_EXi, OP_RF_IF, OP_RIWR_RIWC,
  OP_RIWC_RIWG, OP_oI7b, OP_oI31b, OP_oI32b,
  OP_oIffffb, OP_oI255c, OP_oRR, OP_oRRnpc,
  OP_oRRw, OP_oRND, OP_oRNQ, OP_oRNDQ,
  OP_oRNSDQ, OP_oSHll, OP_oSHar, OP_oSHllar,
  OP_oROR, OP_oBARRIER, OP_FIRST_OPTIONAL = OP_oI7b
}
enum  t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB }
enum  neon_opc { NEON_ENC_TAB }
enum  neon_shape { NEON_SHAPE_DEF, NS_NULL }
enum  neon_shape_class { SC_SINGLE, SC_DOUBLE, SC_QUAD, SC_MIXED }

Functions

static int skip_past_char (char **str, char c)
static int walk_no_bignums (symbolS *sp)
static int my_get_expression (expressionS *ep, char **str, int prefix_mode)
char * md_atof (int type, char *litP, int *sizeP)
void md_operand (expressionS *expr)
static struct reg_entryarm_reg_parse_multi (char **ccp)
static int arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg, enum arm_reg_type type)
static int arm_reg_parse (char **ccp, enum arm_reg_type type)
static int parse_neon_type (struct neon_type *type, char **str)
static void first_error (const char *err)
static int parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
static int parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type, enum arm_reg_type *rtype, struct neon_typed_alias *typeinfo)
static int arm_typed_reg_parse (char **ccp, enum arm_reg_type type, enum arm_reg_type *rtype, struct neon_type_el *vectype)
static int parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
static long parse_reg_list (char **strp)
static int parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
static int neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
static int parse_neon_el_struct_list (char **str, unsigned *pbase, struct neon_type_el *eltype)
static int parse_reloc (char **str)
static struct reg_entryinsert_reg_alias (char *str, int number, int type)
static void insert_neon_reg_alias (char *str, int number, int type, struct neon_typed_alias *atype)
static int create_register_alias (char *newname, char *p)
static int create_neon_reg_alias (char *newname, char *p)
static void s_req (int a ATTRIBUTE_UNUSED)
static void s_dn (int a ATTRIBUTE_UNUSED)
static void s_qn (int a ATTRIBUTE_UNUSED)
static void s_unreq (int a ATTRIBUTE_UNUSED)
static symbolS * find_real_start (symbolS *symbolP)
static void opcode_select (int width)
static void s_arm (int ignore ATTRIBUTE_UNUSED)
static void s_thumb (int ignore ATTRIBUTE_UNUSED)
static void s_code (int unused ATTRIBUTE_UNUSED)
static void s_force_thumb (int ignore ATTRIBUTE_UNUSED)
static void s_thumb_func (int ignore ATTRIBUTE_UNUSED)
static void s_thumb_set (int equiv)
static void s_syntax (int unused ATTRIBUTE_UNUSED)
static void s_align (int unused ATTRIBUTE_UNUSED)
static void s_bss (int ignore ATTRIBUTE_UNUSED)
static void s_even (int ignore ATTRIBUTE_UNUSED)
static literal_poolfind_literal_pool (void)
static literal_poolfind_or_make_literal_pool (void)
static int add_to_lit_pool (void)
static void symbol_locate (symbolS *symbolP, const char *name, segT segment, valueT valu, fragS *frag)
static void s_ltorg (int ignored ATTRIBUTE_UNUSED)
static void s_arm_arch (int)
static void s_arm_object_arch (int)
static void s_arm_cpu (int)
static void s_arm_fpu (int)
static int parse_immediate (char **str, int *val, int min, int max, bfd_boolean prefix_opt)
static int parse_big_immediate (char **str, int i)
static int parse_fpa_immediate (char **str)
static int is_quarter_float (unsigned imm)
static unsigned parse_qfloat_immediate (char **ccp, int *immed)
static int parse_shift (char **str, int i, enum parse_shift_mode mode)
static int parse_shifter_operand (char **str, int i)
static int find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
static parse_operand_result parse_shifter_operand_group_reloc (char **str, int i)
static parse_operand_result parse_address_main (char **str, int i, int group_relocations, group_reloc_type group_type)
static int parse_address (char **str, int i)
static parse_operand_result parse_address_group_reloc (char **str, int i, group_reloc_type type)
static int parse_half (char **str)
static int parse_psr (char **str)
static int parse_cps_flags (char **str)
static int parse_endian_specifier (char **str)
static int parse_ror (char **str)
static int parse_cond (char **str)
static int parse_barrier (char **str)
static int parse_tb (char **str)
static int parse_neon_mov (char **str, int *which_operand)
static int parse_operands (char *str, const unsigned char *pattern)
static unsigned int encode_arm_immediate (unsigned int val)
static unsigned int encode_thumb32_immediate (unsigned int val)
static void encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
static void encode_arm_shift (int i)
static void encode_arm_shifter_operand (int i)
static void encode_arm_addr_mode_common (int i, bfd_boolean is_t)
static void encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
static void encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
static int encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
static int move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
static void do_noargs (void)
static void do_rd (void)
static void do_rd_rm (void)
static void do_rd_rn (void)
static void do_rn_rd (void)
static void do_rd_rm_rn (void)
static void do_rd_rn_rm (void)
static void do_rm_rd_rn (void)
static void do_imm0 (void)
static void do_rd_cpaddr (void)
static void do_adr (void)
static void do_adrl (void)
static void do_arit (void)
static void do_barrier (void)
static void do_bfc (void)
static void do_bfi (void)
static void do_bfx (void)
static void do_bkpt (void)
static void encode_branch (int default_reloc)
static void do_branch (void)
static void do_bl (void)
static void do_blx (void)
static void do_bx (void)
static void do_bxj (void)
static void do_cdp (void)
static void do_cmp (void)
static void do_co_reg (void)
static void do_co_reg2c (void)
static void do_cpsi (void)
static void do_dbg (void)
static void do_it (void)
static void do_ldmstm (void)
static void do_ldrd (void)
static void do_ldrex (void)
static void do_ldrexd (void)
static void do_ldst (void)
static void do_ldstt (void)
static void do_ldstv4 (void)
static void do_ldsttv4 (void)
static void do_lstc (void)
static void do_mlas (void)
static void do_mov (void)
static void do_mov16 (void)
static void do_vfp_nsyn_opcode (const char *)
static int do_vfp_nsyn_mrs (void)
static int do_vfp_nsyn_msr (void)
static void do_mrs (void)
static void do_msr (void)
static void do_mul (void)
static void do_mull (void)
static void do_nop (void)
static void do_pkhbt (void)
static void do_pkhtb (void)
static void do_pld (void)
static void do_pli (void)
static void do_push_pop (void)
static void do_rfe (void)
static void do_ssat (void)
static void do_usat (void)
static void do_ssat16 (void)
static void do_usat16 (void)
static void do_setend (void)
static void do_shift (void)
static void do_smc (void)
static void do_swi (void)
static void do_smla (void)
static void do_smlal (void)
static void do_smul (void)
static void do_srs (void)
static void do_strex (void)
static void do_strexd (void)
static void do_sxtah (void)
static void do_sxth (void)
static void do_vfp_sp_monadic (void)
static void do_vfp_sp_dyadic (void)
static void do_vfp_sp_compare_z (void)
static void do_vfp_dp_sp_cvt (void)
static void do_vfp_sp_dp_cvt (void)
static void do_vfp_reg_from_sp (void)
static void do_vfp_reg2_from_sp2 (void)
static void do_vfp_sp_from_reg (void)
static void do_vfp_sp2_from_reg2 (void)
static void do_vfp_sp_ldst (void)
static void do_vfp_dp_ldst (void)
static void vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
static void vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
static void do_vfp_sp_ldstmia (void)
static void do_vfp_sp_ldstmdb (void)
static void do_vfp_dp_ldstmia (void)
static void do_vfp_dp_ldstmdb (void)
static void do_vfp_xp_ldstmia (void)
static void do_vfp_xp_ldstmdb (void)
static void do_vfp_dp_rd_rm (void)
static void do_vfp_dp_rn_rd (void)
static void do_vfp_dp_rd_rn (void)
static void do_vfp_dp_rd_rn_rm (void)
static void do_vfp_dp_rd (void)
static void do_vfp_dp_rm_rd_rn (void)
static void do_vfp_sp_const (void)
static void do_vfp_dp_const (void)
static void vfp_conv (int srcsize)
static void do_vfp_sp_conv_16 (void)
static void do_vfp_dp_conv_16 (void)
static void do_vfp_sp_conv_32 (void)
static void do_vfp_dp_conv_32 (void)
static void do_fpa_cmp (void)
static void do_fpa_ldmstm (void)
static void do_iwmmxt_tandorc (void)
static void do_iwmmxt_textrc (void)
static void do_iwmmxt_textrm (void)
static void do_iwmmxt_tinsr (void)
static void do_iwmmxt_tmia (void)
static void do_iwmmxt_waligni (void)
static void do_iwmmxt_wmerge (void)
static void do_iwmmxt_wmov (void)
static void do_iwmmxt_wldstbh (void)
static void do_iwmmxt_wldstw (void)
static void do_iwmmxt_wldstd (void)
static void do_iwmmxt_wshufh (void)
static void do_iwmmxt_wzero (void)
static void do_iwmmxt_wrwrwr_or_imm5 (void)
static void do_mav_triple (void)
static void do_mav_quad (void)
static void do_mav_dspsc (void)
static void do_mav_shift (void)
static void do_xsc_mia (void)
static void do_xsc_mar (void)
static void do_xsc_mra (void)
static void encode_thumb32_shifted_operand (int i)
static void encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
static void do_t_add_sub_w (void)
static void do_t_add_sub (void)
static void do_t_adr (void)
static void do_t_arit3 (void)
static void do_t_arit3c (void)
static void do_t_barrier (void)
static void do_t_bfc (void)
static void do_t_bfi (void)
static void do_t_bfx (void)
static void do_t_blx (void)
static void do_t_branch (void)
static void do_t_bkpt (void)
static void do_t_branch23 (void)
static void do_t_bx (void)
static void do_t_bxj (void)
static void do_t_clz (void)
static void do_t_cps (void)
static void do_t_cpsi (void)
static void do_t_cpy (void)
static void do_t_cbz (void)
static void do_t_dbg (void)
static void do_t_div (void)
static void do_t_hint (void)
static void do_t_it (void)
static void encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
static void do_t_ldmstm (void)
static void do_t_ldrex (void)
static void do_t_ldrexd (void)
static void do_t_ldst (void)
static void do_t_ldstd (void)
static void do_t_ldstt (void)
static void do_t_mla (void)
static void do_t_mlal (void)
static void do_t_mov_cmp (void)
static void do_t_mov16 (void)
static void do_t_mvn_tst (void)
static void do_t_mrs (void)
static void do_t_msr (void)
static void do_t_mul (void)
static void do_t_mull (void)
static void do_t_nop (void)
static void do_t_neg (void)
static void do_t_pkhbt (void)
static void do_t_pkhtb (void)
static void do_t_pld (void)
static void do_t_push_pop (void)
static void do_t_rbit (void)
static void do_t_rev (void)
static void do_t_rsb (void)
static void do_t_setend (void)
static void do_t_shift (void)
static void do_t_simd (void)
static void do_t_smc (void)
static void do_t_ssat (void)
static void do_t_ssat16 (void)
static void do_t_strex (void)
static void do_t_strexd (void)
static void do_t_sxtah (void)
static void do_t_sxth (void)
static void do_t_swi (void)
static void do_t_tb (void)
static void do_t_usat (void)
static void do_t_usat16 (void)

Variables

static arm_feature_set cpu_variant
static arm_feature_set arm_arch_used
static arm_feature_set thumb_arch_used
static int uses_apcs_26 = FALSE
static int atpcs = FALSE
static int support_interwork = FALSE
static int uses_apcs_float = FALSE
static int pic_code = FALSE
static const arm_feature_setlegacy_cpu = NULL
static const arm_feature_setlegacy_fpu = NULL
static const arm_feature_setmcpu_cpu_opt = NULL
static const arm_feature_setmcpu_fpu_opt = NULL
static const arm_feature_setmarch_cpu_opt = NULL
static const arm_feature_setmarch_fpu_opt = NULL
static const arm_feature_setmfpu_opt = NULL
static const arm_feature_setobject_arch = NULL
static const arm_feature_set fpu_default = FPU_DEFAULT
static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1
static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2
static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3
static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1
static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA
static const arm_feature_set fpu_any_hard = FPU_ANY_HARD
static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK
static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE
static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0)
static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0)
static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0)
static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0)
static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0)
static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0)
static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0)
static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0)
static const arm_feature_set arm_ext_v4t_5
static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0)
static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0)
static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0)
static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0)
static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0)
static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0)
static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0)
static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0)
static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0)
static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0)
static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0)
static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0)
static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0)
static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0)
static const arm_feature_set arm_arch_any = ARM_ANY
static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1)
static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2
static const arm_feature_set arm_arch_none = ARM_ARCH_NONE
static const arm_feature_set arm_cext_iwmmxt2
static const arm_feature_set arm_cext_iwmmxt
static const arm_feature_set arm_cext_xscale
static const arm_feature_set arm_cext_maverick
static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1)
static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2)
static const arm_feature_set fpu_vfp_ext_v1xd
static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1)
static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2)
static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3)
static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1)
static const arm_feature_set fpu_vfp_v3_or_neon_ext
static int mfloat_abi_opt = -1
static arm_feature_set selected_cpu = ARM_ARCH_NONE
static char selected_cpu_name [16]
static int thumb_mode = 0
static bfd_boolean unified_syntax = FALSE
static struct arm_it
const char * fp_const []
LITTLENUM_TYPE fp_values [NUM_FLOAT_VALS][MAX_LITTLENUMS]
const char *const reg_expected_msgs []
static struct hash_controlarm_ops_hsh
static struct hash_controlarm_cond_hsh
static struct hash_controlarm_shift_hsh
static struct hash_controlarm_psr_hsh
static struct hash_controlarm_v7m_psr_hsh
static struct hash_controlarm_reg_hsh
static struct hash_controlarm_reloc_hsh
static struct hash_controlarm_barrier_opt_hsh
symbolS * last_label_seen
static int label_is_thumb_function_name = FALSE
literal_poollist_of_pools = NULL
static bfd_boolean current_it_mask = 0
static int current_cc
const char comment_chars [] = "@"
const char line_comment_chars [] = "#"
const char line_separator_chars [] = ";"
const char EXP_CHARS [] = "eE"
const char FLT_CHARS [] = "rRsSfFdDxXeEpP"
static int in_my_get_expression = 0
const pseudo_typeS md_pseudo_table []
static struct group_reloc_table_entry []
static const unsigned short thumb_op16 [] = { T16_32_TAB }
static const unsigned int thumb_op32 [] = { T16_32_TAB }
static struct neon_tab_entry []

Class Documentation

struct neon_type_el

Definition at line 290 of file tc-arm.c.

struct neon_type

Definition at line 298 of file tc-arm.c.

Class Members
unsigned elems
struct arm_it

Definition at line 304 of file tc-arm.c.

Class Members
int cond
const char * error
unsigned long instruction
struct arm_it operands
unsigned long relax
struct arm_it reloc
int size
int size_req
int uncond_value
struct asm_cond

Definition at line 383 of file tc-arm.c.

Class Members
const char * template
unsigned long value
struct asm_psr

Definition at line 391 of file tc-arm.c.

Class Members
unsigned long field
const char * template
struct asm_barrier_opt

Definition at line 397 of file tc-arm.c.

Class Members
const char * template
unsigned long value
struct reloc_entry

Definition at line 412 of file tc-arm.c.

Class Members
char * name
bfd_reloc_code_real_type reloc
struct neon_typed_alias

Definition at line 433 of file tc-arm.c.

Class Members
unsigned char defined
unsigned char index
struct reg_entry

Definition at line 471 of file tc-arm.c.

Collaboration diagram for reg_entry:
Class Members
unsigned char builtin
int image
char * name
const char * name
struct neon_typed_alias * neon
int number
unsigned char number
unsigned int reg_flags
char * reg_name
unsigned int reg_num
unsigned int reg_type
reg_type type
unsigned char type
union reg_entry value
struct literal_pool

Definition at line 687 of file tc-arm.c.

Collaboration diagram for literal_pool:
Class Members
unsigned int id
expressionS literals
struct literal_pool * next
unsigned int next_free_entry
segT section
subsegT sub_section
symbolS * symbol
struct asm_shift_name

Definition at line 4249 of file tc-arm.c.

Class Members
const char * name
struct group_reloc_table_entry

Definition at line 4433 of file tc-arm.c.

Class Members
int alu_code
int ldc_code
int ldr_code
int ldrs_code
const char * name
struct neon_tab_entry

Definition at line 10286 of file tc-arm.c.

Class Members
unsigned float_or_poly
unsigned integer
unsigned scalar_or_imm
struct arm_it.reloc

Definition at line 319 of file tc-arm.c.

Class Members
expressionS exp
int pc_rel
bfd_reloc_code_real_type type
struct arm_it.operands

Definition at line 326 of file tc-arm.c.

Class Members
unsigned hasreloc: 1
signed int imm
unsigned immisalign: 1
unsigned immisfloat: 1
unsigned immisreg: 1
unsigned isquad: 1
unsigned isreg: 1
unsigned isscalar: 1
unsigned issingle: 1
unsigned isvec: 1
unsigned negative: 1
unsigned postind: 1
unsigned preind: 1
unsigned present: 1
unsigned reg
unsigned regisimm: 1
unsigned shift_kind: 3
unsigned shifted: 1
unsigned writeback: 1

Define Documentation

#define ARM_VARIANT   &arm_ext_v1 /* Core ARM Instructions. */
#define ARM_VARIANT   &arm_ext_v2 /* ARM 2 - multiplies. */
#define ARM_VARIANT   &arm_ext_v2s /* ARM 3 - swp instructions. */
#define ARM_VARIANT   &arm_ext_v3 /* ARM 6 Status register instructions. */
#define ARM_VARIANT   &arm_ext_v3m /* ARM 7M long multiplies. */
#define ARM_VARIANT   &arm_ext_v4 /* ARM Architecture 4. */
#define ARM_VARIANT   &arm_ext_v4t_5
#define ARM_VARIANT   &arm_ext_v5 /* ARM Architecture 5T. */
#define ARM_VARIANT   &arm_ext_v5exp /* ARM Architecture 5TExP. */
#define ARM_VARIANT   &arm_ext_v5e /* ARM Architecture 5TE. */
#define ARM_VARIANT   &arm_ext_v5j /* ARM Architecture 5TEJ. */
#define ARM_VARIANT   &arm_ext_v6 /* ARM V6. */
#define ARM_VARIANT   &arm_ext_v6k
#define ARM_VARIANT   &arm_ext_v6z
#define ARM_VARIANT   &arm_ext_v6t2
#define ARM_VARIANT   &arm_ext_v1
#define ARM_VARIANT   NULL
#define ARM_VARIANT   &arm_ext_v7
#define ARM_VARIANT   &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#define ARM_VARIANT   &fpu_fpa_ext_v2
#define ARM_VARIANT   &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
#define ARM_VARIANT   &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
#define ARM_VARIANT   &fpu_vfp_ext_v2
#define ARM_VARIANT   &fpu_vfp_ext_v3
#define ARM_VARIANT   &arm_cext_xscale /* Intel XScale extensions. */
#define ARM_VARIANT   &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
#define ARM_VARIANT   &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
#define ARM_VARIANT   &arm_cext_maverick /* Cirrus Maverick instructions. */
#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");

Definition at line 656 of file tc-arm.c.

#define BAD_ARGS   _("bad arguments to instruction")

Definition at line 650 of file tc-arm.c.

#define BAD_BRANCH   _("branch must be last instruction in IT block")

Definition at line 657 of file tc-arm.c.

#define BAD_COND   _("instruction cannot be conditional")

Definition at line 652 of file tc-arm.c.

#define BAD_FPU   _("selected FPU does not support instruction")

Definition at line 659 of file tc-arm.c.

#define BAD_HIREG   _("lo register required")

Definition at line 654 of file tc-arm.c.

#define BAD_NOT_IT   _("instruction not allowed in IT block")

Definition at line 658 of file tc-arm.c.

#define BAD_OVERLAP   _("registers may not be the same")

Definition at line 653 of file tc-arm.c.

#define BAD_PC   _("r15 not allowed here")

Definition at line 651 of file tc-arm.c.

#define BAD_THUMB32   _("instruction not supported in Thumb16 mode")

Definition at line 655 of file tc-arm.c.

#define C3 (   mnem,
  op,
  nops,
  ops,
  ae 
)    { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
#define C3E (   mnem,
  op,
  nops,
  ops,
  ae 
)
Value:
{ #mnem, OPS##nops ops, OT_csuf_or_in3, \
    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
#define cCE (   mnem,
  op,
  nops,
  ops,
  ae 
)    { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
#define cCL (   mnem,
  op,
  nops,
  ops,
  ae 
)
Value:
{ #mnem, OPS##nops ops, OT_cinfix3_legacy, \
    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
#define CE (   mnem,
  op,
  nops,
  ops,
  ae 
)    { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
#define CL (   mnem,
  op,
  nops,
  ops,
  ae 
)
Value:
{ #mnem, OPS##nops ops, OT_cinfix3_legacy, \
    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
#define CM (   m1,
  m2,
  op,
  nops,
  ops,
  ae 
)
Value:
xCM_(m1,   , m2, op, nops, ops, ae),      \
  xCM_(m1, eq, m2, op, nops, ops, ae),    \
  xCM_(m1, ne, m2, op, nops, ops, ae),    \
  xCM_(m1, cs, m2, op, nops, ops, ae),    \
  xCM_(m1, hs, m2, op, nops, ops, ae),    \
  xCM_(m1, cc, m2, op, nops, ops, ae),    \
  xCM_(m1, ul, m2, op, nops, ops, ae),    \
  xCM_(m1, lo, m2, op, nops, ops, ae),    \
  xCM_(m1, mi, m2, op, nops, ops, ae),    \
  xCM_(m1, pl, m2, op, nops, ops, ae),    \
  xCM_(m1, vs, m2, op, nops, ops, ae),    \
  xCM_(m1, vc, m2, op, nops, ops, ae),    \
  xCM_(m1, hi, m2, op, nops, ops, ae),    \
  xCM_(m1, ls, m2, op, nops, ops, ae),    \
  xCM_(m1, ge, m2, op, nops, ops, ae),    \
  xCM_(m1, lt, m2, op, nops, ops, ae),    \
  xCM_(m1, gt, m2, op, nops, ops, ae),    \
  xCM_(m1, le, m2, op, nops, ops, ae),    \
  xCM_(m1, al, m2, op, nops, ops, ae)
#define COND_ALWAYS   0xE

Definition at line 389 of file tc-arm.c.

#define CONDS_BIT   0x00100000

Definition at line 378 of file tc-arm.c.

#define constraint (   expr,
  err 
)
Value:
do {          \
  if (expr)                               \
    {                                     \
      inst.error = err;                          \
      return;                             \
    }                                     \
} while (0)

Definition at line 6109 of file tc-arm.c.

#define CP_T_X   0x00008000

Definition at line 375 of file tc-arm.c.

#define CP_T_Y   0x00400000

Definition at line 376 of file tc-arm.c.

#define CPSI_MMOD   0x00020000

Definition at line 552 of file tc-arm.c.

#define CVT_VAR (   C,
  X,
  Y 
)
Value:
et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y));       \
  if (et.type != NT_invtype)                                          \
    {                                                          \
      inst.error = NULL;                                       \
      return (C);                                              \
    }
#define DATA_OP_SHIFT   21

Definition at line 558 of file tc-arm.c.

#define do_0   0
#define DOUBLE_LOAD_FLAG   0x00000001

Definition at line 381 of file tc-arm.c.

#define FAIL   (-1)

Definition at line 367 of file tc-arm.c.

#define FPU_DEFAULT   FPU_ARCH_FPA

Definition at line 130 of file tc-arm.c.

#define GE_IMM_PREFIX   1

Definition at line 778 of file tc-arm.c.

#define GE_NO_PREFIX   0

Definition at line 777 of file tc-arm.c.

#define GE_OPT_PREFIX   2

Definition at line 779 of file tc-arm.c.

#define GE_OPT_PREFIX_BIG   3

Definition at line 782 of file tc-arm.c.

#define HI1 (   R)    (((R) >> 4) & 1)
#define HWOFFSET_IMM   0x00400000

Definition at line 546 of file tc-arm.c.

#define INDEX_UP   0x00800000

Definition at line 549 of file tc-arm.c.

#define INSN_SIZE   4

Definition at line 513 of file tc-arm.c.

#define INST_IMMEDIATE   0x02000000

Definition at line 544 of file tc-arm.c.

#define is_immediate_prefix (   C)    ((C) == '#' || (C) == '$')

Definition at line 735 of file tc-arm.c.

#define LDM_TYPE_2_OR_3   0x00400000

Definition at line 551 of file tc-arm.c.

#define LITERAL_MASK   0xf000f000

Definition at line 554 of file tc-arm.c.

#define LOAD_BIT   0x00100000

Definition at line 379 of file tc-arm.c.

#define LOW4 (   R)    ((R) & 0xf)
#define mapping_state (   x)    /* nothing */

Definition at line 2353 of file tc-arm.c.

#define MAX_LITERAL_POOL_SIZE   1024

Definition at line 686 of file tc-arm.c.

#define MAX_LITTLENUMS   6

Definition at line 363 of file tc-arm.c.

#define N_ALLMODS   (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
#define N_I_ALL   (N_I8 | N_I16 | N_I32 | N_I64)
#define N_IF_32   (N_I8 | N_I16 | N_I32 | N_F32)
#define N_IGNORE_TYPE   (N_KEY | N_EQK)
#define N_INV   -1u

Definition at line 10284 of file tc-arm.c.

#define N_SU_16_64   (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
#define N_SU_32   (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
#define N_SU_ALL   (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
#define N_SUF_32   (N_SU_32 | N_F32)
#define NCE (   mnem,
  op,
  nops,
  ops,
  enc 
)    NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
#define nCE (   mnem,
  op,
  nops,
  ops,
  enc 
)    nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
#define NCE_tag (   mnem,
  op,
  nops,
  ops,
  enc,
  tag 
)
Value:
{ #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT,             \
    THUMB_VARIANT, do_##enc, do_##enc }
#define nCE_tag (   mnem,
  op,
  nops,
  ops,
  enc,
  tag 
)
Value:
{ #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op,         \
    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
#define NCEF (   mnem,
  op,
  nops,
  ops,
  enc 
)    NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
#define nCEF (   mnem,
  op,
  nops,
  ops,
  enc 
)    nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
#define NEON_ALL_LANES   15

Definition at line 1233 of file tc-arm.c.

#define NEON_ENC_ARMREG (   X)    (neon_enc_tab[(X) & 0x0fffffff].integer)

Definition at line 10366 of file tc-arm.c.

#define NEON_ENC_DOUBLE (   X)    ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))

Definition at line 10376 of file tc-arm.c.

#define NEON_ENC_DUP (   X)    (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)

Definition at line 10373 of file tc-arm.c.

#define NEON_ENC_FLOAT (   X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)

Definition at line 10368 of file tc-arm.c.

#define NEON_ENC_IMMED (   X)    (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)

Definition at line 10370 of file tc-arm.c.

#define NEON_ENC_INTEGER (   X)    (neon_enc_tab[(X) & 0x0fffffff].integer)

Definition at line 10365 of file tc-arm.c.

#define NEON_ENC_INTERLV (   X)    (neon_enc_tab[(X) & 0x0fffffff].integer)

Definition at line 10371 of file tc-arm.c.

#define NEON_ENC_LANE (   X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)

Definition at line 10372 of file tc-arm.c.

#define NEON_ENC_POLY (   X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)

Definition at line 10367 of file tc-arm.c.

#define NEON_ENC_SCALAR (   X)    (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)

Definition at line 10369 of file tc-arm.c.

#define NEON_ENC_SINGLE (   X)    ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))

Definition at line 10374 of file tc-arm.c.

#define NEON_ENC_TAB

Definition at line 10294 of file tc-arm.c.

#define NEON_INTERLEAVE_LANES   14

Definition at line 1234 of file tc-arm.c.

#define NEON_LANE (   X)    ((X) & 0xf)

Definition at line 1766 of file tc-arm.c.

#define NEON_MAX_TYPE_ELS   4

Definition at line 296 of file tc-arm.c.

#define NEON_REG_STRIDE (   X)    ((((X) >> 4) & 1) + 1)

Definition at line 1767 of file tc-arm.c.

#define NEON_REGLIST_LENGTH (   X)    ((((X) >> 5) & 3) + 1)

Definition at line 1768 of file tc-arm.c.

#define NEON_SCALAR_INDEX (   X)    ((X) & 15)

Definition at line 1380 of file tc-arm.c.

#define NEON_SCALAR_REG (   X)    ((X) >> 4)

Definition at line 1379 of file tc-arm.c.

#define NEON_SHAPE_DEF

Definition at line 10397 of file tc-arm.c.

#define NO_RELOC   0

Definition at line 30 of file tc-arm.c.

#define NTA_HASINDEX   2

Definition at line 431 of file tc-arm.c.

#define NTA_HASTYPE   1

Definition at line 430 of file tc-arm.c.

#define NUF (   mnem,
  op,
  nops,
  ops,
  enc 
)
Value:
{ #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,            \
    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
#define nUF (   mnem,
  op,
  nops,
  ops,
  enc 
)
Value:
{ #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op,  \
    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
#define NUM_FLOAT_VALS   8

Definition at line 355 of file tc-arm.c.

#define OFFSET_REG   0x02000000

Definition at line 545 of file tc-arm.c.

#define OPCODE_ADC   5

Definition at line 569 of file tc-arm.c.

#define OPCODE_ADD   4

Definition at line 568 of file tc-arm.c.

#define OPCODE_AND   0

Definition at line 564 of file tc-arm.c.

#define OPCODE_BIC   14

Definition at line 578 of file tc-arm.c.

#define OPCODE_CMN   11

Definition at line 575 of file tc-arm.c.

#define OPCODE_CMP   10

Definition at line 574 of file tc-arm.c.

#define OPCODE_EOR   1

Definition at line 565 of file tc-arm.c.

#define OPCODE_MASK   0xfe1fffff

Definition at line 555 of file tc-arm.c.

#define OPCODE_MOV   13

Definition at line 577 of file tc-arm.c.

#define OPCODE_MVN   15

Definition at line 579 of file tc-arm.c.

#define OPCODE_ORR   12

Definition at line 576 of file tc-arm.c.

#define OPCODE_RSB   3

Definition at line 567 of file tc-arm.c.

#define OPCODE_RSC   7

Definition at line 571 of file tc-arm.c.

#define OPCODE_SBC   6

Definition at line 570 of file tc-arm.c.

#define OPCODE_SUB   2

Definition at line 566 of file tc-arm.c.

#define OPCODE_TEQ   9

Definition at line 573 of file tc-arm.c.

#define OPCODE_TST   8

Definition at line 572 of file tc-arm.c.

#define OPS0 ( )    { OP_stop, }
#define OPS1 (   a)    { OP_##a, }
#define OPS2 (   a,
  b 
)    { OP_##a,OP_##b, }
#define OPS3 (   a,
  b,
  c 
)    { OP_##a,OP_##b,OP_##c, }
#define OPS4 (   a,
  b,
  c,
  d 
)    { OP_##a,OP_##b,OP_##c,OP_##d, }
#define OPS5 (   a,
  b,
  c,
  d,
  e 
)    { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
#define OPS6 (   a,
  b,
  c,
  d,
  e,
  f 
)    { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
#define OPTION_EL   (OPTION_MD_BASE + 1)
#define po_char_or_fail (   chr)
Value:
do {          \
  if (skip_past_char (&str, chr) == FAIL) \
    goto bad_args;                        \
} while (0)
#define po_imm_or_fail (   min,
  max,
  popt 
)
Value:
do {                 \
  if (parse_immediate (&str, &val, min, max, popt) == FAIL)    \
    goto failure;                                       \
  inst.operands[i].imm = val;                                  \
} while (0)
#define po_misc_or_fail (   expr)
Value:
do {          \
  if (expr)                               \
    goto failure;                         \
} while (0)
Value:
do {   \
  result = expr;                          \
  if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
    backtrack_pos = 0;                           \
  if (result != PARSE_OPERAND_SUCCESS)           \
    goto failure;                         \
} while (0)
#define po_reg_or_fail (   regtype)
Value:
do {                        \
  val = arm_typed_reg_parse (&str, regtype, &rtype,            \
                          &inst.operands[i].vectype);   \
  if (val == FAIL)                                      \
    {                                                   \
      first_error (_(reg_expected_msgs[regtype]));             \
      goto failure;                                     \
    }                                                   \
  inst.operands[i].reg = val;                                  \
  inst.operands[i].isreg = 1;                                  \
  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);            \
  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);         \
  inst.operands[i].isvec = (rtype == REG_TYPE_VFS              \
                            || rtype == REG_TYPE_VFD           \
                            || rtype == REG_TYPE_NQ);          \
} while (0)
#define po_reg_or_goto (   regtype,
  label 
)
Value:
do {                 \
  val = arm_typed_reg_parse (&str, regtype, &rtype,            \
                             &inst.operands[i].vectype);       \
  if (val == FAIL)                                      \
    goto label;                                                \
                                                        \
  inst.operands[i].reg = val;                                  \
  inst.operands[i].isreg = 1;                                  \
  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);            \
  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);         \
  inst.operands[i].isvec = (rtype == REG_TYPE_VFS              \
                            || rtype == REG_TYPE_VFD           \
                            || rtype == REG_TYPE_NQ);          \
} while (0)
#define po_scalar_or_goto (   elsz,
  label 
)
Value:
do {                 \
  val = parse_scalar (&str, elsz, &inst.operands[i].vectype);  \
  if (val == FAIL)                                      \
    goto label;                                                \
  inst.operands[i].reg = val;                                  \
  inst.operands[i].isscalar = 1;                        \
} while (0)
#define PRE_INDEX   0x01000000

Definition at line 548 of file tc-arm.c.

#define PSR_c   (1 << 16)

Definition at line 407 of file tc-arm.c.

#define PSR_f   (1 << 19)

Definition at line 410 of file tc-arm.c.

#define PSR_s   (1 << 18)

Definition at line 409 of file tc-arm.c.

#define PSR_x   (1 << 17)

Definition at line 408 of file tc-arm.c.

#define REG_LR   14

Definition at line 508 of file tc-arm.c.

#define REG_PC   15

Definition at line 509 of file tc-arm.c.

#define REG_SP   13

Definition at line 507 of file tc-arm.c.

#define REGDEF (   s,
  n,
  t 
)    { #s, n, REG_TYPE_##t, TRUE, 0 }
#define REGNUM (   p,
  n,
  t 
)    REGDEF(p##n, n, t)
#define REGNUM2 (   p,
  n,
  t 
)    REGDEF(p##n, 2 * n, t)
#define REGSET (   p,
  t 
)
Value:
REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
  REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
  REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
  REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
#define REGSET2 (   p,
  t 
)
Value:
REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
  REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
  REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
  REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
#define REGSETH (   p,
  t 
)
Value:
REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
  REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
  REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
  REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
#define rotate_left (   v,
  n 
)    (v << n | v >> (32 - n))

Definition at line 6119 of file tc-arm.c.

#define S2 (   A,
  B 
)    NS_##A##B

Definition at line 10439 of file tc-arm.c.

#define S2 (   A,
  B 
)    { SE_##A, SE_##B }

Definition at line 10439 of file tc-arm.c.

#define S3 (   A,
  B,
  C 
)    NS_##A##B##C

Definition at line 10440 of file tc-arm.c.

#define S3 (   A,
  B,
  C 
)    { SE_##A, SE_##B, SE_##C }

Definition at line 10440 of file tc-arm.c.

#define S4 (   A,
  B,
  C,
  D 
)    NS_##A##B##C##D

Definition at line 10441 of file tc-arm.c.

#define S4 (   A,
  B,
  C,
  D 
)    { SE_##A, SE_##B, SE_##C, SE_##D }

Definition at line 10441 of file tc-arm.c.

#define SHIFT_BY_REG   0x00000010

Definition at line 547 of file tc-arm.c.

#define skip_past_comma (   str)    skip_past_char (str, ',')

Definition at line 752 of file tc-arm.c.

#define skip_whitespace (   str)    do { if (*(str) == ' ') ++(str); } while (0)

Definition at line 739 of file tc-arm.c.

#define SPSR_BIT   (1 << 22)

Definition at line 404 of file tc-arm.c.

#define streq (   a,
  b 
)    (strcmp (a, b) == 0)

Definition at line 134 of file tc-arm.c.

#define STUB_NAME   ".real_start_of"
#define SUCCESS   (0)

Definition at line 368 of file tc-arm.c.

#define SUFF_D   2

Definition at line 371 of file tc-arm.c.

#define SUFF_E   3

Definition at line 372 of file tc-arm.c.

#define SUFF_P   4

Definition at line 373 of file tc-arm.c.

#define SUFF_S   1

Definition at line 370 of file tc-arm.c.

#define T16_32_TAB

Definition at line 8265 of file tc-arm.c.

#define T2_DATA_OP_SHIFT   21

Definition at line 561 of file tc-arm.c.

#define T2_OPCODE_ADC   10

Definition at line 587 of file tc-arm.c.

#define T2_OPCODE_ADD   8

Definition at line 586 of file tc-arm.c.

#define T2_OPCODE_AND   0

Definition at line 581 of file tc-arm.c.

#define T2_OPCODE_BIC   1

Definition at line 582 of file tc-arm.c.

#define T2_OPCODE_EOR   4

Definition at line 585 of file tc-arm.c.

#define T2_OPCODE_MASK   0xfe1fffff

Definition at line 560 of file tc-arm.c.

#define T2_OPCODE_ORN   3

Definition at line 584 of file tc-arm.c.

#define T2_OPCODE_ORR   2

Definition at line 583 of file tc-arm.c.

#define T2_OPCODE_RSB   14

Definition at line 590 of file tc-arm.c.

#define T2_OPCODE_SBC   11

Definition at line 588 of file tc-arm.c.

#define T2_OPCODE_SUB   13

Definition at line 589 of file tc-arm.c.

#define T_OPCODE_ADD_HI   0x4400

Definition at line 600 of file tc-arm.c.

#define T_OPCODE_ADD_I3   0x1c00

Definition at line 607 of file tc-arm.c.

#define T_OPCODE_ADD_I8   0x3000

Definition at line 605 of file tc-arm.c.

#define T_OPCODE_ADD_PC   0xa000

Definition at line 604 of file tc-arm.c.

#define T_OPCODE_ADD_R3   0x1800

Definition at line 598 of file tc-arm.c.

#define T_OPCODE_ADD_SP   0xa800

Definition at line 603 of file tc-arm.c.

#define T_OPCODE_ADD_ST   0xb000

Definition at line 601 of file tc-arm.c.

#define T_OPCODE_ASR_I   0x1000

Definition at line 614 of file tc-arm.c.

#define T_OPCODE_ASR_R   0x4100

Definition at line 610 of file tc-arm.c.

#define T_OPCODE_BRANCH   0xe000

Definition at line 643 of file tc-arm.c.

#define T_OPCODE_CMN   0x42c0

Definition at line 594 of file tc-arm.c.

#define T_OPCODE_CMP_HR   0x4500

Definition at line 622 of file tc-arm.c.

#define T_OPCODE_CMP_I8   0x2800

Definition at line 619 of file tc-arm.c.

#define T_OPCODE_CMP_LR   0x4280

Definition at line 620 of file tc-arm.c.

#define T_OPCODE_LDR_IB   0x7800

Definition at line 631 of file tc-arm.c.

#define T_OPCODE_LDR_IH   0x8800

Definition at line 629 of file tc-arm.c.

#define T_OPCODE_LDR_IW   0x6800

Definition at line 627 of file tc-arm.c.

#define T_OPCODE_LDR_PC   0x4800

Definition at line 624 of file tc-arm.c.

#define T_OPCODE_LDR_RB   0x5c00

Definition at line 637 of file tc-arm.c.

#define T_OPCODE_LDR_RH   0x5a00

Definition at line 635 of file tc-arm.c.

#define T_OPCODE_LDR_RW   0x5800

Definition at line 633 of file tc-arm.c.

#define T_OPCODE_LDR_SP   0x9800

Definition at line 625 of file tc-arm.c.

#define T_OPCODE_LSL_I   0x0000

Definition at line 615 of file tc-arm.c.

#define T_OPCODE_LSL_R   0x4080

Definition at line 611 of file tc-arm.c.

#define T_OPCODE_LSR_I   0x0800

Definition at line 616 of file tc-arm.c.

#define T_OPCODE_LSR_R   0x40c0

Definition at line 612 of file tc-arm.c.

#define T_OPCODE_MOV_HR   0x4600

Definition at line 621 of file tc-arm.c.

#define T_OPCODE_MOV_I8   0x2000

Definition at line 618 of file tc-arm.c.

#define T_OPCODE_MUL   0x4340

Definition at line 592 of file tc-arm.c.

#define T_OPCODE_MVN   0x43c0

Definition at line 596 of file tc-arm.c.

#define T_OPCODE_NEG   0x4240

Definition at line 595 of file tc-arm.c.

#define T_OPCODE_POP   0xbc00

Definition at line 641 of file tc-arm.c.

#define T_OPCODE_PUSH   0xb400

Definition at line 640 of file tc-arm.c.

#define T_OPCODE_ROR_R   0x41c0

Definition at line 613 of file tc-arm.c.

#define T_OPCODE_STR_IB   0x7000

Definition at line 632 of file tc-arm.c.

#define T_OPCODE_STR_IH   0x8000

Definition at line 630 of file tc-arm.c.

#define T_OPCODE_STR_IW   0x6000

Definition at line 628 of file tc-arm.c.

#define T_OPCODE_STR_RB   0x5400

Definition at line 638 of file tc-arm.c.

#define T_OPCODE_STR_RH   0x5200

Definition at line 636 of file tc-arm.c.

#define T_OPCODE_STR_RW   0x5000

Definition at line 634 of file tc-arm.c.

#define T_OPCODE_STR_SP   0x9000

Definition at line 626 of file tc-arm.c.

#define T_OPCODE_SUB_I3   0x1e00

Definition at line 608 of file tc-arm.c.

#define T_OPCODE_SUB_I8   0x3800

Definition at line 606 of file tc-arm.c.

#define T_OPCODE_SUB_R3   0x1a00

Definition at line 599 of file tc-arm.c.

#define T_OPCODE_SUB_ST   0xb080

Definition at line 602 of file tc-arm.c.

#define T_OPCODE_TST   0x4200

Definition at line 593 of file tc-arm.c.

#define TC3 (   mnem,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
#define tC3 (   mnem,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
#define TC3w (   mnem,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
#define tC3w (   mnem,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
#define TCE (   mnem,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
#define tCE (   mnem,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
#define TCM (   m1,
  m2,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
#define tCM (   m1,
  m2,
  aop,
  top,
  nops,
  ops,
  ae,
  te 
)    TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
#define THUMB2_LOAD_BIT   0x00100000

Definition at line 648 of file tc-arm.c.

#define THUMB_LOAD_BIT   0x0800

Definition at line 647 of file tc-arm.c.

#define THUMB_OP16 (   n)    (thumb_op16[(n) - (T16_32_OFFSET + 1)])

Definition at line 8353 of file tc-arm.c.

#define THUMB_OP32 (   n)    (thumb_op32[(n) - (T16_32_OFFSET + 1)])

Definition at line 8358 of file tc-arm.c.

#define THUMB_PP_PC_LR   0x0100

Definition at line 646 of file tc-arm.c.

#define THUMB_SETS_FLAGS (   n)    (THUMB_OP32 (n) & 0x00100000)

Definition at line 8359 of file tc-arm.c.

#define THUMB_SIZE   2 /* Size of thumb instruction. */

Definition at line 645 of file tc-arm.c.

#define THUMB_VARIANT   &arm_ext_v4t
#define THUMB_VARIANT   &arm_ext_v6
#define THUMB_VARIANT   &arm_ext_v6t2
#define THUMB_VARIANT   &arm_ext_v4t
#define THUMB_VARIANT   &arm_ext_v6t2
#define THUMB_VARIANT   &arm_ext_v4t
#define THUMB_VARIANT   &arm_ext_v5t
#define THUMB_VARIANT   &arm_ext_v6t2
#define THUMB_VARIANT   &arm_ext_v6
#define THUMB_VARIANT   &arm_ext_v6t2
#define THUMB_VARIANT   &arm_ext_v6k
#define THUMB_VARIANT   &arm_ext_v6t2
#define THUMB_VARIANT   &arm_ext_div
#define THUMB_VARIANT   &arm_ext_v7
#define TUE (   mnem,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
{ #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
    THUMB_VARIANT, do_##ae, do_##te }
#define TUF (   mnem,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
{ #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
    THUMB_VARIANT, do_##ae, do_##te }
#define TxC3 (   mnem,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
{ #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
    THUMB_VARIANT, do_##ae, do_##te }
#define TxC3w (   mnem,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
{ #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
    THUMB_VARIANT, do_##ae, do_##te }
#define TxCE (   mnem,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
{ #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
    THUMB_VARIANT, do_##ae, do_##te }
#define TxCM (   m1,
  m2,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
TxCM_(m1,   , m2, op, top, nops, ops, ae, te),   \
  TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
  TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
#define TxCM_ (   m1,
  m2,
  m3,
  op,
  top,
  nops,
  ops,
  ae,
  te 
)
Value:
{ #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
    0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
#define UE (   mnem,
  op,
  nops,
  ops,
  ae 
)    { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
#define UF (   mnem,
  op,
  nops,
  ops,
  ae 
)    { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
#define UT (   mnem,
  op,
  nops,
  ops,
  te 
)    TUE(mnem, 0, op, nops, ops, 0, te)
#define V4_STR_BIT   0x00000020

Definition at line 556 of file tc-arm.c.

#define WARN_DEPRECATED   1

Definition at line 45 of file tc-arm.c.

#define WRITE_BACK   0x00200000

Definition at line 550 of file tc-arm.c.

#define X (   a,
  b,
  c 
)    T_MNEM_##a

Definition at line 10464 of file tc-arm.c.

#define X (   a,
  b,
  c 
)    0x##b

Definition at line 10464 of file tc-arm.c.

#define X (   a,
  b,
  c 
)    0x##c

Definition at line 10464 of file tc-arm.c.

#define X (   OPC,
  I,
  F,
  S 
)    N_MNEM_##OPC

Definition at line 10464 of file tc-arm.c.

#define X (   OPC,
  I,
  F,
  S 
)    { (I), (F), (S) }

Definition at line 10464 of file tc-arm.c.

#define X (   N,
  L,
  C 
)    S##N L

Definition at line 10464 of file tc-arm.c.

#define X (   N,
  L,
  C 
)    SC_##C

Definition at line 10464 of file tc-arm.c.

#define X (   N,
  L,
  C 
)    { N, S##N L }

Definition at line 10464 of file tc-arm.c.

#define xCM_ (   m1,
  m2,
  m3,
  op,
  nops,
  ops,
  ae 
)
Value:
{ #m1 #m2 #m3, OPS##nops ops, \
    sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }

Typedef Documentation


Enumeration Type Documentation

Enumerator:
ARM_FLOAT_ABI_HARD 
ARM_FLOAT_ABI_SOFTFP 
ARM_FLOAT_ABI_SOFT 

Definition at line 98 of file tc-arm.c.

Enumerator:
REG_TYPE_RN 
REG_TYPE_CP 
REG_TYPE_CN 
REG_TYPE_FN 
REG_TYPE_VFS 
REG_TYPE_VFD 
REG_TYPE_NQ 
REG_TYPE_VFSD 
REG_TYPE_NDQ 
REG_TYPE_NSDQ 
REG_TYPE_VFC 
REG_TYPE_MVF 
REG_TYPE_MVD 
REG_TYPE_MVFX 
REG_TYPE_MVDX 
REG_TYPE_MVAX 
REG_TYPE_DSPSC 
REG_TYPE_MMXWR 
REG_TYPE_MMXWC 
REG_TYPE_MMXWCG 
REG_TYPE_XSCALE 

Definition at line 442 of file tc-arm.c.

Enumerator:
GROUP_LDR 
GROUP_LDRS 
GROUP_LDC 

Definition at line 4442 of file tc-arm.c.

{
  /* Varieties of non-ALU group relocation.  */

  GROUP_LDR,
  GROUP_LDRS,
  GROUP_LDC
} group_reloc_type;
Enumerator:
NT_invtype 
NT_untyped 
NT_integer 
NT_float 
NT_poly 
NT_signed 
NT_unsigned 

Definition at line 279 of file tc-arm.c.

enum neon_opc
Enumerator:
NEON_ENC_TAB 

Definition at line 10351 of file tc-arm.c.

{
#define X(OPC,I,F,S) N_MNEM_##OPC
NEON_ENC_TAB
#undef X
enum neon_shape
Enumerator:
NEON_SHAPE_DEF 
NS_NULL 

Definition at line 10445 of file tc-arm.c.

Enumerator:
SC_SINGLE 
SC_DOUBLE 
SC_QUAD 
SC_MIXED 

Definition at line 10456 of file tc-arm.c.

Enumerator:
OP_stop 
OP_RR 
OP_RRnpc 
OP_RRnpcb 
OP_RRw 
OP_RCP 
OP_RCN 
OP_RF 
OP_RVS 
OP_RVD 
OP_RND 
OP_RNQ 
OP_RVSD 
OP_RNDQ 
OP_RNSDQ 
OP_RNSC 
OP_RVC 
OP_RMF 
OP_RMD 
OP_RMFX 
OP_RMDX 
OP_RMAX 
OP_RMDS 
OP_RIWR 
OP_RIWC 
OP_RIWG 
OP_RXA 
OP_REGLST 
OP_VRSLST 
OP_VRDLST 
OP_VRSDLST 
OP_NRDLST 
OP_NSTRLST 
OP_NILO 
OP_RNDQ_I0 
OP_RVSD_I0 
OP_RR_RNSC 
OP_RNSDQ_RNSC 
OP_RNDQ_RNSC 
OP_RND_RNSC 
OP_VMOV 
OP_RNDQ_IMVNb 
OP_RNDQ_I63b 
OP_RIWR_I32z 
OP_I0 
OP_I7 
OP_I15 
OP_I16 
OP_I16z 
OP_I31 
OP_I31w 
OP_I32 
OP_I32z 
OP_I63 
OP_I63s 
OP_I64 
OP_I64z 
OP_I255 
OP_I4b 
OP_I7b 
OP_I15b 
OP_I31b 
OP_SH 
OP_SHG 
OP_ADDR 
OP_ADDRGLDR 
OP_ADDRGLDRS 
OP_ADDRGLDC 
OP_EXP 
OP_EXPi 
OP_EXPr 
OP_HALF 
OP_CPSF 
OP_ENDI 
OP_PSR 
OP_COND 
OP_TB 
OP_RVC_PSR 
OP_APSR_RR 
OP_RRnpc_I0 
OP_RR_EXr 
OP_RR_EXi 
OP_RF_IF 
OP_RIWR_RIWC 
OP_RIWC_RIWG 
OP_oI7b 
OP_oI31b 
OP_oI32b 
OP_oIffffb 
OP_oI255c 
OP_oRR 
OP_oRRnpc 
OP_oRRw 
OP_oRND 
OP_oRNQ 
OP_oRNDQ 
OP_oRNSDQ 
OP_oSHll 
OP_oSHar 
OP_oSHllar 
OP_oROR 
OP_oBARRIER 
OP_FIRST_OPTIONAL 

Definition at line 5375 of file tc-arm.c.

{
  OP_stop,    /* end of line */

  OP_RR,      /* ARM register */
  OP_RRnpc,   /* ARM register, not r15 */
  OP_RRnpcb,  /* ARM register, not r15, in square brackets */
  OP_RRw,     /* ARM register, not r15, optional trailing ! */
  OP_RCP,     /* Coprocessor number */
  OP_RCN,     /* Coprocessor register */
  OP_RF,      /* FPA register */
  OP_RVS,     /* VFP single precision register */
  OP_RVD,     /* VFP double precision register (0..15) */
  OP_RND,       /* Neon double precision register (0..31) */
  OP_RNQ,     /* Neon quad precision register */
  OP_RVSD,    /* VFP single or double precision register */
  OP_RNDQ,      /* Neon double or quad precision register */
  OP_RNSDQ,   /* Neon single, double or quad precision register */
  OP_RNSC,      /* Neon scalar D[X] */
  OP_RVC,     /* VFP control register */
  OP_RMF,     /* Maverick F register */
  OP_RMD,     /* Maverick D register */
  OP_RMFX,    /* Maverick FX register */
  OP_RMDX,    /* Maverick DX register */
  OP_RMAX,    /* Maverick AX register */
  OP_RMDS,    /* Maverick DSPSC register */
  OP_RIWR,    /* iWMMXt wR register */
  OP_RIWC,    /* iWMMXt wC register */
  OP_RIWG,    /* iWMMXt wCG register */
  OP_RXA,     /* XScale accumulator register */

  OP_REGLST,  /* ARM register list */
  OP_VRSLST,  /* VFP single-precision register list */
  OP_VRDLST,  /* VFP double-precision register list */
  OP_VRSDLST,   /* VFP single or double-precision register list (& quad) */
  OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
  OP_NSTRLST,   /* Neon element/structure list */

  OP_NILO,      /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...)  */
  OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
  OP_RVSD_I0, /* VFP S or D reg, or immediate zero.  */
  OP_RR_RNSC,   /* ARM reg or Neon scalar.  */
  OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar.  */
  OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar.  */
  OP_RND_RNSC,  /* Neon D reg, or Neon scalar.  */
  OP_VMOV,      /* Neon VMOV operands.  */
  OP_RNDQ_IMVNb,/* Neon D or Q reg, or immediate good for VMVN.  */
  OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
  OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */

  OP_I0,        /* immediate zero */
  OP_I7,      /* immediate value 0 .. 7 */
  OP_I15,     /*               0 .. 15 */
  OP_I16,     /*               1 .. 16 */
  OP_I16z,      /*                 0 .. 16 */
  OP_I31,     /*               0 .. 31 */
  OP_I31w,    /*               0 .. 31, optional trailing ! */
  OP_I32,     /*               1 .. 32 */
  OP_I32z,    /*               0 .. 32 */
  OP_I63,     /*               0 .. 63 */
  OP_I63s,    /*             -64 .. 63 */
  OP_I64,     /*               1 .. 64 */
  OP_I64z,    /*               0 .. 64 */
  OP_I255,    /*               0 .. 255 */

  OP_I4b,     /* immediate, prefix optional, 1 .. 4 */
  OP_I7b,     /*                          0 .. 7 */
  OP_I15b,    /*                          0 .. 15 */
  OP_I31b,    /*                          0 .. 31 */

  OP_SH,      /* shifter operand */
  OP_SHG,     /* shifter operand with possible group relocation */
  OP_ADDR,    /* Memory address expression (any mode) */
  OP_ADDRGLDR,       /* Mem addr expr (any mode) with possible LDR group reloc */
  OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
  OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
  OP_EXP,     /* arbitrary expression */
  OP_EXPi,    /* same, with optional immediate prefix */
  OP_EXPr,    /* same, with optional relocation suffix */
  OP_HALF,    /* 0 .. 65535 or low/high reloc.  */

  OP_CPSF,    /* CPS flags */
  OP_ENDI,    /* Endianness specifier */
  OP_PSR,     /* CPSR/SPSR mask for msr */
  OP_COND,    /* conditional code */
  OP_TB,      /* Table branch.  */

  OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register.  */
  OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */

  OP_RRnpc_I0,       /* ARM register or literal 0 */
  OP_RR_EXr,  /* ARM register or expression with opt. reloc suff. */
  OP_RR_EXi,  /* ARM register or expression with imm prefix */
  OP_RF_IF,   /* FPA register or immediate */
  OP_RIWR_RIWC, /* iWMMXt R or C reg */
  OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */

  /* Optional operands.      */
  OP_oI7b,     /* immediate, prefix optional, 0 .. 7 */
  OP_oI31b,    /*                         0 .. 31 */
  OP_oI32b,      /*                             1 .. 32 */
  OP_oIffffb,  /*                         0 .. 65535 */
  OP_oI255c,   /*      curly-brace enclosed, 0 .. 255 */

  OP_oRR,      /* ARM register */
  OP_oRRnpc,   /* ARM register, not the PC */
  OP_oRRw,     /* ARM register, not r15, optional trailing ! */
  OP_oRND,       /* Optional Neon double precision register */
  OP_oRNQ,       /* Optional Neon quad precision register */
  OP_oRNDQ,      /* Optional Neon double or quad precision register */
  OP_oRNSDQ,   /* Optional single, double or quad precision vector register */
  OP_oSHll,    /* LSL immediate */
  OP_oSHar,    /* ASR immediate */
  OP_oSHllar,  /* LSL or ASR immediate */
  OP_oROR,     /* ROR 0/8/16/24 */
  OP_oBARRIER,        /* Option argument for a barrier instruction.  */

  OP_FIRST_OPTIONAL = OP_oI7b
};
Enumerator:
PARSE_OPERAND_SUCCESS 
PARSE_OPERAND_FAIL 
PARSE_OPERAND_FAIL_NO_BACKTRACK 

Definition at line 91 of file tc-arm.c.

Enumerator:
NO_SHIFT_RESTRICT 
SHIFT_IMMEDIATE 
SHIFT_LSL_OR_ASR_IMMEDIATE 
SHIFT_ASR_IMMEDIATE 
SHIFT_LSL_IMMEDIATE 

Definition at line 4256 of file tc-arm.c.

{
  NO_SHIFT_RESTRICT,        /* Any kind of shift is accepted.  */
  SHIFT_IMMEDIATE,          /* Shift operand must be an immediate.    */
  SHIFT_LSL_OR_ASR_IMMEDIATE,      /* Shift must be LSL or ASR immediate.    */
  SHIFT_ASR_IMMEDIATE,             /* Shift must be ASR immediate.     */
  SHIFT_LSL_IMMEDIATE,             /* Shift must be LSL immediate.     */
};
Enumerator:
REGLIST_VFP_S 
REGLIST_VFP_D 
REGLIST_NEON_D 

Definition at line 1544 of file tc-arm.c.

enum shift_kind
Enumerator:
SHIFT_LSL 
SHIFT_LSR 
SHIFT_ASR 
SHIFT_ROR 
SHIFT_RRX 

Definition at line 4244 of file tc-arm.c.

Enumerator:
T16_32_OFFSET 
T16_32_TAB 

Definition at line 8348 of file tc-arm.c.

{ T16_32_OFFSET = 0xF7FF, T16_32_TAB };
Enumerator:
VFP_LDSTMIA 
VFP_LDSTMDB 
VFP_LDSTMIAX 
VFP_LDSTMDBX 

Definition at line 424 of file tc-arm.c.

Enumerator:
VFP_REG_Sd 
VFP_REG_Sm 
VFP_REG_Sn 
VFP_REG_Dd 
VFP_REG_Dm 
VFP_REG_Dn 

Definition at line 418 of file tc-arm.c.


Function Documentation

static int add_to_lit_pool ( void  ) [static]

Definition at line 2726 of file tc-arm.c.

{
  literal_pool * pool;
  unsigned int entry;

  pool = find_or_make_literal_pool ();

  /* Check if this literal value is already in the pool.  */
  for (entry = 0; entry < pool->next_free_entry; entry ++)
    {
      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
         && (inst.reloc.exp.X_op == O_constant)
         && (pool->literals[entry].X_add_number
             == inst.reloc.exp.X_add_number)
         && (pool->literals[entry].X_unsigned
             == inst.reloc.exp.X_unsigned))
       break;

      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
         && (inst.reloc.exp.X_op == O_symbol)
         && (pool->literals[entry].X_add_number
             == inst.reloc.exp.X_add_number)
         && (pool->literals[entry].X_add_symbol
             == inst.reloc.exp.X_add_symbol)
         && (pool->literals[entry].X_op_symbol
             == inst.reloc.exp.X_op_symbol))
       break;
    }

  /* Do we need to create a new entry?    */
  if (entry == pool->next_free_entry)
    {
      if (entry >= MAX_LITERAL_POOL_SIZE)
       {
         inst.error = _("literal pool overflow");
         return FAIL;
       }

      pool->literals[entry] = inst.reloc.exp;
      pool->next_free_entry += 1;
    }

  inst.reloc.exp.X_op             = O_symbol;
  inst.reloc.exp.X_add_number = ((int) entry) * 4;
  inst.reloc.exp.X_add_symbol = pool->symbol;

  return SUCCESS;
}

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static int arm_reg_alt_syntax ( char **  ccp,
char *  start,
struct reg_entry reg,
enum arm_reg_type  type 
) [static]

Definition at line 1035 of file tc-arm.c.

{
  /* Alternative syntaxes are accepted for a few register classes.  */
  switch (type)
    {
    case REG_TYPE_MVF:
    case REG_TYPE_MVD:
    case REG_TYPE_MVFX:
    case REG_TYPE_MVDX:
      /* Generic coprocessor register names are allowed for these.  */
      if (reg && reg->type == REG_TYPE_CN)
       return reg->number;
      break;

    case REG_TYPE_CP:
      /* For backward compatibility, a bare number is valid here.  */
      {
       unsigned long processor = strtoul (start, ccp, 10);
       if (*ccp != start && processor <= 15)
         return processor;
      }

    case REG_TYPE_MMXWC:
      /* WC includes WCG.  ??? I'm not sure this is true for all
        instructions that take WC registers.  */
      if (reg && reg->type == REG_TYPE_MMXWCG)
       return reg->number;
      break;

    default:
      break;
    }

  return FAIL;
}

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static int arm_reg_parse ( char **  ccp,
enum arm_reg_type  type 
) [static]

Definition at line 1076 of file tc-arm.c.

{
  char *start = *ccp;
  struct reg_entry *reg = arm_reg_parse_multi (ccp);
  int ret;

  /* Do not allow a scalar (reg+index) to parse as a register.  */
  if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
    return FAIL;

  if (reg && reg->type == type)
    return reg->number;

  if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
    return ret;

  *ccp = start;
  return FAIL;
}

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static struct reg_entry* arm_reg_parse_multi ( char **  ccp) [static, read]

Definition at line 1001 of file tc-arm.c.

{
  char *start = *ccp;
  char *p;
  struct reg_entry *reg;

#ifdef REGISTER_PREFIX
  if (*start != REGISTER_PREFIX)
    return NULL;
  start++;
#endif
#ifdef OPTIONAL_REGISTER_PREFIX
  if (*start == OPTIONAL_REGISTER_PREFIX)
    start++;
#endif

  p = start;
  if (!ISALPHA (*p) || !is_name_beginner (*p))
    return NULL;

  do
    p++;
  while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');

  reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);

  if (!reg)
    return NULL;

  *ccp = p;
  return reg;
}

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static int arm_typed_reg_parse ( char **  ccp,
enum arm_reg_type  type,
enum arm_reg_type rtype,
struct neon_type_el vectype 
) [static]

Definition at line 1354 of file tc-arm.c.

{
  struct neon_typed_alias atype;
  char *str = *ccp;
  int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);

  if (reg == FAIL)
    return FAIL;

  /* Do not allow a scalar (reg+index) to parse as a register.  */
  if ((atype.defined & NTA_HASINDEX) != 0)
    {
      first_error (_("register operand expected, but got scalar"));
      return FAIL;
    }

  if (vectype)
    *vectype = atype.eltype;

  *ccp = str;

  return reg;
}

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static int create_neon_reg_alias ( char *  newname,
char *  p 
) [static]

Definition at line 2086 of file tc-arm.c.

{
  enum arm_reg_type basetype;
  struct reg_entry *basereg;
  struct reg_entry mybasereg;
  struct neon_type ntype;
  struct neon_typed_alias typeinfo;
  char *namebuf, *nameend;
  int namelen;
  
  typeinfo.defined = 0;
  typeinfo.eltype.type = NT_invtype;
  typeinfo.eltype.size = -1;
  typeinfo.index = -1;
  
  nameend = p;
  
  if (strncmp (p, " .dn ", 5) == 0)
    basetype = REG_TYPE_VFD;
  else if (strncmp (p, " .qn ", 5) == 0)
    basetype = REG_TYPE_NQ;
  else
    return 0;
  
  p += 5;
  
  if (*p == '\0')
    return 0;
  
  basereg = arm_reg_parse_multi (&p);

  if (basereg && basereg->type != basetype)
    {
      as_bad (_("bad type for register"));
      return 0;
    }

  if (basereg == NULL)
    {
      expressionS exp;
      /* Try parsing as an integer.  */
      my_get_expression (&exp, &p, GE_NO_PREFIX);
      if (exp.X_op != O_constant)
        {
          as_bad (_("expression must be constant"));
          return 0;
        }
      basereg = &mybasereg;
      basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
                                                  : exp.X_add_number;
      basereg->neon = 0;
    }

  if (basereg->neon)
    typeinfo = *basereg->neon;

  if (parse_neon_type (&ntype, &p) == SUCCESS)
    {
      /* We got a type.  */
      if (typeinfo.defined & NTA_HASTYPE)
        {
          as_bad (_("can't redefine the type of a register alias"));
          return 0;
        }
      
      typeinfo.defined |= NTA_HASTYPE;
      if (ntype.elems != 1)
        {
          as_bad (_("you must specify a single type only"));
          return 0;
        }
      typeinfo.eltype = ntype.el[0];
    }
  
  if (skip_past_char (&p, '[') == SUCCESS)
    {
      expressionS exp;
      /* We got a scalar index.  */
    
      if (typeinfo.defined & NTA_HASINDEX)
        {
          as_bad (_("can't redefine the index of a scalar alias"));
          return 0;
        }
    
      my_get_expression (&exp, &p, GE_NO_PREFIX);
    
      if (exp.X_op != O_constant)
        {
          as_bad (_("scalar index must be constant"));
          return 0;
        }
      
      typeinfo.defined |= NTA_HASINDEX;
      typeinfo.index = exp.X_add_number;
    
      if (skip_past_char (&p, ']') == FAIL)
        {
          as_bad (_("expecting ]"));
          return 0;
        }
    }

  namelen = nameend - newname;
  namebuf = alloca (namelen + 1);
  strncpy (namebuf, newname, namelen);
  namebuf[namelen] = '\0';
  
  insert_neon_reg_alias (namebuf, basereg->number, basetype,
                         typeinfo.defined != 0 ? &typeinfo : NULL);
    
  /* Insert name in all uppercase.  */
  for (p = namebuf; *p; p++)
    *p = TOUPPER (*p);
  
  if (strncmp (namebuf, newname, namelen))
    insert_neon_reg_alias (namebuf, basereg->number, basetype,
                           typeinfo.defined != 0 ? &typeinfo : NULL);
  
  /* Insert name in all lowercase.  */
  for (p = namebuf; *p; p++)
    *p = TOLOWER (*p);
  
  if (strncmp (namebuf, newname, namelen))
    insert_neon_reg_alias (namebuf, basereg->number, basetype,
                           typeinfo.defined != 0 ? &typeinfo : NULL);
  
  return 1;
}

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static int create_register_alias ( char *  newname,
char *  p 
) [static]

Definition at line 2017 of file tc-arm.c.

{
  struct reg_entry *old;
  char *oldname, *nbuf;
  size_t nlen;

  /* The input scrubber ensures that whitespace after the mnemonic is
     collapsed to single spaces.  */
  oldname = p;
  if (strncmp (oldname, " .req ", 6) != 0)
    return 0;

  oldname += 6;
  if (*oldname == '\0')
    return 0;

  old = hash_find (arm_reg_hsh, oldname);
  if (!old)
    {
      as_warn (_("unknown register '%s' -- .req ignored"), oldname);
      return 1;
    }

  /* If TC_CASE_SENSITIVE is defined, then newname already points to
     the desired alias name, and p points to its end.  If not, then
     the desired alias name is in the global original_case_string.  */
#ifdef TC_CASE_SENSITIVE
  nlen = p - newname;
#else
  newname = original_case_string;
  nlen = strlen (newname);
#endif

  nbuf = alloca (nlen + 1);
  memcpy (nbuf, newname, nlen);
  nbuf[nlen] = '\0';

  /* Create aliases under the new name as stated; an all-lowercase
     version of the new name; and an all-uppercase version of the new
     name.  */
  insert_reg_alias (nbuf, old->number, old->type);

  for (p = nbuf; *p; p++)
    *p = TOUPPER (*p);

  if (strncmp (nbuf, newname, nlen))
    insert_reg_alias (nbuf, old->number, old->type);

  for (p = nbuf; *p; p++)
    *p = TOLOWER (*p);

  if (strncmp (nbuf, newname, nlen))
    insert_reg_alias (nbuf, old->number, old->type);

  return 1;
}

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static void do_adr ( void  ) [static]

Definition at line 6583 of file tc-arm.c.

{
  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */

  /* Frag hacking will turn this into a sub instruction if the offset turns
     out to be negative.  */
  inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
  inst.reloc.pc_rel = 1;
  inst.reloc.exp.X_add_number -= 8;
}
static void do_adrl ( void  ) [static]

Definition at line 6600 of file tc-arm.c.

{
  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */

  /* Frag hacking will turn this into a sub instruction if the offset turns
     out to be negative.  */
  inst.reloc.type           = BFD_RELOC_ARM_ADRL_IMMEDIATE;
  inst.reloc.pc_rel         = 1;
  inst.size                 = INSN_SIZE * 2;
  inst.reloc.exp.X_add_number -= 8;
}
static void do_arit ( void  ) [static]

Definition at line 6613 of file tc-arm.c.

{
  if (!inst.operands[1].present)
    inst.operands[1].reg = inst.operands[0].reg;
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  encode_arm_shifter_operand (2);
}

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static void do_barrier ( void  ) [static]

Definition at line 6623 of file tc-arm.c.

{
  if (inst.operands[0].present)
    {
      constraint ((inst.instruction & 0xf0) != 0x40
                && inst.operands[0].imm != 0xf,
                "bad barrier type");
      inst.instruction |= inst.operands[0].imm;
    }
  else
    inst.instruction |= 0xf;
}
static void do_bfc ( void  ) [static]

Definition at line 6637 of file tc-arm.c.

{
  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
  constraint (msb > 32, _("bit-field extends past end of register"));
  /* The instruction encoding stores the LSB and MSB,
     not the LSB and width.  */
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].imm << 7;
  inst.instruction |= (msb - 1) << 16;
}
static void do_bfi ( void  ) [static]

Definition at line 6649 of file tc-arm.c.

{
  unsigned int msb;

  /* #0 in second position is alternative syntax for bfc, which is
     the same instruction but with REG_PC in the Rm field.  */
  if (!inst.operands[1].isreg)
    inst.operands[1].reg = REG_PC;

  msb = inst.operands[2].imm + inst.operands[3].imm;
  constraint (msb > 32, _("bit-field extends past end of register"));
  /* The instruction encoding stores the LSB and MSB,
     not the LSB and width.  */
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].imm << 7;
  inst.instruction |= (msb - 1) << 16;
}
static void do_bfx ( void  ) [static]

Definition at line 6669 of file tc-arm.c.

{
  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
             _("bit-field extends past end of register"));
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].imm << 7;
  inst.instruction |= (inst.operands[3].imm - 1) << 16;
}
static void do_bkpt ( void  ) [static]

Definition at line 6686 of file tc-arm.c.

{
  /* Top 12 of 16 bits to bits 19:8.  */
  inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;

  /* Bottom 4 of 16 bits to bits 3:0.  */
  inst.instruction |= inst.operands[0].imm & 0xf;
}
static void do_bl ( void  ) [static]

Definition at line 6723 of file tc-arm.c.

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static void do_blx ( void  ) [static]

Definition at line 6747 of file tc-arm.c.

{
  if (inst.operands[0].isreg)
    {
      /* Arg is a register; the opcode provided by insns[] is correct.
        It is not illegal to do "blx pc", just useless.  */
      if (inst.operands[0].reg == REG_PC)
       as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));

      inst.instruction |= inst.operands[0].reg;
    }
  else
    {
      /* Arg is an address; this instruction cannot be executed
        conditionally, and the opcode must be adjusted.  */
      constraint (inst.cond != COND_ALWAYS, BAD_COND);
      inst.instruction = 0xfa000000;
#ifdef OBJ_ELF
      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
       encode_branch (BFD_RELOC_ARM_PCREL_CALL);
      else
#endif
       encode_branch (BFD_RELOC_ARM_PCREL_BLX);
    }
}

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static void do_branch ( void  ) [static]

Definition at line 6712 of file tc-arm.c.

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static void do_bx ( void  ) [static]

Definition at line 6774 of file tc-arm.c.

{
  if (inst.operands[0].reg == REG_PC)
    as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));

  inst.instruction |= inst.operands[0].reg;
}

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static void do_bxj ( void  ) [static]

Definition at line 6786 of file tc-arm.c.

{
  if (inst.operands[0].reg == REG_PC)
    as_tsktsk (_("use of r15 in bxj is not really useful"));

  inst.instruction |= inst.operands[0].reg;
}

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static void do_cdp ( void  ) [static]

Definition at line 6798 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].imm << 20;
  inst.instruction |= inst.operands[2].reg << 12;
  inst.instruction |= inst.operands[3].reg << 16;
  inst.instruction |= inst.operands[4].reg;
  inst.instruction |= inst.operands[5].imm << 5;
}
static void do_cmp ( void  ) [static]

Definition at line 6809 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  encode_arm_shifter_operand (1);
}

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static void do_co_reg ( void  ) [static]

Definition at line 6824 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].imm << 21;
  inst.instruction |= inst.operands[2].reg << 12;
  inst.instruction |= inst.operands[3].reg << 16;
  inst.instruction |= inst.operands[4].reg;
  inst.instruction |= inst.operands[5].imm << 5;
}
static void do_co_reg2c ( void  ) [static]

Definition at line 6848 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].imm << 4;
  inst.instruction |= inst.operands[2].reg << 12;
  inst.instruction |= inst.operands[3].reg << 16;
  inst.instruction |= inst.operands[4].reg;
}
static void do_cpsi ( void  ) [static]

Definition at line 6858 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].imm << 6;
  if (inst.operands[1].present)
    {
      inst.instruction |= CPSI_MMOD;
      inst.instruction |= inst.operands[1].imm;
    }
}
static void do_dbg ( void  ) [static]

Definition at line 6869 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].imm;
}
static void do_fpa_cmp ( void  ) [static]

Definition at line 7826 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg;
}
static void do_fpa_ldmstm ( void  ) [static]

Definition at line 7833 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  switch (inst.operands[1].imm)
    {
    case 1: inst.instruction |= CP_T_X;           break;
    case 2: inst.instruction |= CP_T_Y;           break;
    case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
    case 4:                                break;
    default: abort ();
    }

  if (inst.instruction & (PRE_INDEX | INDEX_UP))
    {
      /* The instruction specified "ea" or "fd", so we can only accept
        [Rn]{!}.  The instruction does not really support stacking or
        unstacking, so we have to emulate these by setting appropriate
        bits and offsets.  */
      constraint (inst.reloc.exp.X_op != O_constant
                || inst.reloc.exp.X_add_number != 0,
                _("this instruction does not support indexing"));

      if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
       inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;

      if (!(inst.instruction & INDEX_UP))
       inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;

      if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
       {
         inst.operands[2].preind = 0;
         inst.operands[2].postind = 1;
       }
    }

  encode_arm_cp_address (2, TRUE, TRUE, 0);
}

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static void do_imm0 ( void  ) [static]

Definition at line 6563 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].imm;
}
static void do_it ( void  ) [static]

Definition at line 6875 of file tc-arm.c.

{
  /* There is no IT instruction in ARM mode.  We
     process it but do not generate code for it.  */
  inst.size = 0;
}
static void do_iwmmxt_tandorc ( void  ) [static]

Definition at line 7875 of file tc-arm.c.

{
  constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
}
static void do_iwmmxt_textrc ( void  ) [static]

Definition at line 7881 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].imm;
}
static void do_iwmmxt_textrm ( void  ) [static]

Definition at line 7888 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].imm;
}
static void do_iwmmxt_tinsr ( void  ) [static]

Definition at line 7896 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg << 12;
  inst.instruction |= inst.operands[2].imm;
}
static void do_iwmmxt_tmia ( void  ) [static]

Definition at line 7904 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 5;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 12;
}
static void do_iwmmxt_waligni ( void  ) [static]

Definition at line 7912 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
  inst.instruction |= inst.operands[3].imm << 20;
}
static void do_iwmmxt_wldstbh ( void  ) [static]

Definition at line 7939 of file tc-arm.c.

{
  int reloc;
  inst.instruction |= inst.operands[0].reg << 12;
  if (thumb_mode)
    reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
  else
    reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
  encode_arm_cp_address (1, TRUE, FALSE, reloc);
}

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static void do_iwmmxt_wldstd ( void  ) [static]

Definition at line 7965 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
      && inst.operands[1].immisreg)
    {
      inst.instruction &= ~0x1a000ff;
      inst.instruction |= (0xf << 28);
      if (inst.operands[1].preind)
       inst.instruction |= PRE_INDEX;
      if (!inst.operands[1].negative)
       inst.instruction |= INDEX_UP;
      if (inst.operands[1].writeback)
       inst.instruction |= WRITE_BACK;
      inst.instruction |= inst.operands[1].reg << 16;
      inst.instruction |= inst.reloc.exp.X_add_number << 4;
      inst.instruction |= inst.operands[1].imm;
    }
  else
    encode_arm_cp_address (1, TRUE, FALSE, 0);
}

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static void do_iwmmxt_wldstw ( void  ) [static]

Definition at line 7951 of file tc-arm.c.

{
  /* RIWR_RIWC clears .isreg for a control register.  */
  if (!inst.operands[0].isreg)
    {
      constraint (inst.cond != COND_ALWAYS, BAD_COND);
      inst.instruction |= 0xf0000000;
    }

  inst.instruction |= inst.operands[0].reg << 12;
  encode_arm_cp_address (1, TRUE, TRUE, 0);
}

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static void do_iwmmxt_wmerge ( void  ) [static]

Definition at line 7921 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
  inst.instruction |= inst.operands[3].imm << 21;
}
static void do_iwmmxt_wmov ( void  ) [static]

Definition at line 7930 of file tc-arm.c.

{
  /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[1].reg;
}
static void do_iwmmxt_wrwrwr_or_imm5 ( void  ) [static]

Definition at line 8006 of file tc-arm.c.

{
  if (inst.operands[2].isreg)
    do_rd_rn_rm ();
  else {
    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
              _("immediate operand requires iWMMXt2"));
    do_rd_rn ();
    if (inst.operands[2].imm == 0)
      {
       switch ((inst.instruction >> 20) & 0xf)
         {
         case 4:
         case 5:
         case 6:
         case 7: 
           /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16.  */
           inst.operands[2].imm = 16;
           inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
           break;
         case 8:
         case 9:
         case 10:
         case 11:
           /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32.  */
           inst.operands[2].imm = 32;
           inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
           break;
         case 12:
         case 13:
         case 14:
         case 15:
           {
             /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn.  */
             unsigned long wrn;
             wrn = (inst.instruction >> 16) & 0xf;
             inst.instruction &= 0xff0fff0f;
             inst.instruction |= wrn;
             /* Bail out here; the instruction is now assembled.  */
             return;
           }
         }
      }
    /* Map 32 -> 0, etc.  */
    inst.operands[2].imm &= 0x1f;
    inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
  }
}

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static void do_iwmmxt_wshufh ( void  ) [static]

Definition at line 7988 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
  inst.instruction |= (inst.operands[2].imm & 0x0f);
}
static void do_iwmmxt_wzero ( void  ) [static]

Definition at line 7997 of file tc-arm.c.

{
  /* WZERO reg is an alias for WANDN reg, reg, reg.  */
  inst.instruction |= inst.operands[0].reg;
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[0].reg << 16;
}
static void do_ldmstm ( void  ) [static]

Definition at line 6883 of file tc-arm.c.

{
  int base_reg = inst.operands[0].reg;
  int range = inst.operands[1].imm;

  inst.instruction |= base_reg << 16;
  inst.instruction |= range;

  if (inst.operands[1].writeback)
    inst.instruction |= LDM_TYPE_2_OR_3;

  if (inst.operands[0].writeback)
    {
      inst.instruction |= WRITE_BACK;
      /* Check for unpredictable uses of writeback.  */
      if (inst.instruction & LOAD_BIT)
       {
         /* Not allowed in LDM type 2.     */
         if ((inst.instruction & LDM_TYPE_2_OR_3)
             && ((range & (1 << REG_PC)) == 0))
           as_warn (_("writeback of base register is UNPREDICTABLE"));
         /* Only allowed if base reg not in list for other types.  */
         else if (range & (1 << base_reg))
           as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
       }
      else /* STM.  */
       {
         /* Not allowed for type 2.  */
         if (inst.instruction & LDM_TYPE_2_OR_3)
           as_warn (_("writeback of base register is UNPREDICTABLE"));
         /* Only allowed if base reg not in list, or first in list.  */
         else if ((range & (1 << base_reg))
                 && (range & ((1 << base_reg) - 1)))
           as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
       }
    }
}

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static void do_ldrd ( void  ) [static]

Definition at line 6928 of file tc-arm.c.

{
  constraint (inst.operands[0].reg % 2 != 0,
             _("first destination register must be even"));
  constraint (inst.operands[1].present
             && inst.operands[1].reg != inst.operands[0].reg + 1,
             _("can only load two consecutive registers"));
  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
  constraint (!inst.operands[2].isreg, _("'[' expected"));

  if (!inst.operands[1].present)
    inst.operands[1].reg = inst.operands[0].reg + 1;
  
  if (inst.instruction & LOAD_BIT)
    {
      /* encode_arm_addr_mode_3 will diagnose overlap between the base
        register and the first register written; we have to diagnose
        overlap between the base and the second register written here.        */

      if (inst.operands[2].reg == inst.operands[1].reg
         && (inst.operands[2].writeback || inst.operands[2].postind))
       as_warn (_("base register written back, and overlaps "
                 "second destination register"));

      /* For an index-register load, the index register must not overlap the
        destination (even if not write-back).    */
      else if (inst.operands[2].immisreg
              && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
                 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
       as_warn (_("index register overlaps destination register"));
    }

  inst.instruction |= inst.operands[0].reg << 12;
  encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
}

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static void do_ldrex ( void  ) [static]

Definition at line 6965 of file tc-arm.c.

{
  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
             || inst.operands[1].postind || inst.operands[1].writeback
             || inst.operands[1].immisreg || inst.operands[1].shifted
             || inst.operands[1].negative
             /* This can arise if the programmer has written
                 strex rN, rM, foo
               or if they have mistakenly used a register name as the last
               operand,  eg:
                 strex rN, rM, rX
               It is very difficult to distinguish between these two cases
               because "rX" might actually be a label. ie the register
               name has been occluded by a symbol of the same name. So we
               just generate a general 'bad addressing mode' type error
               message and leave it up to the programmer to discover the
               true cause and fix their mistake.  */
             || (inst.operands[1].reg == REG_PC),
             BAD_ADDR_MODE);

  constraint (inst.reloc.exp.X_op != O_constant
             || inst.reloc.exp.X_add_number != 0,
             _("offset must be zero in ARM encoding"));

  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.reloc.type = BFD_RELOC_UNUSED;
}
static void do_ldrexd ( void  ) [static]

Definition at line 6995 of file tc-arm.c.

{
  constraint (inst.operands[0].reg % 2 != 0,
             _("even register required"));
  constraint (inst.operands[1].present
             && inst.operands[1].reg != inst.operands[0].reg + 1,
             _("can only load two consecutive registers"));
  /* If op 1 were present and equal to PC, this function wouldn't
     have been called in the first place.  */
  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));

  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[2].reg << 16;
}
static void do_ldst ( void  ) [static]

Definition at line 7011 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  if (!inst.operands[1].isreg)
    if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
      return;
  encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
}

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static void do_ldstt ( void  ) [static]

Definition at line 7021 of file tc-arm.c.

{
  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
     reject [Rn,...].  */
  if (inst.operands[1].preind)
    {
      constraint (inst.reloc.exp.X_op != O_constant ||
                inst.reloc.exp.X_add_number != 0,
                _("this instruction requires a post-indexed address"));

      inst.operands[1].preind = 0;
      inst.operands[1].postind = 1;
      inst.operands[1].writeback = 1;
    }
  inst.instruction |= inst.operands[0].reg << 12;
  encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
}

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static void do_ldsttv4 ( void  ) [static]

Definition at line 7052 of file tc-arm.c.

{
  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
     reject [Rn,...].  */
  if (inst.operands[1].preind)
    {
      constraint (inst.reloc.exp.X_op != O_constant ||
                inst.reloc.exp.X_add_number != 0,
                _("this instruction requires a post-indexed address"));

      inst.operands[1].preind = 0;
      inst.operands[1].postind = 1;
      inst.operands[1].writeback = 1;
    }
  inst.instruction |= inst.operands[0].reg << 12;
  encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
}

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static void do_ldstv4 ( void  ) [static]

Definition at line 7042 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  if (!inst.operands[1].isreg)
    if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
      return;
  encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
}

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static void do_lstc ( void  ) [static]

Definition at line 7073 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].reg << 12;
  encode_arm_cp_address (2, TRUE, TRUE, 0);
}

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static void do_mav_dspsc ( void  ) [static]

Definition at line 8082 of file tc-arm.c.

{
  inst.instruction |= inst.operands[1].reg << 12;
}
static void do_mav_quad ( void  ) [static]

Definition at line 8072 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 5;
  inst.instruction |= inst.operands[1].reg << 12;
  inst.instruction |= inst.operands[2].reg << 16;
  inst.instruction |= inst.operands[3].reg;
}
static void do_mav_shift ( void  ) [static]

Definition at line 8092 of file tc-arm.c.

{
  int imm = inst.operands[2].imm;

  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;

  /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
     Bits 5-7 of the insn should have bits 4-6 of the immediate.
     Bit 4 should be 0.      */
  imm = (imm & 0xf) | ((imm & 0x70) << 1);

  inst.instruction |= imm;
}
static void do_mav_triple ( void  ) [static]

Definition at line 8061 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 12;
}
static void do_mlas ( void  ) [static]

Definition at line 7081 of file tc-arm.c.

{
  /* This restriction does not apply to mls (nor to mla in v6 or later).  */
  if (inst.operands[0].reg == inst.operands[1].reg
      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
      && !(inst.instruction & 0x00400000))
    as_tsktsk (_("Rd and Rm should be different in mla"));

  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 8;
  inst.instruction |= inst.operands[3].reg << 12;
}

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static void do_mov ( void  ) [static]

Definition at line 7096 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  encode_arm_shifter_operand (1);
}

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static void do_mov16 ( void  ) [static]

Definition at line 7104 of file tc-arm.c.

{
  bfd_vma imm;
  bfd_boolean top;

  top = (inst.instruction & 0x00400000) != 0;
  constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
             _(":lower16: not allowed this instruction"));
  constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
             _(":upper16: not allowed instruction"));
  inst.instruction |= inst.operands[0].reg << 12;
  if (inst.reloc.type == BFD_RELOC_UNUSED)
    {
      imm = inst.reloc.exp.X_add_number;
      /* The value is in two pieces: 0:11, 16:19.  */
      inst.instruction |= (imm & 0x00000fff);
      inst.instruction |= (imm & 0x0000f000) << 4;
    }
}
static void do_mrs ( void  ) [static]

Definition at line 7157 of file tc-arm.c.

{
  if (do_vfp_nsyn_mrs () == SUCCESS)
    return;

  /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
  constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
             != (PSR_c|PSR_f),
             _("'CPSR' or 'SPSR' expected"));
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
}

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static void do_msr ( void  ) [static]

Definition at line 7175 of file tc-arm.c.

{
  if (do_vfp_nsyn_msr () == SUCCESS)
    return;

  inst.instruction |= inst.operands[0].imm;
  if (inst.operands[1].isreg)
    inst.instruction |= inst.operands[1].reg;
  else
    {
      inst.instruction |= INST_IMMEDIATE;
      inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
      inst.reloc.pc_rel = 0;
    }
}

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static void do_mul ( void  ) [static]

Definition at line 7192 of file tc-arm.c.

{
  if (!inst.operands[2].present)
    inst.operands[2].reg = inst.operands[0].reg;
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 8;

  if (inst.operands[0].reg == inst.operands[1].reg
      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
    as_tsktsk (_("Rd and Rm should be different in mul"));
}

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static void do_mull ( void  ) [static]

Definition at line 7212 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
  inst.instruction |= inst.operands[3].reg << 8;

  /* rdhi, rdlo and rm must all be different.  */
  if (inst.operands[0].reg == inst.operands[1].reg
      || inst.operands[0].reg == inst.operands[2].reg
      || inst.operands[1].reg == inst.operands[2].reg)
    as_tsktsk (_("rdhi, rdlo and rm must all be different"));
}

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static void do_noargs ( void  ) [static]

Definition at line 6502 of file tc-arm.c.

{
}
static void do_nop ( void  ) [static]

Definition at line 7227 of file tc-arm.c.

{
  if (inst.operands[0].present)
    {
      /* Architectural NOP hints are CPSR sets with no bits selected.  */
      inst.instruction &= 0xf0000000;
      inst.instruction |= 0x0320f000 + inst.operands[0].imm;
    }
}
static void do_pkhbt ( void  ) [static]

Definition at line 7243 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
  if (inst.operands[3].present)
    encode_arm_shift (3);
}

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static void do_pkhtb ( void  ) [static]

Definition at line 7255 of file tc-arm.c.

{
  if (!inst.operands[3].present)
    {
      /* If the shift specifier is omitted, turn the instruction
        into pkhbt rd, rm, rn. */
      inst.instruction &= 0xfff00010;
      inst.instruction |= inst.operands[0].reg << 12;
      inst.instruction |= inst.operands[1].reg;
      inst.instruction |= inst.operands[2].reg << 16;
    }
  else
    {
      inst.instruction |= inst.operands[0].reg << 12;
      inst.instruction |= inst.operands[1].reg << 16;
      inst.instruction |= inst.operands[2].reg;
      encode_arm_shift (3);
    }
}

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static void do_pld ( void  ) [static]

Definition at line 7282 of file tc-arm.c.

{
  constraint (!inst.operands[0].isreg,
             _("'[' expected after PLD mnemonic"));
  constraint (inst.operands[0].postind,
             _("post-indexed expression used in preload instruction"));
  constraint (inst.operands[0].writeback,
             _("writeback used in preload instruction"));
  constraint (!inst.operands[0].preind,
             _("unindexed addressing used in preload instruction"));
  encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
}

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static void do_pli ( void  ) [static]

Definition at line 7297 of file tc-arm.c.

{
  constraint (!inst.operands[0].isreg,
             _("'[' expected after PLI mnemonic"));
  constraint (inst.operands[0].postind,
             _("post-indexed expression used in preload instruction"));
  constraint (inst.operands[0].writeback,
             _("writeback used in preload instruction"));
  constraint (!inst.operands[0].preind,
             _("unindexed addressing used in preload instruction"));
  encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
  inst.instruction &= ~PRE_INDEX;
}

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static void do_push_pop ( void  ) [static]

Definition at line 7312 of file tc-arm.c.

{
  inst.operands[1] = inst.operands[0];
  memset (&inst.operands[0], 0, sizeof inst.operands[0]);
  inst.operands[0].isreg = 1;
  inst.operands[0].writeback = 1;
  inst.operands[0].reg = REG_SP;
  do_ldmstm ();
}

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static void do_rd ( void  ) [static]

Definition at line 6507 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
}
static void do_rd_cpaddr ( void  ) [static]

Definition at line 6569 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  encode_arm_cp_address (1, TRUE, TRUE, 0);
}

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static void do_rd_rm ( void  ) [static]

Definition at line 6513 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
}
static void do_rd_rm_rn ( void  ) [static]

Definition at line 6534 of file tc-arm.c.

{
  unsigned Rn = inst.operands[2].reg;
  /* Enforce restrictions on SWP instruction.  */
  if ((inst.instruction & 0x0fbfffff) == 0x01000090)
    constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
              _("Rn must not overlap other operands"));
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= Rn << 16;
}
static void do_rd_rn ( void  ) [static]

Definition at line 6520 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
}

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static void do_rd_rn_rm ( void  ) [static]

Definition at line 6547 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
}

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static void do_rfe ( void  ) [static]

Definition at line 7329 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  if (inst.operands[0].writeback)
    inst.instruction |= WRITE_BACK;
}
static void do_rm_rd_rn ( void  ) [static]

Definition at line 6555 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg;
  inst.instruction |= inst.operands[1].reg << 12;
  inst.instruction |= inst.operands[2].reg << 16;
}
static void do_rn_rd ( void  ) [static]

Definition at line 6527 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg << 12;
}
static void do_setend ( void  ) [static]

Definition at line 7387 of file tc-arm.c.

{
  if (inst.operands[0].imm)
    inst.instruction |= 0x200;
}
static void do_shift ( void  ) [static]

Definition at line 7394 of file tc-arm.c.

{
  unsigned int Rm = (inst.operands[1].present
                   ? inst.operands[1].reg
                   : inst.operands[0].reg);

  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= Rm;
  if (inst.operands[2].isreg)  /* Rd, {Rm,} Rs */
    {
      inst.instruction |= inst.operands[2].reg << 8;
      inst.instruction |= SHIFT_BY_REG;
    }
  else
    inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
}
static void do_smc ( void  ) [static]

Definition at line 7412 of file tc-arm.c.

{
  inst.reloc.type = BFD_RELOC_ARM_SMC;
  inst.reloc.pc_rel = 0;
}
static void do_smla ( void  ) [static]

Definition at line 7431 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 8;
  inst.instruction |= inst.operands[3].reg << 12;
}
static void do_smlal ( void  ) [static]

Definition at line 7445 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
  inst.instruction |= inst.operands[3].reg << 8;

  if (inst.operands[0].reg == inst.operands[1].reg)
    as_tsktsk (_("rdhi and rdlo must be different"));
}

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static void do_smul ( void  ) [static]

Definition at line 7461 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 16;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 8;
}
static void do_srs ( void  ) [static]

Definition at line 7472 of file tc-arm.c.

{
  int reg;

  if (inst.operands[0].present)
    {
      reg = inst.operands[0].reg;
      constraint (reg != 13, _("SRS base register must be r13"));
    }
  else
    reg = 13;

  inst.instruction |= reg << 16;
  inst.instruction |= inst.operands[1].imm;
  if (inst.operands[0].writeback || inst.operands[1].writeback)
    inst.instruction |= WRITE_BACK;
}
static void do_ssat ( void  ) [static]

Definition at line 7339 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= (inst.operands[1].imm - 1) << 16;
  inst.instruction |= inst.operands[2].reg;

  if (inst.operands[3].present)
    encode_arm_shift (3);
}

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static void do_ssat16 ( void  ) [static]

Definition at line 7365 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= ((inst.operands[1].imm - 1) << 16);
  inst.instruction |= inst.operands[2].reg;
}
static void do_strex ( void  ) [static]

Definition at line 7493 of file tc-arm.c.

{
  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
             || inst.operands[2].postind || inst.operands[2].writeback
             || inst.operands[2].immisreg || inst.operands[2].shifted
             || inst.operands[2].negative
             /* See comment in do_ldrex().  */
             || (inst.operands[2].reg == REG_PC),
             BAD_ADDR_MODE);

  constraint (inst.operands[0].reg == inst.operands[1].reg
             || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);

  constraint (inst.reloc.exp.X_op != O_constant
             || inst.reloc.exp.X_add_number != 0,
             _("offset must be zero in ARM encoding"));

  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].reg << 16;
  inst.reloc.type = BFD_RELOC_UNUSED;
}
static void do_strexd ( void  ) [static]

Definition at line 7517 of file tc-arm.c.

{
  constraint (inst.operands[1].reg % 2 != 0,
             _("even register required"));
  constraint (inst.operands[2].present
             && inst.operands[2].reg != inst.operands[1].reg + 1,
             _("can only store two consecutive registers"));
  /* If op 2 were present and equal to PC, this function wouldn't
     have been called in the first place.  */
  constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));

  constraint (inst.operands[0].reg == inst.operands[1].reg
             || inst.operands[0].reg == inst.operands[1].reg + 1
             || inst.operands[0].reg == inst.operands[3].reg,
             BAD_OVERLAP);

  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[3].reg << 16;
}
static void do_swi ( void  ) [static]

Definition at line 7419 of file tc-arm.c.

{
  inst.reloc.type = BFD_RELOC_ARM_SWI;
  inst.reloc.pc_rel = 0;
}
static void do_sxtah ( void  ) [static]

Definition at line 7547 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
  inst.instruction |= inst.operands[3].imm << 10;
}
static void do_sxth ( void  ) [static]

Definition at line 7562 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 12;
  inst.instruction |= inst.operands[1].reg;
  inst.instruction |= inst.operands[2].imm << 10;
}
static void do_t_add_sub ( void  ) [static]

Definition at line 8383 of file tc-arm.c.

{
  int Rd, Rs, Rn;

  Rd = inst.operands[0].reg;
  Rs = (inst.operands[1].present
       ? inst.operands[1].reg    /* Rd, Rs, foo */
       : inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */

  if (unified_syntax)
    {
      bfd_boolean flags;
      bfd_boolean narrow;
      int opcode;

      flags = (inst.instruction == T_MNEM_adds
              || inst.instruction == T_MNEM_subs);
      if (flags)
       narrow = (current_it_mask == 0);
      else
       narrow = (current_it_mask != 0);
      if (!inst.operands[2].isreg)
       {
         int add;

         add = (inst.instruction == T_MNEM_add
               || inst.instruction == T_MNEM_adds);
         opcode = 0;
         if (inst.size_req != 4)
           {
             /* Attempt to use a narrow opcode, with relaxation if
                appropriate.  */
             if (Rd == REG_SP && Rs == REG_SP && !flags)
              opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
             else if (Rd <= 7 && Rs == REG_SP && add && !flags)
              opcode = T_MNEM_add_sp;
             else if (Rd <= 7 && Rs == REG_PC && add && !flags)
              opcode = T_MNEM_add_pc;
             else if (Rd <= 7 && Rs <= 7 && narrow)
              {
                if (flags)
                  opcode = add ? T_MNEM_addis : T_MNEM_subis;
                else
                  opcode = add ? T_MNEM_addi : T_MNEM_subi;
              }
             if (opcode)
              {
                inst.instruction = THUMB_OP16(opcode);
                inst.instruction |= (Rd << 4) | Rs;
                inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
                if (inst.size_req != 2)
                  inst.relax = opcode;
              }
             else
              constraint (inst.size_req == 2, BAD_HIREG);
           }
         if (inst.size_req == 4
             || (inst.size_req != 2 && !opcode))
           {
             if (Rs == REG_PC)
              {
                /* Always use addw/subw.  */
                inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
                inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
              }
             else
              {
                inst.instruction = THUMB_OP32 (inst.instruction);
                inst.instruction = (inst.instruction & 0xe1ffffff)
                                 | 0x10000000;
                if (flags)
                  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
                else
                  inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
              }
             inst.instruction |= Rd << 8;
             inst.instruction |= Rs << 16;
           }
       }
      else
       {
         Rn = inst.operands[2].reg;
         /* See if we can do this with a 16-bit instruction.  */
         if (!inst.operands[2].shifted && inst.size_req != 4)
           {
             if (Rd > 7 || Rs > 7 || Rn > 7)
              narrow = FALSE;

             if (narrow)
              {
                inst.instruction = ((inst.instruction == T_MNEM_adds
                                   || inst.instruction == T_MNEM_add)
                                  ? T_OPCODE_ADD_R3
                                  : T_OPCODE_SUB_R3);
                inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
                return;
              }

             if (inst.instruction == T_MNEM_add)
              {
                if (Rd == Rs)
                  {
                    inst.instruction = T_OPCODE_ADD_HI;
                    inst.instruction |= (Rd & 8) << 4;
                    inst.instruction |= (Rd & 7);
                    inst.instruction |= Rn << 3;
                    return;
                  }
                /* ... because addition is commutative! */
                else if (Rd == Rn)
                  {
                    inst.instruction = T_OPCODE_ADD_HI;
                    inst.instruction |= (Rd & 8) << 4;
                    inst.instruction |= (Rd & 7);
                    inst.instruction |= Rs << 3;
                    return;
                  }
              }
           }
         /* If we get here, it can't be done in 16 bits.  */
         constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
                    _("shift must be constant"));
         inst.instruction = THUMB_OP32 (inst.instruction);
         inst.instruction |= Rd << 8;
         inst.instruction |= Rs << 16;
         encode_thumb32_shifted_operand (2);
       }
    }
  else
    {
      constraint (inst.instruction == T_MNEM_adds
                || inst.instruction == T_MNEM_subs,
                BAD_THUMB32);

      if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
       {
         constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
                    || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
                    BAD_HIREG);

         inst.instruction = (inst.instruction == T_MNEM_add
                           ? 0x0000 : 0x8000);
         inst.instruction |= (Rd << 4) | Rs;
         inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
         return;
       }

      Rn = inst.operands[2].reg;
      constraint (inst.operands[2].shifted, _("unshifted register required"));

      /* We now have Rd, Rs, and Rn set to registers.  */
      if (Rd > 7 || Rs > 7 || Rn > 7)
       {
         /* Can't do this for SUB.  */
         constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
         inst.instruction = T_OPCODE_ADD_HI;
         inst.instruction |= (Rd & 8) << 4;
         inst.instruction |= (Rd & 7);
         if (Rs == Rd)
           inst.instruction |= Rn << 3;
         else if (Rn == Rd)
           inst.instruction |= Rs << 3;
         else
           constraint (1, _("dest must overlap one source register"));
       }
      else
       {
         inst.instruction = (inst.instruction == T_MNEM_add
                           ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
         inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
       }
    }
}

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static void do_t_add_sub_w ( void  ) [static]

Definition at line 8367 of file tc-arm.c.

{
  int Rd, Rn;

  Rd = inst.operands[0].reg;
  Rn = inst.operands[1].reg;

  constraint (Rd == 15, _("PC not allowed as destination"));
  inst.instruction |= (Rn << 16) | (Rd << 8);
  inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
}
static void do_t_adr ( void  ) [static]

Definition at line 8558 of file tc-arm.c.

{
  if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
    {
      /* Defer to section relaxation.  */
      inst.relax = inst.instruction;
      inst.instruction = THUMB_OP16 (inst.instruction);
      inst.instruction |= inst.operands[0].reg << 4;
    }
  else if (unified_syntax && inst.size_req != 2)
    {
      /* Generate a 32-bit opcode.  */
      inst.instruction = THUMB_OP32 (inst.instruction);
      inst.instruction |= inst.operands[0].reg << 8;
      inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
      inst.reloc.pc_rel = 1;
    }
  else
    {
      /* Generate a 16-bit opcode.  */
      inst.instruction = THUMB_OP16 (inst.instruction);
      inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
      inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
      inst.reloc.pc_rel = 1;

      inst.instruction |= inst.operands[0].reg << 4;
    }
}
static void do_t_arit3 ( void  ) [static]

Definition at line 8594 of file tc-arm.c.

{
  int Rd, Rs, Rn;

  Rd = inst.operands[0].reg;
  Rs = (inst.operands[1].present
       ? inst.operands[1].reg    /* Rd, Rs, foo */
       : inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
  Rn = inst.operands[2].reg;

  if (unified_syntax)
    {
      if (!inst.operands[2].isreg)
       {
         /* For an immediate, we always generate a 32-bit opcode;
            section relaxation will shrink it later if possible.  */
         inst.instruction = THUMB_OP32 (inst.instruction);
         inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
         inst.instruction |= Rd << 8;
         inst.instruction |= Rs << 16;
         inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
       }
      else
       {
         bfd_boolean narrow;

         /* See if we can do this with a 16-bit instruction.  */
         if (THUMB_SETS_FLAGS (inst.instruction))
           narrow = current_it_mask == 0;
         else
           narrow = current_it_mask != 0;

         if (Rd > 7 || Rn > 7 || Rs > 7)
           narrow = FALSE;
         if (inst.operands[2].shifted)
           narrow = FALSE;
         if (inst.size_req == 4)
           narrow = FALSE;

         if (narrow
             && Rd == Rs)
           {
             inst.instruction = THUMB_OP16 (inst.instruction);
             inst.instruction |= Rd;
             inst.instruction |= Rn << 3;
             return;
           }

         /* If we get here, it can't be done in 16 bits.  */
         constraint (inst.operands[2].shifted
                    && inst.operands[2].immisreg,
                    _("shift must be constant"));
         inst.instruction = THUMB_OP32 (inst.instruction);
         inst.instruction |= Rd << 8;
         inst.instruction |= Rs << 16;
         encode_thumb32_shifted_operand (2);
       }
    }
  else
    {
      /* On its face this is a lie - the instruction does set the
        flags.  However, the only supported mnemonic in this mode
        says it doesn't.  */
      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);

      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
                _("unshifted register required"));
      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
      constraint (Rd != Rs,
                _("dest and source1 must be the same register"));

      inst.instruction = THUMB_OP16 (inst.instruction);
      inst.instruction |= Rd;
      inst.instruction |= Rn << 3;
    }
}

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static void do_t_arit3c ( void  ) [static]

Definition at line 8677 of file tc-arm.c.

{
  int Rd, Rs, Rn;

  Rd = inst.operands[0].reg;
  Rs = (inst.operands[1].present
       ? inst.operands[1].reg    /* Rd, Rs, foo */
       : inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
  Rn = inst.operands[2].reg;

  if (unified_syntax)
    {
      if (!inst.operands[2].isreg)
       {
         /* For an immediate, we always generate a 32-bit opcode;
            section relaxation will shrink it later if possible.  */
         inst.instruction = THUMB_OP32 (inst.instruction);
         inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
         inst.instruction |= Rd << 8;
         inst.instruction |= Rs << 16;
         inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
       }
      else
       {
         bfd_boolean narrow;

         /* See if we can do this with a 16-bit instruction.  */
         if (THUMB_SETS_FLAGS (inst.instruction))
           narrow = current_it_mask == 0;
         else
           narrow = current_it_mask != 0;

         if (Rd > 7 || Rn > 7 || Rs > 7)
           narrow = FALSE;
         if (inst.operands[2].shifted)
           narrow = FALSE;
         if (inst.size_req == 4)
           narrow = FALSE;

         if (narrow)
           {
             if (Rd == Rs)
              {
                inst.instruction = THUMB_OP16 (inst.instruction);
                inst.instruction |= Rd;
                inst.instruction |= Rn << 3;
                return;
              }
             if (Rd == Rn)
              {
                inst.instruction = THUMB_OP16 (inst.instruction);
                inst.instruction |= Rd;
                inst.instruction |= Rs << 3;
                return;
              }
           }

         /* If we get here, it can't be done in 16 bits.  */
         constraint (inst.operands[2].shifted
                    && inst.operands[2].immisreg,
                    _("shift must be constant"));
         inst.instruction = THUMB_OP32 (inst.instruction);
         inst.instruction |= Rd << 8;
         inst.instruction |= Rs << 16;
         encode_thumb32_shifted_operand (2);
       }
    }
  else
    {
      /* On its face this is a lie - the instruction does set the
        flags.  However, the only supported mnemonic in this mode
        says it doesn't.  */
      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);

      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
                _("unshifted register required"));
      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);

      inst.instruction = THUMB_OP16 (inst.instruction);
      inst.instruction |= Rd;

      if (Rd == Rs)
       inst.instruction |= Rn << 3;
      else if (Rd == Rn)
       inst.instruction |= Rs << 3;
      else
       constraint (1, _("dest must overlap one source register"));
    }
}

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static void do_t_barrier ( void  ) [static]

Definition at line 8768 of file tc-arm.c.

{
  if (inst.operands[0].present)
    {
      constraint ((inst.instruction & 0xf0) != 0x40
                && inst.operands[0].imm != 0xf,
                "bad barrier type");
      inst.instruction |= inst.operands[0].imm;
    }
  else
    inst.instruction |= 0xf;
}
static void do_t_bfc ( void  ) [static]

Definition at line 8782 of file tc-arm.c.

{
  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
  constraint (msb > 32, _("bit-field extends past end of register"));
  /* The instruction encoding stores the LSB and MSB,
     not the LSB and width.  */
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
  inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
  inst.instruction |= msb - 1;
}
static void do_t_bfi ( void  ) [static]

Definition at line 8795 of file tc-arm.c.

{
  unsigned int msb;

  /* #0 in second position is alternative syntax for bfc, which is
     the same instruction but with REG_PC in the Rm field.  */
  if (!inst.operands[1].isreg)
    inst.operands[1].reg = REG_PC;

  msb = inst.operands[2].imm + inst.operands[3].imm;
  constraint (msb > 32, _("bit-field extends past end of register"));
  /* The instruction encoding stores the LSB and MSB,
     not the LSB and width.  */
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
  inst.instruction |= msb - 1;
}
static void do_t_bfx ( void  ) [static]

Definition at line 8816 of file tc-arm.c.

{
  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
             _("bit-field extends past end of register"));
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
  inst.instruction |= inst.operands[3].imm - 1;
}
static void do_t_bkpt ( void  ) [static]

Definition at line 8911 of file tc-arm.c.

{
  constraint (inst.cond != COND_ALWAYS,
             _("instruction is always unconditional"));
  if (inst.operands[0].present)
    {
      constraint (inst.operands[0].imm > 255,
                _("immediate value out of range"));
      inst.instruction |= inst.operands[0].imm;
    }
}
static void do_t_blx ( void  ) [static]

Definition at line 8838 of file tc-arm.c.

{
  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
  if (inst.operands[0].isreg)
    /* We have a register, so this is BLX(2).  */
    inst.instruction |= inst.operands[0].reg << 3;
  else
    {
      /* No register.  This must be BLX(1).  */
      inst.instruction = 0xf000e800;
#ifdef OBJ_ELF
      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
       inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
      else
#endif
       inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
      inst.reloc.pc_rel = 1;
    }
}
static void do_t_branch ( void  ) [static]

Definition at line 8859 of file tc-arm.c.

{
  int opcode;
  int cond;

  if (current_it_mask)
    {
      /* Conditional branches inside IT blocks are encoded as unconditional
         branches.  */
      cond = COND_ALWAYS;
      /* A branch must be the last instruction in an IT block.  */
      constraint (current_it_mask != 0x10, BAD_BRANCH);
    }
  else
    cond = inst.cond;

  if (cond != COND_ALWAYS)
    opcode = T_MNEM_bcond;
  else
    opcode = inst.instruction;

  if (unified_syntax && inst.size_req == 4)
    {
      inst.instruction = THUMB_OP32(opcode);
      if (cond == COND_ALWAYS)
       inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
      else
       {
         assert (cond != 0xF);
         inst.instruction |= cond << 22;
         inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
       }
    }
  else
    {
      inst.instruction = THUMB_OP16(opcode);
      if (cond == COND_ALWAYS)
       inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
      else
       {
         inst.instruction |= cond << 8;
         inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
       }
      /* Allow section relaxation.  */
      if (unified_syntax && inst.size_req != 2)
       inst.relax = opcode;
    }

  inst.reloc.pc_rel = 1;
}
static void do_t_branch23 ( void  ) [static]

Definition at line 8924 of file tc-arm.c.

{
  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
  inst.reloc.type   = BFD_RELOC_THUMB_PCREL_BRANCH23;
  inst.reloc.pc_rel = 1;

  /* If the destination of the branch is a defined symbol which does not have
     the THUMB_FUNC attribute, then we must be calling a function which has
     the (interfacearm) attribute.  We look for the Thumb entry point to that
     function and change the branch to refer to that function instead.       */
  if (  inst.reloc.exp.X_op == O_symbol
      && inst.reloc.exp.X_add_symbol != NULL
      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
      && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
    inst.reloc.exp.X_add_symbol =
      find_real_start (inst.reloc.exp.X_add_symbol);
}

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static void do_t_bx ( void  ) [static]

Definition at line 8943 of file tc-arm.c.

{
  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
  inst.instruction |= inst.operands[0].reg << 3;
  /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC.        The reloc
     should cause the alignment to be checked once it is known.        This is
     because BX PC only works if the instruction is word aligned.  */
}
static void do_t_bxj ( void  ) [static]

Definition at line 8953 of file tc-arm.c.

{
  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
  if (inst.operands[0].reg == REG_PC)
    as_tsktsk (_("use of r15 in bxj is not really useful"));

  inst.instruction |= inst.operands[0].reg << 16;
}

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static void do_t_cbz ( void  ) [static]

Definition at line 9025 of file tc-arm.c.

{
  constraint (current_it_mask, BAD_NOT_IT);
  constraint (inst.operands[0].reg > 7, BAD_HIREG);
  inst.instruction |= inst.operands[0].reg;
  inst.reloc.pc_rel = 1;
  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
}
static void do_t_clz ( void  ) [static]

Definition at line 8963 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[1].reg;
}
static void do_t_cps ( void  ) [static]

Definition at line 8971 of file tc-arm.c.

{
  constraint (current_it_mask, BAD_NOT_IT);
  inst.instruction |= inst.operands[0].imm;
}
static void do_t_cpsi ( void  ) [static]

Definition at line 8978 of file tc-arm.c.

{
  constraint (current_it_mask, BAD_NOT_IT);
  if (unified_syntax
      && (inst.operands[1].present || inst.size_req == 4)
      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
    {
      unsigned int imod = (inst.instruction & 0x0030) >> 4;
      inst.instruction = 0xf3af8000;
      inst.instruction |= imod << 9;
      inst.instruction |= inst.operands[0].imm << 5;
      if (inst.operands[1].present)
       inst.instruction |= 0x100 | inst.operands[1].imm;
    }
  else
    {
      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
                && (inst.operands[0].imm & 4),
                _("selected processor does not support 'A' form "
                  "of this instruction"));
      constraint (inst.operands[1].present || inst.size_req == 4,
                _("Thumb does not support the 2-argument "
                  "form of this instruction"));
      inst.instruction |= inst.operands[0].imm;
    }
}
static void do_t_cpy ( void  ) [static]

Definition at line 9008 of file tc-arm.c.

{
  if (inst.size_req == 4)
    {
      inst.instruction = THUMB_OP32 (T_MNEM_mov);
      inst.instruction |= inst.operands[0].reg << 8;
      inst.instruction |= inst.operands[1].reg;
    }
  else
    {
      inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
      inst.instruction |= (inst.operands[0].reg & 0x7);
      inst.instruction |= inst.operands[1].reg << 3;
    }
}

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static void do_t_dbg ( void  ) [static]

Definition at line 9035 of file tc-arm.c.

{
  inst.instruction |= inst.operands[0].imm;
}
static void do_t_div ( void  ) [static]

Definition at line 9041 of file tc-arm.c.

{
  if (!inst.operands[1].present)
    inst.operands[1].reg = inst.operands[0].reg;
  inst.instruction |= inst.operands[0].reg << 8;
  inst.instruction |= inst.operands[1].reg << 16;
  inst.instruction |= inst.operands[2].reg;
}
static void do_t_hint ( void  ) [static]

Definition at line 9051 of file tc-arm.c.

{
  if (unified_syntax && inst.size_req == 4)
    inst.instruction = THUMB_OP32 (inst.instruction);
  else
    inst.instruction = THUMB_OP16 (inst.instruction);
}
static void do_t_it ( void  ) [static]

Definition at line 9060 of file tc-arm.c.

{
  unsigned int