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cell-binutils  2.17cvs20070401
splet.d
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00001 #as: -Asparclet
00002 #objdump: -dr
00003 #name: sparclet extensions
00004 
00005 .*: +file format .*
00006 
00007 Disassembly of section .text:
00008 
00009 0+ <start>:
00010    0:  a1 40 00 00   rd  %y, %l0
00011    4:  a1 40 40 00   rd  %asr1, %l0
00012    8:  a1 43 c0 00   rd  %asr15, %l0
00013    c:  a1 44 40 00   rd  %asr17, %l0
00014   10:  a1 44 80 00   rd  %asr18, %l0
00015   14:  a1 44 c0 00   rd  %asr19, %l0
00016   18:  a1 45 00 00   rd  %asr20, %l0
00017   1c:  a1 45 40 00   rd  %asr21, %l0
00018   20:  a1 45 80 00   rd  %asr22, %l0
00019   24:  81 84 20 00   mov  %l0, %y
00020   28:  83 84 20 00   mov  %l0, %asr1
00021   2c:  9f 84 20 00   mov  %l0, %asr15
00022   30:  a3 84 20 00   mov  %l0, %asr17
00023   34:  a5 84 20 00   mov  %l0, %asr18
00024   38:  a7 84 20 00   mov  %l0, %asr19
00025   3c:  a9 84 20 00   mov  %l0, %asr20
00026   40:  ab 84 20 00   mov  %l0, %asr21
00027   44:  ad 84 20 00   mov  %l0, %asr22
00028 
00029 0+48 <test_umul>:
00030   48:  86 50 40 02   umul  %g1, %g2, %g3
00031   4c:  86 50 40 02   umul  %g1, %g2, %g3
00032 
00033 0+50 <test_smul>:
00034   50:  86 58 40 02   smul  %g1, %g2, %g3
00035   54:  86 58 40 02   smul  %g1, %g2, %g3
00036 
00037 0+58 <test_stbar>:
00038   58:  81 43 c0 00   stbar 
00039   5c:  81 43 c0 00   stbar 
00040   60:  00 00 00 01   unimp  0x1
00041   64:  81 dc 40 00   flush  %l1
00042 
00043 0+68 <test_scan>:
00044   68:  a7 64 7f ff   scan  %l1, -1, %l3
00045   6c:  a7 64 60 00   scan  %l1, 0, %l3
00046   70:  a7 64 40 11   scan  %l1, %l1, %l3
00047 
00048 0+74 <test_shuffle>:
00049   74:  a3 6c 20 01   shuffle  %l0, 1, %l1
00050   78:  a3 6c 20 02   shuffle  %l0, 2, %l1
00051   7c:  a3 6c 20 04   shuffle  %l0, 4, %l1
00052   80:  a3 6c 20 08   shuffle  %l0, 8, %l1
00053   84:  a3 6c 20 10   shuffle  %l0, 0x10, %l1
00054   88:  a3 6c 20 18   shuffle  %l0, 0x18, %l1
00055 
00056 0+8c <test_umac>:
00057   8c:  a1 f4 40 12   umac  %l1, %l2, %l0
00058   90:  a1 f4 60 02   umac  %l1, 2, %l0
00059   94:  a1 f4 60 02   umac  %l1, 2, %l0
00060 
00061 0+98 <test_umacd>:
00062   98:  a1 74 80 14   umacd  %l2, %l4, %l0
00063   9c:  a1 74 a0 03   umacd  %l2, 3, %l0
00064   a0:  a1 74 a0 03   umacd  %l2, 3, %l0
00065 
00066 0+a4 <test_smac>:
00067   a4:  a1 fc 40 12   smac  %l1, %l2, %l0
00068   a8:  a1 fc 7f d6   smac  %l1, -42, %l0
00069   ac:  a1 fc 7f d6   smac  %l1, -42, %l0
00070 
00071 0+b0 <test_smacd>:
00072   b0:  a1 7c 80 14   smacd  %l2, %l4, %l0
00073   b4:  a1 7c a0 7b   smacd  %l2, 0x7b, %l0
00074   b8:  a1 7c a0 7b   smacd  %l2, 0x7b, %l0
00075 
00076 0+bc <test_umuld>:
00077   bc:  90 4a 80 0c   umuld  %o2, %o4, %o0
00078   c0:  90 4a a2 34   umuld  %o2, 0x234, %o0
00079   c4:  90 4a a5 67   umuld  %o2, 0x567, %o0
00080 
00081 0+c8 <test_smuld>:
00082   c8:  b0 6e 80 1c   smuld  %i2, %i4, %i0
00083   cc:  b0 6e b0 00   smuld  %i2, -4096, %i0
00084   d0:  b0 6f 2f ff   smuld  %i4, 0xfff, %i0
00085 
00086 0+d4 <test_coprocessor>:
00087   d4:  81 b4 00 11   cpush  %l0, %l1
00088   d8:  81 b4 20 01   cpush  %l0, 1
00089   dc:  81 b4 00 51   cpusha  %l0, %l1
00090   e0:  81 b4 20 41   cpusha  %l0, 1
00091   e4:  a1 b0 00 80   cpull  %l0
00092   e8:  a1 b0 01 00   crdcxt  %ccsr, %l0
00093   ec:  a1 b0 41 00   crdcxt  %ccfr, %l0
00094   f0:  a1 b0 c1 00   crdcxt  %ccpr, %l0
00095   f4:  a1 b0 81 00   crdcxt  %cccrcr, %l0
00096   f8:  81 b4 00 c0   cwrcxt  %l0, %ccsr
00097   fc:  83 b4 00 c0   cwrcxt  %l0, %ccfr
00098  100:  87 b4 00 c0   cwrcxt  %l0, %ccpr
00099  104:  85 b4 00 c0   cwrcxt  %l0, %cccrcr
00100  108:  01 c0 00 01   cbn  10c <test_coprocessor\+(0x|)38>
00101                      108: WDISP22  stop\+0xfffffef8
00102  10c:  01 00 00 00   nop 
00103  110:  21 c0 00 01   cbn,a   114 <test_coprocessor\+(0x|)40>
00104                      110: WDISP22  stop\+0xfffffef0
00105  114:  01 00 00 00   nop 
00106  118:  03 c0 00 01   cbe  11c <test_coprocessor\+(0x|)48>
00107                      118: WDISP22  stop\+0xfffffee8
00108  11c:  01 00 00 00   nop 
00109  120:  23 c0 00 01   cbe,a   124 <test_coprocessor\+(0x|)50>
00110                      120: WDISP22  stop\+0xfffffee0
00111  124:  01 00 00 00   nop 
00112  128:  05 c0 00 01   cbf  12c <test_coprocessor\+(0x|)58>
00113                      128: WDISP22  stop\+0xfffffed8
00114  12c:  01 00 00 00   nop 
00115  130:  25 c0 00 01   cbf,a   134 <test_coprocessor\+(0x|)60>
00116                      130: WDISP22  stop\+0xfffffed0
00117  134:  01 00 00 00   nop 
00118  138:  07 c0 00 01   cbef  13c <test_coprocessor\+(0x|)68>
00119                      138: WDISP22  stop\+0xfffffec8
00120  13c:  01 00 00 00   nop 
00121  140:  27 c0 00 01   cbef,a   144 <test_coprocessor\+(0x|)70>
00122                      140: WDISP22  stop\+0xfffffec0
00123  144:  01 00 00 00   nop 
00124  148:  09 c0 00 01   cbr  14c <test_coprocessor\+(0x|)78>
00125                      148: WDISP22  stop\+0xfffffeb8
00126  14c:  01 00 00 00   nop 
00127  150:  29 c0 00 01   cbr,a   154 <test_coprocessor\+(0x|)80>
00128                      150: WDISP22  stop\+0xfffffeb0
00129  154:  01 00 00 00   nop 
00130  158:  0b c0 00 01   cber  15c <test_coprocessor\+(0x|)88>
00131                      158: WDISP22  stop\+0xfffffea8
00132  15c:  01 00 00 00   nop 
00133  160:  2b c0 00 01   cber,a   164 <test_coprocessor\+(0x|)90>
00134                      160: WDISP22  stop\+0xfffffea0
00135  164:  01 00 00 00   nop 
00136  168:  0d c0 00 01   cbfr  16c <test_coprocessor\+(0x|)98>
00137                      168: WDISP22  stop\+0xfffffe98
00138  16c:  01 00 00 00   nop 
00139  170:  2d c0 00 01   cbfr,a   174 <test_coprocessor\+(0x|)a0>
00140                      170: WDISP22  stop\+0xfffffe90
00141  174:  01 00 00 00   nop 
00142  178:  0f c0 00 01   cbefr  17c <test_coprocessor\+(0x|)a8>
00143                      178: WDISP22  stop\+0xfffffe88
00144  17c:  01 00 00 00   nop 
00145  180:  2f c0 00 01   cbefr,a   184 <test_coprocessor\+(0x|)b0>
00146                      180: WDISP22  stop\+0xfffffe80
00147  184:  01 00 00 00   nop 
00148  188:  11 c0 00 01   cba  18c <test_coprocessor\+(0x|)b8>
00149                      188: WDISP22  stop\+0xfffffe78
00150  18c:  01 00 00 00   nop 
00151  190:  31 c0 00 01   cba,a   194 <test_coprocessor\+(0x|)c0>
00152                      190: WDISP22  stop\+0xfffffe70
00153  194:  01 00 00 00   nop 
00154  198:  13 c0 00 01   cbne  19c <test_coprocessor\+(0x|)c8>
00155                      198: WDISP22  stop\+0xfffffe68
00156  19c:  01 00 00 00   nop 
00157  1a0:  33 c0 00 01   cbne,a   1a4 <test_coprocessor\+(0x|)d0>
00158                      1a0: WDISP22  stop\+0xfffffe60
00159  1a4:  01 00 00 00   nop 
00160  1a8:  15 c0 00 01   cbnf  1ac <test_coprocessor\+(0x|)d8>
00161                      1a8: WDISP22  stop\+0xfffffe58
00162  1ac:  01 00 00 00   nop 
00163  1b0:  35 c0 00 01   cbnf,a   1b4 <test_coprocessor\+(0x|)e0>
00164                      1b0: WDISP22  stop\+0xfffffe50
00165  1b4:  01 00 00 00   nop 
00166  1b8:  17 c0 00 01   cbnef  1bc <test_coprocessor\+(0x|)e8>
00167                      1b8: WDISP22  stop\+0xfffffe48
00168  1bc:  01 00 00 00   nop 
00169  1c0:  37 c0 00 01   cbnef,a   1c4 <test_coprocessor\+(0x|)f0>
00170                      1c0: WDISP22  stop\+0xfffffe40
00171  1c4:  01 00 00 00   nop 
00172  1c8:  19 c0 00 01   cbnr  1cc <test_coprocessor\+(0x|)f8>
00173                      1c8: WDISP22  stop\+0xfffffe38
00174  1cc:  01 00 00 00   nop 
00175  1d0:  39 c0 00 01   cbnr,a   1d4 <test_coprocessor\+(0x|)100>
00176                      1d0: WDISP22  stop\+0xfffffe30
00177  1d4:  01 00 00 00   nop 
00178  1d8:  1b c0 00 01   cbner  1dc <test_coprocessor\+(0x|)108>
00179                      1d8: WDISP22  stop\+0xfffffe28
00180  1dc:  01 00 00 00   nop 
00181  1e0:  3b c0 00 01   cbner,a   1e4 <test_coprocessor\+(0x|)110>
00182                      1e0: WDISP22  stop\+0xfffffe20
00183  1e4:  01 00 00 00   nop 
00184  1e8:  1d c0 00 01   cbnfr  1ec <test_coprocessor\+(0x|)118>
00185                      1e8: WDISP22  stop\+0xfffffe18
00186  1ec:  01 00 00 00   nop 
00187  1f0:  3d c0 00 01   cbnfr,a   1f4 <test_coprocessor\+(0x|)120>
00188                      1f0: WDISP22  stop\+0xfffffe10
00189  1f4:  01 00 00 00   nop 
00190  1f8:  1f c0 00 01   cbnefr  1fc <test_coprocessor\+(0x|)128>
00191                      1f8: WDISP22  stop\+0xfffffe08
00192  1fc:  01 00 00 00   nop 
00193  200:  3f c0 00 01   cbnefr,a   204 <test_coprocessor\+(0x|)130>
00194                      200: WDISP22  stop\+0xfffffe00
00195  204:  01 00 00 00   nop