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cell-binutils  2.17cvs20070401
sim-sh.h
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00001 /* This file defines the interface between the sh simulator and gdb.
00002    Copyright (C) 2000, 2002, 2004, 2007 Free Software Foundation, Inc.
00003 
00004 This file is part of GDB.
00005 
00006 This program is free software; you can redistribute it and/or modify
00007 it under the terms of the GNU General Public License as published by
00008 the Free Software Foundation; either version 2 of the License, or
00009 (at your option) any later version.
00010 
00011 This program is distributed in the hope that it will be useful,
00012 but WITHOUT ANY WARRANTY; without even the implied warranty of
00013 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00014 GNU General Public License for more details.
00015 
00016 You should have received a copy of the GNU General Public License
00017 along with this program; if not, write to the Free Software
00018 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
00019 
00020 #if !defined (SIM_SH_H)
00021 #define SIM_SH_H
00022 
00023 #ifdef __cplusplus
00024 extern "C" { // }
00025 #endif
00026 
00027 /* The simulator makes use of the following register information. */
00028 
00029 enum
00030 {
00031   SIM_SH_R0_REGNUM = 0,
00032   SIM_SH_R1_REGNUM,
00033   SIM_SH_R2_REGNUM,
00034   SIM_SH_R3_REGNUM,
00035   SIM_SH_R4_REGNUM,
00036   SIM_SH_R5_REGNUM,
00037   SIM_SH_R6_REGNUM,
00038   SIM_SH_R7_REGNUM,
00039   SIM_SH_R8_REGNUM,
00040   SIM_SH_R9_REGNUM,
00041   SIM_SH_R10_REGNUM,
00042   SIM_SH_R11_REGNUM,
00043   SIM_SH_R12_REGNUM,
00044   SIM_SH_R13_REGNUM,
00045   SIM_SH_R14_REGNUM,
00046   SIM_SH_R15_REGNUM,
00047   SIM_SH_PC_REGNUM,
00048   SIM_SH_PR_REGNUM,
00049   SIM_SH_GBR_REGNUM,
00050   SIM_SH_VBR_REGNUM,
00051   SIM_SH_MACH_REGNUM,
00052   SIM_SH_MACL_REGNUM,
00053   SIM_SH_SR_REGNUM,
00054   SIM_SH_FPUL_REGNUM,
00055   SIM_SH_FPSCR_REGNUM,
00056   SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */
00057   SIM_SH_FR1_REGNUM,
00058   SIM_SH_FR2_REGNUM,
00059   SIM_SH_FR3_REGNUM,
00060   SIM_SH_FR4_REGNUM,
00061   SIM_SH_FR5_REGNUM,
00062   SIM_SH_FR6_REGNUM,
00063   SIM_SH_FR7_REGNUM,
00064   SIM_SH_FR8_REGNUM,
00065   SIM_SH_FR9_REGNUM,
00066   SIM_SH_FR10_REGNUM,
00067   SIM_SH_FR11_REGNUM,
00068   SIM_SH_FR12_REGNUM,
00069   SIM_SH_FR13_REGNUM,
00070   SIM_SH_FR14_REGNUM,
00071   SIM_SH_FR15_REGNUM,
00072   SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */
00073   SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */
00074   SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */
00075   SIM_SH_R1_BANK0_REGNUM,
00076   SIM_SH_R2_BANK0_REGNUM,
00077   SIM_SH_R3_BANK0_REGNUM,
00078   SIM_SH_R4_BANK0_REGNUM,
00079   SIM_SH_R5_BANK0_REGNUM,
00080   SIM_SH_R6_BANK0_REGNUM,
00081   SIM_SH_R7_BANK0_REGNUM,
00082   SIM_SH_R0_BANK1_REGNUM,
00083   SIM_SH_R1_BANK1_REGNUM,
00084   SIM_SH_R2_BANK1_REGNUM,
00085   SIM_SH_R3_BANK1_REGNUM,
00086   SIM_SH_R4_BANK1_REGNUM,
00087   SIM_SH_R5_BANK1_REGNUM,
00088   SIM_SH_R6_BANK1_REGNUM,
00089   SIM_SH_R7_BANK1_REGNUM,
00090   SIM_SH_XF0_REGNUM,
00091   SIM_SH_XF1_REGNUM,
00092   SIM_SH_XF2_REGNUM,
00093   SIM_SH_XF3_REGNUM,
00094   SIM_SH_XF4_REGNUM,
00095   SIM_SH_XF5_REGNUM,
00096   SIM_SH_XF6_REGNUM,
00097   SIM_SH_XF7_REGNUM,
00098   SIM_SH_XF8_REGNUM,
00099   SIM_SH_XF9_REGNUM,
00100   SIM_SH_XF10_REGNUM,
00101   SIM_SH_XF11_REGNUM,
00102   SIM_SH_XF12_REGNUM,
00103   SIM_SH_XF13_REGNUM,
00104   SIM_SH_XF14_REGNUM,
00105   SIM_SH_XF15_REGNUM,
00106   SIM_SH_SGR_REGNUM,
00107   SIM_SH_DBR_REGNUM,
00108   SIM_SH4_NUM_REGS, /* 77 */
00109 
00110   /* sh[3]-dsp */
00111   SIM_SH_DSR_REGNUM,
00112   SIM_SH_A0G_REGNUM,
00113   SIM_SH_A0_REGNUM,
00114   SIM_SH_A1G_REGNUM,
00115   SIM_SH_A1_REGNUM,
00116   SIM_SH_M0_REGNUM,
00117   SIM_SH_M1_REGNUM,
00118   SIM_SH_X0_REGNUM,
00119   SIM_SH_X1_REGNUM,
00120   SIM_SH_Y0_REGNUM,
00121   SIM_SH_Y1_REGNUM,
00122   SIM_SH_MOD_REGNUM,
00123   SIM_SH_RS_REGNUM,
00124   SIM_SH_RE_REGNUM,
00125   SIM_SH_R0_BANK_REGNUM,
00126   SIM_SH_R1_BANK_REGNUM,
00127   SIM_SH_R2_BANK_REGNUM,
00128   SIM_SH_R3_BANK_REGNUM,
00129   SIM_SH_R4_BANK_REGNUM,
00130   SIM_SH_R5_BANK_REGNUM,
00131   SIM_SH_R6_BANK_REGNUM,
00132   SIM_SH_R7_BANK_REGNUM,
00133   /* 109..127: room for expansion.  */
00134   SIM_SH_TBR_REGNUM,
00135   SIM_SH_IBNR_REGNUM,
00136   SIM_SH_IBCR_REGNUM,
00137   SIM_SH_BANK_REGNUM,
00138   SIM_SH_BANK_MACL_REGNUM,
00139   SIM_SH_BANK_GBR_REGNUM,
00140   SIM_SH_BANK_PR_REGNUM,
00141   SIM_SH_BANK_IVN_REGNUM,
00142   SIM_SH_BANK_MACH_REGNUM
00143 };
00144 
00145 enum
00146 {
00147   SIM_SH64_R0_REGNUM = 0,
00148   SIM_SH64_SP_REGNUM = 15,
00149   SIM_SH64_PC_REGNUM = 64,
00150   SIM_SH64_SR_REGNUM = 65,
00151   SIM_SH64_SSR_REGNUM = 66,
00152   SIM_SH64_SPC_REGNUM = 67,
00153   SIM_SH64_TR0_REGNUM = 68,
00154   SIM_SH64_FPCSR_REGNUM = 76,
00155   SIM_SH64_FR0_REGNUM = 77
00156 };
00157 
00158 enum
00159 {
00160   SIM_SH64_NR_REGS = 141,  /* total number of architectural registers */
00161   SIM_SH64_NR_R_REGS = 64, /* number of general registers */
00162   SIM_SH64_NR_TR_REGS = 8, /* number of target registers */
00163   SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */
00164 };
00165 
00166 #ifdef __cplusplus
00167 }
00168 #endif
00169 
00170 #endif