Back to index

cell-binutils  2.17cvs20070401
score-inst.h
Go to the documentation of this file.
00001 /* score-inst.h -- Score Instructions Table
00002    Copyright 2006 Free Software Foundation, Inc.
00003    Contributed by: 
00004    Mei Ligang (ligang@sunnorth.com.cn)
00005    Pei-Lin Tsai (pltsai@sunplus.com)
00006 
00007    This file is part of GAS, the GNU Assembler.
00008 
00009    GAS is free software; you can redistribute it and/or modify
00010    it under the terms of the GNU General Public License as published by
00011    the Free Software Foundation; either version 2, or (at your option)
00012    any later version.
00013 
00014    GAS is distributed in the hope that it will be useful,
00015    but WITHOUT ANY WARRANTY; without even the implied warranty of
00016    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017    GNU General Public License for more details.
00018 
00019    You should have received a copy of the GNU General Public License
00020    along with GAS; see the file COPYING.  If not, write to the Free
00021    Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
00022    02110-1301, USA.  */
00023 
00024 #ifndef SCORE_INST_H
00025 #define SCORE_INST_H
00026 
00027 #define LDST_UNALIGN_MASK 0x0000007f
00028 #define UA_LCB                0x00000060
00029 #define UA_LCW                0x00000062
00030 #define UA_LCE                0x00000066
00031 #define UA_SCB                0x00000068
00032 #define UA_SCW                0x0000006a
00033 #define UA_SCE                0x0000006e
00034 #define UA_LL          0x0000000c
00035 #define UA_SC          0x0000000e
00036 #define LDST16_RR_MASK   0x0000000f
00037 #define N16_LW           8
00038 #define N16_LH           9
00039 #define N16_POP          10
00040 #define N16_LBU          11
00041 #define N16_SW           12
00042 #define N16_SH           13
00043 #define N16_PUSH         14
00044 #define N16_SB           15
00045 #define LDST16_RI_MASK   0x7007
00046 #define N16_LWP          0x7000
00047 #define N16_LHP          0x7001
00048 #define N16_LBUP         0x7003
00049 #define N16_SWP          0x7004
00050 #define N16_SHP          0x7005
00051 #define N16_SBP          0x7007
00052 #define N16_LIU          0x5000
00053 
00054 #define OPC_PSEUDOLDST_MASK 0x00000007
00055 
00056 enum
00057 {
00058   INSN_LW = 0,
00059   INSN_LH = 1,
00060   INSN_LHU = 2,
00061   INSN_LB = 3,
00062   INSN_SW = 4,
00063   INSN_SH = 5,
00064   INSN_LBU = 6,
00065   INSN_SB = 7,
00066 };
00067 
00068 /* Sub opcdoe opcode.  */
00069 enum
00070 {
00071   INSN16_LBU = 11,
00072   INSN16_LH = 9,
00073   INSN16_LW = 8,
00074   INSN16_SB = 15,
00075   INSN16_SH = 13,
00076   INSN16_SW = 12,
00077 };
00078 
00079 enum
00080 {
00081   LDST_NOUPDATE = 0,
00082   LDST_PRE = 1,
00083   LDST_POST = 2,
00084 };
00085 
00086 enum score_insn_type
00087 {
00088   Rd_I4,
00089   Rd_I5,
00090   Rd_rvalueBP_I5,
00091   Rd_lvalueBP_I5,
00092   Rd_Rs_I5,
00093   x_Rs_I5,
00094   x_I5_x,
00095   Rd_I8,
00096   Rd_Rs_I14,
00097   I15,
00098   Rd_I16,
00099   Rd_rvalueRs_SI10,
00100   Rd_lvalueRs_SI10,
00101   Rd_rvalueRs_preSI12,
00102   Rd_rvalueRs_postSI12,
00103   Rd_lvalueRs_preSI12,
00104   Rd_lvalueRs_postSI12,
00105   Rd_Rs_SI14,
00106   Rd_rvalueRs_SI15,
00107   Rd_lvalueRs_SI15,
00108   Rd_SI16,
00109   PC_DISP8div2,
00110   PC_DISP11div2,
00111   PC_DISP19div2,
00112   PC_DISP24div2,
00113   Rd_Rs_Rs,
00114   x_Rs_x,
00115   x_Rs_Rs,
00116   Rd_Rs_x,
00117   Rd_x_Rs,
00118   Rd_x_x,
00119   Rd_Rs,
00120   Rd_HighRs,
00121   Rd_lvalueRs,
00122   Rd_rvalueRs,
00123   Rd_lvalue32Rs,
00124   Rd_rvalue32Rs,
00125   x_Rs,
00126   NO_OPD,
00127   NO16_OPD,
00128   OP5_rvalueRs_SI15,
00129   I5_Rs_Rs_I5_OP5,
00130   x_rvalueRs_post4,
00131   Rd_rvalueRs_post4,
00132   Rd_x_I5,
00133   Rd_lvalueRs_post4,
00134   x_lvalueRs_post4,
00135   Rd_LowRs,
00136   Rd_Rs_Rs_imm,
00137   Insn_Type_PCE,
00138   Insn_Type_SYN,
00139   Insn_GP,
00140   Insn_PIC,
00141   Insn_internal,
00142 };
00143 
00144 enum score_data_type
00145 {
00146   _IMM4 = 0,
00147   _IMM5,
00148   _IMM8,
00149   _IMM14,
00150   _IMM15,
00151   _IMM16,
00152   _SIMM10 = 6,
00153   _SIMM12,
00154   _SIMM14,
00155   _SIMM15,
00156   _SIMM16,
00157   _SIMM14_NEG = 11,
00158   _IMM16_NEG,
00159   _SIMM16_NEG,
00160   _IMM20,
00161   _IMM25,
00162   _DISP8div2 = 16,
00163   _DISP11div2,
00164   _DISP19div2,
00165   _DISP24div2,
00166   _VALUE,
00167   _VALUE_HI16,
00168   _VALUE_LO16,
00169   _VALUE_LDST_LO16 = 23,
00170   _SIMM16_LA,
00171   _IMM5_RSHIFT_1,
00172   _IMM5_RSHIFT_2,
00173   _SIMM16_LA_POS,
00174   _IMM5_RANGE_8_31,
00175   _IMM10_RSHIFT_2,
00176   _GP_IMM15 = 30,
00177   _GP_IMM14 = 31,
00178   _SIMM16_pic = 42,   /* Index in score_df_range.  */
00179   _IMM16_LO16_pic = 43,
00180   _IMM16_pic = 44,
00181 };
00182 
00183 #define REG_TMP                      1
00184 
00185 #define OP_REG_TYPE             (1 << 6)
00186 #define OP_IMM_TYPE             (1 << 7)
00187 #define OP_SH_REGD              (OP_REG_TYPE |20)
00188 #define       OP_SH_REGS1             (OP_REG_TYPE |15)
00189 #define OP_SH_REGS2             (OP_REG_TYPE |10)
00190 #define OP_SH_I                 (OP_IMM_TYPE | 1)
00191 #define OP_SH_RI15              (OP_IMM_TYPE | 0)
00192 #define OP_SH_I12               (OP_IMM_TYPE | 3)
00193 #define OP_SH_DISP24            (OP_IMM_TYPE | 1)
00194 #define OP_SH_DISP19_p1         (OP_IMM_TYPE |15)
00195 #define OP_SH_DISP19_p2         (OP_IMM_TYPE | 1)
00196 #define OP_SH_I5                (OP_IMM_TYPE |10)
00197 #define OP_SH_I10               (OP_IMM_TYPE | 5)
00198 #define OP_SH_COPID             (OP_IMM_TYPE | 5)
00199 #define OP_SH_TRAPI5            (OP_IMM_TYPE |15)
00200 #define OP_SH_I15               (OP_IMM_TYPE |10)
00201 
00202 #define OP16_SH_REGD            (OP_REG_TYPE | 8)
00203 #define       OP16_SH_REGS1           (OP_REG_TYPE | 4)
00204 #define       OP16_SH_I45             (OP_IMM_TYPE | 3)
00205 #define       OP16_SH_I8              (OP_IMM_TYPE | 0)
00206 #define OP16_SH_DISP8           (OP_IMM_TYPE | 0)
00207 #define OP16_SH_DISP11          (OP_IMM_TYPE | 1)
00208 
00209 struct datafield_range
00210 {
00211   int data_type;
00212   int bits;
00213   int range[2];
00214 };
00215 
00216 struct datafield_range score_df_range[] =
00217 {
00218   {_IMM4,             4,  {0, (1 << 4) - 1}},            /* (     0 ~ 15   ) */
00219   {_IMM5,             5,  {0, (1 << 5) - 1}},            /* (     0 ~ 31   ) */
00220   {_IMM8,             8,  {0, (1 << 8) - 1}},            /* (     0 ~ 255  ) */
00221   {_IMM14,            14, {0, (1 << 14) - 1}},           /* (     0 ~ 16383) */
00222   {_IMM15,            15, {0, (1 << 15) - 1}},           /* (     0 ~ 32767) */
00223   {_IMM16,            16, {0, (1 << 16) - 1}},           /* (     0 ~ 65535) */
00224   {_SIMM10,           10, {-(1 << 9), (1 << 9) - 1}},   /* (  -512 ~ 511  ) */
00225   {_SIMM12,           12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
00226   {_SIMM14,           14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
00227   {_SIMM15,           15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
00228   {_SIMM16,           16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
00229   {_SIMM14_NEG,       14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
00230   {_IMM16_NEG,        16, {0, (1 << 16) - 1}},           /* (-65535 ~ 0    ) */
00231   {_SIMM16_NEG,       16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
00232   {_IMM20,            20, {0, (1 << 20) - 1}},
00233   {_IMM25,            25, {0, (1 << 25) - 1}},
00234   {_DISP8div2,        8,  {-(1 << 8), (1 << 8) - 1}},   /* (  -256 ~ 255  ) */
00235   {_DISP11div2,       11, {0, 0}},
00236   {_DISP19div2,       19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
00237   {_DISP24div2,       24, {0, 0}},
00238   {_VALUE,            32, {0, ((unsigned int)1 << 31) - 1}},
00239   {_VALUE_HI16,       16, {0, (1 << 16) - 1}},
00240   {_VALUE_LO16,       16, {0, (1 << 16) - 1}},
00241   {_VALUE_LDST_LO16,  16, {0, (1 << 16) - 1}},
00242   {_SIMM16_LA,        16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
00243   {_IMM5_RSHIFT_1,    5,  {0, (1 << 6) - 1}},            /* (     0 ~ 63   ) */
00244   {_IMM5_RSHIFT_2,    5,  {0, (1 << 7) - 1}},            /* (     0 ~ 127  ) */
00245   {_SIMM16_LA_POS,    16, {0, (1 << 15) - 1}},           /* (     0 ~ 32767) */
00246   {_IMM5_RANGE_8_31,  5,  {8, 31}},                       /* But for cop0 the valid data : (8 ~ 31). */
00247   {_IMM10_RSHIFT_2,   10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
00248   {_SIMM10,           10, {0, (1 << 10) - 1}},           /* ( -1024 ~ 1023 ) */
00249   {_SIMM12,           12, {0, (1 << 12) - 1}},           /* ( -2048 ~ 2047 ) */
00250   {_SIMM14,           14, {0, (1 << 14) - 1}},          /* ( -8192 ~ 8191 ) */
00251   {_SIMM15,           15, {0, (1 << 15) - 1}},           /* (-16384 ~ 16383) */
00252   {_SIMM16,           16, {0, (1 << 16) - 1}},           /* (-65536 ~ 65536) */
00253   {_SIMM14_NEG,       14, {0, (1 << 16) - 1}},          /* ( -8191 ~ 8192 ) */
00254   {_IMM16_NEG,        16, {0, (1 << 16) - 1}},           /* ( 65535 ~ 0    ) */
00255   {_SIMM16_NEG,       16, {0, (1 << 16) - 1}},           /* ( 65535 ~ 0    ) */
00256   {_IMM20,            20, {0, (1 << 20) - 1}},           /* (-32768 ~ 32767) */
00257   {_IMM25,            25, {0, (1 << 25) - 1}},           /* (-32768 ~ 32767) */
00258   {_GP_IMM15,         15, {0, (1 << 15) - 1}},           /* (     0 ~ 65535) */
00259   {_GP_IMM14,         14, {0, (1 << 14) - 1}},           /* (     0 ~ 65535) */
00260   {_SIMM16_pic,       16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
00261   {_IMM16_LO16_pic,   16, {0, (1 << 16) - 1}},           /* ( 65535 ~ 0    ) */
00262   {_IMM16_pic,        16, {0, (1 << 16) - 1}},           /* (     0 ~ 65535) */
00263 };
00264 
00265 struct shift_bitmask
00266 {
00267   int opd_type;
00268   int opd_num;
00269   struct datafield_range *df_range;
00270   int sh[4];
00271   long fieldbits[4];
00272 };
00273 
00274 struct shift_bitmask score_sh_bits_map[] =
00275 {
00276   {
00277    Rd_I4, 2, &score_df_range[_IMM4],
00278    {OP16_SH_REGD, OP16_SH_I45, 0, 0},
00279    {0xf, 0xf, 0, 0},
00280    },
00281   {
00282    Rd_I5, 2, &score_df_range[_IMM5],
00283    {OP16_SH_REGD, OP16_SH_I45, 0, 0},
00284    {0xf, 0x1f, 0, 0},
00285    },
00286   {
00287    Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
00288    {OP16_SH_REGD, OP16_SH_I45, 0, 0},
00289    {0xf, 0x1f, 0, 0},
00290    },
00291   {
00292    Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
00293    {OP16_SH_REGD, OP16_SH_I45, 0, 0},
00294    {0xf, 0x1f, 0, 0},
00295    },
00296   {
00297    Rd_Rs_I5, 3, &score_df_range[_IMM5],
00298    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
00299    {0x1f, 0x1f, 0x1f, 0},
00300    },
00301   {
00302    x_Rs_I5, 2, &score_df_range[_IMM5],
00303    {OP_SH_REGS1, OP_SH_I5, 0, 0},
00304    {0x1f, 0x1f, 0, 0},
00305    },
00306   {
00307    x_I5_x, 1, &score_df_range[_IMM5],
00308    {OP_SH_TRAPI5, 0, 0, 0},
00309    {0x1f, 0, 0, 0},
00310    },
00311   {
00312    Rd_I8, 2, &score_df_range[_IMM8],
00313    {OP16_SH_REGD, OP16_SH_I8, 0, 0},
00314    {0xf, 0xff, 0, 0},
00315    },
00316   {
00317    Rd_Rs_I14, 3, &score_df_range[_IMM14],
00318    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
00319    {0x1f, 0x1f, 0x3fff, 0},
00320    },
00321   {
00322    I15, 1, &score_df_range[_IMM15],
00323    {OP_SH_I15, 0, 0, 0},
00324    {0x7fff, 0, 0, 0},
00325    },
00326   {
00327    Rd_I16, 2, &score_df_range[_IMM16],
00328    {OP_SH_REGD, OP_SH_I, 0, 0},
00329    {0x1f, 0xffff, 0, 0},
00330    },
00331   {
00332    Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
00333    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
00334    {0x1f, 0x1f, 0x3ff, 0},
00335    },
00336   {
00337    Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
00338    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
00339    {0x1f, 0x1f, 0x3ff, 0},
00340    },
00341   {
00342    Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
00343    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
00344    {0xf, 0xf, 0xfff, 0},
00345    },
00346   {
00347    Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
00348    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
00349    {0xf, 0xf, 0xfff, 0},
00350    },
00351   {
00352    Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
00353    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
00354    {0xf, 0xf, 0xfff, 0},
00355    },
00356   {
00357    Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
00358    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
00359    {0xf, 0xf, 0xfff, 0},
00360    },
00361   {
00362    Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
00363    {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
00364    {0x1f, 0x1f, 0x3fff, 0},
00365    },
00366   {
00367    Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
00368    {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
00369    {0x1f, 0x1f, 0x7fff, 0},
00370    },
00371   {
00372    Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
00373    {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
00374    {0x1f, 0x1f, 0x7fff, 0},
00375    },
00376   {
00377    Rd_SI16, 2, &score_df_range[_SIMM16],
00378    {OP_SH_REGD, OP_SH_I, 0, 0},
00379    {0x1f, 0xffff, 0, 0},
00380    },
00381   {
00382    PC_DISP8div2, 1, &score_df_range[_DISP8div2],
00383    {OP16_SH_DISP8, 0, 0, 0},
00384    {0xff, 0, 0, 0},
00385    },
00386   {
00387    PC_DISP11div2, 1, &score_df_range[_DISP11div2],
00388    {OP16_SH_DISP11, 0, 0, 0},
00389    {0x7ff, 0, 0, 0},
00390    },
00391   {
00392    PC_DISP19div2, 2, &score_df_range[_DISP19div2],
00393    {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
00394    {0x3ff, 0x1ff, 0, 0},
00395    },
00396   {
00397    PC_DISP24div2, 1, &score_df_range[_DISP24div2],
00398    {OP_SH_DISP24, 0, 0, 0},
00399    {0xffffff, 0, 0, 0},
00400    },
00401   {
00402    Rd_Rs_Rs, 3, NULL,
00403    {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
00404    {0x1f, 0x1f, 0x1f, 0}
00405    },
00406   {
00407    Rd_Rs_x, 2, NULL,
00408    {OP_SH_REGD, OP_SH_REGS1, 0, 0},
00409    {0x1f, 0x1f, 0, 0},
00410    },
00411   {
00412    Rd_x_Rs, 2, NULL,
00413    {OP_SH_REGD, OP_SH_REGS2, 0, 0},
00414    {0x1f, 0x1f, 0, 0},
00415    },
00416   {
00417    Rd_x_x, 1, NULL,
00418    {OP_SH_REGD, 0, 0, 0},
00419    {0x1f, 0, 0, 0},
00420    },
00421   {
00422    x_Rs_Rs, 2, NULL,
00423    {OP_SH_REGS1, OP_SH_REGS2, 0, 0},
00424    {0x1f, 0x1f, 0, 0},
00425    },
00426   {
00427    x_Rs_x, 1, NULL,
00428    {OP_SH_REGS1, 0, 0, 0},
00429    {0x1f, 0, 0, 0},
00430    },
00431   {
00432    Rd_Rs, 2, NULL,
00433    {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
00434    {0xf, 0xf, 0, 0},
00435    },
00436   {
00437    Rd_HighRs, 2, NULL,
00438    {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
00439    {0xf, 0xf, 0x1f, 0},
00440    },
00441   {
00442    Rd_rvalueRs, 2, NULL,
00443    {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
00444    {0xf, 0xf, 0, 0},
00445    },
00446   {
00447    Rd_lvalueRs, 2, NULL,
00448    {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
00449    {0xf, 0xf, 0, 0}
00450    },
00451    {
00452    Rd_lvalue32Rs, 2, NULL,
00453    {OP_SH_REGD, OP_SH_REGS1, 0, 0},
00454    {0x1f, 0x1f, 0, 0},
00455    },
00456    {
00457    Rd_rvalue32Rs, 2, NULL,
00458    {OP_SH_REGD, OP_SH_REGS1, 0, 0},
00459    {0x1f, 0x1f, 0, 0},
00460    },
00461   {
00462    x_Rs, 1, NULL,
00463    {OP16_SH_REGS1, 0, 0, 0},
00464    {0xf, 0, 0, 0},
00465    },
00466   {
00467    NO_OPD, 0, NULL,
00468    {0, 0, 0, 0},
00469    {0, 0, 0, 0},
00470    },
00471   {
00472    NO16_OPD, 0, NULL,
00473    {0, 0, 0, 0},
00474    {0, 0, 0, 0},
00475    },
00476 };
00477 
00478 struct asm_opcode
00479 {
00480   /* Instruction name.  */
00481   const char *template;
00482 
00483   /* Instruction Opcode.  */
00484   unsigned long value;
00485 
00486   /* Instruction bit mask.  */
00487   unsigned long bitmask;
00488 
00489   /* Relax instruction opcode.  0x8000 imply no relaxation.  */
00490   unsigned long relax_value;
00491 
00492   /* Instruction type.  */
00493   enum score_insn_type type;
00494 
00495   /* Function to call to parse args.  */
00496   void (*parms) (char *);
00497 };
00498 
00499 enum insn_class
00500 {
00501   INSN_CLASS_16,
00502   INSN_CLASS_32,
00503   INSN_CLASS_PCE,
00504   INSN_CLASS_SYN
00505 };
00506 
00507 #endif