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cell-binutils  2.17cvs20070401
Defines | Variables
s390-opc.c File Reference
#include <stdio.h>
#include "ansidecl.h"
#include "opcode/s390.h"
#include "s390-opc.tab"

Go to the source code of this file.

Defines

#define UNUSED   0
#define R_8   1 /* GPR starting at position 8 */
#define R_12   2 /* GPR starting at position 12 */
#define R_16   3 /* GPR starting at position 16 */
#define R_20   4 /* GPR starting at position 20 */
#define R_24   5 /* GPR starting at position 24 */
#define R_28   6 /* GPR starting at position 28 */
#define R_32   7 /* GPR starting at position 32 */
#define F_8   8 /* FPR starting at position 8 */
#define F_12   9 /* FPR starting at position 12 */
#define F_16   10 /* FPR starting at position 16 */
#define F_20   11 /* FPR starting at position 16 */
#define F_24   12 /* FPR starting at position 24 */
#define F_28   13 /* FPR starting at position 28 */
#define F_32   14 /* FPR starting at position 32 */
#define A_8   15 /* Access reg. starting at position 8 */
#define A_12   16 /* Access reg. starting at position 12 */
#define A_24   17 /* Access reg. starting at position 24 */
#define A_28   18 /* Access reg. starting at position 28 */
#define C_8   19 /* Control reg. starting at position 8 */
#define C_12   20 /* Control reg. starting at position 12 */
#define B_16   21 /* Base register starting at position 16 */
#define B_32   22 /* Base register starting at position 32 */
#define X_12   23 /* Index register starting at position 12 */
#define D_20   24 /* Displacement starting at position 20 */
#define D_36   25 /* Displacement starting at position 36 */
#define D20_20   26 /* 20 bit displacement starting at 20 */
#define L4_8   27 /* 4 bit length starting at position 8 */
#define L4_12   28 /* 4 bit length starting at position 12 */
#define L8_8   29 /* 8 bit length starting at position 8 */
#define U4_8   30 /* 4 bit unsigned value starting at 8 */
#define U4_12   31 /* 4 bit unsigned value starting at 12 */
#define U4_16   32 /* 4 bit unsigned value starting at 16 */
#define U4_20   33 /* 4 bit unsigned value starting at 20 */
#define U8_8   34 /* 8 bit unsigned value starting at 8 */
#define U8_16   35 /* 8 bit unsigned value starting at 16 */
#define I16_16   36 /* 16 bit signed value starting at 16 */
#define U16_16   37 /* 16 bit unsigned value starting at 16 */
#define J16_16   38 /* PC relative jump offset at 16 */
#define J32_16   39 /* PC relative long offset at 16 */
#define I32_16   40 /* 32 bit signed value starting at 16 */
#define U32_16   41 /* 32 bit unsigned value starting at 16 */
#define M_16   42 /* 4 bit optional mask starting at 16 */
#define RO_28   43 /* optional GPR starting at position 28 */
#define OP8(x)   { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define OP16(x)   { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
#define OP48(x)
#define INSTR_E   2, { 0,0,0,0,0,0 } /* e.g. pr */
#define INSTR_RIE_RRP   6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */
#define INSTR_RIL_0P   6, { J32_16,0,0,0,0 } /* e.g. jg */
#define INSTR_RIL_RP   6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */
#define INSTR_RIL_UP   6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */
#define INSTR_RIL_RI   6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */
#define INSTR_RIL_RU   6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */
#define INSTR_RI_0P   4, { J16_16,0,0,0,0,0 } /* e.g. j */
#define INSTR_RI_RI   4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */
#define INSTR_RI_RP   4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */
#define INSTR_RI_RU   4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */
#define INSTR_RI_UP   4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */
#define INSTR_RRE_00   4, { 0,0,0,0,0,0 } /* e.g. palb */
#define INSTR_RRE_0R   4, { R_28,0,0,0,0,0 } /* e.g. tb */
#define INSTR_RRE_AA   4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */
#define INSTR_RRE_AR   4, { A_24,R_28,0,0,0,0 } /* e.g. sar */
#define INSTR_RRE_F0   4, { F_24,0,0,0,0,0 } /* e.g. sqer */
#define INSTR_RRE_FF   4, { F_24,F_28,0,0,0,0 } /* e.g. debr */
#define INSTR_RRE_R0   4, { R_24,0,0,0,0,0 } /* e.g. ipm */
#define INSTR_RRE_RA   4, { R_24,A_28,0,0,0,0 } /* e.g. ear */
#define INSTR_RRE_RF   4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */
#define INSTR_RRE_RR   4, { R_24,R_28,0,0,0,0 } /* e.g. lura */
#define INSTR_RRE_FR   4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */
#define INSTR_RRE_RR_OPT   4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
#define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
#define INSTR_RRF_F0FF2   4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
#define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
#define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
#define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
#define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */
#define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
#define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
#define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
#define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */
#define INSTR_RRF_FFFU   4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */
#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */
#define INSTR_RR_0R   2, { R_12, 0,0,0,0,0 } /* e.g. br */
#define INSTR_RR_FF   2, { F_8,F_12,0,0,0,0 } /* e.g. adr */
#define INSTR_RR_R0   2, { R_8, 0,0,0,0,0 } /* e.g. spm */
#define INSTR_RR_RR   2, { R_8,R_12,0,0,0,0 } /* e.g. lr */
#define INSTR_RR_U0   2, { U8_8, 0,0,0,0,0 } /* e.g. svc */
#define INSTR_RR_UR   2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */
#define INSTR_RRR_F0FF   4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */
#define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */
#define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */
#define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */
#define INSTR_RSL_R0RD   6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */
#define INSTR_RSI_RRP   4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */
#define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */
#define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */
#define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */
#define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */
#define INSTR_RS_AARD   4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */
#define INSTR_RS_CCRD   4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */
#define INSTR_RS_R0RD   4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */
#define INSTR_RS_RRRD   4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */
#define INSTR_RS_RURD   4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */
#define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */
#define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */
#define INSTR_RXF_FRRDF   6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */
#define INSTR_RXF_RRRDR   6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */
#define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */
#define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
#define INSTR_RX_0RRD   4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
#define INSTR_RX_FRRD   4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
#define INSTR_RX_RRRD   4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */
#define INSTR_RX_URRD   4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */
#define INSTR_SI_URD   4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */
#define INSTR_SIY_URD   6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */
#define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */
#define INSTR_SS_L0RDRD   6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */
#define INSTR_SS_L2RDRD   6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */
#define INSTR_SS_LIRDRD   6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */
#define INSTR_SS_LLRDRD   6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */
#define INSTR_SS_RRRDRD   6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */
#define INSTR_SS_RRRDRD2   6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */
#define INSTR_SS_RRRDRD3   6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */
#define INSTR_S_00   4, { 0,0,0,0,0,0 } /* e.g. hsch */
#define INSTR_S_RD   4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */
#define INSTR_SSF_RRDRD   6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */
#define MASK_E   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIE_RRP   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RIL_0P   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_UP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RIL_RU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_0P   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_RU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RI_UP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRE_00   { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_RRE_0R   { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
#define MASK_RRE_AA   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_AR   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_F0   { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
#define MASK_RRE_FF   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_R0   { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
#define MASK_RRE_RA   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RF   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RR   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_FR   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRE_RR_OPT   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
#define MASK_RRF_F0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_F0FR   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_FUFF   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_RURR   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_R0RR   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_U0RF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RRF_UUFF   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_0UFF   { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }
#define MASK_RRF_FFFU   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRF_M0RR   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RR_0R   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_FF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_R0   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_RR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_U0   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RR_UR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RRR_F0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
#define MASK_RSE_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSE_CCRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSE_RURD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSL_R0RD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSI_RRP   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_AARD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_CCRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_R0RD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RS_RURD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RSY_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_RURD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_AARD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RSY_CCRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXE_FRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXE_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RXY_FRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_RX_0RRD   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_FRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_RX_URRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SI_URD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SIY_URD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
#define MASK_SSE_RDRD   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_L2RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_LLRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD2   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SS_RRRDRD3   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
#define MASK_S_00   { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
#define MASK_S_RD   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
#define MASK_SSF_RRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Variables

const int s390_num_opformats

Define Documentation

#define A_12   16 /* Access reg. starting at position 12 */
#define A_24   17 /* Access reg. starting at position 24 */
#define A_28   18 /* Access reg. starting at position 28 */
#define A_8   15 /* Access reg. starting at position 8 */
#define B_16   21 /* Base register starting at position 16 */
#define B_32   22 /* Base register starting at position 32 */
#define C_12   20 /* Control reg. starting at position 12 */
#define C_8   19 /* Control reg. starting at position 8 */
#define D20_20   26 /* 20 bit displacement starting at 20 */
#define D_20   24 /* Displacement starting at position 20 */
#define D_36   25 /* Displacement starting at position 36 */
#define F_12   9 /* FPR starting at position 12 */
#define F_16   10 /* FPR starting at position 16 */
#define F_20   11 /* FPR starting at position 16 */
#define F_24   12 /* FPR starting at position 24 */
#define F_28   13 /* FPR starting at position 28 */
#define F_32   14 /* FPR starting at position 32 */
#define F_8   8 /* FPR starting at position 8 */
#define I16_16   36 /* 16 bit signed value starting at 16 */
#define I32_16   40 /* 32 bit signed value starting at 16 */
#define INSTR_E   2, { 0,0,0,0,0,0 } /* e.g. pr */

Definition at line 186 of file s390-opc.c.

#define INSTR_RI_0P   4, { J16_16,0,0,0,0,0 } /* e.g. j */

Definition at line 193 of file s390-opc.c.

#define INSTR_RI_RI   4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */

Definition at line 194 of file s390-opc.c.

#define INSTR_RI_RP   4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */

Definition at line 195 of file s390-opc.c.

#define INSTR_RI_RU   4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */

Definition at line 196 of file s390-opc.c.

#define INSTR_RI_UP   4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */

Definition at line 197 of file s390-opc.c.

#define INSTR_RIE_RRP   6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */

Definition at line 187 of file s390-opc.c.

#define INSTR_RIL_0P   6, { J32_16,0,0,0,0 } /* e.g. jg */

Definition at line 188 of file s390-opc.c.

#define INSTR_RIL_RI   6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */

Definition at line 191 of file s390-opc.c.

#define INSTR_RIL_RP   6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */

Definition at line 189 of file s390-opc.c.

#define INSTR_RIL_RU   6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */

Definition at line 192 of file s390-opc.c.

#define INSTR_RIL_UP   6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */

Definition at line 190 of file s390-opc.c.

#define INSTR_RR_0R   2, { R_12, 0,0,0,0,0 } /* e.g. br */

Definition at line 224 of file s390-opc.c.

#define INSTR_RR_FF   2, { F_8,F_12,0,0,0,0 } /* e.g. adr */

Definition at line 225 of file s390-opc.c.

#define INSTR_RR_R0   2, { R_8, 0,0,0,0,0 } /* e.g. spm */

Definition at line 226 of file s390-opc.c.

#define INSTR_RR_RR   2, { R_8,R_12,0,0,0,0 } /* e.g. lr */

Definition at line 227 of file s390-opc.c.

#define INSTR_RR_U0   2, { U8_8, 0,0,0,0,0 } /* e.g. svc */

Definition at line 228 of file s390-opc.c.

#define INSTR_RR_UR   2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */

Definition at line 229 of file s390-opc.c.

#define INSTR_RRE_00   4, { 0,0,0,0,0,0 } /* e.g. palb */

Definition at line 198 of file s390-opc.c.

#define INSTR_RRE_0R   4, { R_28,0,0,0,0,0 } /* e.g. tb */

Definition at line 199 of file s390-opc.c.

#define INSTR_RRE_AA   4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */

Definition at line 200 of file s390-opc.c.

#define INSTR_RRE_AR   4, { A_24,R_28,0,0,0,0 } /* e.g. sar */

Definition at line 201 of file s390-opc.c.

#define INSTR_RRE_F0   4, { F_24,0,0,0,0,0 } /* e.g. sqer */

Definition at line 202 of file s390-opc.c.

#define INSTR_RRE_FF   4, { F_24,F_28,0,0,0,0 } /* e.g. debr */

Definition at line 203 of file s390-opc.c.

#define INSTR_RRE_FR   4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */

Definition at line 208 of file s390-opc.c.

#define INSTR_RRE_R0   4, { R_24,0,0,0,0,0 } /* e.g. ipm */

Definition at line 204 of file s390-opc.c.

#define INSTR_RRE_RA   4, { R_24,A_28,0,0,0,0 } /* e.g. ear */

Definition at line 205 of file s390-opc.c.

#define INSTR_RRE_RF   4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */

Definition at line 206 of file s390-opc.c.

#define INSTR_RRE_RR   4, { R_24,R_28,0,0,0,0 } /* e.g. lura */

Definition at line 207 of file s390-opc.c.

#define INSTR_RRE_RR_OPT   4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */

Definition at line 211 of file s390-opc.c.

#define INSTR_RRF_0UFF   4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */

Definition at line 221 of file s390-opc.c.

#define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */

Definition at line 212 of file s390-opc.c.

#define INSTR_RRF_F0FF2   4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */

Definition at line 213 of file s390-opc.c.

#define INSTR_RRF_F0FR   4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */

Definition at line 214 of file s390-opc.c.

#define INSTR_RRF_FFFU   4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */

Definition at line 222 of file s390-opc.c.

#define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */

Definition at line 215 of file s390-opc.c.

#define INSTR_RRF_M0RR   4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */

Definition at line 223 of file s390-opc.c.

#define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */

Definition at line 217 of file s390-opc.c.

#define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */

Definition at line 216 of file s390-opc.c.

#define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */

Definition at line 218 of file s390-opc.c.

#define INSTR_RRF_U0RF   4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */

Definition at line 219 of file s390-opc.c.

#define INSTR_RRF_UUFF   4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */

Definition at line 220 of file s390-opc.c.

#define INSTR_RRR_F0FF   4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */

Definition at line 230 of file s390-opc.c.

#define INSTR_RS_AARD   4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */

Definition at line 240 of file s390-opc.c.

#define INSTR_RS_CCRD   4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */

Definition at line 241 of file s390-opc.c.

#define INSTR_RS_R0RD   4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */

Definition at line 242 of file s390-opc.c.

#define INSTR_RS_RRRD   4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */

Definition at line 243 of file s390-opc.c.

#define INSTR_RS_RURD   4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */

Definition at line 244 of file s390-opc.c.

#define INSTR_RSE_CCRD   6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */

Definition at line 232 of file s390-opc.c.

#define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */

Definition at line 231 of file s390-opc.c.

#define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */

Definition at line 233 of file s390-opc.c.

#define INSTR_RSI_RRP   4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */

Definition at line 235 of file s390-opc.c.

#define INSTR_RSL_R0RD   6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */

Definition at line 234 of file s390-opc.c.

#define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */

Definition at line 238 of file s390-opc.c.

#define INSTR_RSY_CCRD   6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */

Definition at line 239 of file s390-opc.c.

#define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */

Definition at line 236 of file s390-opc.c.

#define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */

Definition at line 237 of file s390-opc.c.

#define INSTR_RX_0RRD   4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */

Definition at line 251 of file s390-opc.c.

#define INSTR_RX_FRRD   4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */

Definition at line 252 of file s390-opc.c.

#define INSTR_RX_RRRD   4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */

Definition at line 253 of file s390-opc.c.

#define INSTR_RX_URRD   4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */

Definition at line 254 of file s390-opc.c.

#define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */

Definition at line 245 of file s390-opc.c.

#define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */

Definition at line 246 of file s390-opc.c.

#define INSTR_RXF_FRRDF   6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */

Definition at line 247 of file s390-opc.c.

#define INSTR_RXF_RRRDR   6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */

Definition at line 248 of file s390-opc.c.

#define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */

Definition at line 250 of file s390-opc.c.

#define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */

Definition at line 249 of file s390-opc.c.

#define INSTR_S_00   4, { 0,0,0,0,0,0 } /* e.g. hsch */

Definition at line 265 of file s390-opc.c.

#define INSTR_S_RD   4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */

Definition at line 266 of file s390-opc.c.

#define INSTR_SI_URD   4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */

Definition at line 255 of file s390-opc.c.

#define INSTR_SIY_URD   6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */

Definition at line 256 of file s390-opc.c.

#define INSTR_SS_L0RDRD   6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */

Definition at line 258 of file s390-opc.c.

#define INSTR_SS_L2RDRD   6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */

Definition at line 259 of file s390-opc.c.

#define INSTR_SS_LIRDRD   6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */

Definition at line 260 of file s390-opc.c.

#define INSTR_SS_LLRDRD   6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */

Definition at line 261 of file s390-opc.c.

#define INSTR_SS_RRRDRD   6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */

Definition at line 262 of file s390-opc.c.

#define INSTR_SS_RRRDRD2   6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */

Definition at line 263 of file s390-opc.c.

#define INSTR_SS_RRRDRD3   6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */

Definition at line 264 of file s390-opc.c.

#define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */

Definition at line 257 of file s390-opc.c.

#define INSTR_SSF_RRDRD   6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */

Definition at line 267 of file s390-opc.c.

#define J16_16   38 /* PC relative jump offset at 16 */
#define J32_16   39 /* PC relative long offset at 16 */
#define L4_12   28 /* 4 bit length starting at position 12 */
#define L4_8   27 /* 4 bit length starting at position 8 */
#define L8_8   29 /* 8 bit length starting at position 8 */
#define M_16   42 /* 4 bit optional mask starting at 16 */
#define MASK_E   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 269 of file s390-opc.c.

#define MASK_RI_0P   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 276 of file s390-opc.c.

#define MASK_RI_RI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 277 of file s390-opc.c.

#define MASK_RI_RP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 278 of file s390-opc.c.

#define MASK_RI_RU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 279 of file s390-opc.c.

#define MASK_RI_UP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 280 of file s390-opc.c.

#define MASK_RIE_RRP   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 270 of file s390-opc.c.

#define MASK_RIL_0P   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 271 of file s390-opc.c.

#define MASK_RIL_RI   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 274 of file s390-opc.c.

#define MASK_RIL_RP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 272 of file s390-opc.c.

#define MASK_RIL_RU   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 275 of file s390-opc.c.

#define MASK_RIL_UP   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 273 of file s390-opc.c.

#define MASK_RR_0R   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }

Definition at line 305 of file s390-opc.c.

#define MASK_RR_FF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 306 of file s390-opc.c.

#define MASK_RR_R0   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 307 of file s390-opc.c.

#define MASK_RR_RR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 308 of file s390-opc.c.

#define MASK_RR_U0   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 309 of file s390-opc.c.

#define MASK_RR_UR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 310 of file s390-opc.c.

#define MASK_RRE_00   { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }

Definition at line 281 of file s390-opc.c.

#define MASK_RRE_0R   { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }

Definition at line 282 of file s390-opc.c.

#define MASK_RRE_AA   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 283 of file s390-opc.c.

#define MASK_RRE_AR   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 284 of file s390-opc.c.

#define MASK_RRE_F0   { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }

Definition at line 285 of file s390-opc.c.

#define MASK_RRE_FF   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 286 of file s390-opc.c.

#define MASK_RRE_FR   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 291 of file s390-opc.c.

#define MASK_RRE_R0   { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }

Definition at line 287 of file s390-opc.c.

#define MASK_RRE_RA   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 288 of file s390-opc.c.

#define MASK_RRE_RF   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 289 of file s390-opc.c.

#define MASK_RRE_RR   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 290 of file s390-opc.c.

#define MASK_RRE_RR_OPT   { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }

Definition at line 292 of file s390-opc.c.

#define MASK_RRF_0UFF   { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 }

Definition at line 302 of file s390-opc.c.

#define MASK_RRF_F0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 293 of file s390-opc.c.

#define MASK_RRF_F0FF2   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 294 of file s390-opc.c.

#define MASK_RRF_F0FR   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 295 of file s390-opc.c.

#define MASK_RRF_FFFU   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 303 of file s390-opc.c.

#define MASK_RRF_FUFF   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 296 of file s390-opc.c.

#define MASK_RRF_M0RR   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 304 of file s390-opc.c.

#define MASK_RRF_R0RR   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 298 of file s390-opc.c.

#define MASK_RRF_RURR   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 297 of file s390-opc.c.

#define MASK_RRF_U0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 299 of file s390-opc.c.

#define MASK_RRF_U0RF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 300 of file s390-opc.c.

#define MASK_RRF_UUFF   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 301 of file s390-opc.c.

#define MASK_RRR_F0FF   { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }

Definition at line 311 of file s390-opc.c.

#define MASK_RS_AARD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 317 of file s390-opc.c.

#define MASK_RS_CCRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 318 of file s390-opc.c.

#define MASK_RS_R0RD   { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }

Definition at line 319 of file s390-opc.c.

#define MASK_RS_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 320 of file s390-opc.c.

#define MASK_RS_RURD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 321 of file s390-opc.c.

#define MASK_RSE_CCRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 313 of file s390-opc.c.

#define MASK_RSE_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 312 of file s390-opc.c.

#define MASK_RSE_RURD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 314 of file s390-opc.c.

#define MASK_RSI_RRP   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 316 of file s390-opc.c.

#define MASK_RSL_R0RD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 315 of file s390-opc.c.

#define MASK_RSY_AARD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 324 of file s390-opc.c.

#define MASK_RSY_CCRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 325 of file s390-opc.c.

#define MASK_RSY_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 322 of file s390-opc.c.

#define MASK_RSY_RURD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 323 of file s390-opc.c.

#define MASK_RX_0RRD   { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }

Definition at line 332 of file s390-opc.c.

#define MASK_RX_FRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 333 of file s390-opc.c.

#define MASK_RX_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 334 of file s390-opc.c.

#define MASK_RX_URRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 335 of file s390-opc.c.

#define MASK_RXE_FRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 326 of file s390-opc.c.

#define MASK_RXE_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 327 of file s390-opc.c.

#define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 328 of file s390-opc.c.

#define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 329 of file s390-opc.c.

#define MASK_RXY_FRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 331 of file s390-opc.c.

#define MASK_RXY_RRRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 330 of file s390-opc.c.

#define MASK_S_00   { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }

Definition at line 346 of file s390-opc.c.

#define MASK_S_RD   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 347 of file s390-opc.c.

#define MASK_SI_URD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 336 of file s390-opc.c.

#define MASK_SIY_URD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }

Definition at line 337 of file s390-opc.c.

#define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 339 of file s390-opc.c.

#define MASK_SS_L2RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 340 of file s390-opc.c.

#define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 341 of file s390-opc.c.

#define MASK_SS_LLRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 342 of file s390-opc.c.

#define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 343 of file s390-opc.c.

#define MASK_SS_RRRDRD2   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 344 of file s390-opc.c.

#define MASK_SS_RRRDRD3   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 345 of file s390-opc.c.

#define MASK_SSE_RDRD   { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }

Definition at line 338 of file s390-opc.c.

#define MASK_SSF_RRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 348 of file s390-opc.c.

#define OP16 (   x)    { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }

Definition at line 147 of file s390-opc.c.

#define OP48 (   x)
Value:
{ x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
                  (x >> 16) & 255, (x >> 8) & 255, x & 255}

Definition at line 148 of file s390-opc.c.

#define OP8 (   x)    { x, 0x00, 0x00, 0x00, 0x00, 0x00 }

Definition at line 146 of file s390-opc.c.

#define R_12   2 /* GPR starting at position 12 */
#define R_16   3 /* GPR starting at position 16 */
#define R_20   4 /* GPR starting at position 20 */
#define R_24   5 /* GPR starting at position 24 */
#define R_28   6 /* GPR starting at position 28 */
#define R_32   7 /* GPR starting at position 32 */
#define R_8   1 /* GPR starting at position 8 */
#define RO_28   43 /* optional GPR starting at position 28 */
#define U16_16   37 /* 16 bit unsigned value starting at 16 */
#define U32_16   41 /* 32 bit unsigned value starting at 16 */
#define U4_12   31 /* 4 bit unsigned value starting at 12 */
#define U4_16   32 /* 4 bit unsigned value starting at 16 */
#define U4_20   33 /* 4 bit unsigned value starting at 20 */
#define U4_8   30 /* 4 bit unsigned value starting at 8 */
#define U8_16   35 /* 8 bit unsigned value starting at 16 */
#define U8_8   34 /* 8 bit unsigned value starting at 8 */
#define UNUSED   0
#define X_12   23 /* Index register starting at position 12 */

Variable Documentation

Initial value:
  sizeof (s390_opformats) / sizeof (s390_opformats[0])

Definition at line 378 of file s390-opc.c.