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cell-binutils  2.17cvs20070401
rol64.d
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00001 #objdump: -dr --prefix-addresses
00002 #name: MIPS macro drol/dror
00003 
00004 # Test the drol and dror macros.
00005 
00006 .*: +file format .*mips.*
00007 
00008 Disassembly of section .text:
00009 0+0000 <[^>]*> dnegu at,a1
00010 0+0004 <[^>]*> dsrlv at,a0,at
00011 0+0008 <[^>]*> dsllv a0,a0,a1
00012 0+000c <[^>]*> or    a0,a0,at
00013 0+0010 <[^>]*> dnegu at,a2
00014 0+0014 <[^>]*> dsrlv at,a1,at
00015 0+0018 <[^>]*> dsllv a0,a1,a2
00016 0+001c <[^>]*> or    a0,a0,at
00017 0+0020 <[^>]*> dsll  at,a0,0x1
00018 0+0024 <[^>]*> dsrl32       a0,a0,0x1f
00019 0+0028 <[^>]*> or    a0,a0,at
00020 0+002c <[^>]*> dsrl  a0,a1,0x0
00021 0+0030 <[^>]*> dsll  at,a1,0x1
00022 0+0034 <[^>]*> dsrl32       a0,a1,0x1f
00023 0+0038 <[^>]*> or    a0,a0,at
00024 0+003c <[^>]*> dsll  at,a1,0x1f
00025 0+0040 <[^>]*> dsrl32       a0,a1,0x1
00026 0+0044 <[^>]*> or    a0,a0,at
00027 0+0048 <[^>]*> dsll32       at,a1,0x0
00028 0+004c <[^>]*> dsrl32       a0,a1,0x0
00029 0+0050 <[^>]*> or    a0,a0,at
00030 0+0054 <[^>]*> dsll32       at,a1,0x1
00031 0+0058 <[^>]*> dsrl  a0,a1,0x1f
00032 0+005c <[^>]*> or    a0,a0,at
00033 0+0060 <[^>]*> dsll32       at,a1,0x1f
00034 0+0064 <[^>]*> dsrl  a0,a1,0x1
00035 0+0068 <[^>]*> or    a0,a0,at
00036 0+006c <[^>]*> dsrl  a0,a1,0x0
00037 0+0070 <[^>]*> dnegu at,a1
00038 0+0074 <[^>]*> dsllv at,a0,at
00039 0+0078 <[^>]*> dsrlv a0,a0,a1
00040 0+007c <[^>]*> or    a0,a0,at
00041 0+0080 <[^>]*> dnegu at,a2
00042 0+0084 <[^>]*> dsllv at,a1,at
00043 0+0088 <[^>]*> dsrlv a0,a1,a2
00044 0+008c <[^>]*> or    a0,a0,at
00045 0+0090 <[^>]*> dsrl  at,a0,0x1
00046 0+0094 <[^>]*> dsll32       a0,a0,0x1f
00047 0+0098 <[^>]*> or    a0,a0,at
00048 0+009c <[^>]*> dsrl  a0,a1,0x0
00049 0+00a0 <[^>]*> dsrl  at,a1,0x1
00050 0+00a4 <[^>]*> dsll32       a0,a1,0x1f
00051 0+00a8 <[^>]*> or    a0,a0,at
00052 0+00ac <[^>]*> dsrl  at,a1,0x1f
00053 0+00b0 <[^>]*> dsll32       a0,a1,0x1
00054 0+00b4 <[^>]*> or    a0,a0,at
00055 0+00b8 <[^>]*> dsrl32       at,a1,0x0
00056 0+00bc <[^>]*> dsll32       a0,a1,0x0
00057 0+00c0 <[^>]*> or    a0,a0,at
00058 0+00c4 <[^>]*> dsrl32       at,a1,0x1
00059 0+00c8 <[^>]*> dsll  a0,a1,0x1f
00060 0+00cc <[^>]*> or    a0,a0,at
00061 0+00d0 <[^>]*> dsrl32       at,a1,0x1f
00062 0+00d4 <[^>]*> dsll  a0,a1,0x1
00063 0+00d8 <[^>]*> or    a0,a0,at
00064 0+00dc <[^>]*> dsrl  a0,a1,0x0
00065 0+00e0 <[^>]*> dsll  at,a1,0x1
00066 0+00e4 <[^>]*> dsrl32       a0,a1,0x1f
00067 0+00e8 <[^>]*> or    a0,a0,at
00068 0+00ec <[^>]*> dsll  at,a1,0x1f
00069 0+00f0 <[^>]*> dsrl32       a0,a1,0x1
00070 0+00f4 <[^>]*> or    a0,a0,at
00071 0+00f8 <[^>]*> dsll32       at,a1,0x0
00072 0+00fc <[^>]*> dsrl32       a0,a1,0x0
00073 0+0100 <[^>]*> or    a0,a0,at
00074 0+0104 <[^>]*> dsll32       at,a1,0x1
00075 0+0108 <[^>]*> dsrl  a0,a1,0x1f
00076 0+010c <[^>]*> or    a0,a0,at
00077 0+0110 <[^>]*> dsll32       at,a1,0x1f
00078 0+0114 <[^>]*> dsrl  a0,a1,0x1
00079 0+0118 <[^>]*> or    a0,a0,at
00080 0+011c <[^>]*> dsrl  at,a1,0x1
00081 0+0120 <[^>]*> dsll32       a0,a1,0x1f
00082 0+0124 <[^>]*> or    a0,a0,at
00083 0+0128 <[^>]*> dsrl  at,a1,0x1f
00084 0+012c <[^>]*> dsll32       a0,a1,0x1
00085 0+0130 <[^>]*> or    a0,a0,at
00086 0+0134 <[^>]*> dsrl32       at,a1,0x0
00087 0+0138 <[^>]*> dsll32       a0,a1,0x0
00088 0+013c <[^>]*> or    a0,a0,at
00089 0+0140 <[^>]*> dsrl32       at,a1,0x1
00090 0+0144 <[^>]*> dsll  a0,a1,0x1f
00091 0+0148 <[^>]*> or    a0,a0,at
00092 0+014c <[^>]*> dsrl32       at,a1,0x1f
00093 0+0150 <[^>]*> dsll  a0,a1,0x1
00094 0+0154 <[^>]*> or    a0,a0,at
00095        ...