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ppc-opc.c
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00001 /* ppc-opc.c -- PowerPC opcode list
00002    Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
00003    2005, 2006, 2007 Free Software Foundation, Inc.
00004    Written by Ian Lance Taylor, Cygnus Support
00005 
00006    This file is part of GDB, GAS, and the GNU binutils.
00007 
00008    GDB, GAS, and the GNU binutils are free software; you can redistribute
00009    them and/or modify them under the terms of the GNU General Public
00010    License as published by the Free Software Foundation; either version
00011    2, or (at your option) any later version.
00012 
00013    GDB, GAS, and the GNU binutils are distributed in the hope that they
00014    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016    the GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with this file; see the file COPYING.  If not, write to the Free
00020    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00021    02110-1301, USA.  */
00022 
00023 #include <stdio.h>
00024 #include "sysdep.h"
00025 #include "opcode/ppc.h"
00026 #include "opintl.h"
00027 
00028 /* This file holds the PowerPC opcode table.  The opcode table
00029    includes almost all of the extended instruction mnemonics.  This
00030    permits the disassembler to use them, and simplifies the assembler
00031    logic, at the cost of increasing the table size.  The table is
00032    strictly constant data, so the compiler should be able to put it in
00033    the .text section.
00034 
00035    This file also holds the operand table.  All knowledge about
00036    inserting operands into instructions and vice-versa is kept in this
00037    file.  */
00038 
00039 /* Local insertion and extraction functions.  */
00040 
00041 static unsigned long insert_bat (unsigned long, long, int, const char **);
00042 static long extract_bat (unsigned long, int, int *);
00043 static unsigned long insert_bba (unsigned long, long, int, const char **);
00044 static long extract_bba (unsigned long, int, int *);
00045 static unsigned long insert_bd (unsigned long, long, int, const char **);
00046 static long extract_bd (unsigned long, int, int *);
00047 static unsigned long insert_bdm (unsigned long, long, int, const char **);
00048 static long extract_bdm (unsigned long, int, int *);
00049 static unsigned long insert_bdp (unsigned long, long, int, const char **);
00050 static long extract_bdp (unsigned long, int, int *);
00051 static unsigned long insert_bo (unsigned long, long, int, const char **);
00052 static long extract_bo (unsigned long, int, int *);
00053 static unsigned long insert_boe (unsigned long, long, int, const char **);
00054 static long extract_boe (unsigned long, int, int *);
00055 static unsigned long insert_dq (unsigned long, long, int, const char **);
00056 static long extract_dq (unsigned long, int, int *);
00057 static unsigned long insert_ds (unsigned long, long, int, const char **);
00058 static long extract_ds (unsigned long, int, int *);
00059 static unsigned long insert_de (unsigned long, long, int, const char **);
00060 static long extract_de (unsigned long, int, int *);
00061 static unsigned long insert_des (unsigned long, long, int, const char **);
00062 static long extract_des (unsigned long, int, int *);
00063 static unsigned long insert_fxm (unsigned long, long, int, const char **);
00064 static long extract_fxm (unsigned long, int, int *);
00065 static unsigned long insert_li (unsigned long, long, int, const char **);
00066 static long extract_li (unsigned long, int, int *);
00067 static unsigned long insert_mbe (unsigned long, long, int, const char **);
00068 static long extract_mbe (unsigned long, int, int *);
00069 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
00070 static long extract_mb6 (unsigned long, int, int *);
00071 static unsigned long insert_nb (unsigned long, long, int, const char **);
00072 static long extract_nb (unsigned long, int, int *);
00073 static unsigned long insert_nsi (unsigned long, long, int, const char **);
00074 static long extract_nsi (unsigned long, int, int *);
00075 static unsigned long insert_ral (unsigned long, long, int, const char **);
00076 static unsigned long insert_ram (unsigned long, long, int, const char **);
00077 static unsigned long insert_raq (unsigned long, long, int, const char **);
00078 static unsigned long insert_ras (unsigned long, long, int, const char **);
00079 static unsigned long insert_rbs (unsigned long, long, int, const char **);
00080 static long extract_rbs (unsigned long, int, int *);
00081 static unsigned long insert_rsq (unsigned long, long, int, const char **);
00082 static unsigned long insert_rtq (unsigned long, long, int, const char **);
00083 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
00084 static long extract_sh6 (unsigned long, int, int *);
00085 static unsigned long insert_spr (unsigned long, long, int, const char **);
00086 static long extract_spr (unsigned long, int, int *);
00087 static unsigned long insert_sprg (unsigned long, long, int, const char **);
00088 static long extract_sprg (unsigned long, int, int *);
00089 static unsigned long insert_tbr (unsigned long, long, int, const char **);
00090 static long extract_tbr (unsigned long, int, int *);
00091 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
00092 static long extract_ev2 (unsigned long, int, int *);
00093 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
00094 static long extract_ev4 (unsigned long, int, int *);
00095 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
00096 static long extract_ev8 (unsigned long, int, int *);
00097 
00098 /* The operands table.
00099 
00100    The fields are bits, shift, insert, extract, flags.
00101 
00102    We used to put parens around the various additions, like the one
00103    for BA just below.  However, that caused trouble with feeble
00104    compilers with a limit on depth of a parenthesized expression, like
00105    (reportedly) the compiler in Microsoft Developer Studio 5.  So we
00106    omit the parens, since the macros are never used in a context where
00107    the addition will be ambiguous.  */
00108 
00109 const struct powerpc_operand powerpc_operands[] =
00110 {
00111   /* The zero index is used to indicate the end of the list of
00112      operands.  */
00113 #define UNUSED 0
00114   { 0, 0, NULL, NULL, 0 },
00115 
00116   /* The BA field in an XL form instruction.  */
00117 #define BA UNUSED + 1
00118 #define BA_MASK (0x1f << 16)
00119   { 5, 16, NULL, NULL, PPC_OPERAND_CR },
00120 
00121   /* The BA field in an XL form instruction when it must be the same
00122      as the BT field in the same instruction.  */
00123 #define BAT BA + 1
00124   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
00125 
00126   /* The BB field in an XL form instruction.  */
00127 #define BB BAT + 1
00128 #define BB_MASK (0x1f << 11)
00129   { 5, 11, NULL, NULL, PPC_OPERAND_CR },
00130 
00131   /* The BB field in an XL form instruction when it must be the same
00132      as the BA field in the same instruction.  */
00133 #define BBA BB + 1
00134   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
00135 
00136   /* The BD field in a B form instruction.  The lower two bits are
00137      forced to zero.  */
00138 #define BD BBA + 1
00139   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00140 
00141   /* The BD field in a B form instruction when absolute addressing is
00142      used.  */
00143 #define BDA BD + 1
00144   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00145 
00146   /* The BD field in a B form instruction when the - modifier is used.
00147      This sets the y bit of the BO field appropriately.  */
00148 #define BDM BDA + 1
00149   { 16, 0, insert_bdm, extract_bdm,
00150       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00151 
00152   /* The BD field in a B form instruction when the - modifier is used
00153      and absolute address is used.  */
00154 #define BDMA BDM + 1
00155   { 16, 0, insert_bdm, extract_bdm,
00156       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00157 
00158   /* The BD field in a B form instruction when the + modifier is used.
00159      This sets the y bit of the BO field appropriately.  */
00160 #define BDP BDMA + 1
00161   { 16, 0, insert_bdp, extract_bdp,
00162       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00163 
00164   /* The BD field in a B form instruction when the + modifier is used
00165      and absolute addressing is used.  */
00166 #define BDPA BDP + 1
00167   { 16, 0, insert_bdp, extract_bdp,
00168       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00169 
00170   /* The BF field in an X or XL form instruction.  */
00171 #define BF BDPA + 1
00172   { 3, 23, NULL, NULL, PPC_OPERAND_CR },
00173 
00174   /* An optional BF field.  This is used for comparison instructions,
00175      in which an omitted BF field is taken as zero.  */
00176 #define OBF BF + 1
00177   { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
00178 
00179   /* The BFA field in an X or XL form instruction.  */
00180 #define BFA OBF + 1
00181   { 3, 18, NULL, NULL, PPC_OPERAND_CR },
00182 
00183   /* The BI field in a B form or XL form instruction.  */
00184 #define BI BFA + 1
00185 #define BI_MASK (0x1f << 16)
00186   { 5, 16, NULL, NULL, PPC_OPERAND_CR },
00187 
00188   /* The BO field in a B form instruction.  Certain values are
00189      illegal.  */
00190 #define BO BI + 1
00191 #define BO_MASK (0x1f << 21)
00192   { 5, 21, insert_bo, extract_bo, 0 },
00193 
00194   /* The BO field in a B form instruction when the + or - modifier is
00195      used.  This is like the BO field, but it must be even.  */
00196 #define BOE BO + 1
00197   { 5, 21, insert_boe, extract_boe, 0 },
00198 
00199 #define BH BOE + 1
00200   { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
00201 
00202   /* The BT field in an X or XL form instruction.  */
00203 #define BT BH + 1
00204   { 5, 21, NULL, NULL, PPC_OPERAND_CR },
00205 
00206   /* The condition register number portion of the BI field in a B form
00207      or XL form instruction.  This is used for the extended
00208      conditional branch mnemonics, which set the lower two bits of the
00209      BI field.  This field is optional.  */
00210 #define CR BT + 1
00211   { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
00212 
00213   /* The CRB field in an X form instruction.  */
00214 #define CRB CR + 1
00215   { 5, 6, NULL, NULL, 0 },
00216 
00217   /* The CRFD field in an X form instruction.  */
00218 #define CRFD CRB + 1
00219   { 3, 23, NULL, NULL, PPC_OPERAND_CR },
00220 
00221   /* The CRFS field in an X form instruction.  */
00222 #define CRFS CRFD + 1
00223   { 3, 0, NULL, NULL, PPC_OPERAND_CR },
00224 
00225   /* The CT field in an X form instruction.  */
00226 #define CT CRFS + 1
00227   { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
00228 
00229   /* The D field in a D form instruction.  This is a displacement off
00230      a register, and implies that the next operand is a register in
00231      parentheses.  */
00232 #define D CT + 1
00233   { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
00234 
00235   /* The DE field in a DE form instruction.  This is like D, but is 12
00236      bits only.  */
00237 #define DE D + 1
00238   { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
00239 
00240   /* The DES field in a DES form instruction.  This is like DS, but is 14
00241      bits only (12 stored.)  */
00242 #define DES DE + 1
00243   { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
00244 
00245   /* The DQ field in a DQ form instruction.  This is like D, but the
00246      lower four bits are forced to zero. */
00247 #define DQ DES + 1
00248   { 16, 0, insert_dq, extract_dq,
00249       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
00250 
00251   /* The DS field in a DS form instruction.  This is like D, but the
00252      lower two bits are forced to zero.  */
00253 #define DS DQ + 1
00254   { 16, 0, insert_ds, extract_ds,
00255       PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
00256 
00257   /* The E field in a wrteei instruction.  */
00258 #define E DS + 1
00259   { 1, 15, NULL, NULL, 0 },
00260 
00261   /* The FL1 field in a POWER SC form instruction.  */
00262 #define FL1 E + 1
00263   { 4, 12, NULL, NULL, 0 },
00264 
00265   /* The FL2 field in a POWER SC form instruction.  */
00266 #define FL2 FL1 + 1
00267   { 3, 2, NULL, NULL, 0 },
00268 
00269   /* The FLM field in an XFL form instruction.  */
00270 #define FLM FL2 + 1
00271   { 8, 17, NULL, NULL, 0 },
00272 
00273   /* The FRA field in an X or A form instruction.  */
00274 #define FRA FLM + 1
00275 #define FRA_MASK (0x1f << 16)
00276   { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
00277 
00278   /* The FRB field in an X or A form instruction.  */
00279 #define FRB FRA + 1
00280 #define FRB_MASK (0x1f << 11)
00281   { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
00282 
00283   /* The FRC field in an A form instruction.  */
00284 #define FRC FRB + 1
00285 #define FRC_MASK (0x1f << 6)
00286   { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
00287 
00288   /* The FRS field in an X form instruction or the FRT field in a D, X
00289      or A form instruction.  */
00290 #define FRS FRC + 1
00291 #define FRT FRS
00292   { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
00293 
00294   /* The FXM field in an XFX instruction.  */
00295 #define FXM FRS + 1
00296 #define FXM_MASK (0xff << 12)
00297   { 8, 12, insert_fxm, extract_fxm, 0 },
00298 
00299   /* Power4 version for mfcr.  */
00300 #define FXM4 FXM + 1
00301   { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
00302 
00303   /* The L field in a D or X form instruction.  */
00304 #define L FXM4 + 1
00305   { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
00306 
00307   /* The LEV field in a POWER SVC form instruction.  */
00308 #define SVC_LEV L + 1
00309   { 7, 5, NULL, NULL, 0 },
00310 
00311   /* The LEV field in an SC form instruction.  */
00312 #define LEV SVC_LEV + 1
00313   { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
00314 
00315   /* The LI field in an I form instruction.  The lower two bits are
00316      forced to zero.  */
00317 #define LI LEV + 1
00318   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
00319 
00320   /* The LI field in an I form instruction when used as an absolute
00321      address.  */
00322 #define LIA LI + 1
00323   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
00324 
00325   /* The LS field in an X (sync) form instruction.  */
00326 #define LS LIA + 1
00327   { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
00328 
00329   /* The MB field in an M form instruction.  */
00330 #define MB LS + 1
00331 #define MB_MASK (0x1f << 6)
00332   { 5, 6, NULL, NULL, 0 },
00333 
00334   /* The ME field in an M form instruction.  */
00335 #define ME MB + 1
00336 #define ME_MASK (0x1f << 1)
00337   { 5, 1, NULL, NULL, 0 },
00338 
00339   /* The MB and ME fields in an M form instruction expressed a single
00340      operand which is a bitmask indicating which bits to select.  This
00341      is a two operand form using PPC_OPERAND_NEXT.  See the
00342      description in opcode/ppc.h for what this means.  */
00343 #define MBE ME + 1
00344   { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
00345   { 32, 0, insert_mbe, extract_mbe, 0 },
00346 
00347   /* The MB or ME field in an MD or MDS form instruction.  The high
00348      bit is wrapped to the low end.  */
00349 #define MB6 MBE + 2
00350 #define ME6 MB6
00351 #define MB6_MASK (0x3f << 5)
00352   { 6, 5, insert_mb6, extract_mb6, 0 },
00353 
00354   /* The MO field in an mbar instruction.  */
00355 #define MO MB6 + 1
00356   { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
00357 
00358   /* The NB field in an X form instruction.  The value 32 is stored as
00359      0.  */
00360 #define NB MO + 1
00361   { 6, 11, insert_nb, extract_nb, 0 },
00362 
00363   /* The NSI field in a D form instruction.  This is the same as the
00364      SI field, only negated.  */
00365 #define NSI NB + 1
00366   { 16, 0, insert_nsi, extract_nsi,
00367       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
00368 
00369   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
00370 #define RA NSI + 1
00371 #define RA_MASK (0x1f << 16)
00372   { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
00373 
00374   /* As above, but 0 in the RA field means zero, not r0.  */
00375 #define RA0 RA + 1
00376   { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
00377 
00378   /* The RA field in the DQ form lq instruction, which has special
00379      value restrictions.  */
00380 #define RAQ RA0 + 1
00381   { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
00382 
00383   /* The RA field in a D or X form instruction which is an updating
00384      load, which means that the RA field may not be zero and may not
00385      equal the RT field.  */
00386 #define RAL RAQ + 1
00387   { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
00388 
00389   /* The RA field in an lmw instruction, which has special value
00390      restrictions.  */
00391 #define RAM RAL + 1
00392   { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
00393 
00394   /* The RA field in a D or X form instruction which is an updating
00395      store or an updating floating point load, which means that the RA
00396      field may not be zero.  */
00397 #define RAS RAM + 1
00398   { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
00399 
00400   /* The RA field of the tlbwe instruction, which is optional.  */
00401 #define RAOPT RAS + 1
00402   { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
00403 
00404   /* The RB field in an X, XO, M, or MDS form instruction.  */
00405 #define RB RAOPT + 1
00406 #define RB_MASK (0x1f << 11)
00407   { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
00408 
00409   /* The RB field in an X form instruction when it must be the same as
00410      the RS field in the instruction.  This is used for extended
00411      mnemonics like mr.  */
00412 #define RBS RB + 1
00413   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
00414 
00415   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
00416      instruction or the RT field in a D, DS, X, XFX or XO form
00417      instruction.  */
00418 #define RS RBS + 1
00419 #define RT RS
00420 #define RT_MASK (0x1f << 21)
00421   { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
00422 
00423   /* The RS field of the DS form stq instruction, which has special
00424      value restrictions.  */
00425 #define RSQ RS + 1
00426   { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 },
00427 
00428   /* The RT field of the DQ form lq instruction, which has special
00429      value restrictions.  */
00430 #define RTQ RSQ + 1
00431   { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 },
00432 
00433   /* The RS field of the tlbwe instruction, which is optional.  */
00434 #define RSO RTQ + 1
00435 #define RTO RSO
00436   { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
00437 
00438   /* The SH field in an X or M form instruction.  */
00439 #define SH RSO + 1
00440 #define SH_MASK (0x1f << 11)
00441   { 5, 11, NULL, NULL, 0 },
00442 
00443   /* The SH field in an MD form instruction.  This is split.  */
00444 #define SH6 SH + 1
00445 #define SH6_MASK ((0x1f << 11) | (1 << 1))
00446   { 6, 1, insert_sh6, extract_sh6, 0 },
00447 
00448   /* The SH field of the tlbwe instruction, which is optional.  */
00449 #define SHO SH6 + 1
00450   { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL },
00451 
00452   /* The SI field in a D form instruction.  */
00453 #define SI SHO + 1
00454   { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
00455 
00456   /* The SI field in a D form instruction when we accept a wide range
00457      of positive values.  */
00458 #define SISIGNOPT SI + 1
00459   { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
00460 
00461   /* The SPR field in an XFX form instruction.  This is flipped--the
00462      lower 5 bits are stored in the upper 5 and vice- versa.  */
00463 #define SPR SISIGNOPT + 1
00464 #define PMR SPR
00465 #define SPR_MASK (0x3ff << 11)
00466   { 10, 11, insert_spr, extract_spr, 0 },
00467 
00468   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
00469 #define SPRBAT SPR + 1
00470 #define SPRBAT_MASK (0x3 << 17)
00471   { 2, 17, NULL, NULL, 0 },
00472 
00473   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
00474 #define SPRG SPRBAT + 1
00475   { 5, 16, insert_sprg, extract_sprg, 0 },
00476 
00477   /* The SR field in an X form instruction.  */
00478 #define SR SPRG + 1
00479   { 4, 16, NULL, NULL, 0 },
00480 
00481   /* The STRM field in an X AltiVec form instruction.  */
00482 #define STRM SR + 1
00483 #define STRM_MASK (0x3 << 21)
00484   { 2, 21, NULL, NULL, 0 },
00485 
00486   /* The SV field in a POWER SC form instruction.  */
00487 #define SV STRM + 1
00488   { 14, 2, NULL, NULL, 0 },
00489 
00490   /* The TBR field in an XFX form instruction.  This is like the SPR
00491      field, but it is optional.  */
00492 #define TBR SV + 1
00493   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
00494 
00495   /* The TO field in a D or X form instruction.  */
00496 #define TO TBR + 1
00497 #define TO_MASK (0x1f << 21)
00498   { 5, 21, NULL, NULL, 0 },
00499 
00500   /* The U field in an X form instruction.  */
00501 #define U TO + 1
00502   { 4, 12, NULL, NULL, 0 },
00503 
00504   /* The UI field in a D form instruction.  */
00505 #define UI U + 1
00506   { 16, 0, NULL, NULL, 0 },
00507 
00508   /* The VA field in a VA, VX or VXR form instruction.  */
00509 #define VA UI + 1
00510 #define VA_MASK      (0x1f << 16)
00511   { 5, 16, NULL, NULL, PPC_OPERAND_VR },
00512 
00513   /* The VB field in a VA, VX or VXR form instruction.  */
00514 #define VB VA + 1
00515 #define VB_MASK (0x1f << 11)
00516   { 5, 11, NULL, NULL, PPC_OPERAND_VR },
00517 
00518   /* The VC field in a VA form instruction.  */
00519 #define VC VB + 1
00520 #define VC_MASK (0x1f << 6)
00521   { 5, 6, NULL, NULL, PPC_OPERAND_VR },
00522 
00523   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
00524 #define VD VC + 1
00525 #define VS VD
00526 #define VD_MASK (0x1f << 21)
00527   { 5, 21, NULL, NULL, PPC_OPERAND_VR },
00528 
00529   /* The SIMM field in a VX form instruction.  */
00530 #define SIMM VD + 1
00531   { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
00532 
00533   /* The UIMM field in a VX form instruction.  */
00534 #define UIMM SIMM + 1
00535   { 5, 16, NULL, NULL, 0 },
00536 
00537   /* The SHB field in a VA form instruction.  */
00538 #define SHB UIMM + 1
00539   { 4, 6, NULL, NULL, 0 },
00540 
00541   /* The other UIMM field in a EVX form instruction.  */
00542 #define EVUIMM SHB + 1
00543   { 5, 11, NULL, NULL, 0 },
00544 
00545   /* The other UIMM field in a half word EVX form instruction.  */
00546 #define EVUIMM_2 EVUIMM + 1
00547   { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
00548 
00549   /* The other UIMM field in a word EVX form instruction.  */
00550 #define EVUIMM_4 EVUIMM_2 + 1
00551   { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
00552 
00553   /* The other UIMM field in a double EVX form instruction.  */
00554 #define EVUIMM_8 EVUIMM_4 + 1
00555   { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
00556 
00557   /* The WS field.  */
00558 #define WS EVUIMM_8 + 1
00559 #define WS_MASK (0x7 << 11)
00560   { 3, 11, NULL, NULL, 0 },
00561 
00562   /* The L field in an mtmsrd or A form instruction.  */
00563 #define MTMSRD_L WS + 1
00564 #define A_L MTMSRD_L
00565   { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
00566 
00567   /* The DCM field in a Z form instruction.  */
00568 #define DCM MTMSRD_L + 1
00569   { 6, 16, NULL, NULL, 0 },
00570 
00571   /* Likewise, the DGM field in a Z form instruction.  */
00572 #define DGM DCM + 1
00573   { 6, 16, NULL, NULL, 0 },
00574 
00575 #define TE DGM + 1
00576   { 5, 11, NULL, NULL, 0 },
00577 
00578 #define RMC TE + 1
00579   { 2, 21, NULL, NULL, 0 },
00580 
00581 #define R RMC + 1
00582   { 1, 15, NULL, NULL, 0 },
00583 
00584 #define SP R + 1
00585   { 2, 11, NULL, NULL, 0 },
00586 
00587 #define S SP + 1
00588   { 1, 11, NULL, NULL, 0 },
00589 
00590   /* SH field starting at bit position 16.  */
00591 #define SH16 S + 1
00592   { 6, 10, NULL, NULL, 0 },
00593 
00594   /* The L field in an X form with the RT field fixed instruction.  */
00595 #define XRT_L SH16 + 1
00596   { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
00597 
00598   /* The EH field in larx instruction.  */
00599 #define EH XRT_L + 1
00600   { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
00601 };
00602 
00603 /* The functions used to insert and extract complicated operands.  */
00604 
00605 /* The BA field in an XL form instruction when it must be the same as
00606    the BT field in the same instruction.  This operand is marked FAKE.
00607    The insertion function just copies the BT field into the BA field,
00608    and the extraction function just checks that the fields are the
00609    same.  */
00610 
00611 static unsigned long
00612 insert_bat (unsigned long insn,
00613            long value ATTRIBUTE_UNUSED,
00614            int dialect ATTRIBUTE_UNUSED,
00615            const char **errmsg ATTRIBUTE_UNUSED)
00616 {
00617   return insn | (((insn >> 21) & 0x1f) << 16);
00618 }
00619 
00620 static long
00621 extract_bat (unsigned long insn,
00622             int dialect ATTRIBUTE_UNUSED,
00623             int *invalid)
00624 {
00625   if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
00626     *invalid = 1;
00627   return 0;
00628 }
00629 
00630 /* The BB field in an XL form instruction when it must be the same as
00631    the BA field in the same instruction.  This operand is marked FAKE.
00632    The insertion function just copies the BA field into the BB field,
00633    and the extraction function just checks that the fields are the
00634    same.  */
00635 
00636 static unsigned long
00637 insert_bba (unsigned long insn,
00638            long value ATTRIBUTE_UNUSED,
00639            int dialect ATTRIBUTE_UNUSED,
00640            const char **errmsg ATTRIBUTE_UNUSED)
00641 {
00642   return insn | (((insn >> 16) & 0x1f) << 11);
00643 }
00644 
00645 static long
00646 extract_bba (unsigned long insn,
00647             int dialect ATTRIBUTE_UNUSED,
00648             int *invalid)
00649 {
00650   if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
00651     *invalid = 1;
00652   return 0;
00653 }
00654 
00655 /* The BD field in a B form instruction.  The lower two bits are
00656    forced to zero.  */
00657 
00658 static unsigned long
00659 insert_bd (unsigned long insn,
00660           long value,
00661           int dialect ATTRIBUTE_UNUSED,
00662           const char **errmsg ATTRIBUTE_UNUSED)
00663 {
00664   return insn | (value & 0xfffc);
00665 }
00666 
00667 static long
00668 extract_bd (unsigned long insn,
00669            int dialect ATTRIBUTE_UNUSED,
00670            int *invalid ATTRIBUTE_UNUSED)
00671 {
00672   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
00673 }
00674 
00675 /* The BD field in a B form instruction when the - modifier is used.
00676    This modifier means that the branch is not expected to be taken.
00677    For chips built to versions of the architecture prior to version 2
00678    (ie. not Power4 compatible), we set the y bit of the BO field to 1
00679    if the offset is negative.  When extracting, we require that the y
00680    bit be 1 and that the offset be positive, since if the y bit is 0
00681    we just want to print the normal form of the instruction.
00682    Power4 compatible targets use two bits, "a", and "t", instead of
00683    the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
00684    "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
00685    in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
00686    for branch on CTR.  We only handle the taken/not-taken hint here.
00687    Note that we don't relax the conditions tested here when
00688    disassembling with -Many because insns using extract_bdm and
00689    extract_bdp always occur in pairs.  One or the other will always
00690    be valid.  */
00691 
00692 static unsigned long
00693 insert_bdm (unsigned long insn,
00694            long value,
00695            int dialect,
00696            const char **errmsg ATTRIBUTE_UNUSED)
00697 {
00698   if ((dialect & PPC_OPCODE_POWER4) == 0)
00699     {
00700       if ((value & 0x8000) != 0)
00701        insn |= 1 << 21;
00702     }
00703   else
00704     {
00705       if ((insn & (0x14 << 21)) == (0x04 << 21))
00706        insn |= 0x02 << 21;
00707       else if ((insn & (0x14 << 21)) == (0x10 << 21))
00708        insn |= 0x08 << 21;
00709     }
00710   return insn | (value & 0xfffc);
00711 }
00712 
00713 static long
00714 extract_bdm (unsigned long insn,
00715             int dialect,
00716             int *invalid)
00717 {
00718   if ((dialect & PPC_OPCODE_POWER4) == 0)
00719     {
00720       if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
00721        *invalid = 1;
00722     }
00723   else
00724     {
00725       if ((insn & (0x17 << 21)) != (0x06 << 21)
00726          && (insn & (0x1d << 21)) != (0x18 << 21))
00727        *invalid = 1;
00728     }
00729 
00730   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
00731 }
00732 
00733 /* The BD field in a B form instruction when the + modifier is used.
00734    This is like BDM, above, except that the branch is expected to be
00735    taken.  */
00736 
00737 static unsigned long
00738 insert_bdp (unsigned long insn,
00739            long value,
00740            int dialect,
00741            const char **errmsg ATTRIBUTE_UNUSED)
00742 {
00743   if ((dialect & PPC_OPCODE_POWER4) == 0)
00744     {
00745       if ((value & 0x8000) == 0)
00746        insn |= 1 << 21;
00747     }
00748   else
00749     {
00750       if ((insn & (0x14 << 21)) == (0x04 << 21))
00751        insn |= 0x03 << 21;
00752       else if ((insn & (0x14 << 21)) == (0x10 << 21))
00753        insn |= 0x09 << 21;
00754     }
00755   return insn | (value & 0xfffc);
00756 }
00757 
00758 static long
00759 extract_bdp (unsigned long insn,
00760             int dialect,
00761             int *invalid)
00762 {
00763   if ((dialect & PPC_OPCODE_POWER4) == 0)
00764     {
00765       if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
00766        *invalid = 1;
00767     }
00768   else
00769     {
00770       if ((insn & (0x17 << 21)) != (0x07 << 21)
00771          && (insn & (0x1d << 21)) != (0x19 << 21))
00772        *invalid = 1;
00773     }
00774 
00775   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
00776 }
00777 
00778 /* Check for legal values of a BO field.  */
00779 
00780 static int
00781 valid_bo (long value, int dialect, int extract)
00782 {
00783   if ((dialect & PPC_OPCODE_POWER4) == 0)
00784     {
00785       int valid;
00786       /* Certain encodings have bits that are required to be zero.
00787         These are (z must be zero, y may be anything):
00788             001zy
00789             011zy
00790             1z00y
00791             1z01y
00792             1z1zz
00793       */
00794       switch (value & 0x14)
00795        {
00796        default:
00797        case 0:
00798          valid = 1;
00799          break;
00800        case 0x4:
00801          valid = (value & 0x2) == 0;
00802          break;
00803        case 0x10:
00804          valid = (value & 0x8) == 0;
00805          break;
00806        case 0x14:
00807          valid = value == 0x14;
00808          break;
00809        }
00810       /* When disassembling with -Many, accept power4 encodings too.  */
00811       if (valid
00812          || (dialect & PPC_OPCODE_ANY) == 0
00813          || !extract)
00814        return valid;
00815     }
00816 
00817   /* Certain encodings have bits that are required to be zero.
00818      These are (z must be zero, a & t may be anything):
00819         0000z
00820         0001z
00821         0100z
00822         0101z
00823         001at
00824         011at
00825         1a00t
00826         1a01t
00827         1z1zz
00828   */
00829   if ((value & 0x14) == 0)
00830     return (value & 0x1) == 0;
00831   else if ((value & 0x14) == 0x14)
00832     return value == 0x14;
00833   else
00834     return 1;
00835 }
00836 
00837 /* The BO field in a B form instruction.  Warn about attempts to set
00838    the field to an illegal value.  */
00839 
00840 static unsigned long
00841 insert_bo (unsigned long insn,
00842           long value,
00843           int dialect,
00844           const char **errmsg)
00845 {
00846   if (!valid_bo (value, dialect, 0))
00847     *errmsg = _("invalid conditional option");
00848   return insn | ((value & 0x1f) << 21);
00849 }
00850 
00851 static long
00852 extract_bo (unsigned long insn,
00853            int dialect,
00854            int *invalid)
00855 {
00856   long value;
00857 
00858   value = (insn >> 21) & 0x1f;
00859   if (!valid_bo (value, dialect, 1))
00860     *invalid = 1;
00861   return value;
00862 }
00863 
00864 /* The BO field in a B form instruction when the + or - modifier is
00865    used.  This is like the BO field, but it must be even.  When
00866    extracting it, we force it to be even.  */
00867 
00868 static unsigned long
00869 insert_boe (unsigned long insn,
00870            long value,
00871            int dialect,
00872            const char **errmsg)
00873 {
00874   if (!valid_bo (value, dialect, 0))
00875     *errmsg = _("invalid conditional option");
00876   else if ((value & 1) != 0)
00877     *errmsg = _("attempt to set y bit when using + or - modifier");
00878 
00879   return insn | ((value & 0x1f) << 21);
00880 }
00881 
00882 static long
00883 extract_boe (unsigned long insn,
00884             int dialect,
00885             int *invalid)
00886 {
00887   long value;
00888 
00889   value = (insn >> 21) & 0x1f;
00890   if (!valid_bo (value, dialect, 1))
00891     *invalid = 1;
00892   return value & 0x1e;
00893 }
00894 
00895 /* The DQ field in a DQ form instruction.  This is like D, but the
00896    lower four bits are forced to zero. */
00897 
00898 static unsigned long
00899 insert_dq (unsigned long insn,
00900           long value,
00901           int dialect ATTRIBUTE_UNUSED,
00902           const char **errmsg)
00903 {
00904   if ((value & 0xf) != 0)
00905     *errmsg = _("offset not a multiple of 16");
00906   return insn | (value & 0xfff0);
00907 }
00908 
00909 static long
00910 extract_dq (unsigned long insn,
00911            int dialect ATTRIBUTE_UNUSED,
00912            int *invalid ATTRIBUTE_UNUSED)
00913 {
00914   return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
00915 }
00916 
00917 static unsigned long
00918 insert_ev2 (unsigned long insn,
00919            long value,
00920            int dialect ATTRIBUTE_UNUSED,
00921            const char **errmsg)
00922 {
00923   if ((value & 1) != 0)
00924     *errmsg = _("offset not a multiple of 2");
00925   if ((value > 62) != 0)
00926     *errmsg = _("offset greater than 62");
00927   return insn | ((value & 0x3e) << 10);
00928 }
00929 
00930 static long
00931 extract_ev2 (unsigned long insn,
00932             int dialect ATTRIBUTE_UNUSED,
00933             int *invalid ATTRIBUTE_UNUSED)
00934 {
00935   return (insn >> 10) & 0x3e;
00936 }
00937 
00938 static unsigned long
00939 insert_ev4 (unsigned long insn,
00940            long value,
00941            int dialect ATTRIBUTE_UNUSED,
00942            const char **errmsg)
00943 {
00944   if ((value & 3) != 0)
00945     *errmsg = _("offset not a multiple of 4");
00946   if ((value > 124) != 0)
00947     *errmsg = _("offset greater than 124");
00948   return insn | ((value & 0x7c) << 9);
00949 }
00950 
00951 static long
00952 extract_ev4 (unsigned long insn,
00953             int dialect ATTRIBUTE_UNUSED,
00954             int *invalid ATTRIBUTE_UNUSED)
00955 {
00956   return (insn >> 9) & 0x7c;
00957 }
00958 
00959 static unsigned long
00960 insert_ev8 (unsigned long insn,
00961            long value,
00962            int dialect ATTRIBUTE_UNUSED,
00963            const char **errmsg)
00964 {
00965   if ((value & 7) != 0)
00966     *errmsg = _("offset not a multiple of 8");
00967   if ((value > 248) != 0)
00968     *errmsg = _("offset greater than 248");
00969   return insn | ((value & 0xf8) << 8);
00970 }
00971 
00972 static long
00973 extract_ev8 (unsigned long insn,
00974             int dialect ATTRIBUTE_UNUSED,
00975             int *invalid ATTRIBUTE_UNUSED)
00976 {
00977   return (insn >> 8) & 0xf8;
00978 }
00979 
00980 /* The DS field in a DS form instruction.  This is like D, but the
00981    lower two bits are forced to zero.  */
00982 
00983 static unsigned long
00984 insert_ds (unsigned long insn,
00985           long value,
00986           int dialect ATTRIBUTE_UNUSED,
00987           const char **errmsg)
00988 {
00989   if ((value & 3) != 0)
00990     *errmsg = _("offset not a multiple of 4");
00991   return insn | (value & 0xfffc);
00992 }
00993 
00994 static long
00995 extract_ds (unsigned long insn,
00996            int dialect ATTRIBUTE_UNUSED,
00997            int *invalid ATTRIBUTE_UNUSED)
00998 {
00999   return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
01000 }
01001 
01002 /* The DE field in a DE form instruction.  */
01003 
01004 static unsigned long
01005 insert_de (unsigned long insn,
01006           long value,
01007           int dialect ATTRIBUTE_UNUSED,
01008           const char **errmsg)
01009 {
01010   if (value > 2047 || value < -2048)
01011     *errmsg = _("offset not between -2048 and 2047");
01012   return insn | ((value << 4) & 0xfff0);
01013 }
01014 
01015 static long
01016 extract_de (unsigned long insn,
01017            int dialect ATTRIBUTE_UNUSED,
01018            int *invalid ATTRIBUTE_UNUSED)
01019 {
01020   return (insn & 0xfff0) >> 4;
01021 }
01022 
01023 /* The DES field in a DES form instruction.  */
01024 
01025 static unsigned long
01026 insert_des (unsigned long insn,
01027            long value,
01028            int dialect ATTRIBUTE_UNUSED,
01029            const char **errmsg)
01030 {
01031   if (value > 8191 || value < -8192)
01032     *errmsg = _("offset not between -8192 and 8191");
01033   else if ((value & 3) != 0)
01034     *errmsg = _("offset not a multiple of 4");
01035   return insn | ((value << 2) & 0xfff0);
01036 }
01037 
01038 static long
01039 extract_des (unsigned long insn,
01040             int dialect ATTRIBUTE_UNUSED,
01041             int *invalid ATTRIBUTE_UNUSED)
01042 {
01043   return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
01044 }
01045 
01046 /* FXM mask in mfcr and mtcrf instructions.  */
01047 
01048 static unsigned long
01049 insert_fxm (unsigned long insn,
01050            long value,
01051            int dialect,
01052            const char **errmsg)
01053 {
01054   /* If we're handling the mfocrf and mtocrf insns ensure that exactly
01055      one bit of the mask field is set.  */
01056   if ((insn & (1 << 20)) != 0)
01057     {
01058       if (value == 0 || (value & -value) != value)
01059        {
01060          *errmsg = _("invalid mask field");
01061          value = 0;
01062        }
01063     }
01064 
01065   /* If the optional field on mfcr is missing that means we want to use
01066      the old form of the instruction that moves the whole cr.  In that
01067      case we'll have VALUE zero.  There doesn't seem to be a way to
01068      distinguish this from the case where someone writes mfcr %r3,0.  */
01069   else if (value == 0)
01070     ;
01071 
01072   /* If only one bit of the FXM field is set, we can use the new form
01073      of the instruction, which is faster.  Unlike the Power4 branch hint
01074      encoding, this is not backward compatible.  Do not generate the
01075      new form unless -mpower4 has been given, or -many and the two
01076      operand form of mfcr was used.  */
01077   else if ((value & -value) == value
01078           && ((dialect & PPC_OPCODE_POWER4) != 0
01079               || ((dialect & PPC_OPCODE_ANY) != 0
01080                  && (insn & (0x3ff << 1)) == 19 << 1)))
01081     insn |= 1 << 20;
01082 
01083   /* Any other value on mfcr is an error.  */
01084   else if ((insn & (0x3ff << 1)) == 19 << 1)
01085     {
01086       *errmsg = _("ignoring invalid mfcr mask");
01087       value = 0;
01088     }
01089 
01090   return insn | ((value & 0xff) << 12);
01091 }
01092 
01093 static long
01094 extract_fxm (unsigned long insn,
01095             int dialect ATTRIBUTE_UNUSED,
01096             int *invalid)
01097 {
01098   long mask = (insn >> 12) & 0xff;
01099 
01100   /* Is this a Power4 insn?  */
01101   if ((insn & (1 << 20)) != 0)
01102     {
01103       /* Exactly one bit of MASK should be set.  */
01104       if (mask == 0 || (mask & -mask) != mask)
01105        *invalid = 1;
01106     }
01107 
01108   /* Check that non-power4 form of mfcr has a zero MASK.  */
01109   else if ((insn & (0x3ff << 1)) == 19 << 1)
01110     {
01111       if (mask != 0)
01112        *invalid = 1;
01113     }
01114 
01115   return mask;
01116 }
01117 
01118 /* The LI field in an I form instruction.  The lower two bits are
01119    forced to zero.  */
01120 
01121 static unsigned long
01122 insert_li (unsigned long insn,
01123           long value,
01124           int dialect ATTRIBUTE_UNUSED,
01125           const char **errmsg)
01126 {
01127   if ((value & 3) != 0)
01128     *errmsg = _("ignoring least significant bits in branch offset");
01129   return insn | (value & 0x3fffffc);
01130 }
01131 
01132 static long
01133 extract_li (unsigned long insn,
01134            int dialect ATTRIBUTE_UNUSED,
01135            int *invalid ATTRIBUTE_UNUSED)
01136 {
01137   return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
01138 }
01139 
01140 /* The MB and ME fields in an M form instruction expressed as a single
01141    operand which is itself a bitmask.  The extraction function always
01142    marks it as invalid, since we never want to recognize an
01143    instruction which uses a field of this type.  */
01144 
01145 static unsigned long
01146 insert_mbe (unsigned long insn,
01147            long value,
01148            int dialect ATTRIBUTE_UNUSED,
01149            const char **errmsg)
01150 {
01151   unsigned long uval, mask;
01152   int mb, me, mx, count, last;
01153 
01154   uval = value;
01155 
01156   if (uval == 0)
01157     {
01158       *errmsg = _("illegal bitmask");
01159       return insn;
01160     }
01161 
01162   mb = 0;
01163   me = 32;
01164   if ((uval & 1) != 0)
01165     last = 1;
01166   else
01167     last = 0;
01168   count = 0;
01169 
01170   /* mb: location of last 0->1 transition */
01171   /* me: location of last 1->0 transition */
01172   /* count: # transitions */
01173 
01174   for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
01175     {
01176       if ((uval & mask) && !last)
01177        {
01178          ++count;
01179          mb = mx;
01180          last = 1;
01181        }
01182       else if (!(uval & mask) && last)
01183        {
01184          ++count;
01185          me = mx;
01186          last = 0;
01187        }
01188     }
01189   if (me == 0)
01190     me = 32;
01191 
01192   if (count != 2 && (count != 0 || ! last))
01193     *errmsg = _("illegal bitmask");
01194 
01195   return insn | (mb << 6) | ((me - 1) << 1);
01196 }
01197 
01198 static long
01199 extract_mbe (unsigned long insn,
01200             int dialect ATTRIBUTE_UNUSED,
01201             int *invalid)
01202 {
01203   long ret;
01204   int mb, me;
01205   int i;
01206 
01207   *invalid = 1;
01208 
01209   mb = (insn >> 6) & 0x1f;
01210   me = (insn >> 1) & 0x1f;
01211   if (mb < me + 1)
01212     {
01213       ret = 0;
01214       for (i = mb; i <= me; i++)
01215        ret |= 1L << (31 - i);
01216     }
01217   else if (mb == me + 1)
01218     ret = ~0;
01219   else /* (mb > me + 1) */
01220     {
01221       ret = ~0;
01222       for (i = me + 1; i < mb; i++)
01223        ret &= ~(1L << (31 - i));
01224     }
01225   return ret;
01226 }
01227 
01228 /* The MB or ME field in an MD or MDS form instruction.  The high bit
01229    is wrapped to the low end.  */
01230 
01231 static unsigned long
01232 insert_mb6 (unsigned long insn,
01233            long value,
01234            int dialect ATTRIBUTE_UNUSED,
01235            const char **errmsg ATTRIBUTE_UNUSED)
01236 {
01237   return insn | ((value & 0x1f) << 6) | (value & 0x20);
01238 }
01239 
01240 static long
01241 extract_mb6 (unsigned long insn,
01242             int dialect ATTRIBUTE_UNUSED,
01243             int *invalid ATTRIBUTE_UNUSED)
01244 {
01245   return ((insn >> 6) & 0x1f) | (insn & 0x20);
01246 }
01247 
01248 /* The NB field in an X form instruction.  The value 32 is stored as
01249    0.  */
01250 
01251 static unsigned long
01252 insert_nb (unsigned long insn,
01253           long value,
01254           int dialect ATTRIBUTE_UNUSED,
01255           const char **errmsg)
01256 {
01257   if (value < 0 || value > 32)
01258     *errmsg = _("value out of range");
01259   if (value == 32)
01260     value = 0;
01261   return insn | ((value & 0x1f) << 11);
01262 }
01263 
01264 static long
01265 extract_nb (unsigned long insn,
01266            int dialect ATTRIBUTE_UNUSED,
01267            int *invalid ATTRIBUTE_UNUSED)
01268 {
01269   long ret;
01270 
01271   ret = (insn >> 11) & 0x1f;
01272   if (ret == 0)
01273     ret = 32;
01274   return ret;
01275 }
01276 
01277 /* The NSI field in a D form instruction.  This is the same as the SI
01278    field, only negated.  The extraction function always marks it as
01279    invalid, since we never want to recognize an instruction which uses
01280    a field of this type.  */
01281 
01282 static unsigned long
01283 insert_nsi (unsigned long insn,
01284            long value,
01285            int dialect ATTRIBUTE_UNUSED,
01286            const char **errmsg ATTRIBUTE_UNUSED)
01287 {
01288   return insn | (-value & 0xffff);
01289 }
01290 
01291 static long
01292 extract_nsi (unsigned long insn,
01293             int dialect ATTRIBUTE_UNUSED,
01294             int *invalid)
01295 {
01296   *invalid = 1;
01297   return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
01298 }
01299 
01300 /* The RA field in a D or X form instruction which is an updating
01301    load, which means that the RA field may not be zero and may not
01302    equal the RT field.  */
01303 
01304 static unsigned long
01305 insert_ral (unsigned long insn,
01306            long value,
01307            int dialect ATTRIBUTE_UNUSED,
01308            const char **errmsg)
01309 {
01310   if (value == 0
01311       || (unsigned long) value == ((insn >> 21) & 0x1f))
01312     *errmsg = "invalid register operand when updating";
01313   return insn | ((value & 0x1f) << 16);
01314 }
01315 
01316 /* The RA field in an lmw instruction, which has special value
01317    restrictions.  */
01318 
01319 static unsigned long
01320 insert_ram (unsigned long insn,
01321            long value,
01322            int dialect ATTRIBUTE_UNUSED,
01323            const char **errmsg)
01324 {
01325   if ((unsigned long) value >= ((insn >> 21) & 0x1f))
01326     *errmsg = _("index register in load range");
01327   return insn | ((value & 0x1f) << 16);
01328 }
01329 
01330 /* The RA field in the DQ form lq instruction, which has special
01331    value restrictions.  */
01332 
01333 static unsigned long
01334 insert_raq (unsigned long insn,
01335            long value,
01336            int dialect ATTRIBUTE_UNUSED,
01337            const char **errmsg)
01338 {
01339   long rtvalue = (insn & RT_MASK) >> 21;
01340 
01341   if (value == rtvalue)
01342     *errmsg = _("source and target register operands must be different");
01343   return insn | ((value & 0x1f) << 16);
01344 }
01345 
01346 /* The RA field in a D or X form instruction which is an updating
01347    store or an updating floating point load, which means that the RA
01348    field may not be zero.  */
01349 
01350 static unsigned long
01351 insert_ras (unsigned long insn,
01352            long value,
01353            int dialect ATTRIBUTE_UNUSED,
01354            const char **errmsg)
01355 {
01356   if (value == 0)
01357     *errmsg = _("invalid register operand when updating");
01358   return insn | ((value & 0x1f) << 16);
01359 }
01360 
01361 /* The RB field in an X form instruction when it must be the same as
01362    the RS field in the instruction.  This is used for extended
01363    mnemonics like mr.  This operand is marked FAKE.  The insertion
01364    function just copies the BT field into the BA field, and the
01365    extraction function just checks that the fields are the same.  */
01366 
01367 static unsigned long
01368 insert_rbs (unsigned long insn,
01369            long value ATTRIBUTE_UNUSED,
01370            int dialect ATTRIBUTE_UNUSED,
01371            const char **errmsg ATTRIBUTE_UNUSED)
01372 {
01373   return insn | (((insn >> 21) & 0x1f) << 11);
01374 }
01375 
01376 static long
01377 extract_rbs (unsigned long insn,
01378             int dialect ATTRIBUTE_UNUSED,
01379             int *invalid)
01380 {
01381   if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
01382     *invalid = 1;
01383   return 0;
01384 }
01385 
01386 /* The RT field of the DQ form lq instruction, which has special
01387    value restrictions.  */
01388 
01389 static unsigned long
01390 insert_rtq (unsigned long insn,
01391            long value,
01392            int dialect ATTRIBUTE_UNUSED,
01393            const char **errmsg)
01394 {
01395   if ((value & 1) != 0)
01396     *errmsg = _("target register operand must be even");
01397   return insn | ((value & 0x1f) << 21);
01398 }
01399 
01400 /* The RS field of the DS form stq instruction, which has special
01401    value restrictions.  */
01402 
01403 static unsigned long
01404 insert_rsq (unsigned long insn,
01405            long value ATTRIBUTE_UNUSED,
01406            int dialect ATTRIBUTE_UNUSED,
01407            const char **errmsg)
01408 {
01409   if ((value & 1) != 0)
01410     *errmsg = _("source register operand must be even");
01411   return insn | ((value & 0x1f) << 21);
01412 }
01413 
01414 /* The SH field in an MD form instruction.  This is split.  */
01415 
01416 static unsigned long
01417 insert_sh6 (unsigned long insn,
01418            long value,
01419            int dialect ATTRIBUTE_UNUSED,
01420            const char **errmsg ATTRIBUTE_UNUSED)
01421 {
01422   return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
01423 }
01424 
01425 static long
01426 extract_sh6 (unsigned long insn,
01427             int dialect ATTRIBUTE_UNUSED,
01428             int *invalid ATTRIBUTE_UNUSED)
01429 {
01430   return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
01431 }
01432 
01433 /* The SPR field in an XFX form instruction.  This is flipped--the
01434    lower 5 bits are stored in the upper 5 and vice- versa.  */
01435 
01436 static unsigned long
01437 insert_spr (unsigned long insn,
01438            long value,
01439            int dialect ATTRIBUTE_UNUSED,
01440            const char **errmsg ATTRIBUTE_UNUSED)
01441 {
01442   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
01443 }
01444 
01445 static long
01446 extract_spr (unsigned long insn,
01447             int dialect ATTRIBUTE_UNUSED,
01448             int *invalid ATTRIBUTE_UNUSED)
01449 {
01450   return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
01451 }
01452 
01453 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
01454 
01455 static unsigned long
01456 insert_sprg (unsigned long insn,
01457             long value,
01458             int dialect,
01459             const char **errmsg)
01460 {
01461   /* This check uses PPC_OPCODE_403 because PPC405 is later defined
01462      as a synonym.  If ever a 405 specific dialect is added this
01463      check should use that instead.  */
01464   if (value > 7
01465       || (value > 3
01466          && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
01467     *errmsg = _("invalid sprg number");
01468 
01469   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
01470      user mode.  Anything else must use spr 272..279.  */
01471   if (value <= 3 || (insn & 0x100) != 0)
01472     value |= 0x10;
01473 
01474   return insn | ((value & 0x17) << 16);
01475 }
01476 
01477 static long
01478 extract_sprg (unsigned long insn,
01479              int dialect,
01480              int *invalid)
01481 {
01482   unsigned long val = (insn >> 16) & 0x1f;
01483 
01484   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
01485      If not BOOKE or 405, then both use only 272..275.  */
01486   if (val <= 3
01487       || (val < 0x10 && (insn & 0x100) != 0)
01488       || (val - 0x10 > 3
01489          && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
01490     *invalid = 1;
01491   return val & 7;
01492 }
01493 
01494 /* The TBR field in an XFX instruction.  This is just like SPR, but it
01495    is optional.  When TBR is omitted, it must be inserted as 268 (the
01496    magic number of the TB register).  These functions treat 0
01497    (indicating an omitted optional operand) as 268.  This means that
01498    ``mftb 4,0'' is not handled correctly.  This does not matter very
01499    much, since the architecture manual does not define mftb as
01500    accepting any values other than 268 or 269.  */
01501 
01502 #define TB (268)
01503 
01504 static unsigned long
01505 insert_tbr (unsigned long insn,
01506            long value,
01507            int dialect ATTRIBUTE_UNUSED,
01508            const char **errmsg ATTRIBUTE_UNUSED)
01509 {
01510   if (value == 0)
01511     value = TB;
01512   return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
01513 }
01514 
01515 static long
01516 extract_tbr (unsigned long insn,
01517             int dialect ATTRIBUTE_UNUSED,
01518             int *invalid ATTRIBUTE_UNUSED)
01519 {
01520   long ret;
01521 
01522   ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
01523   if (ret == TB)
01524     ret = 0;
01525   return ret;
01526 }
01527 
01528 /* Macros used to form opcodes.  */
01529 
01530 /* The main opcode.  */
01531 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
01532 #define OP_MASK OP (0x3f)
01533 
01534 /* The main opcode combined with a trap code in the TO field of a D
01535    form instruction.  Used for extended mnemonics for the trap
01536    instructions.  */
01537 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
01538 #define OPTO_MASK (OP_MASK | TO_MASK)
01539 
01540 /* The main opcode combined with a comparison size bit in the L field
01541    of a D form or X form instruction.  Used for extended mnemonics for
01542    the comparison instructions.  */
01543 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
01544 #define OPL_MASK OPL (0x3f,1)
01545 
01546 /* An A form instruction.  */
01547 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
01548 #define A_MASK A (0x3f, 0x1f, 1)
01549 
01550 /* An A_MASK with the FRB field fixed.  */
01551 #define AFRB_MASK (A_MASK | FRB_MASK)
01552 
01553 /* An A_MASK with the FRC field fixed.  */
01554 #define AFRC_MASK (A_MASK | FRC_MASK)
01555 
01556 /* An A_MASK with the FRA and FRC fields fixed.  */
01557 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
01558 
01559 /* An AFRAFRC_MASK, but with L bit clear.  */
01560 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
01561 
01562 /* A B form instruction.  */
01563 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
01564 #define B_MASK B (0x3f, 1, 1)
01565 
01566 /* A B form instruction setting the BO field.  */
01567 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
01568 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
01569 
01570 /* A BBO_MASK with the y bit of the BO field removed.  This permits
01571    matching a conditional branch regardless of the setting of the y
01572    bit.  Similarly for the 'at' bits used for power4 branch hints.  */
01573 #define Y_MASK   (((unsigned long) 1) << 21)
01574 #define AT1_MASK (((unsigned long) 3) << 21)
01575 #define AT2_MASK (((unsigned long) 9) << 21)
01576 #define BBOY_MASK  (BBO_MASK &~ Y_MASK)
01577 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
01578 
01579 /* A B form instruction setting the BO field and the condition bits of
01580    the BI field.  */
01581 #define BBOCB(op, bo, cb, aa, lk) \
01582   (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
01583 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
01584 
01585 /* A BBOCB_MASK with the y bit of the BO field removed.  */
01586 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
01587 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
01588 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
01589 
01590 /* A BBOYCB_MASK in which the BI field is fixed.  */
01591 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
01592 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
01593 
01594 /* An Context form instruction.  */
01595 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
01596 #define CTX_MASK CTX(0x3f, 0x7)
01597 
01598 /* An User Context form instruction.  */
01599 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
01600 #define UCTX_MASK UCTX(0x3f, 0x1f)
01601 
01602 /* The main opcode mask with the RA field clear.  */
01603 #define DRA_MASK (OP_MASK | RA_MASK)
01604 
01605 /* A DS form instruction.  */
01606 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
01607 #define DS_MASK DSO (0x3f, 3)
01608 
01609 /* A DE form instruction.  */
01610 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
01611 #define DE_MASK DEO (0x3e, 0xf)
01612 
01613 /* An EVSEL form instruction.  */
01614 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
01615 #define EVSEL_MASK EVSEL(0x3f, 0xff)
01616 
01617 /* An M form instruction.  */
01618 #define M(op, rc) (OP (op) | ((rc) & 1))
01619 #define M_MASK M (0x3f, 1)
01620 
01621 /* An M form instruction with the ME field specified.  */
01622 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
01623 
01624 /* An M_MASK with the MB and ME fields fixed.  */
01625 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
01626 
01627 /* An M_MASK with the SH and ME fields fixed.  */
01628 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
01629 
01630 /* An MD form instruction.  */
01631 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
01632 #define MD_MASK MD (0x3f, 0x7, 1)
01633 
01634 /* An MD_MASK with the MB field fixed.  */
01635 #define MDMB_MASK (MD_MASK | MB6_MASK)
01636 
01637 /* An MD_MASK with the SH field fixed.  */
01638 #define MDSH_MASK (MD_MASK | SH6_MASK)
01639 
01640 /* An MDS form instruction.  */
01641 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
01642 #define MDS_MASK MDS (0x3f, 0xf, 1)
01643 
01644 /* An MDS_MASK with the MB field fixed.  */
01645 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
01646 
01647 /* An SC form instruction.  */
01648 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
01649 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
01650 
01651 /* An VX form instruction.  */
01652 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
01653 
01654 /* The mask for an VX form instruction.  */
01655 #define VX_MASK      VX(0x3f, 0x7ff)
01656 
01657 /* An VA form instruction.  */
01658 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
01659 
01660 /* The mask for an VA form instruction.  */
01661 #define VXA_MASK VXA(0x3f, 0x3f)
01662 
01663 /* An VXR form instruction.  */
01664 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
01665 
01666 /* The mask for a VXR form instruction.  */
01667 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
01668 
01669 /* An X form instruction.  */
01670 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
01671 
01672 /* A Z form instruction.  */
01673 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
01674 
01675 /* An X form instruction with the RC bit specified.  */
01676 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
01677 
01678 /* A Z form instruction with the RC bit specified.  */
01679 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
01680 
01681 /* The mask for an X form instruction.  */
01682 #define X_MASK XRC (0x3f, 0x3ff, 1)
01683 
01684 /* The mask for a Z form instruction.  */
01685 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
01686 
01687 /* An X_MASK with the RA field fixed.  */
01688 #define XRA_MASK (X_MASK | RA_MASK)
01689 
01690 /* An X_MASK with the RB field fixed.  */
01691 #define XRB_MASK (X_MASK | RB_MASK)
01692 
01693 /* An X_MASK with the RT field fixed.  */
01694 #define XRT_MASK (X_MASK | RT_MASK)
01695 
01696 /* An XRT_MASK mask with the L bits clear.  */
01697 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
01698 
01699 /* An X_MASK with the RA and RB fields fixed.  */
01700 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
01701 
01702 /* An XRARB_MASK, but with the L bit clear.  */
01703 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
01704 
01705 /* An X_MASK with the RT and RA fields fixed.  */
01706 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
01707 
01708 /* An XRTRA_MASK, but with L bit clear.  */
01709 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
01710 
01711 /* An X form instruction with the L bit specified.  */
01712 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
01713 
01714 /* The mask for an X form comparison instruction.  */
01715 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
01716 
01717 /* The mask for an X form comparison instruction with the L field
01718    fixed.  */
01719 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
01720 
01721 /* An X form trap instruction with the TO field specified.  */
01722 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
01723 #define XTO_MASK (X_MASK | TO_MASK)
01724 
01725 /* An X form tlb instruction with the SH field specified.  */
01726 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
01727 #define XTLB_MASK (X_MASK | SH_MASK)
01728 
01729 /* An X form sync instruction.  */
01730 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
01731 
01732 /* An X form sync instruction with everything filled in except the LS field.  */
01733 #define XSYNC_MASK (0xff9fffff)
01734 
01735 /* An X_MASK, but with the EH bit clear.  */
01736 #define XEH_MASK (X_MASK & ~((unsigned long )1))
01737 
01738 /* An X form AltiVec dss instruction.  */
01739 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
01740 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
01741 
01742 /* An XFL form instruction.  */
01743 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
01744 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
01745 
01746 /* An X form isel instruction.  */
01747 #define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
01748 #define XISEL_MASK      XISEL(0x3f, 0x1f)
01749 
01750 /* An XL form instruction with the LK field set to 0.  */
01751 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
01752 
01753 /* An XL form instruction which uses the LK field.  */
01754 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
01755 
01756 /* The mask for an XL form instruction.  */
01757 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
01758 
01759 /* An XL form instruction which explicitly sets the BO field.  */
01760 #define XLO(op, bo, xop, lk) \
01761   (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
01762 #define XLO_MASK (XL_MASK | BO_MASK)
01763 
01764 /* An XL form instruction which explicitly sets the y bit of the BO
01765    field.  */
01766 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
01767 #define XLYLK_MASK (XL_MASK | Y_MASK)
01768 
01769 /* An XL form instruction which sets the BO field and the condition
01770    bits of the BI field.  */
01771 #define XLOCB(op, bo, cb, xop, lk) \
01772   (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
01773 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
01774 
01775 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
01776 #define XLBB_MASK (XL_MASK | BB_MASK)
01777 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
01778 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
01779 
01780 /* A mask for branch instructions using the BH field.  */
01781 #define XLBH_MASK (XL_MASK | (0x1c << 11))
01782 
01783 /* An XL_MASK with the BO and BB fields fixed.  */
01784 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
01785 
01786 /* An XL_MASK with the BO, BI and BB fields fixed.  */
01787 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
01788 
01789 /* An XO form instruction.  */
01790 #define XO(op, xop, oe, rc) \
01791   (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
01792 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
01793 
01794 /* An XO_MASK with the RB field fixed.  */
01795 #define XORB_MASK (XO_MASK | RB_MASK)
01796 
01797 /* An XS form instruction.  */
01798 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
01799 #define XS_MASK XS (0x3f, 0x1ff, 1)
01800 
01801 /* A mask for the FXM version of an XFX form instruction.  */
01802 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
01803 
01804 /* An XFX form instruction with the FXM field filled in.  */
01805 #define XFXM(op, xop, fxm, p4) \
01806   (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
01807    | ((unsigned long)(p4) << 20))
01808 
01809 /* An XFX form instruction with the SPR field filled in.  */
01810 #define XSPR(op, xop, spr) \
01811   (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
01812 #define XSPR_MASK (X_MASK | SPR_MASK)
01813 
01814 /* An XFX form instruction with the SPR field filled in except for the
01815    SPRBAT field.  */
01816 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
01817 
01818 /* An XFX form instruction with the SPR field filled in except for the
01819    SPRG field.  */
01820 #define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16))
01821 
01822 /* An X form instruction with everything filled in except the E field.  */
01823 #define XE_MASK (0xffff7fff)
01824 
01825 /* An X form user context instruction.  */
01826 #define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
01827 #define XUC_MASK      XUC(0x3f, 0x1f)
01828 
01829 /* The BO encodings used in extended conditional branch mnemonics.  */
01830 #define BODNZF       (0x0)
01831 #define BODNZFP      (0x1)
01832 #define BODZF (0x2)
01833 #define BODZFP       (0x3)
01834 #define BODNZT       (0x8)
01835 #define BODNZTP      (0x9)
01836 #define BODZT (0xa)
01837 #define BODZTP       (0xb)
01838 
01839 #define BOF   (0x4)
01840 #define BOFP  (0x5)
01841 #define BOFM4 (0x6)
01842 #define BOFP4 (0x7)
01843 #define BOT   (0xc)
01844 #define BOTP  (0xd)
01845 #define BOTM4 (0xe)
01846 #define BOTP4 (0xf)
01847 
01848 #define BODNZ (0x10)
01849 #define BODNZP       (0x11)
01850 #define BODZ  (0x12)
01851 #define BODZP (0x13)
01852 #define BODNZM4 (0x18)
01853 #define BODNZP4 (0x19)
01854 #define BODZM4       (0x1a)
01855 #define BODZP4       (0x1b)
01856 
01857 #define BOU   (0x14)
01858 
01859 /* The BI condition bit encodings used in extended conditional branch
01860    mnemonics.  */
01861 #define CBLT  (0)
01862 #define CBGT  (1)
01863 #define CBEQ  (2)
01864 #define CBSO  (3)
01865 
01866 /* The TO encodings used in extended trap mnemonics.  */
01867 #define TOLGT (0x1)
01868 #define TOLLT (0x2)
01869 #define TOEQ  (0x4)
01870 #define TOLGE (0x5)
01871 #define TOLNL (0x5)
01872 #define TOLLE (0x6)
01873 #define TOLNG (0x6)
01874 #define TOGT  (0x8)
01875 #define TOGE  (0xc)
01876 #define TONL  (0xc)
01877 #define TOLT  (0x10)
01878 #define TOLE  (0x14)
01879 #define TONG  (0x14)
01880 #define TONE  (0x18)
01881 #define TOU   (0x1f)
01882 
01883 /* Smaller names for the flags so each entry in the opcodes table will
01884    fit on a single line.  */
01885 #undef PPC
01886 #define PPC     PPC_OPCODE_PPC
01887 #define PPCCOM       PPC_OPCODE_PPC | PPC_OPCODE_COMMON
01888 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
01889 #define POWER4       PPC_OPCODE_POWER4
01890 #define POWER5       PPC_OPCODE_POWER5
01891 #define POWER6       PPC_OPCODE_POWER6
01892 #define CELL  PPC_OPCODE_CELL
01893 #define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
01894 #define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
01895 #define PPC403       PPC_OPCODE_403
01896 #define PPC405       PPC403
01897 #define PPC440       PPC_OPCODE_440
01898 #define PPC750       PPC
01899 #define PPC860       PPC
01900 #define PPCVEC       PPC_OPCODE_ALTIVEC
01901 #define       POWER   PPC_OPCODE_POWER
01902 #define       POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
01903 #define PPCPWR2      PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
01904 #define       POWER32       PPC_OPCODE_POWER | PPC_OPCODE_32
01905 #define       COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
01906 #define       COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
01907 #define       M601    PPC_OPCODE_POWER | PPC_OPCODE_601
01908 #define PWRCOM       PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
01909 #define       MFDEC1 PPC_OPCODE_POWER
01910 #define       MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
01911 #define BOOKE PPC_OPCODE_BOOKE
01912 #define BOOKE64      PPC_OPCODE_BOOKE64
01913 #define CLASSIC      PPC_OPCODE_CLASSIC
01914 #define PPCE300 PPC_OPCODE_E300
01915 #define PPCSPE       PPC_OPCODE_SPE
01916 #define PPCISEL      PPC_OPCODE_ISEL
01917 #define PPCEFS       PPC_OPCODE_EFS
01918 #define PPCBRLK      PPC_OPCODE_BRLOCK
01919 #define PPCPMR       PPC_OPCODE_PMR
01920 #define PPCCHLK      PPC_OPCODE_CACHELCK
01921 #define PPCCHLK64    PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
01922 #define PPCRFMCI     PPC_OPCODE_RFMCI
01923 
01924 /* The opcode table.
01925 
01926    The format of the opcode table is:
01927 
01928    NAME            OPCODE   MASK          FLAGS         { OPERANDS }
01929 
01930    NAME is the name of the instruction.
01931    OPCODE is the instruction opcode.
01932    MASK is the opcode mask; this is used to tell the disassembler
01933      which bits in the actual opcode must match OPCODE.
01934    FLAGS are flags indicated what processors support the instruction.
01935    OPERANDS is the list of operands.
01936 
01937    The disassembler reads the table in order and prints the first
01938    instruction which matches, so this table is sorted to put more
01939    specific instructions before more general instructions.  It is also
01940    sorted by major opcode.  */
01941 
01942 const struct powerpc_opcode powerpc_opcodes[] = {
01943 { "attn",    X(0,256), X_MASK,            POWER4,              { 0 } },
01944 { "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,    PPC64,        { RA, SI } },
01945 { "tdllti",  OPTO(2,TOLLT), OPTO_MASK,    PPC64,        { RA, SI } },
01946 { "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,     PPC64,        { RA, SI } },
01947 { "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,    PPC64,        { RA, SI } },
01948 { "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,    PPC64,        { RA, SI } },
01949 { "tdllei",  OPTO(2,TOLLE), OPTO_MASK,    PPC64,        { RA, SI } },
01950 { "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,    PPC64,        { RA, SI } },
01951 { "tdgti",   OPTO(2,TOGT), OPTO_MASK,     PPC64,        { RA, SI } },
01952 { "tdgei",   OPTO(2,TOGE), OPTO_MASK,     PPC64,        { RA, SI } },
01953 { "tdnli",   OPTO(2,TONL), OPTO_MASK,     PPC64,        { RA, SI } },
01954 { "tdlti",   OPTO(2,TOLT), OPTO_MASK,     PPC64,        { RA, SI } },
01955 { "tdlei",   OPTO(2,TOLE), OPTO_MASK,     PPC64,        { RA, SI } },
01956 { "tdngi",   OPTO(2,TONG), OPTO_MASK,     PPC64,        { RA, SI } },
01957 { "tdnei",   OPTO(2,TONE), OPTO_MASK,     PPC64,        { RA, SI } },
01958 { "tdi",     OP(2),  OP_MASK,      PPC64,        { TO, RA, SI } },
01959 
01960 { "twlgti",  OPTO(3,TOLGT), OPTO_MASK,    PPCCOM,              { RA, SI } },
01961 { "tlgti",   OPTO(3,TOLGT), OPTO_MASK,    PWRCOM,              { RA, SI } },
01962 { "twllti",  OPTO(3,TOLLT), OPTO_MASK,    PPCCOM,              { RA, SI } },
01963 { "tllti",   OPTO(3,TOLLT), OPTO_MASK,    PWRCOM,              { RA, SI } },
01964 { "tweqi",   OPTO(3,TOEQ), OPTO_MASK,     PPCCOM,              { RA, SI } },
01965 { "teqi",    OPTO(3,TOEQ), OPTO_MASK,     PWRCOM,              { RA, SI } },
01966 { "twlgei",  OPTO(3,TOLGE), OPTO_MASK,    PPCCOM,              { RA, SI } },
01967 { "tlgei",   OPTO(3,TOLGE), OPTO_MASK,    PWRCOM,              { RA, SI } },
01968 { "twlnli",  OPTO(3,TOLNL), OPTO_MASK,    PPCCOM,              { RA, SI } },
01969 { "tlnli",   OPTO(3,TOLNL), OPTO_MASK,    PWRCOM,              { RA, SI } },
01970 { "twllei",  OPTO(3,TOLLE), OPTO_MASK,    PPCCOM,              { RA, SI } },
01971 { "tllei",   OPTO(3,TOLLE), OPTO_MASK,    PWRCOM,              { RA, SI } },
01972 { "twlngi",  OPTO(3,TOLNG), OPTO_MASK,    PPCCOM,              { RA, SI } },
01973 { "tlngi",   OPTO(3,TOLNG), OPTO_MASK,    PWRCOM,              { RA, SI } },
01974 { "twgti",   OPTO(3,TOGT), OPTO_MASK,     PPCCOM,              { RA, SI } },
01975 { "tgti",    OPTO(3,TOGT), OPTO_MASK,     PWRCOM,              { RA, SI } },
01976 { "twgei",   OPTO(3,TOGE), OPTO_MASK,     PPCCOM,              { RA, SI } },
01977 { "tgei",    OPTO(3,TOGE), OPTO_MASK,     PWRCOM,              { RA, SI } },
01978 { "twnli",   OPTO(3,TONL), OPTO_MASK,     PPCCOM,              { RA, SI } },
01979 { "tnli",    OPTO(3,TONL), OPTO_MASK,     PWRCOM,              { RA, SI } },
01980 { "twlti",   OPTO(3,TOLT), OPTO_MASK,     PPCCOM,              { RA, SI } },
01981 { "tlti",    OPTO(3,TOLT), OPTO_MASK,     PWRCOM,              { RA, SI } },
01982 { "twlei",   OPTO(3,TOLE), OPTO_MASK,     PPCCOM,              { RA, SI } },
01983 { "tlei",    OPTO(3,TOLE), OPTO_MASK,     PWRCOM,              { RA, SI } },
01984 { "twngi",   OPTO(3,TONG), OPTO_MASK,     PPCCOM,              { RA, SI } },
01985 { "tngi",    OPTO(3,TONG), OPTO_MASK,     PWRCOM,              { RA, SI } },
01986 { "twnei",   OPTO(3,TONE), OPTO_MASK,     PPCCOM,              { RA, SI } },
01987 { "tnei",    OPTO(3,TONE), OPTO_MASK,     PWRCOM,              { RA, SI } },
01988 { "twi",     OP(3),  OP_MASK,      PPCCOM,              { TO, RA, SI } },
01989 { "ti",      OP(3),  OP_MASK,      PWRCOM,              { TO, RA, SI } },
01990 
01991 { "macchw",   XO(4,172,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01992 { "macchw.",  XO(4,172,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01993 { "macchwo",  XO(4,172,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01994 { "macchwo.", XO(4,172,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01995 { "macchws",  XO(4,236,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01996 { "macchws.", XO(4,236,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01997 { "macchwso", XO(4,236,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01998 { "macchwso.",       XO(4,236,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
01999 { "macchwsu", XO(4,204,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02000 { "macchwsu.",       XO(4,204,0,1), XO_MASK, PPC405|PPC440,    { RT, RA, RB } },
02001 { "macchwsuo",       XO(4,204,1,0), XO_MASK, PPC405|PPC440,    { RT, RA, RB } },
02002 { "macchwsuo.",      XO(4,204,1,1), XO_MASK, PPC405|PPC440,    { RT, RA, RB } },
02003 { "macchwu",  XO(4,140,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02004 { "macchwu.", XO(4,140,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02005 { "macchwuo", XO(4,140,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02006 { "macchwuo.",       XO(4,140,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02007 { "machhw",   XO(4,44,0,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02008 { "machhw.",  XO(4,44,0,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02009 { "machhwo",  XO(4,44,1,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02010 { "machhwo.", XO(4,44,1,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02011 { "machhws",  XO(4,108,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02012 { "machhws.", XO(4,108,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02013 { "machhwso", XO(4,108,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02014 { "machhwso.",       XO(4,108,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02015 { "machhwsu", XO(4,76,0,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02016 { "machhwsu.",       XO(4,76,0,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02017 { "machhwsuo",       XO(4,76,1,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02018 { "machhwsuo.",      XO(4,76,1,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02019 { "machhwu",  XO(4,12,0,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02020 { "machhwu.", XO(4,12,0,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02021 { "machhwuo", XO(4,12,1,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02022 { "machhwuo.",       XO(4,12,1,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02023 { "maclhw",   XO(4,428,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02024 { "maclhw.",  XO(4,428,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02025 { "maclhwo",  XO(4,428,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02026 { "maclhwo.", XO(4,428,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02027 { "maclhws",  XO(4,492,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02028 { "maclhws.", XO(4,492,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02029 { "maclhwso", XO(4,492,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02030 { "maclhwso.",       XO(4,492,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02031 { "maclhwsu", XO(4,460,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02032 { "maclhwsu.",       XO(4,460,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02033 { "maclhwsuo",       XO(4,460,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02034 { "maclhwsuo.",      XO(4,460,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02035 { "maclhwu",  XO(4,396,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02036 { "maclhwu.", XO(4,396,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02037 { "maclhwuo", XO(4,396,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02038 { "maclhwuo.",       XO(4,396,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02039 { "mulchw",   XRC(4,168,0),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02040 { "mulchw.",  XRC(4,168,1),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02041 { "mulchwu",  XRC(4,136,0),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02042 { "mulchwu.", XRC(4,136,1),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02043 { "mulhhw",   XRC(4,40,0),   X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02044 { "mulhhw.",  XRC(4,40,1),   X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02045 { "mulhhwu",  XRC(4,8,0),    X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02046 { "mulhhwu.", XRC(4,8,1),    X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02047 { "mullhw",   XRC(4,424,0),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02048 { "mullhw.",  XRC(4,424,1),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02049 { "mullhwu",  XRC(4,392,0),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02050 { "mullhwu.", XRC(4,392,1),  X_MASK,      PPC405|PPC440,       { RT, RA, RB } },
02051 { "nmacchw",  XO(4,174,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02052 { "nmacchw.", XO(4,174,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02053 { "nmacchwo", XO(4,174,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02054 { "nmacchwo.",       XO(4,174,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02055 { "nmacchws", XO(4,238,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02056 { "nmacchws.",       XO(4,238,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02057 { "nmacchwso",       XO(4,238,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02058 { "nmacchwso.",      XO(4,238,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02059 { "nmachhw",  XO(4,46,0,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02060 { "nmachhw.", XO(4,46,0,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02061 { "nmachhwo", XO(4,46,1,0),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02062 { "nmachhwo.",       XO(4,46,1,1),  XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02063 { "nmachhws", XO(4,110,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02064 { "nmachhws.",       XO(4,110,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02065 { "nmachhwso",       XO(4,110,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02066 { "nmachhwso.",      XO(4,110,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02067 { "nmaclhw",  XO(4,430,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02068 { "nmaclhw.", XO(4,430,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02069 { "nmaclhwo", XO(4,430,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02070 { "nmaclhwo.",       XO(4,430,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02071 { "nmaclhws", XO(4,494,0,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02072 { "nmaclhws.",       XO(4,494,0,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02073 { "nmaclhwso",       XO(4,494,1,0), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02074 { "nmaclhwso.",      XO(4,494,1,1), XO_MASK,     PPC405|PPC440,       { RT, RA, RB } },
02075 { "mfvscr",  VX(4, 1540), VX_MASK, PPCVEC,              { VD } },
02076 { "mtvscr",  VX(4, 1604), VX_MASK, PPCVEC,              { VB } },
02077 
02078   /* Double-precision opcodes.  */
02079   /* Some of these conflict with AltiVec, so move them before, since
02080      PPCVEC includes the PPC_OPCODE_PPC set.  */
02081 { "efscfd",   VX(4, 719), VX_MASK, PPCEFS,              { RS, RB } },
02082 { "efdabs",   VX(4, 740), VX_MASK, PPCEFS,              { RS, RA } },
02083 { "efdnabs",  VX(4, 741), VX_MASK, PPCEFS,              { RS, RA } },
02084 { "efdneg",   VX(4, 742), VX_MASK, PPCEFS,              { RS, RA } },
02085 { "efdadd",   VX(4, 736), VX_MASK, PPCEFS,              { RS, RA, RB } },
02086 { "efdsub",   VX(4, 737), VX_MASK, PPCEFS,              { RS, RA, RB } },
02087 { "efdmul",   VX(4, 744), VX_MASK, PPCEFS,              { RS, RA, RB } },
02088 { "efddiv",   VX(4, 745), VX_MASK, PPCEFS,              { RS, RA, RB } },
02089 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02090 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02091 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02092 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02093 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02094 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02095 { "efdcfsi",  VX(4, 753), VX_MASK, PPCEFS,              { RS, RB } },
02096 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS,              { RS, RB } },
02097 { "efdcfui",  VX(4, 752), VX_MASK, PPCEFS,              { RS, RB } },
02098 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS,              { RS, RB } },
02099 { "efdcfsf",  VX(4, 755), VX_MASK, PPCEFS,              { RS, RB } },
02100 { "efdcfuf",  VX(4, 754), VX_MASK, PPCEFS,              { RS, RB } },
02101 { "efdctsi",  VX(4, 757), VX_MASK, PPCEFS,              { RS, RB } },
02102 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS,              { RS, RB } },
02103 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS,              { RS, RB } },
02104 { "efdctui",  VX(4, 756), VX_MASK, PPCEFS,              { RS, RB } },
02105 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS,              { RS, RB } },
02106 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS,              { RS, RB } },
02107 { "efdctsf",  VX(4, 759), VX_MASK, PPCEFS,              { RS, RB } },
02108 { "efdctuf",  VX(4, 758), VX_MASK, PPCEFS,              { RS, RB } },
02109 { "efdcfs",   VX(4, 751), VX_MASK, PPCEFS,              { RS, RB } },
02110   /* End of double-precision opcodes.  */
02111 
02112 { "vaddcuw", VX(4,  384), VX_MASK, PPCVEC,              { VD, VA, VB } },
02113 { "vaddfp",  VX(4,   10), VX_MASK,        PPCVEC,              { VD, VA, VB } },
02114 { "vaddsbs", VX(4,  768), VX_MASK, PPCVEC,              { VD, VA, VB } },
02115 { "vaddshs", VX(4,  832), VX_MASK, PPCVEC,              { VD, VA, VB } },
02116 { "vaddsws", VX(4,  896), VX_MASK, PPCVEC,              { VD, VA, VB } },
02117 { "vaddubm", VX(4,    0), VX_MASK,        PPCVEC,              { VD, VA, VB } },
02118 { "vaddubs", VX(4,  512), VX_MASK, PPCVEC,              { VD, VA, VB } },
02119 { "vadduhm", VX(4,   64), VX_MASK, PPCVEC,              { VD, VA, VB } },
02120 { "vadduhs", VX(4,  576), VX_MASK, PPCVEC,              { VD, VA, VB } },
02121 { "vadduwm", VX(4,  128), VX_MASK, PPCVEC,              { VD, VA, VB } },
02122 { "vadduws", VX(4,  640), VX_MASK, PPCVEC,              { VD, VA, VB } },
02123 { "vand",    VX(4, 1028), VX_MASK, PPCVEC,              { VD, VA, VB } },
02124 { "vandc",   VX(4, 1092), VX_MASK, PPCVEC,              { VD, VA, VB } },
02125 { "vavgsb",  VX(4, 1282), VX_MASK, PPCVEC,              { VD, VA, VB } },
02126 { "vavgsh",  VX(4, 1346), VX_MASK, PPCVEC,              { VD, VA, VB } },
02127 { "vavgsw",  VX(4, 1410), VX_MASK, PPCVEC,              { VD, VA, VB } },
02128 { "vavgub",  VX(4, 1026), VX_MASK, PPCVEC,              { VD, VA, VB } },
02129 { "vavguh",  VX(4, 1090), VX_MASK, PPCVEC,              { VD, VA, VB } },
02130 { "vavguw",  VX(4, 1154), VX_MASK, PPCVEC,              { VD, VA, VB } },
02131 { "vcfsx",   VX(4,  842), VX_MASK, PPCVEC,              { VD, VB, UIMM } },
02132 { "vcfux",   VX(4,  778), VX_MASK, PPCVEC,              { VD, VB, UIMM } },
02133 { "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02134 { "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02135 { "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02136 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02137 { "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02138 { "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02139 { "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02140 { "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02141 { "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02142 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02143 { "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02144 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02145 { "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02146 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02147 { "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02148 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02149 { "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02150 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02151 { "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02152 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02153 { "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02154 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02155 { "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02156 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02157 { "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
02158 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
02159 { "vctsxs",    VX(4,  970), VX_MASK,      PPCVEC,              { VD, VB, UIMM } },
02160 { "vctuxs",    VX(4,  906), VX_MASK,      PPCVEC,              { VD, VB, UIMM } },
02161 { "vexptefp",  VX(4,  394), VX_MASK,      PPCVEC,              { VD, VB } },
02162 { "vlogefp",   VX(4,  458), VX_MASK,      PPCVEC,              { VD, VB } },
02163 { "vmaddfp",   VXA(4,  46), VXA_MASK,     PPCVEC,              { VD, VA, VC, VB } },
02164 { "vmaxfp",    VX(4, 1034), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02165 { "vmaxsb",    VX(4,  258), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02166 { "vmaxsh",    VX(4,  322), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02167 { "vmaxsw",    VX(4,  386), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02168 { "vmaxub",    VX(4,    2), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02169 { "vmaxuh",    VX(4,   66), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02170 { "vmaxuw",    VX(4,  130), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02171 { "vmhaddshs", VXA(4,  32), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02172 { "vmhraddshs", VXA(4, 33), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02173 { "vminfp",    VX(4, 1098), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02174 { "vminsb",    VX(4,  770), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02175 { "vminsh",    VX(4,  834), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02176 { "vminsw",    VX(4,  898), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02177 { "vminub",    VX(4,  514), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02178 { "vminuh",    VX(4,  578), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02179 { "vminuw",    VX(4,  642), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02180 { "vmladduhm", VXA(4,  34), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02181 { "vmrghb",    VX(4,   12), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02182 { "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
02183 { "vmrghw",    VX(4,  140), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02184 { "vmrglb",    VX(4,  268), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02185 { "vmrglh",    VX(4,  332), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02186 { "vmrglw",    VX(4,  396), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02187 { "vmsummbm",  VXA(4,  37), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02188 { "vmsumshm",  VXA(4,  40), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02189 { "vmsumshs",  VXA(4,  41), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02190 { "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
02191 { "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
02192 { "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
02193 { "vmulesb",   VX(4,  776), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02194 { "vmulesh",   VX(4,  840), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02195 { "vmuleub",   VX(4,  520), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02196 { "vmuleuh",   VX(4,  584), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02197 { "vmulosb",   VX(4,  264), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02198 { "vmulosh",   VX(4,  328), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02199 { "vmuloub",   VX(4,    8), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02200 { "vmulouh",   VX(4,   72), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02201 { "vnmsubfp",  VXA(4,  47), VXA_MASK,     PPCVEC,              { VD, VA, VC, VB } },
02202 { "vnor",      VX(4, 1284), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02203 { "vor",       VX(4, 1156), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02204 { "vperm",     VXA(4,  43), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02205 { "vpkpx",     VX(4,  782), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02206 { "vpkshss",   VX(4,  398), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02207 { "vpkshus",   VX(4,  270), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02208 { "vpkswss",   VX(4,  462), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02209 { "vpkswus",   VX(4,  334), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02210 { "vpkuhum",   VX(4,   14), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02211 { "vpkuhus",   VX(4,  142), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02212 { "vpkuwum",   VX(4,   78), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02213 { "vpkuwus",   VX(4,  206), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02214 { "vrefp",     VX(4,  266), VX_MASK,      PPCVEC,              { VD, VB } },
02215 { "vrfim",     VX(4,  714), VX_MASK,      PPCVEC,              { VD, VB } },
02216 { "vrfin",     VX(4,  522), VX_MASK,      PPCVEC,              { VD, VB } },
02217 { "vrfip",     VX(4,  650), VX_MASK,      PPCVEC,              { VD, VB } },
02218 { "vrfiz",     VX(4,  586), VX_MASK,      PPCVEC,              { VD, VB } },
02219 { "vrlb",      VX(4,    4), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02220 { "vrlh",      VX(4,   68), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02221 { "vrlw",      VX(4,  132), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02222 { "vrsqrtefp", VX(4,  330), VX_MASK,      PPCVEC,              { VD, VB } },
02223 { "vsel",      VXA(4,  42), VXA_MASK,     PPCVEC,              { VD, VA, VB, VC } },
02224 { "vsl",       VX(4,  452), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02225 { "vslb",      VX(4,  260), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02226 { "vsldoi",    VXA(4,  44), VXA_MASK,     PPCVEC,              { VD, VA, VB, SHB } },
02227 { "vslh",      VX(4,  324), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02228 { "vslo",      VX(4, 1036), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02229 { "vslw",      VX(4,  388), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02230 { "vspltb",    VX(4,  524), VX_MASK,      PPCVEC,              { VD, VB, UIMM } },
02231 { "vsplth",    VX(4,  588), VX_MASK,      PPCVEC,              { VD, VB, UIMM } },
02232 { "vspltisb",  VX(4,  780), VX_MASK,      PPCVEC,              { VD, SIMM } },
02233 { "vspltish",  VX(4,  844), VX_MASK,      PPCVEC,              { VD, SIMM } },
02234 { "vspltisw",  VX(4,  908), VX_MASK,      PPCVEC,              { VD, SIMM } },
02235 { "vspltw",    VX(4,  652), VX_MASK,      PPCVEC,              { VD, VB, UIMM } },
02236 { "vsr",       VX(4,  708), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02237 { "vsrab",     VX(4,  772), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02238 { "vsrah",     VX(4,  836), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02239 { "vsraw",     VX(4,  900), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02240 { "vsrb",      VX(4,  516), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02241 { "vsrh",      VX(4,  580), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02242 { "vsro",      VX(4, 1100), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02243 { "vsrw",      VX(4,  644), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02244 { "vsubcuw",   VX(4, 1408), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02245 { "vsubfp",    VX(4,   74), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02246 { "vsubsbs",   VX(4, 1792), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02247 { "vsubshs",   VX(4, 1856), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02248 { "vsubsws",   VX(4, 1920), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02249 { "vsububm",   VX(4, 1024), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02250 { "vsububs",   VX(4, 1536), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02251 { "vsubuhm",   VX(4, 1088), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02252 { "vsubuhs",   VX(4, 1600), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02253 { "vsubuwm",   VX(4, 1152), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02254 { "vsubuws",   VX(4, 1664), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02255 { "vsumsws",   VX(4, 1928), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02256 { "vsum2sws",  VX(4, 1672), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02257 { "vsum4sbs",  VX(4, 1800), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02258 { "vsum4shs",  VX(4, 1608), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02259 { "vsum4ubs",  VX(4, 1544), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02260 { "vupkhpx",   VX(4,  846), VX_MASK,      PPCVEC,              { VD, VB } },
02261 { "vupkhsb",   VX(4,  526), VX_MASK,      PPCVEC,              { VD, VB } },
02262 { "vupkhsh",   VX(4,  590), VX_MASK,      PPCVEC,              { VD, VB } },
02263 { "vupklpx",   VX(4,  974), VX_MASK,      PPCVEC,              { VD, VB } },
02264 { "vupklsb",   VX(4,  654), VX_MASK,      PPCVEC,              { VD, VB } },
02265 { "vupklsh",   VX(4,  718), VX_MASK,      PPCVEC,              { VD, VB } },
02266 { "vxor",      VX(4, 1220), VX_MASK,      PPCVEC,              { VD, VA, VB } },
02267 
02268 { "evaddw",    VX(4, 512), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02269 { "evaddiw",   VX(4, 514), VX_MASK,       PPCSPE,              { RS, RB, UIMM } },
02270 { "evsubfw",   VX(4, 516), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02271 { "evsubw",    VX(4, 516), VX_MASK,       PPCSPE,              { RS, RB, RA } },
02272 { "evsubifw",  VX(4, 518), VX_MASK,       PPCSPE,              { RS, UIMM, RB } },
02273 { "evsubiw",   VX(4, 518), VX_MASK,       PPCSPE,              { RS, RB, UIMM } },
02274 { "evabs",     VX(4, 520), VX_MASK,       PPCSPE,              { RS, RA } },
02275 { "evneg",     VX(4, 521), VX_MASK,       PPCSPE,              { RS, RA } },
02276 { "evextsb",   VX(4, 522), VX_MASK,       PPCSPE,              { RS, RA } },
02277 { "evextsh",   VX(4, 523), VX_MASK,       PPCSPE,              { RS, RA } },
02278 { "evrndw",    VX(4, 524), VX_MASK,       PPCSPE,              { RS, RA } },
02279 { "evcntlzw",  VX(4, 525), VX_MASK,       PPCSPE,              { RS, RA } },
02280 { "evcntlsw",  VX(4, 526), VX_MASK,       PPCSPE,              { RS, RA } },
02281 
02282 { "brinc",     VX(4, 527), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02283 
02284 { "evand",     VX(4, 529), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02285 { "evandc",    VX(4, 530), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02286 { "evmr",      VX(4, 535), VX_MASK,       PPCSPE,              { RS, RA, BBA } },
02287 { "evor",      VX(4, 535), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02288 { "evorc",     VX(4, 539), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02289 { "evxor",     VX(4, 534), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02290 { "eveqv",     VX(4, 537), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02291 { "evnand",    VX(4, 542), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02292 { "evnot",     VX(4, 536), VX_MASK,       PPCSPE,              { RS, RA, BBA } },
02293 { "evnor",     VX(4, 536), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02294 
02295 { "evrlw",     VX(4, 552), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02296 { "evrlwi",    VX(4, 554), VX_MASK,       PPCSPE,              { RS, RA, EVUIMM } },
02297 { "evslw",     VX(4, 548), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02298 { "evslwi",    VX(4, 550), VX_MASK,       PPCSPE,              { RS, RA, EVUIMM } },
02299 { "evsrws",    VX(4, 545), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02300 { "evsrwu",    VX(4, 544), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02301 { "evsrwis",   VX(4, 547), VX_MASK,       PPCSPE,              { RS, RA, EVUIMM } },
02302 { "evsrwiu",   VX(4, 546), VX_MASK,       PPCSPE,              { RS, RA, EVUIMM } },
02303 { "evsplati",  VX(4, 553), VX_MASK,       PPCSPE,              { RS, SIMM } },
02304 { "evsplatfi", VX(4, 555), VX_MASK,       PPCSPE,              { RS, SIMM } },
02305 { "evmergehi", VX(4, 556), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02306 { "evmergelo", VX(4, 557), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02307 { "evmergehilo",VX(4,558), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02308 { "evmergelohi",VX(4,559), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02309 
02310 { "evcmpgts",  VX(4, 561), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02311 { "evcmpgtu",  VX(4, 560), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02312 { "evcmplts",  VX(4, 563), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02313 { "evcmpltu",  VX(4, 562), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02314 { "evcmpeq",   VX(4, 564), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02315 { "evsel",     EVSEL(4,79),EVSEL_MASK,    PPCSPE,              { RS, RA, RB, CRFS } },
02316 
02317 { "evldd",     VX(4, 769), VX_MASK,       PPCSPE,              { RS, EVUIMM_8, RA } },
02318 { "evlddx",    VX(4, 768), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02319 { "evldw",     VX(4, 771), VX_MASK,       PPCSPE,              { RS, EVUIMM_8, RA } },
02320 { "evldwx",    VX(4, 770), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02321 { "evldh",     VX(4, 773), VX_MASK,       PPCSPE,              { RS, EVUIMM_8, RA } },
02322 { "evldhx",    VX(4, 772), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02323 { "evlwhe",    VX(4, 785), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02324 { "evlwhex",   VX(4, 784), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02325 { "evlwhou",   VX(4, 789), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02326 { "evlwhoux",  VX(4, 788), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02327 { "evlwhos",   VX(4, 791), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02328 { "evlwhosx",  VX(4, 790), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02329 { "evlwwsplat",VX(4, 793), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02330 { "evlwwsplatx",VX(4, 792), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02331 { "evlwhsplat",VX(4, 797), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02332 { "evlwhsplatx",VX(4, 796), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02333 { "evlhhesplat",VX(4, 777), VX_MASK,      PPCSPE,              { RS, EVUIMM_2, RA } },
02334 { "evlhhesplatx",VX(4, 776), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02335 { "evlhhousplat",VX(4, 781), VX_MASK,     PPCSPE,              { RS, EVUIMM_2, RA } },
02336 { "evlhhousplatx",VX(4, 780), VX_MASK,    PPCSPE,              { RS, RA, RB } },
02337 { "evlhhossplat",VX(4, 783), VX_MASK,     PPCSPE,              { RS, EVUIMM_2, RA } },
02338 { "evlhhossplatx",VX(4, 782), VX_MASK,    PPCSPE,              { RS, RA, RB } },
02339 
02340 { "evstdd",    VX(4, 801), VX_MASK,       PPCSPE,              { RS, EVUIMM_8, RA } },
02341 { "evstddx",   VX(4, 800), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02342 { "evstdw",    VX(4, 803), VX_MASK,       PPCSPE,              { RS, EVUIMM_8, RA } },
02343 { "evstdwx",   VX(4, 802), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02344 { "evstdh",    VX(4, 805), VX_MASK,       PPCSPE,              { RS, EVUIMM_8, RA } },
02345 { "evstdhx",   VX(4, 804), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02346 { "evstwwe",   VX(4, 825), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02347 { "evstwwex",  VX(4, 824), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02348 { "evstwwo",   VX(4, 829), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02349 { "evstwwox",  VX(4, 828), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02350 { "evstwhe",   VX(4, 817), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02351 { "evstwhex",  VX(4, 816), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02352 { "evstwho",   VX(4, 821), VX_MASK,       PPCSPE,              { RS, EVUIMM_4, RA } },
02353 { "evstwhox",  VX(4, 820), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02354 
02355 { "evfsabs",   VX(4, 644), VX_MASK,       PPCSPE,              { RS, RA } },
02356 { "evfsnabs",  VX(4, 645), VX_MASK,       PPCSPE,              { RS, RA } },
02357 { "evfsneg",   VX(4, 646), VX_MASK,       PPCSPE,              { RS, RA } },
02358 { "evfsadd",   VX(4, 640), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02359 { "evfssub",   VX(4, 641), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02360 { "evfsmul",   VX(4, 648), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02361 { "evfsdiv",   VX(4, 649), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02362 { "evfscmpgt", VX(4, 652), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02363 { "evfscmplt", VX(4, 653), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02364 { "evfscmpeq", VX(4, 654), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02365 { "evfststgt", VX(4, 668), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02366 { "evfststlt", VX(4, 669), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02367 { "evfststeq", VX(4, 670), VX_MASK,       PPCSPE,              { CRFD, RA, RB } },
02368 { "evfscfui",  VX(4, 656), VX_MASK,       PPCSPE,              { RS, RB } },
02369 { "evfsctuiz", VX(4, 664), VX_MASK,       PPCSPE,              { RS, RB } },
02370 { "evfscfsi",  VX(4, 657), VX_MASK,       PPCSPE,              { RS, RB } },
02371 { "evfscfuf",  VX(4, 658), VX_MASK,       PPCSPE,              { RS, RB } },
02372 { "evfscfsf",  VX(4, 659), VX_MASK,       PPCSPE,              { RS, RB } },
02373 { "evfsctui",  VX(4, 660), VX_MASK,       PPCSPE,              { RS, RB } },
02374 { "evfsctsi",  VX(4, 661), VX_MASK,       PPCSPE,              { RS, RB } },
02375 { "evfsctsiz", VX(4, 666), VX_MASK,       PPCSPE,              { RS, RB } },
02376 { "evfsctuf",  VX(4, 662), VX_MASK,       PPCSPE,              { RS, RB } },
02377 { "evfsctsf",  VX(4, 663), VX_MASK,       PPCSPE,              { RS, RB } },
02378 
02379 { "efsabs",   VX(4, 708), VX_MASK, PPCEFS,              { RS, RA } },
02380 { "efsnabs",  VX(4, 709), VX_MASK, PPCEFS,              { RS, RA } },
02381 { "efsneg",   VX(4, 710), VX_MASK, PPCEFS,              { RS, RA } },
02382 { "efsadd",   VX(4, 704), VX_MASK, PPCEFS,              { RS, RA, RB } },
02383 { "efssub",   VX(4, 705), VX_MASK, PPCEFS,              { RS, RA, RB } },
02384 { "efsmul",   VX(4, 712), VX_MASK, PPCEFS,              { RS, RA, RB } },
02385 { "efsdiv",   VX(4, 713), VX_MASK, PPCEFS,              { RS, RA, RB } },
02386 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02387 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02388 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02389 { "efststgt", VX(4, 732), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02390 { "efststlt", VX(4, 733), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02391 { "efststeq", VX(4, 734), VX_MASK, PPCEFS,              { CRFD, RA, RB } },
02392 { "efscfui",  VX(4, 720), VX_MASK, PPCEFS,              { RS, RB } },
02393 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS,              { RS, RB } },
02394 { "efscfsi",  VX(4, 721), VX_MASK, PPCEFS,              { RS, RB } },
02395 { "efscfuf",  VX(4, 722), VX_MASK, PPCEFS,              { RS, RB } },
02396 { "efscfsf",  VX(4, 723), VX_MASK, PPCEFS,              { RS, RB } },
02397 { "efsctui",  VX(4, 724), VX_MASK, PPCEFS,              { RS, RB } },
02398 { "efsctsi",  VX(4, 725), VX_MASK, PPCEFS,              { RS, RB } },
02399 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS,              { RS, RB } },
02400 { "efsctuf",  VX(4, 726), VX_MASK, PPCEFS,              { RS, RB } },
02401 { "efsctsf",  VX(4, 727), VX_MASK, PPCEFS,              { RS, RB } },
02402 
02403 { "evmhossf",  VX(4, 1031), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02404 { "evmhossfa", VX(4, 1063), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02405 { "evmhosmf",  VX(4, 1039), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02406 { "evmhosmfa", VX(4, 1071), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02407 { "evmhosmi",  VX(4, 1037), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02408 { "evmhosmia", VX(4, 1069), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02409 { "evmhoumi",  VX(4, 1036), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02410 { "evmhoumia", VX(4, 1068), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02411 { "evmhessf",  VX(4, 1027), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02412 { "evmhessfa", VX(4, 1059), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02413 { "evmhesmf",  VX(4, 1035), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02414 { "evmhesmfa", VX(4, 1067), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02415 { "evmhesmi",  VX(4, 1033), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02416 { "evmhesmia", VX(4, 1065), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02417 { "evmheumi",  VX(4, 1032), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02418 { "evmheumia", VX(4, 1064), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02419 
02420 { "evmhossfaaw",VX(4, 1287), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02421 { "evmhossiaaw",VX(4, 1285), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02422 { "evmhosmfaaw",VX(4, 1295), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02423 { "evmhosmiaaw",VX(4, 1293), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02424 { "evmhousiaaw",VX(4, 1284), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02425 { "evmhoumiaaw",VX(4, 1292), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02426 { "evmhessfaaw",VX(4, 1283), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02427 { "evmhessiaaw",VX(4, 1281), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02428 { "evmhesmfaaw",VX(4, 1291), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02429 { "evmhesmiaaw",VX(4, 1289), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02430 { "evmheusiaaw",VX(4, 1280), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02431 { "evmheumiaaw",VX(4, 1288), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02432 
02433 { "evmhossfanw",VX(4, 1415), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02434 { "evmhossianw",VX(4, 1413), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02435 { "evmhosmfanw",VX(4, 1423), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02436 { "evmhosmianw",VX(4, 1421), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02437 { "evmhousianw",VX(4, 1412), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02438 { "evmhoumianw",VX(4, 1420), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02439 { "evmhessfanw",VX(4, 1411), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02440 { "evmhessianw",VX(4, 1409), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02441 { "evmhesmfanw",VX(4, 1419), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02442 { "evmhesmianw",VX(4, 1417), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02443 { "evmheusianw",VX(4, 1408), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02444 { "evmheumianw",VX(4, 1416), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02445 
02446 { "evmhogsmfaa",VX(4, 1327), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02447 { "evmhogsmiaa",VX(4, 1325), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02448 { "evmhogumiaa",VX(4, 1324), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02449 { "evmhegsmfaa",VX(4, 1323), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02450 { "evmhegsmiaa",VX(4, 1321), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02451 { "evmhegumiaa",VX(4, 1320), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02452 
02453 { "evmhogsmfan",VX(4, 1455), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02454 { "evmhogsmian",VX(4, 1453), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02455 { "evmhogumian",VX(4, 1452), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02456 { "evmhegsmfan",VX(4, 1451), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02457 { "evmhegsmian",VX(4, 1449), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02458 { "evmhegumian",VX(4, 1448), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02459 
02460 { "evmwhssf",  VX(4, 1095), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02461 { "evmwhssfa", VX(4, 1127), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02462 { "evmwhsmf",  VX(4, 1103), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02463 { "evmwhsmfa", VX(4, 1135), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02464 { "evmwhsmi",  VX(4, 1101), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02465 { "evmwhsmia", VX(4, 1133), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02466 { "evmwhumi",  VX(4, 1100), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02467 { "evmwhumia", VX(4, 1132), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02468 
02469 { "evmwlumi",  VX(4, 1096), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02470 { "evmwlumia", VX(4, 1128), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02471 
02472 { "evmwlssiaaw",VX(4, 1345), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02473 { "evmwlsmiaaw",VX(4, 1353), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02474 { "evmwlusiaaw",VX(4, 1344), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02475 { "evmwlumiaaw",VX(4, 1352), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02476 
02477 { "evmwlssianw",VX(4, 1473), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02478 { "evmwlsmianw",VX(4, 1481), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02479 { "evmwlusianw",VX(4, 1472), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02480 { "evmwlumianw",VX(4, 1480), VX_MASK,     PPCSPE,              { RS, RA, RB } },
02481 
02482 { "evmwssf",   VX(4, 1107), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02483 { "evmwssfa",  VX(4, 1139), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02484 { "evmwsmf",   VX(4, 1115), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02485 { "evmwsmfa",  VX(4, 1147), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02486 { "evmwsmi",   VX(4, 1113), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02487 { "evmwsmia",  VX(4, 1145), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02488 { "evmwumi",   VX(4, 1112), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02489 { "evmwumia",  VX(4, 1144), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02490 
02491 { "evmwssfaa", VX(4, 1363), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02492 { "evmwsmfaa", VX(4, 1371), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02493 { "evmwsmiaa", VX(4, 1369), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02494 { "evmwumiaa", VX(4, 1368), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02495 
02496 { "evmwssfan", VX(4, 1491), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02497 { "evmwsmfan", VX(4, 1499), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02498 { "evmwsmian", VX(4, 1497), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02499 { "evmwumian", VX(4, 1496), VX_MASK,      PPCSPE,              { RS, RA, RB } },
02500 
02501 { "evaddssiaaw",VX(4, 1217), VX_MASK,     PPCSPE,              { RS, RA } },
02502 { "evaddsmiaaw",VX(4, 1225), VX_MASK,     PPCSPE,              { RS, RA } },
02503 { "evaddusiaaw",VX(4, 1216), VX_MASK,     PPCSPE,              { RS, RA } },
02504 { "evaddumiaaw",VX(4, 1224), VX_MASK,     PPCSPE,              { RS, RA } },
02505 
02506 { "evsubfssiaaw",VX(4, 1219), VX_MASK,    PPCSPE,              { RS, RA } },
02507 { "evsubfsmiaaw",VX(4, 1227), VX_MASK,    PPCSPE,              { RS, RA } },
02508 { "evsubfusiaaw",VX(4, 1218), VX_MASK,    PPCSPE,              { RS, RA } },
02509 { "evsubfumiaaw",VX(4, 1226), VX_MASK,    PPCSPE,              { RS, RA } },
02510 
02511 { "evmra",    VX(4, 1220), VX_MASK,       PPCSPE,              { RS, RA } },
02512 
02513 { "evdivws",  VX(4, 1222), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02514 { "evdivwu",  VX(4, 1223), VX_MASK,       PPCSPE,              { RS, RA, RB } },
02515 
02516 { "mulli",   OP(7),  OP_MASK,      PPCCOM,              { RT, RA, SI } },
02517 { "muli",    OP(7),  OP_MASK,      PWRCOM,              { RT, RA, SI } },
02518 
02519 { "subfic",  OP(8),  OP_MASK,      PPCCOM,              { RT, RA, SI } },
02520 { "sfi",     OP(8),  OP_MASK,      PWRCOM,              { RT, RA, SI } },
02521 
02522 { "dozi",    OP(9),  OP_MASK,      M601,         { RT, RA, SI } },
02523 
02524 { "bce",     B(9,0,0),      B_MASK,              BOOKE64,      { BO, BI, BD } },
02525 { "bcel",    B(9,0,1),      B_MASK,              BOOKE64,      { BO, BI, BD } },
02526 { "bcea",    B(9,1,0),      B_MASK,              BOOKE64,      { BO, BI, BDA } },
02527 { "bcela",   B(9,1,1),      B_MASK,              BOOKE64,      { BO, BI, BDA } },
02528 
02529 { "cmplwi",  OPL(10,0),     OPL_MASK,     PPCCOM,              { OBF, RA, UI } },
02530 { "cmpldi",  OPL(10,1), OPL_MASK,  PPC64,        { OBF, RA, UI } },
02531 { "cmpli",   OP(10), OP_MASK,      PPC,          { BF, L, RA, UI } },
02532 { "cmpli",   OP(10), OP_MASK,      PWRCOM,              { BF, RA, UI } },
02533 
02534 { "cmpwi",   OPL(11,0),     OPL_MASK,     PPCCOM,              { OBF, RA, SI } },
02535 { "cmpdi",   OPL(11,1),     OPL_MASK,     PPC64,        { OBF, RA, SI } },
02536 { "cmpi",    OP(11), OP_MASK,      PPC,          { BF, L, RA, SI } },
02537 { "cmpi",    OP(11), OP_MASK,      PWRCOM,              { BF, RA, SI } },
02538 
02539 { "addic",   OP(12), OP_MASK,      PPCCOM,              { RT, RA, SI } },
02540 { "ai",            OP(12),  OP_MASK,      PWRCOM,              { RT, RA, SI } },
02541 { "subic",   OP(12), OP_MASK,      PPCCOM,              { RT, RA, NSI } },
02542 
02543 { "addic.",  OP(13), OP_MASK,      PPCCOM,              { RT, RA, SI } },
02544 { "ai.",     OP(13), OP_MASK,      PWRCOM,              { RT, RA, SI } },
02545 { "subic.",  OP(13), OP_MASK,      PPCCOM,              { RT, RA, NSI } },
02546 
02547 { "li",            OP(14),  DRA_MASK,     PPCCOM,              { RT, SI } },
02548 { "lil",     OP(14), DRA_MASK,     PWRCOM,              { RT, SI } },
02549 { "addi",    OP(14), OP_MASK,      PPCCOM,              { RT, RA0, SI } },
02550 { "cal",     OP(14), OP_MASK,      PWRCOM,              { RT, D, RA0 } },
02551 { "subi",    OP(14), OP_MASK,      PPCCOM,              { RT, RA0, NSI } },
02552 { "la",            OP(14),  OP_MASK,      PPCCOM,              { RT, D, RA0 } },
02553 
02554 { "lis",     OP(15), DRA_MASK,     PPCCOM,              { RT, SISIGNOPT } },
02555 { "liu",     OP(15), DRA_MASK,     PWRCOM,              { RT, SISIGNOPT } },
02556 { "addis",   OP(15), OP_MASK,      PPCCOM,              { RT,RA0,SISIGNOPT } },
02557 { "cau",     OP(15), OP_MASK,      PWRCOM,              { RT,RA0,SISIGNOPT } },
02558 { "subis",   OP(15), OP_MASK,      PPCCOM,              { RT, RA0, NSI } },
02559 
02560 { "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BDM } },
02561 { "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BDP } },
02562 { "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,     { BD } },
02563 { "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,     { BD } },
02564 { "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BDM } },
02565 { "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BDP } },
02566 { "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,     { BD } },
02567 { "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,     { BD } },
02568 { "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDMA } },
02569 { "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDPA } },
02570 { "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,     { BDA } },
02571 { "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,     { BDA } },
02572 { "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDMA } },
02573 { "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDPA } },
02574 { "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,     { BDA } },
02575 { "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,     { BDA } },
02576 { "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,     { BDM } },
02577 { "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,     { BDP } },
02578 { "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,        { BD } },
02579 { "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,     { BDM } },
02580 { "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,     { BDP } },
02581 { "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,        { BD } },
02582 { "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,     { BDMA } },
02583 { "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,     { BDPA } },
02584 { "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,        { BDA } },
02585 { "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,     { BDMA } },
02586 { "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,     { BDPA } },
02587 { "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,        { BDA } },
02588 { "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02589 { "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02590 { "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02591 { "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02592 { "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02593 { "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02594 { "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02595 { "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02596 { "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02597 { "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02598 { "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02599 { "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02600 { "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02601 { "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02602 { "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02603 { "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02604 { "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02605 { "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02606 { "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02607 { "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02608 { "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02609 { "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02610 { "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02611 { "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02612 { "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02613 { "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02614 { "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02615 { "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02616 { "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02617 { "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02618 { "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02619 { "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02620 { "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02621 { "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02622 { "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02623 { "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02624 { "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02625 { "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02626 { "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02627 { "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02628 { "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02629 { "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02630 { "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02631 { "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02632 { "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02633 { "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02634 { "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02635 { "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02636 { "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02637 { "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02638 { "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BD } },
02639 { "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02640 { "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02641 { "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BD } },
02642 { "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02643 { "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02644 { "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDA } },
02645 { "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02646 { "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02647 { "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDA } },
02648 { "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02649 { "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02650 { "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02651 { "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02652 { "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02653 { "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02654 { "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02655 { "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02656 { "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02657 { "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02658 { "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02659 { "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02660 { "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02661 { "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02662 { "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02663 { "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02664 { "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02665 { "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02666 { "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02667 { "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02668 { "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02669 { "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02670 { "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02671 { "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02672 { "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02673 { "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02674 { "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02675 { "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02676 { "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02677 { "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02678 { "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02679 { "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02680 { "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02681 { "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02682 { "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02683 { "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02684 { "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02685 { "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02686 { "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02687 { "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02688 { "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02689 { "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02690 { "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02691 { "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02692 { "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02693 { "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02694 { "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02695 { "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02696 { "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02697 { "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02698 { "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02699 { "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02700 { "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02701 { "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02702 { "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02703 { "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02704 { "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02705 { "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02706 { "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02707 { "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02708 { "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02709 { "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02710 { "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,        { CR, BD } },
02711 { "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02712 { "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02713 { "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,        { CR, BD } },
02714 { "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02715 { "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02716 { "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,        { CR, BDA } },
02717 { "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02718 { "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02719 { "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,        { CR, BDA } },
02720 { "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02721 { "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02722 { "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,     { CR, BD } },
02723 { "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDM } },
02724 { "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BDP } },
02725 { "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,     { CR, BD } },
02726 { "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02727 { "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02728 { "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,     { CR, BDA } },
02729 { "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDMA } },
02730 { "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDPA } },
02731 { "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,     { CR, BDA } },
02732 { "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
02733 { "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
02734 { "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
02735 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
02736 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
02737 { "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
02738 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
02739 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
02740 { "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
02741 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
02742 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
02743 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
02744 { "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
02745 { "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
02746 { "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
02747 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
02748 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
02749 { "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
02750 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
02751 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
02752 { "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
02753 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
02754 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
02755 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
02756 { "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
02757 { "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
02758 { "bt",            BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
02759 { "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
02760 { "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
02761 { "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
02762 { "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
02763 { "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
02764 { "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
02765 { "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
02766 { "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
02767 { "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
02768 { "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
02769 { "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
02770 { "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
02771 { "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
02772 { "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
02773 { "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
02774 { "bf",            BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
02775 { "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
02776 { "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
02777 { "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
02778 { "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
02779 { "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
02780 { "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
02781 { "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
02782 { "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
02783 { "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
02784 { "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
02785 { "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
02786 { "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
02787 { "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
02788 { "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
02789 { "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
02790 { "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
02791 { "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
02792 { "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
02793 { "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
02794 { "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
02795 { "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
02796 { "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
02797 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
02798 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
02799 { "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
02800 { "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
02801 { "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
02802 { "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
02803 { "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
02804 { "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
02805 { "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
02806 { "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
02807 { "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
02808 { "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
02809 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
02810 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
02811 { "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
02812 { "bc-",     B(16,0,0),     B_MASK,              PPCCOM,              { BOE, BI, BDM } },
02813 { "bc+",     B(16,0,0),     B_MASK,              PPCCOM,              { BOE, BI, BDP } },
02814 { "bc",            B(16,0,0),      B_MASK,              COM,          { BO, BI, BD } },
02815 { "bcl-",    B(16,0,1),     B_MASK,              PPCCOM,              { BOE, BI, BDM } },
02816 { "bcl+",    B(16,0,1),     B_MASK,              PPCCOM,              { BOE, BI, BDP } },
02817 { "bcl",     B(16,0,1),     B_MASK,              COM,          { BO, BI, BD } },
02818 { "bca-",    B(16,1,0),     B_MASK,              PPCCOM,              { BOE, BI, BDMA } },
02819 { "bca+",    B(16,1,0),     B_MASK,              PPCCOM,              { BOE, BI, BDPA } },
02820 { "bca",     B(16,1,0),     B_MASK,              COM,          { BO, BI, BDA } },
02821 { "bcla-",   B(16,1,1),     B_MASK,              PPCCOM,              { BOE, BI, BDMA } },
02822 { "bcla+",   B(16,1,1),     B_MASK,              PPCCOM,              { BOE, BI, BDPA } },
02823 { "bcla",    B(16,1,1),     B_MASK,              COM,          { BO, BI, BDA } },
02824 
02825 { "sc",      SC(17,1,0), SC_MASK,  PPC,          { LEV } },
02826 { "svc",     SC(17,0,0), SC_MASK,  POWER,        { SVC_LEV, FL1, FL2 } },
02827 { "svcl",    SC(17,0,1), SC_MASK,  POWER,        { SVC_LEV, FL1, FL2 } },
02828 { "svca",    SC(17,1,0), SC_MASK,  PWRCOM,              { SV } },
02829 { "svcla",   SC(17,1,1), SC_MASK,  POWER,        { SV } },
02830 
02831 { "b",      B(18,0,0),      B_MASK,              COM,          { LI } },
02832 { "bl",      B(18,0,1),     B_MASK,              COM,          { LI } },
02833 { "ba",      B(18,1,0),     B_MASK,              COM,          { LIA } },
02834 { "bla",     B(18,1,1),     B_MASK,              COM,          { LIA } },
02835 
02836 { "mcrf",    XL(19,0),      XLBB_MASK|(3 << 21)|(3 << 16), COM,       { BF, BFA } },
02837 
02838 { "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
02839 { "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
02840 { "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
02841 { "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
02842 { "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
02843 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
02844 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,      { 0 } },
02845 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,     { 0 } },
02846 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,      { 0 } },
02847 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
02848 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
02849 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,      { 0 } },
02850 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,     { 0 } },
02851 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,      { 0 } },
02852 { "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
02853 { "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
02854 { "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
02855 { "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
02856 { "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
02857 { "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
02858 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
02859 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
02860 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
02861 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
02862 { "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02863 { "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02864 { "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02865 { "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02866 { "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02867 { "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02868 { "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02869 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02870 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02871 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02872 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02873 { "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02874 { "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02875 { "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02876 { "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02877 { "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02878 { "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02879 { "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02880 { "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02881 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02882 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02883 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02884 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02885 { "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02886 { "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02887 { "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02888 { "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02889 { "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02890 { "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02891 { "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02892 { "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02893 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02894 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02895 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02896 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02897 { "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02898 { "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02899 { "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02900 { "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02901 { "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02902 { "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02903 { "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02904 { "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02905 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02906 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02907 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02908 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02909 { "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02910 { "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02911 { "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02912 { "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02913 { "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02914 { "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02915 { "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02916 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02917 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02918 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02919 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02920 { "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02921 { "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02922 { "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02923 { "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02924 { "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02925 { "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02926 { "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02927 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02928 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02929 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02930 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02931 { "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02932 { "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02933 { "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02934 { "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02935 { "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02936 { "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02937 { "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02938 { "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02939 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02940 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02941 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02942 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02943 { "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02944 { "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02945 { "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02946 { "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02947 { "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02948 { "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02949 { "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02950 { "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02951 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02952 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02953 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02954 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02955 { "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02956 { "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02957 { "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02958 { "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02959 { "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02960 { "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02961 { "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02962 { "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02963 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02964 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02965 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02966 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02967 { "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02968 { "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02969 { "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02970 { "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02971 { "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02972 { "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02973 { "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02974 { "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02975 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02976 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02977 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02978 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02979 { "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02980 { "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02981 { "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02982 { "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02983 { "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02984 { "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02985 { "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
02986 { "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02987 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02988 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02989 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02990 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
02991 { "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
02992 { "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
02993 { "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02994 { "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02995 { "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
02996 { "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
02997 { "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
02998 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
02999 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
03000 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03001 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
03002 { "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
03003 { "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
03004 { "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
03005 { "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
03006 { "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
03007 { "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
03008 { "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
03009 { "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
03010 { "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
03011 { "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
03012 { "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
03013 { "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
03014 { "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,     { BI } },
03015 { "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,   { BI } },
03016 { "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,   { BI } },
03017 { "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,  { BI } },
03018 { "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,   { BI } },
03019 { "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,     { BI } },
03020 { "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,     { BI } },
03021 { "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,   { BI } },
03022 { "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,   { BI } },
03023 { "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,  { BI } },
03024 { "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,   { BI } },
03025 { "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,     { BI } },
03026 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
03027 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03028 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03029 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
03030 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03031 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03032 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,  { BI } },
03033 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03034 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03035 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,  { BI } },
03036 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03037 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03038 { "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
03039 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03040 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03041 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
03042 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03043 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03044 { "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,   { BI } },
03045 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03046 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
03047 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,   { BI } },
03048 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03049 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
03050 { "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
03051 { "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
03052 { "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,      { BOE, BI } },
03053 { "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,      { BOE, BI } },
03054 { "bclr",    XLLK(19,16,0), XLBH_MASK,    PPCCOM,              { BO, BI, BH } },
03055 { "bclrl",   XLLK(19,16,1), XLBH_MASK,    PPCCOM,              { BO, BI, BH } },
03056 { "bcr",     XLLK(19,16,0), XLBB_MASK,    PWRCOM,              { BO, BI } },
03057 { "bcrl",    XLLK(19,16,1), XLBB_MASK,    PWRCOM,              { BO, BI } },
03058 { "bclre",   XLLK(19,17,0), XLBB_MASK,    BOOKE64,      { BO, BI } },
03059 { "bclrel",  XLLK(19,17,1), XLBB_MASK,    BOOKE64,      { BO, BI } },
03060 
03061 { "rfid",    XL(19,18),     0xffffffff,   PPC64,        { 0 } },
03062 
03063 { "crnot",   XL(19,33), XL_MASK,   PPCCOM,              { BT, BA, BBA } },
03064 { "crnor",   XL(19,33),     XL_MASK,      COM,          { BT, BA, BB } },
03065 { "rfmci",    X(19,38), 0xffffffff,       PPCRFMCI,     { 0 } },
03066 
03067 { "rfi",     XL(19,50),     0xffffffff,   COM,          { 0 } },
03068 { "rfci",    XL(19,51),     0xffffffff,   PPC403 | BOOKE,      { 0 } },
03069 
03070 { "rfsvc",   XL(19,82),     0xffffffff,   POWER,        { 0 } },
03071 
03072 { "crandc",  XL(19,129), XL_MASK,  COM,          { BT, BA, BB } },
03073 
03074 { "isync",   XL(19,150), 0xffffffff,      PPCCOM,              { 0 } },
03075 { "ics",     XL(19,150), 0xffffffff,      PWRCOM,              { 0 } },
03076 
03077 { "crclr",   XL(19,193), XL_MASK,  PPCCOM,              { BT, BAT, BBA } },
03078 { "crxor",   XL(19,193), XL_MASK,  COM,          { BT, BA, BB } },
03079 
03080 { "crnand",  XL(19,225), XL_MASK,  COM,          { BT, BA, BB } },
03081 
03082 { "crand",   XL(19,257), XL_MASK,  COM,          { BT, BA, BB } },
03083 
03084 { "hrfid",   XL(19,274), 0xffffffff,      POWER5 | CELL,       { 0 } },
03085 
03086 { "crset",   XL(19,289), XL_MASK,  PPCCOM,              { BT, BAT, BBA } },
03087 { "creqv",   XL(19,289), XL_MASK,  COM,          { BT, BA, BB } },
03088 
03089 { "doze",    XL(19,402), 0xffffffff,      POWER6,              { 0 } },
03090 
03091 { "crorc",   XL(19,417), XL_MASK,  COM,          { BT, BA, BB } },
03092 
03093 { "nap",     XL(19,434), 0xffffffff,      POWER6,              { 0 } },
03094 
03095 { "crmove",  XL(19,449), XL_MASK,  PPCCOM,              { BT, BA, BBA } },
03096 { "cror",    XL(19,449), XL_MASK,  COM,          { BT, BA, BB } },
03097 
03098 { "sleep",   XL(19,466), 0xffffffff,      POWER6,              { 0 } },
03099 { "rvwinkle", XL(19,498), 0xffffffff,     POWER6,              { 0 } },
03100 
03101 { "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,     { 0 } },
03102 { "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,     { 0 } },
03103 { "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03104 { "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03105 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03106 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03107 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03108 { "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03109 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03110 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03111 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03112 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03113 { "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03114 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03115 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03116 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03117 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03118 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03119 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03120 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03121 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03122 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03123 { "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03124 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03125 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03126 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03127 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03128 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03129 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03130 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03131 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03132 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03133 { "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03134 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03135 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03136 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03137 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03138 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03139 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03140 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03141 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03142 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03143 { "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03144 { "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03145 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03146 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03147 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03148 { "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03149 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03150 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03151 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03152 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03153 { "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03154 { "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03155 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03156 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03157 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03158 { "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03159 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03160 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03161 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03162 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03163 { "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03164 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03165 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03166 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03167 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03168 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03169 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03170 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03171 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03172 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03173 { "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03174 { "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03175 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03176 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03177 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03178 { "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03179 { "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03180 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03181 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03182 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03183 { "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03184 { "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03185 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03186 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03187 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03188 { "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03189 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03190 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03191 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03192 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03193 { "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03194 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03195 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03196 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03197 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03198 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03199 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03200 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03201 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03202 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03203 { "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03204 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03205 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03206 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03207 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03208 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03209 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03210 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03211 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03212 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03213 { "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM, { CR } },
03214 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03215 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03216 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
03217 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
03218 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM, { CR } },
03219 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
03220 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03221 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
03222 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
03223 { "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
03224 { "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
03225 { "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
03226 { "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
03227 { "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
03228 { "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
03229 { "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
03230 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
03231 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
03232 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
03233 { "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,   { BI } },
03234 { "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
03235 { "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
03236 { "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
03237 { "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
03238 { "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,   { BI } },
03239 { "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
03240 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
03241 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
03242 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
03243 { "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
03244 { "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
03245 { "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
03246 { "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,   { BOE, BI } },
03247 { "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
03248 { "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,   { BO, BI, BH } },
03249 { "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,   { BO, BI } },
03250 { "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,   { BO, BI } },
03251 { "bcctre",  XLLK(19,529,0),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
03252 { "bcctrel", XLLK(19,529,1),     XLYBB_MASK,  BOOKE64,  { BO, BI } },
03253 
03254 { "rlwimi",  M(20,0),       M_MASK,              PPCCOM,              { RA,RS,SH,MBE,ME } },
03255 { "rlimi",   M(20,0),       M_MASK,              PWRCOM,              { RA,RS,SH,MBE,ME } },
03256 
03257 { "rlwimi.", M(20,1),       M_MASK,              PPCCOM,              { RA,RS,SH,MBE,ME } },
03258 { "rlimi.",  M(20,1),       M_MASK,              PWRCOM,              { RA,RS,SH,MBE,ME } },
03259 
03260 { "rotlwi",  MME(21,31,0), MMBME_MASK,    PPCCOM,              { RA, RS, SH } },
03261 { "clrlwi",  MME(21,31,0), MSHME_MASK,    PPCCOM,              { RA, RS, MB } },
03262 { "rlwinm",  M(21,0),       M_MASK,              PPCCOM,              { RA,RS,SH,MBE,ME } },
03263 { "rlinm",   M(21,0),       M_MASK,              PWRCOM,              { RA,RS,SH,MBE,ME } },
03264 { "rotlwi.", MME(21,31,1), MMBME_MASK,    PPCCOM,              { RA,RS,SH } },
03265 { "clrlwi.", MME(21,31,1), MSHME_MASK,    PPCCOM,              { RA, RS, MB } },
03266 { "rlwinm.", M(21,1),       M_MASK,              PPCCOM,              { RA,RS,SH,MBE,ME } },
03267 { "rlinm.",  M(21,1),       M_MASK,              PWRCOM,              { RA,RS,SH,MBE,ME } },
03268 
03269 { "rlmi",    M(22,0),       M_MASK,              M601,         { RA,RS,RB,MBE,ME } },
03270 { "rlmi.",   M(22,1),       M_MASK,              M601,         { RA,RS,RB,MBE,ME } },
03271 
03272 { "be",            B(22,0,0),      B_MASK,              BOOKE64,      { LI } },
03273 { "bel",     B(22,0,1),     B_MASK,              BOOKE64,      { LI } },
03274 { "bea",     B(22,1,0),     B_MASK,              BOOKE64,      { LIA } },
03275 { "bela",    B(22,1,1),     B_MASK,              BOOKE64,      { LIA } },
03276 
03277 { "rotlw",   MME(23,31,0), MMBME_MASK,    PPCCOM,              { RA, RS, RB } },
03278 { "rlwnm",   M(23,0),       M_MASK,              PPCCOM,              { RA,RS,RB,MBE,ME } },
03279 { "rlnm",    M(23,0),       M_MASK,              PWRCOM,              { RA,RS,RB,MBE,ME } },
03280 { "rotlw.",  MME(23,31,1), MMBME_MASK,    PPCCOM,              { RA, RS, RB } },
03281 { "rlwnm.",  M(23,1),       M_MASK,              PPCCOM,              { RA,RS,RB,MBE,ME } },
03282 { "rlnm.",   M(23,1),       M_MASK,              PWRCOM,              { RA,RS,RB,MBE,ME } },
03283 
03284 { "nop",     OP(24), 0xffffffff,   PPCCOM,              { 0 } },
03285 { "ori",     OP(24), OP_MASK,      PPCCOM,              { RA, RS, UI } },
03286 { "oril",    OP(24), OP_MASK,      PWRCOM,              { RA, RS, UI } },
03287 
03288 { "oris",    OP(25), OP_MASK,      PPCCOM,              { RA, RS, UI } },
03289 { "oriu",    OP(25), OP_MASK,      PWRCOM,              { RA, RS, UI } },
03290 
03291 { "xori",    OP(26), OP_MASK,      PPCCOM,              { RA, RS, UI } },
03292 { "xoril",   OP(26), OP_MASK,      PWRCOM,              { RA, RS, UI } },
03293 
03294 { "xoris",   OP(27), OP_MASK,      PPCCOM,              { RA, RS, UI } },
03295 { "xoriu",   OP(27), OP_MASK,      PWRCOM,              { RA, RS, UI } },
03296 
03297 { "andi.",   OP(28), OP_MASK,      PPCCOM,              { RA, RS, UI } },
03298 { "andil.",  OP(28), OP_MASK,      PWRCOM,              { RA, RS, UI } },
03299 
03300 { "andis.",  OP(29), OP_MASK,      PPCCOM,              { RA, RS, UI } },
03301 { "andiu.",  OP(29), OP_MASK,      PWRCOM,              { RA, RS, UI } },
03302 
03303 { "rotldi",  MD(30,0,0), MDMB_MASK,       PPC64,        { RA, RS, SH6 } },
03304 { "clrldi",  MD(30,0,0), MDSH_MASK,       PPC64,        { RA, RS, MB6 } },
03305 { "rldicl",  MD(30,0,0), MD_MASK,  PPC64,        { RA, RS, SH6, MB6 } },
03306 { "rotldi.", MD(30,0,1), MDMB_MASK,       PPC64,        { RA, RS, SH6 } },
03307 { "clrldi.", MD(30,0,1), MDSH_MASK,       PPC64,        { RA, RS, MB6 } },
03308 { "rldicl.", MD(30,0,1), MD_MASK,  PPC64,        { RA, RS, SH6, MB6 } },
03309 
03310 { "rldicr",  MD(30,1,0), MD_MASK,  PPC64,        { RA, RS, SH6, ME6 } },
03311 { "rldicr.", MD(30,1,1), MD_MASK,  PPC64,        { RA, RS, SH6, ME6 } },
03312 
03313 { "rldic",   MD(30,2,0), MD_MASK,  PPC64,        { RA, RS, SH6, MB6 } },
03314 { "rldic.",  MD(30,2,1), MD_MASK,  PPC64