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cell-binutils  2.17cvs20070401
openrisc-desc.h
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00001 /* CPU data header for openrisc.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef OPENRISC_CPU_H
00026 #define OPENRISC_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH openrisc
00031 
00032 /* Given symbol S, return openrisc_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) openrisc##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) openrisc_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_OPENRISCBF
00042 
00043 #define CGEN_INSN_LSB0_P 1
00044 
00045 /* Minimum size of any insn (in bytes).  */
00046 #define CGEN_MIN_INSN_SIZE 4
00047 
00048 /* Maximum size of any insn (in bytes).  */
00049 #define CGEN_MAX_INSN_SIZE 4
00050 
00051 #define CGEN_INT_INSN_P 1
00052 
00053 /* Maximum number of syntax elements in an instruction.  */
00054 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 14
00055 
00056 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00057    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00058    we can't hash on everything up to the space.  */
00059 #define CGEN_MNEMONIC_OPERANDS
00060 
00061 /* Maximum number of fields in an instruction.  */
00062 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
00063 
00064 /* Enums.  */
00065 
00066 /* Enum declaration for exception vectors.  */
00067 typedef enum e_exception {
00068   E_RESET, E_BUSERR, E_DPF, E_IPF
00069  , E_EXTINT, E_ALIGN, E_ILLEGAL, E_PEINT
00070  , E_DTLBMISS, E_ITLBMISS, E_RRANGE, E_SYSCALL
00071  , E_BREAK, E_RESERVED
00072 } E_EXCEPTION;
00073 
00074 /* Enum declaration for FIXME.  */
00075 typedef enum insn_class {
00076   OP1_0, OP1_1, OP1_2, OP1_3
00077 } INSN_CLASS;
00078 
00079 /* Enum declaration for FIXME.  */
00080 typedef enum insn_sub {
00081   OP2_0, OP2_1, OP2_2, OP2_3
00082  , OP2_4, OP2_5, OP2_6, OP2_7
00083  , OP2_8, OP2_9, OP2_10, OP2_11
00084  , OP2_12, OP2_13, OP2_14, OP2_15
00085 } INSN_SUB;
00086 
00087 /* Enum declaration for FIXME.  */
00088 typedef enum insn_op3 {
00089   OP3_0, OP3_1, OP3_2, OP3_3
00090 } INSN_OP3;
00091 
00092 /* Enum declaration for FIXME.  */
00093 typedef enum insn_op4 {
00094   OP4_0, OP4_1, OP4_2, OP4_3
00095  , OP4_4, OP4_5, OP4_6, OP4_7
00096 } INSN_OP4;
00097 
00098 /* Enum declaration for FIXME.  */
00099 typedef enum insn_op5 {
00100   OP5_0, OP5_1, OP5_2, OP5_3
00101  , OP5_4, OP5_5, OP5_6, OP5_7
00102  , OP5_8, OP5_9, OP5_10, OP5_11
00103  , OP5_12, OP5_13, OP5_14, OP5_15
00104  , OP5_16, OP5_17, OP5_18, OP5_19
00105  , OP5_20, OP5_21, OP5_22, OP5_23
00106  , OP5_24, OP5_25, OP5_26, OP5_27
00107  , OP5_28, OP5_29, OP5_30, OP5_31
00108 } INSN_OP5;
00109 
00110 /* Enum declaration for FIXME.  */
00111 typedef enum insn_op6 {
00112   OP6_0, OP6_1, OP6_2, OP6_3
00113  , OP6_4, OP6_5, OP6_6, OP6_7
00114 } INSN_OP6;
00115 
00116 /* Enum declaration for FIXME.  */
00117 typedef enum insn_op7 {
00118   OP7_0, OP7_1, OP7_2, OP7_3
00119  , OP7_4, OP7_5, OP7_6, OP7_7
00120  , OP7_8, OP7_9, OP7_10, OP7_11
00121  , OP7_12, OP7_13, OP7_14, OP7_15
00122 } INSN_OP7;
00123 
00124 /* Attributes.  */
00125 
00126 /* Enum declaration for machine type selection.  */
00127 typedef enum mach_attr {
00128   MACH_BASE, MACH_OPENRISC, MACH_OR1300, MACH_MAX
00129 } MACH_ATTR;
00130 
00131 /* Enum declaration for instruction set selection.  */
00132 typedef enum isa_attr {
00133   ISA_OR32, ISA_MAX
00134 } ISA_ATTR;
00135 
00136 /* Enum declaration for if this model has caches.  */
00137 typedef enum has_cache_attr {
00138   HAS_CACHE_DATA_CACHE, HAS_CACHE_INSN_CACHE
00139 } HAS_CACHE_ATTR;
00140 
00141 /* Number of architecture variants.  */
00142 #define MAX_ISAS  1
00143 #define MAX_MACHS ((int) MACH_MAX)
00144 
00145 /* Ifield support.  */
00146 
00147 /* Ifield attribute indices.  */
00148 
00149 /* Enum declaration for cgen_ifld attrs.  */
00150 typedef enum cgen_ifld_attr {
00151   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00152  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00153  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00154 } CGEN_IFLD_ATTR;
00155 
00156 /* Number of non-boolean elements in cgen_ifld_attr.  */
00157 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00158 
00159 /* cgen_ifld attribute accessor macros.  */
00160 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00161 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00162 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00163 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00164 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00165 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00166 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00167 
00168 /* Enum declaration for openrisc ifield types.  */
00169 typedef enum ifield_type {
00170   OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS, OPENRISC_F_SUB
00171  , OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3, OPENRISC_F_SIMM16
00172  , OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16, OPENRISC_F_LO16
00173  , OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3, OPENRISC_F_OP4
00174  , OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7, OPENRISC_F_I16_1
00175  , OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26, OPENRISC_F_I16NC
00176  , OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1, OPENRISC_F_F_7_3
00177  , OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX
00178 } IFIELD_TYPE;
00179 
00180 #define MAX_IFLD ((int) OPENRISC_F_MAX)
00181 
00182 /* Hardware attribute indices.  */
00183 
00184 /* Enum declaration for cgen_hw attrs.  */
00185 typedef enum cgen_hw_attr {
00186   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00187  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00188 } CGEN_HW_ATTR;
00189 
00190 /* Number of non-boolean elements in cgen_hw_attr.  */
00191 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00192 
00193 /* cgen_hw attribute accessor macros.  */
00194 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00195 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00196 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00197 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00198 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00199 
00200 /* Enum declaration for openrisc hardware types.  */
00201 typedef enum cgen_hw_type {
00202   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00203  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_SR
00204  , HW_H_HI16, HW_H_LO16, HW_H_CBIT, HW_H_DELAY_INSN
00205  , HW_MAX
00206 } CGEN_HW_TYPE;
00207 
00208 #define MAX_HW ((int) HW_MAX)
00209 
00210 /* Operand attribute indices.  */
00211 
00212 /* Enum declaration for cgen_operand attrs.  */
00213 typedef enum cgen_operand_attr {
00214   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00215  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00216  , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
00217 } CGEN_OPERAND_ATTR;
00218 
00219 /* Number of non-boolean elements in cgen_operand_attr.  */
00220 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00221 
00222 /* cgen_operand attribute accessor macros.  */
00223 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00224 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00225 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00226 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00227 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00228 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00229 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00230 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00231 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00232 
00233 /* Enum declaration for openrisc operand types.  */
00234 typedef enum cgen_operand_type {
00235   OPENRISC_OPERAND_PC, OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16
00236  , OPENRISC_OPERAND_UIMM_16, OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5
00237  , OPENRISC_OPERAND_RD, OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23
00238  , OPENRISC_OPERAND_OP_F_3, OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC
00239  , OPENRISC_OPERAND_MAX
00240 } CGEN_OPERAND_TYPE;
00241 
00242 /* Number of operands types.  */
00243 #define MAX_OPERANDS 16
00244 
00245 /* Maximum number of operands referenced by any insn.  */
00246 #define MAX_OPERAND_INSTANCES 8
00247 
00248 /* Insn attribute indices.  */
00249 
00250 /* Enum declaration for cgen_insn attrs.  */
00251 typedef enum cgen_insn_attr {
00252   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00253  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00254  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
00255  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
00256 } CGEN_INSN_ATTR;
00257 
00258 /* Number of non-boolean elements in cgen_insn_attr.  */
00259 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00260 
00261 /* cgen_insn attribute accessor macros.  */
00262 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00263 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00264 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00265 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00266 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00267 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00268 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00269 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00270 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00271 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00272 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00273 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
00274 
00275 /* cgen.h uses things we just defined.  */
00276 #include "opcode/cgen.h"
00277 
00278 extern const struct cgen_ifld openrisc_cgen_ifld_table[];
00279 
00280 /* Attributes.  */
00281 extern const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[];
00282 extern const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[];
00283 extern const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[];
00284 extern const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[];
00285 
00286 /* Hardware decls.  */
00287 
00288 extern CGEN_KEYWORD openrisc_cgen_opval_h_gr;
00289 
00290 extern const CGEN_HW_ENTRY openrisc_cgen_hw_table[];
00291 
00292 
00293 
00294 #endif /* OPENRISC_CPU_H */