Back to index

cell-binutils  2.17cvs20070401
openrisc-desc.c
Go to the documentation of this file.
00001 /* CPU data for openrisc.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "openrisc-desc.h"
00032 #include "openrisc-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "openrisc", MACH_OPENRISC },
00050   { "or1300", MACH_OR1300 },
00051   { "max", MACH_MAX },
00052   { 0, 0 }
00053 };
00054 
00055 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00056 {
00057   { "or32", ISA_OR32 },
00058   { "max", ISA_MAX },
00059   { 0, 0 }
00060 };
00061 
00062 static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] ATTRIBUTE_UNUSED =
00063 {
00064   { "DATA_CACHE", HAS_CACHE_DATA_CACHE },
00065   { "INSN_CACHE", HAS_CACHE_INSN_CACHE },
00066   { 0, 0 }
00067 };
00068 
00069 const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] =
00070 {
00071   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00072   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00073   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00074   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00075   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00076   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00077   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00078   { 0, 0, 0 }
00079 };
00080 
00081 const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] =
00082 {
00083   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00084   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00085   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00086   { "PC", &bool_attr[0], &bool_attr[0] },
00087   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00088   { 0, 0, 0 }
00089 };
00090 
00091 const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] =
00092 {
00093   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00094   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00095   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00096   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00097   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00098   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00099   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00100   { "RELAX", &bool_attr[0], &bool_attr[0] },
00101   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00102   { 0, 0, 0 }
00103 };
00104 
00105 const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] =
00106 {
00107   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00108   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00109   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00110   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00111   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00112   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00113   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00114   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00115   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00116   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00117   { "PBB", &bool_attr[0], &bool_attr[0] },
00118   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00119   { 0, 0, 0 }
00120 };
00121 
00122 /* Instruction set variants.  */
00123 
00124 static const CGEN_ISA openrisc_cgen_isa_table[] = {
00125   { "or32", 32, 32, 32, 32 },
00126   { 0, 0, 0, 0, 0 }
00127 };
00128 
00129 /* Machine variants.  */
00130 
00131 static const CGEN_MACH openrisc_cgen_mach_table[] = {
00132   { "openrisc", "openrisc", MACH_OPENRISC, 0 },
00133   { "or1300", "openrisc:1300", MACH_OR1300, 0 },
00134   { 0, 0, 0, 0 }
00135 };
00136 
00137 static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] =
00138 {
00139   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00140   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
00141   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
00142   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
00143   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
00144   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
00145   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
00146   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
00147   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
00148   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
00149   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
00150   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
00151   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
00152   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
00153   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
00154   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
00155   { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
00156   { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
00157   { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
00158   { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
00159   { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
00160   { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
00161   { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
00162   { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
00163   { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
00164   { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
00165   { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
00166   { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
00167   { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
00168   { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
00169   { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
00170   { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
00171   { "lr", 11, {0, {{{0, 0}}}}, 0, 0 },
00172   { "sp", 1, {0, {{{0, 0}}}}, 0, 0 },
00173   { "fp", 2, {0, {{{0, 0}}}}, 0, 0 }
00174 };
00175 
00176 CGEN_KEYWORD openrisc_cgen_opval_h_gr =
00177 {
00178   & openrisc_cgen_opval_h_gr_entries[0],
00179   35,
00180   0, 0, 0, 0, ""
00181 };
00182 
00183 
00184 /* The hardware table.  */
00185 
00186 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00187 #define A(a) (1 << CGEN_HW_##a)
00188 #else
00189 #define A(a) (1 << CGEN_HW_a)
00190 #endif
00191 
00192 const CGEN_HW_ENTRY openrisc_cgen_hw_table[] =
00193 {
00194   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00195   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00196   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00197   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00198   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00199   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00200   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00201   { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00202   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00203   { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00204   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00205   { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00206   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00207 };
00208 
00209 #undef A
00210 
00211 
00212 /* The instruction field table.  */
00213 
00214 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00215 #define A(a) (1 << CGEN_IFLD_##a)
00216 #else
00217 #define A(a) (1 << CGEN_IFLD_a)
00218 #endif
00219 
00220 const CGEN_IFLD openrisc_cgen_ifld_table[] =
00221 {
00222   { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00223   { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00224   { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00225   { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00226   { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00227   { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00228   { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00229   { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00230   { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00231   { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00232   { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00233   { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00234   { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00235   { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00236   { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00237   { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00238   { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00239   { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00240   { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00241   { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00242   { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00243   { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00244   { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00245   { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00246   { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
00247   { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
00248   { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
00249   { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
00250   { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
00251   { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
00252   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00253 };
00254 
00255 #undef A
00256 
00257 
00258 
00259 /* multi ifield declarations */
00260 
00261 const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
00262 
00263 
00264 /* multi ifield definitions */
00265 
00266 const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
00267 {
00268     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_1] } },
00269     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_2] } },
00270     { 0, { (const PTR) 0 } }
00271 };
00272 
00273 /* The operand table.  */
00274 
00275 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00276 #define A(a) (1 << CGEN_OPERAND_##a)
00277 #else
00278 #define A(a) (1 << CGEN_OPERAND_a)
00279 #endif
00280 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00281 #define OPERAND(op) OPENRISC_OPERAND_##op
00282 #else
00283 #define OPERAND(op) OPENRISC_OPERAND_op
00284 #endif
00285 
00286 const CGEN_OPERAND openrisc_cgen_operand_table[] =
00287 {
00288 /* pc: program counter */
00289   { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
00290     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } }, 
00291     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00292 /* sr: special register */
00293   { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
00294     { 0, { (const PTR) 0 } }, 
00295     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00296 /* cbit: condition bit */
00297   { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
00298     { 0, { (const PTR) 0 } }, 
00299     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00300 /* simm-16: 16 bit signed immediate */
00301   { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
00302     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 
00303     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00304 /* uimm-16: 16 bit unsigned immediate */
00305   { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
00306     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } }, 
00307     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00308 /* disp-26: pc-rel 26 bit */
00309   { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
00310     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } }, 
00311     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00312 /* abs-26: abs 26 bit */
00313   { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
00314     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } }, 
00315     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00316 /* uimm-5: imm5 */
00317   { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
00318     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } }, 
00319     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00320 /* rD: destination register */
00321   { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
00322     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } }, 
00323     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00324 /* rA: source register A */
00325   { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
00326     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } }, 
00327     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00328 /* rB: source register B */
00329   { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
00330     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } }, 
00331     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00332 /* op-f-23: f-op23 */
00333   { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
00334     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } }, 
00335     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00336 /* op-f-3: f-op3 */
00337   { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
00338     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } }, 
00339     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00340 /* hi16: high 16 bit immediate, sign optional */
00341   { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
00342     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 
00343     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00344 /* lo16: low 16 bit immediate, sign optional */
00345   { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
00346     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } }, 
00347     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00348 /* ui16nc: 16 bit immediate, sign optional */
00349   { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
00350     { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } }, 
00351     { 0|A(SIGN_OPT)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00352 /* sentinel */
00353   { 0, 0, 0, 0, 0,
00354     { 0, { (const PTR) 0 } },
00355     { 0, { { { (1<<MACH_BASE), 0 } } } } }
00356 };
00357 
00358 #undef A
00359 
00360 
00361 /* The instruction table.  */
00362 
00363 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00364 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00365 #define A(a) (1 << CGEN_INSN_##a)
00366 #else
00367 #define A(a) (1 << CGEN_INSN_a)
00368 #endif
00369 
00370 static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
00371 {
00372   /* Special null first entry.
00373      A `num' value of zero is thus invalid.
00374      Also, the special `invalid' insn resides here.  */
00375   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00376 /* l.j ${abs-26} */
00377   {
00378     OPENRISC_INSN_L_J, "l-j", "l.j", 32,
00379     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00380   },
00381 /* l.jal ${abs-26} */
00382   {
00383     OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32,
00384     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00385   },
00386 /* l.jr $rA */
00387   {
00388     OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32,
00389     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00390   },
00391 /* l.jalr $rA */
00392   {
00393     OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32,
00394     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00395   },
00396 /* l.bal ${disp-26} */
00397   {
00398     OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32,
00399     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00400   },
00401 /* l.bnf ${disp-26} */
00402   {
00403     OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32,
00404     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00405   },
00406 /* l.bf ${disp-26} */
00407   {
00408     OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32,
00409     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00410   },
00411 /* l.brk ${uimm-16} */
00412   {
00413     OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32,
00414     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00415   },
00416 /* l.rfe $rA */
00417   {
00418     OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32,
00419     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00420   },
00421 /* l.sys ${uimm-16} */
00422   {
00423     OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32,
00424     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00425   },
00426 /* l.nop */
00427   {
00428     OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32,
00429     { 0, { { { (1<<MACH_BASE), 0 } } } }
00430   },
00431 /* l.movhi $rD,$hi16 */
00432   {
00433     OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
00434     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00435   },
00436 /* l.mfsr $rD,$rA */
00437   {
00438     OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32,
00439     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00440   },
00441 /* l.mtsr $rA,$rB */
00442   {
00443     OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32,
00444     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00445   },
00446 /* l.lw $rD,${simm-16}($rA) */
00447   {
00448     OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32,
00449     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00450   },
00451 /* l.lbz $rD,${simm-16}($rA) */
00452   {
00453     OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
00454     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00455   },
00456 /* l.lbs $rD,${simm-16}($rA) */
00457   {
00458     OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32,
00459     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00460   },
00461 /* l.lhz $rD,${simm-16}($rA) */
00462   {
00463     OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
00464     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00465   },
00466 /* l.lhs $rD,${simm-16}($rA) */
00467   {
00468     OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32,
00469     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00470   },
00471 /* l.sw ${ui16nc}($rA),$rB */
00472   {
00473     OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32,
00474     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00475   },
00476 /* l.sb ${ui16nc}($rA),$rB */
00477   {
00478     OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32,
00479     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00480   },
00481 /* l.sh ${ui16nc}($rA),$rB */
00482   {
00483     OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32,
00484     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00485   },
00486 /* l.sll $rD,$rA,$rB */
00487   {
00488     OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32,
00489     { 0, { { { (1<<MACH_BASE), 0 } } } }
00490   },
00491 /* l.slli $rD,$rA,${uimm-5} */
00492   {
00493     OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32,
00494     { 0, { { { (1<<MACH_BASE), 0 } } } }
00495   },
00496 /* l.srl $rD,$rA,$rB */
00497   {
00498     OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32,
00499     { 0, { { { (1<<MACH_BASE), 0 } } } }
00500   },
00501 /* l.srli $rD,$rA,${uimm-5} */
00502   {
00503     OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32,
00504     { 0, { { { (1<<MACH_BASE), 0 } } } }
00505   },
00506 /* l.sra $rD,$rA,$rB */
00507   {
00508     OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32,
00509     { 0, { { { (1<<MACH_BASE), 0 } } } }
00510   },
00511 /* l.srai $rD,$rA,${uimm-5} */
00512   {
00513     OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32,
00514     { 0, { { { (1<<MACH_BASE), 0 } } } }
00515   },
00516 /* l.ror $rD,$rA,$rB */
00517   {
00518     OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32,
00519     { 0, { { { (1<<MACH_BASE), 0 } } } }
00520   },
00521 /* l.rori $rD,$rA,${uimm-5} */
00522   {
00523     OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32,
00524     { 0, { { { (1<<MACH_BASE), 0 } } } }
00525   },
00526 /* l.add $rD,$rA,$rB */
00527   {
00528     OPENRISC_INSN_L_ADD, "l-add", "l.add", 32,
00529     { 0, { { { (1<<MACH_BASE), 0 } } } }
00530   },
00531 /* l.addi $rD,$rA,$lo16 */
00532   {
00533     OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32,
00534     { 0, { { { (1<<MACH_BASE), 0 } } } }
00535   },
00536 /* l.sub $rD,$rA,$rB */
00537   {
00538     OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32,
00539     { 0, { { { (1<<MACH_BASE), 0 } } } }
00540   },
00541 /* l.subi $rD,$rA,$lo16 */
00542   {
00543     OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32,
00544     { 0, { { { (1<<MACH_BASE), 0 } } } }
00545   },
00546 /* l.and $rD,$rA,$rB */
00547   {
00548     OPENRISC_INSN_L_AND, "l-and", "l.and", 32,
00549     { 0, { { { (1<<MACH_BASE), 0 } } } }
00550   },
00551 /* l.andi $rD,$rA,$lo16 */
00552   {
00553     OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32,
00554     { 0, { { { (1<<MACH_BASE), 0 } } } }
00555   },
00556 /* l.or $rD,$rA,$rB */
00557   {
00558     OPENRISC_INSN_L_OR, "l-or", "l.or", 32,
00559     { 0, { { { (1<<MACH_BASE), 0 } } } }
00560   },
00561 /* l.ori $rD,$rA,$lo16 */
00562   {
00563     OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32,
00564     { 0, { { { (1<<MACH_BASE), 0 } } } }
00565   },
00566 /* l.xor $rD,$rA,$rB */
00567   {
00568     OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32,
00569     { 0, { { { (1<<MACH_BASE), 0 } } } }
00570   },
00571 /* l.xori $rD,$rA,$lo16 */
00572   {
00573     OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32,
00574     { 0, { { { (1<<MACH_BASE), 0 } } } }
00575   },
00576 /* l.mul $rD,$rA,$rB */
00577   {
00578     OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32,
00579     { 0, { { { (1<<MACH_BASE), 0 } } } }
00580   },
00581 /* l.muli $rD,$rA,$lo16 */
00582   {
00583     OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32,
00584     { 0, { { { (1<<MACH_BASE), 0 } } } }
00585   },
00586 /* l.div $rD,$rA,$rB */
00587   {
00588     OPENRISC_INSN_L_DIV, "l-div", "l.div", 32,
00589     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00590   },
00591 /* l.divu $rD,$rA,$rB */
00592   {
00593     OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32,
00594     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00595   },
00596 /* l.sfgts $rA,$rB */
00597   {
00598     OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
00599     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00600   },
00601 /* l.sfgtu $rA,$rB */
00602   {
00603     OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
00604     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00605   },
00606 /* l.sfges $rA,$rB */
00607   {
00608     OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
00609     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00610   },
00611 /* l.sfgeu $rA,$rB */
00612   {
00613     OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
00614     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00615   },
00616 /* l.sflts $rA,$rB */
00617   {
00618     OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
00619     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00620   },
00621 /* l.sfltu $rA,$rB */
00622   {
00623     OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
00624     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00625   },
00626 /* l.sfles $rA,$rB */
00627   {
00628     OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
00629     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00630   },
00631 /* l.sfleu $rA,$rB */
00632   {
00633     OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
00634     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00635   },
00636 /* l.sfgtsi $rA,${simm-16} */
00637   {
00638     OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
00639     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00640   },
00641 /* l.sfgtui $rA,${uimm-16} */
00642   {
00643     OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
00644     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00645   },
00646 /* l.sfgesi $rA,${simm-16} */
00647   {
00648     OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
00649     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00650   },
00651 /* l.sfgeui $rA,${uimm-16} */
00652   {
00653     OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
00654     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00655   },
00656 /* l.sfltsi $rA,${simm-16} */
00657   {
00658     OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
00659     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00660   },
00661 /* l.sfltui $rA,${uimm-16} */
00662   {
00663     OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
00664     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00665   },
00666 /* l.sflesi $rA,${simm-16} */
00667   {
00668     OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
00669     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00670   },
00671 /* l.sfleui $rA,${uimm-16} */
00672   {
00673     OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
00674     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00675   },
00676 /* l.sfeq $rA,$rB */
00677   {
00678     OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
00679     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00680   },
00681 /* l.sfeqi $rA,${simm-16} */
00682   {
00683     OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
00684     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00685   },
00686 /* l.sfne $rA,$rB */
00687   {
00688     OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
00689     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00690   },
00691 /* l.sfnei $rA,${simm-16} */
00692   {
00693     OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
00694     { 0|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00695   },
00696 };
00697 
00698 #undef OP
00699 #undef A
00700 
00701 /* Initialize anything needed to be done once, before any cpu_open call.  */
00702 
00703 static void
00704 init_tables (void)
00705 {
00706 }
00707 
00708 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
00709 static void build_hw_table      (CGEN_CPU_TABLE *);
00710 static void build_ifield_table  (CGEN_CPU_TABLE *);
00711 static void build_operand_table (CGEN_CPU_TABLE *);
00712 static void build_insn_table    (CGEN_CPU_TABLE *);
00713 static void openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *);
00714 
00715 /* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name.  */
00716 
00717 static const CGEN_MACH *
00718 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
00719 {
00720   while (table->name)
00721     {
00722       if (strcmp (name, table->bfd_name) == 0)
00723        return table;
00724       ++table;
00725     }
00726   abort ();
00727 }
00728 
00729 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
00730 
00731 static void
00732 build_hw_table (CGEN_CPU_TABLE *cd)
00733 {
00734   int i;
00735   int machs = cd->machs;
00736   const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0];
00737   /* MAX_HW is only an upper bound on the number of selected entries.
00738      However each entry is indexed by it's enum so there can be holes in
00739      the table.  */
00740   const CGEN_HW_ENTRY **selected =
00741     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
00742 
00743   cd->hw_table.init_entries = init;
00744   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
00745   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
00746   /* ??? For now we just use machs to determine which ones we want.  */
00747   for (i = 0; init[i].name != NULL; ++i)
00748     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
00749        & machs)
00750       selected[init[i].type] = &init[i];
00751   cd->hw_table.entries = selected;
00752   cd->hw_table.num_entries = MAX_HW;
00753 }
00754 
00755 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
00756 
00757 static void
00758 build_ifield_table (CGEN_CPU_TABLE *cd)
00759 {
00760   cd->ifld_table = & openrisc_cgen_ifld_table[0];
00761 }
00762 
00763 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
00764 
00765 static void
00766 build_operand_table (CGEN_CPU_TABLE *cd)
00767 {
00768   int i;
00769   int machs = cd->machs;
00770   const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0];
00771   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
00772      However each entry is indexed by it's enum so there can be holes in
00773      the table.  */
00774   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
00775 
00776   cd->operand_table.init_entries = init;
00777   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
00778   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
00779   /* ??? For now we just use mach to determine which ones we want.  */
00780   for (i = 0; init[i].name != NULL; ++i)
00781     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
00782        & machs)
00783       selected[init[i].type] = &init[i];
00784   cd->operand_table.entries = selected;
00785   cd->operand_table.num_entries = MAX_OPERANDS;
00786 }
00787 
00788 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.
00789    ??? This could leave out insns not supported by the specified mach/isa,
00790    but that would cause errors like "foo only supported by bar" to become
00791    "unknown insn", so for now we include all insns and require the app to
00792    do the checking later.
00793    ??? On the other hand, parsing of such insns may require their hardware or
00794    operand elements to be in the table [which they mightn't be].  */
00795 
00796 static void
00797 build_insn_table (CGEN_CPU_TABLE *cd)
00798 {
00799   int i;
00800   const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0];
00801   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
00802 
00803   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
00804   for (i = 0; i < MAX_INSNS; ++i)
00805     insns[i].base = &ib[i];
00806   cd->insn_table.init_entries = insns;
00807   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
00808   cd->insn_table.num_init_entries = MAX_INSNS;
00809 }
00810 
00811 /* Subroutine of openrisc_cgen_cpu_open to rebuild the tables.  */
00812 
00813 static void
00814 openrisc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
00815 {
00816   int i;
00817   CGEN_BITSET *isas = cd->isas;
00818   unsigned int machs = cd->machs;
00819 
00820   cd->int_insn_p = CGEN_INT_INSN_P;
00821 
00822   /* Data derived from the isa spec.  */
00823 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
00824   cd->default_insn_bitsize = UNSET;
00825   cd->base_insn_bitsize = UNSET;
00826   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
00827   cd->max_insn_bitsize = 0;
00828   for (i = 0; i < MAX_ISAS; ++i)
00829     if (cgen_bitset_contains (isas, i))
00830       {
00831        const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
00832 
00833        /* Default insn sizes of all selected isas must be
00834           equal or we set the result to 0, meaning "unknown".  */
00835        if (cd->default_insn_bitsize == UNSET)
00836          cd->default_insn_bitsize = isa->default_insn_bitsize;
00837        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
00838          ; /* This is ok.  */
00839        else
00840          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
00841 
00842        /* Base insn sizes of all selected isas must be equal
00843           or we set the result to 0, meaning "unknown".  */
00844        if (cd->base_insn_bitsize == UNSET)
00845          cd->base_insn_bitsize = isa->base_insn_bitsize;
00846        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
00847          ; /* This is ok.  */
00848        else
00849          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
00850 
00851        /* Set min,max insn sizes.  */
00852        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
00853          cd->min_insn_bitsize = isa->min_insn_bitsize;
00854        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
00855          cd->max_insn_bitsize = isa->max_insn_bitsize;
00856       }
00857 
00858   /* Data derived from the mach spec.  */
00859   for (i = 0; i < MAX_MACHS; ++i)
00860     if (((1 << i) & machs) != 0)
00861       {
00862        const CGEN_MACH *mach = & openrisc_cgen_mach_table[i];
00863 
00864        if (mach->insn_chunk_bitsize != 0)
00865        {
00866          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
00867            {
00868              fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
00869                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
00870              abort ();
00871            }
00872 
00873          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
00874        }
00875       }
00876 
00877   /* Determine which hw elements are used by MACH.  */
00878   build_hw_table (cd);
00879 
00880   /* Build the ifield table.  */
00881   build_ifield_table (cd);
00882 
00883   /* Determine which operands are used by MACH/ISA.  */
00884   build_operand_table (cd);
00885 
00886   /* Build the instruction table.  */
00887   build_insn_table (cd);
00888 }
00889 
00890 /* Initialize a cpu table and return a descriptor.
00891    It's much like opening a file, and must be the first function called.
00892    The arguments are a set of (type/value) pairs, terminated with
00893    CGEN_CPU_OPEN_END.
00894 
00895    Currently supported values:
00896    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
00897    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
00898    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
00899    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
00900    CGEN_CPU_OPEN_END:     terminates arguments
00901 
00902    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
00903    precluded.
00904 
00905    ??? We only support ISO C stdargs here, not K&R.
00906    Laziness, plus experiment to see if anything requires K&R - eventually
00907    K&R will no longer be supported - e.g. GDB is currently trying this.  */
00908 
00909 CGEN_CPU_DESC
00910 openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
00911 {
00912   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
00913   static int init_p;
00914   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
00915   unsigned int machs = 0; /* 0 = "unspecified" */
00916   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
00917   va_list ap;
00918 
00919   if (! init_p)
00920     {
00921       init_tables ();
00922       init_p = 1;
00923     }
00924 
00925   memset (cd, 0, sizeof (*cd));
00926 
00927   va_start (ap, arg_type);
00928   while (arg_type != CGEN_CPU_OPEN_END)
00929     {
00930       switch (arg_type)
00931        {
00932        case CGEN_CPU_OPEN_ISAS :
00933          isas = va_arg (ap, CGEN_BITSET *);
00934          break;
00935        case CGEN_CPU_OPEN_MACHS :
00936          machs = va_arg (ap, unsigned int);
00937          break;
00938        case CGEN_CPU_OPEN_BFDMACH :
00939          {
00940            const char *name = va_arg (ap, const char *);
00941            const CGEN_MACH *mach =
00942              lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name);
00943 
00944            machs |= 1 << mach->num;
00945            break;
00946          }
00947        case CGEN_CPU_OPEN_ENDIAN :
00948          endian = va_arg (ap, enum cgen_endian);
00949          break;
00950        default :
00951          fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n",
00952                  arg_type);
00953          abort (); /* ??? return NULL? */
00954        }
00955       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
00956     }
00957   va_end (ap);
00958 
00959   /* Mach unspecified means "all".  */
00960   if (machs == 0)
00961     machs = (1 << MAX_MACHS) - 1;
00962   /* Base mach is always selected.  */
00963   machs |= 1;
00964   if (endian == CGEN_ENDIAN_UNKNOWN)
00965     {
00966       /* ??? If target has only one, could have a default.  */
00967       fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n");
00968       abort ();
00969     }
00970 
00971   cd->isas = cgen_bitset_copy (isas);
00972   cd->machs = machs;
00973   cd->endian = endian;
00974   /* FIXME: for the sparc case we can determine insn-endianness statically.
00975      The worry here is where both data and insn endian can be independently
00976      chosen, in which case this function will need another argument.
00977      Actually, will want to allow for more arguments in the future anyway.  */
00978   cd->insn_endian = endian;
00979 
00980   /* Table (re)builder.  */
00981   cd->rebuild_tables = openrisc_cgen_rebuild_tables;
00982   openrisc_cgen_rebuild_tables (cd);
00983 
00984   /* Default to not allowing signed overflow.  */
00985   cd->signed_overflow_ok_p = 0;
00986   
00987   return (CGEN_CPU_DESC) cd;
00988 }
00989 
00990 /* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
00991    MACH_NAME is the bfd name of the mach.  */
00992 
00993 CGEN_CPU_DESC
00994 openrisc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
00995 {
00996   return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
00997                             CGEN_CPU_OPEN_ENDIAN, endian,
00998                             CGEN_CPU_OPEN_END);
00999 }
01000 
01001 /* Close a cpu table.
01002    ??? This can live in a machine independent file, but there's currently
01003    no place to put this file (there's no libcgen).  libopcodes is the wrong
01004    place as some simulator ports use this but they don't use libopcodes.  */
01005 
01006 void
01007 openrisc_cgen_cpu_close (CGEN_CPU_DESC cd)
01008 {
01009   unsigned int i;
01010   const CGEN_INSN *insns;
01011 
01012   if (cd->macro_insn_table.init_entries)
01013     {
01014       insns = cd->macro_insn_table.init_entries;
01015       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01016        if (CGEN_INSN_RX ((insns)))
01017          regfree (CGEN_INSN_RX (insns));
01018     }
01019 
01020   if (cd->insn_table.init_entries)
01021     {
01022       insns = cd->insn_table.init_entries;
01023       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01024        if (CGEN_INSN_RX (insns))
01025          regfree (CGEN_INSN_RX (insns));
01026     }  
01027 
01028   if (cd->macro_insn_table.init_entries)
01029     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01030 
01031   if (cd->insn_table.init_entries)
01032     free ((CGEN_INSN *) cd->insn_table.init_entries);
01033 
01034   if (cd->hw_table.entries)
01035     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01036 
01037   if (cd->operand_table.entries)
01038     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01039 
01040   free (cd);
01041 }
01042