Back to index

cell-binutils  2.17cvs20070401
v850.h
Go to the documentation of this file.
00001 /* v850.h -- Header file for NEC V850 opcode table
00002    Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc.
00003    Written by J.T. Conklin, Cygnus Support
00004 
00005 This file is part of GDB, GAS, and the GNU binutils.
00006 
00007 GDB, GAS, and the GNU binutils are free software; you can redistribute
00008 them and/or modify them under the terms of the GNU General Public
00009 License as published by the Free Software Foundation; either version
00010 1, or (at your option) any later version.
00011 
00012 GDB, GAS, and the GNU binutils are distributed in the hope that they
00013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015 the GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this file; see the file COPYING.  If not, write to the Free
00019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 #ifndef V850_H
00022 #define V850_H
00023 
00024 /* The opcode table is an array of struct v850_opcode.  */
00025 
00026 struct v850_opcode
00027 {
00028   /* The opcode name.  */
00029   const char *name;
00030 
00031   /* The opcode itself.  Those bits which will be filled in with
00032      operands are zeroes.  */
00033   unsigned long opcode;
00034 
00035   /* The opcode mask.  This is used by the disassembler.  This is a
00036      mask containing ones indicating those bits which must match the
00037      opcode field, and zeroes indicating those bits which need not
00038      match (and are presumably filled in by operands).  */
00039   unsigned long mask;
00040 
00041   /* An array of operand codes.  Each code is an index into the
00042      operand table.  They appear in the order which the operands must
00043      appear in assembly code, and are terminated by a zero.  */
00044   unsigned char operands[8];
00045 
00046   /* Which (if any) operand is a memory operand.  */
00047   unsigned int memop;
00048 
00049   /* Target processor(s).  A bit field of processors which support
00050      this instruction.  Note a bit field is used as some instructions
00051      are available on multiple, different processor types, whereas
00052      other instructions are only available on one specific type.  */
00053   unsigned int processors;
00054 };
00055 
00056 /* Values for the processors field in the v850_opcode structure.  */
00057 #define PROCESSOR_V850             (1 << 0)             /* Just the V850.  */
00058 #define PROCESSOR_ALL              -1                   /* Any processor.  */
00059 #define PROCESSOR_V850E            (1 << 1)             /* Just the V850E. */
00060 #define PROCESSOR_NOT_V850  (~ PROCESSOR_V850)   /* Any processor except the V850.  */
00061 #define PROCESSOR_V850EA    (1 << 2)             /* Just the V850EA. */
00062 #define PROCESSOR_V850E1    (1 << 3)             /* Just the V850E1. */
00063 
00064 /* The table itself is sorted by major opcode number, and is otherwise
00065    in the order in which the disassembler should consider
00066    instructions.  */
00067 extern const struct v850_opcode v850_opcodes[];
00068 extern const int v850_num_opcodes;
00069 
00070 
00071 /* The operands table is an array of struct v850_operand.  */
00072 
00073 struct v850_operand
00074 {
00075   /* The number of bits in the operand.  */
00076   /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
00077   int bits;
00078 
00079   /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
00080   /* (bits == -1): Bit mask of the bits in the operand.  */
00081   int shift;
00082 
00083   /* Insertion function.  This is used by the assembler.  To insert an
00084      operand value into an instruction, check this field.
00085 
00086      If it is NULL, execute
00087          i |= (op & ((1 << o->bits) - 1)) << o->shift;
00088      (i is the instruction which we are filling in, o is a pointer to
00089      this structure, and op is the opcode value; this assumes twos
00090      complement arithmetic).
00091 
00092      If this field is not NULL, then simply call it with the
00093      instruction and the operand value.  It will return the new value
00094      of the instruction.  If the ERRMSG argument is not NULL, then if
00095      the operand value is illegal, *ERRMSG will be set to a warning
00096      string (the operand will be inserted in any case).  If the
00097      operand value is legal, *ERRMSG will be unchanged (most operands
00098      can accept any value).  */
00099   unsigned long (* insert)
00100     (unsigned long instruction, long op, const char ** errmsg);
00101 
00102   /* Extraction function.  This is used by the disassembler.  To
00103      extract this operand type from an instruction, check this field.
00104 
00105      If it is NULL, compute
00106          op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
00107         if (o->flags & V850_OPERAND_SIGNED)
00108             op = (op << (32 - o->bits)) >> (32 - o->bits);
00109      (i is the instruction, o is a pointer to this structure, and op
00110      is the result; this assumes twos complement arithmetic).
00111 
00112      If this field is not NULL, then simply call it with the
00113      instruction value.  It will return the value of the operand.  If
00114      the INVALID argument is not NULL, *INVALID will be set to
00115      non-zero if this operand type can not actually be extracted from
00116      this operand (i.e., the instruction does not match).  If the
00117      operand is valid, *INVALID will not be changed.  */
00118   unsigned long (* extract) (unsigned long instruction, int * invalid);
00119 
00120   /* One bit syntax flags.  */
00121   int flags;
00122 };
00123 
00124 /* Elements in the table are retrieved by indexing with values from
00125    the operands field of the v850_opcodes table.  */
00126 
00127 extern const struct v850_operand v850_operands[];
00128 
00129 /* Values defined for the flags field of a struct v850_operand.  */
00130 
00131 /* This operand names a general purpose register */
00132 #define V850_OPERAND_REG    0x01
00133 
00134 /* This operand names a system register */
00135 #define V850_OPERAND_SRG    0x02
00136 
00137 /* This operand names a condition code used in the setf instruction */
00138 #define V850_OPERAND_CC            0x04
00139 
00140 /* This operand takes signed values */
00141 #define V850_OPERAND_SIGNED 0x08
00142 
00143 /* This operand is the ep register.  */
00144 #define V850_OPERAND_EP            0x10
00145 
00146 /* This operand is a PC displacement */
00147 #define V850_OPERAND_DISP   0x20
00148 
00149 /* This is a relaxable operand.   Only used for D9->D22 branch relaxing
00150    right now.  We may need others in the future (or maybe handle them like
00151    promoted operands on the mn10300?)  */
00152 #define V850_OPERAND_RELAX  0x40
00153 
00154 /* The register specified must not be r0 */
00155 #define V850_NOT_R0          0x80
00156 
00157 /* push/pop type instruction, V850E specific.  */
00158 #define V850E_PUSH_POP             0x100
00159 
00160 /* 16 bit immediate follows instruction, V850E specific.  */
00161 #define V850E_IMMEDIATE16   0x200
00162 
00163 /* 32 bit immediate follows instruction, V850E specific.  */
00164 #define V850E_IMMEDIATE32   0x400
00165 
00166 #endif /* V850_H */